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6ddcf9b4 WBG |
1 | /* |
2 | * GPIO driver for the ACCES 104-IDI-48 family | |
3 | * Copyright (C) 2015 William Breathitt Gray | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License, version 2, as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
12 | * General Public License for more details. | |
13 | */ | |
14 | #include <linux/bitops.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/gpio/driver.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/irqdesc.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
28 | static unsigned idi_48_base; | |
29 | module_param(idi_48_base, uint, 0); | |
30 | MODULE_PARM_DESC(idi_48_base, "ACCES 104-IDI-48 base address"); | |
31 | static unsigned idi_48_irq; | |
32 | module_param(idi_48_irq, uint, 0); | |
33 | MODULE_PARM_DESC(idi_48_irq, "ACCES 104-IDI-48 interrupt line number"); | |
34 | ||
35 | /** | |
36 | * struct idi_48_gpio - GPIO device private data structure | |
37 | * @chip: instance of the gpio_chip | |
38 | * @lock: synchronization lock to prevent I/O race conditions | |
9ae48210 | 39 | * @ack_lock: synchronization lock to prevent IRQ handler race conditions |
6ddcf9b4 WBG |
40 | * @irq_mask: input bits affected by interrupts |
41 | * @base: base port address of the GPIO device | |
42 | * @extent: extent of port address region of the GPIO device | |
43 | * @irq: Interrupt line number | |
44 | * @cos_enb: Change-Of-State IRQ enable boundaries mask | |
45 | */ | |
46 | struct idi_48_gpio { | |
47 | struct gpio_chip chip; | |
48 | spinlock_t lock; | |
9ae48210 | 49 | spinlock_t ack_lock; |
6ddcf9b4 WBG |
50 | unsigned char irq_mask[6]; |
51 | unsigned base; | |
52 | unsigned extent; | |
53 | unsigned irq; | |
54 | unsigned char cos_enb; | |
55 | }; | |
56 | ||
57 | static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |
58 | { | |
59 | return 1; | |
60 | } | |
61 | ||
62 | static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
63 | { | |
64 | return 0; | |
65 | } | |
66 | ||
6ddcf9b4 WBG |
67 | static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset) |
68 | { | |
1f36bec5 | 69 | struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); |
6ddcf9b4 WBG |
70 | unsigned i; |
71 | const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 }; | |
72 | unsigned base_offset; | |
73 | unsigned mask; | |
74 | ||
75 | for (i = 0; i < 48; i += 8) | |
76 | if (offset < i + 8) { | |
77 | base_offset = register_offset[i / 8]; | |
78 | mask = BIT(offset - i); | |
79 | ||
80 | return !!(inb(idi48gpio->base + base_offset) & mask); | |
81 | } | |
82 | ||
83 | /* The following line should never execute since offset < 48 */ | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static void idi_48_irq_ack(struct irq_data *data) | |
88 | { | |
6ddcf9b4 WBG |
89 | } |
90 | ||
91 | static void idi_48_irq_mask(struct irq_data *data) | |
92 | { | |
93 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
1f36bec5 | 94 | struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); |
6ddcf9b4 WBG |
95 | const unsigned offset = irqd_to_hwirq(data); |
96 | unsigned i; | |
97 | unsigned mask; | |
98 | unsigned boundary; | |
99 | unsigned long flags; | |
100 | ||
101 | for (i = 0; i < 48; i += 8) | |
102 | if (offset < i + 8) { | |
103 | mask = BIT(offset - i); | |
104 | boundary = i / 8; | |
105 | ||
106 | idi48gpio->irq_mask[boundary] &= ~mask; | |
107 | ||
108 | if (!idi48gpio->irq_mask[boundary]) { | |
109 | idi48gpio->cos_enb &= ~BIT(boundary); | |
110 | ||
111 | spin_lock_irqsave(&idi48gpio->lock, flags); | |
112 | ||
113 | outb(idi48gpio->cos_enb, idi48gpio->base + 7); | |
114 | ||
115 | spin_unlock_irqrestore(&idi48gpio->lock, flags); | |
116 | } | |
117 | ||
118 | return; | |
119 | } | |
120 | } | |
121 | ||
122 | static void idi_48_irq_unmask(struct irq_data *data) | |
123 | { | |
124 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
1f36bec5 | 125 | struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); |
6ddcf9b4 WBG |
126 | const unsigned offset = irqd_to_hwirq(data); |
127 | unsigned i; | |
128 | unsigned mask; | |
129 | unsigned boundary; | |
130 | unsigned prev_irq_mask; | |
131 | unsigned long flags; | |
132 | ||
133 | for (i = 0; i < 48; i += 8) | |
134 | if (offset < i + 8) { | |
135 | mask = BIT(offset - i); | |
136 | boundary = i / 8; | |
137 | prev_irq_mask = idi48gpio->irq_mask[boundary]; | |
138 | ||
139 | idi48gpio->irq_mask[boundary] |= mask; | |
140 | ||
141 | if (!prev_irq_mask) { | |
142 | idi48gpio->cos_enb |= BIT(boundary); | |
143 | ||
144 | spin_lock_irqsave(&idi48gpio->lock, flags); | |
145 | ||
146 | outb(idi48gpio->cos_enb, idi48gpio->base + 7); | |
147 | ||
148 | spin_unlock_irqrestore(&idi48gpio->lock, flags); | |
149 | } | |
150 | ||
151 | return; | |
152 | } | |
153 | } | |
154 | ||
155 | static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type) | |
156 | { | |
157 | /* The only valid irq types are none and both-edges */ | |
158 | if (flow_type != IRQ_TYPE_NONE && | |
159 | (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH) | |
160 | return -EINVAL; | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static struct irq_chip idi_48_irqchip = { | |
166 | .name = "104-idi-48", | |
167 | .irq_ack = idi_48_irq_ack, | |
168 | .irq_mask = idi_48_irq_mask, | |
169 | .irq_unmask = idi_48_irq_unmask, | |
170 | .irq_set_type = idi_48_irq_set_type | |
171 | }; | |
172 | ||
173 | static irqreturn_t idi_48_irq_handler(int irq, void *dev_id) | |
174 | { | |
175 | struct idi_48_gpio *const idi48gpio = dev_id; | |
176 | unsigned long cos_status; | |
177 | unsigned long boundary; | |
178 | unsigned long irq_mask; | |
179 | unsigned long bit_num; | |
180 | unsigned long gpio; | |
181 | struct gpio_chip *const chip = &idi48gpio->chip; | |
182 | ||
9ae48210 WBG |
183 | spin_lock(&idi48gpio->ack_lock); |
184 | ||
6ddcf9b4 WBG |
185 | spin_lock(&idi48gpio->lock); |
186 | ||
187 | cos_status = inb(idi48gpio->base + 7); | |
188 | ||
189 | spin_unlock(&idi48gpio->lock); | |
190 | ||
191 | /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */ | |
9ae48210 WBG |
192 | if (cos_status & BIT(6)) { |
193 | spin_unlock(&idi48gpio->ack_lock); | |
6ddcf9b4 | 194 | return IRQ_NONE; |
9ae48210 | 195 | } |
6ddcf9b4 WBG |
196 | |
197 | /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */ | |
198 | cos_status &= 0x3F; | |
199 | ||
200 | for_each_set_bit(boundary, &cos_status, 6) { | |
201 | irq_mask = idi48gpio->irq_mask[boundary]; | |
202 | ||
203 | for_each_set_bit(bit_num, &irq_mask, 8) { | |
204 | gpio = bit_num + boundary * 8; | |
205 | ||
206 | generic_handle_irq(irq_find_mapping(chip->irqdomain, | |
207 | gpio)); | |
208 | } | |
209 | } | |
210 | ||
9ae48210 WBG |
211 | spin_unlock(&idi48gpio->ack_lock); |
212 | ||
6ddcf9b4 WBG |
213 | return IRQ_HANDLED; |
214 | } | |
215 | ||
216 | static int __init idi_48_probe(struct platform_device *pdev) | |
217 | { | |
218 | struct device *dev = &pdev->dev; | |
219 | struct idi_48_gpio *idi48gpio; | |
220 | const unsigned base = idi_48_base; | |
221 | const unsigned extent = 8; | |
222 | const char *const name = dev_name(dev); | |
223 | int err; | |
224 | const unsigned irq = idi_48_irq; | |
225 | ||
226 | idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL); | |
227 | if (!idi48gpio) | |
228 | return -ENOMEM; | |
229 | ||
230 | if (!request_region(base, extent, name)) { | |
231 | dev_err(dev, "Unable to lock %s port addresses (0x%X-0x%X)\n", | |
232 | name, base, base + extent); | |
233 | err = -EBUSY; | |
234 | goto err_lock_io_port; | |
235 | } | |
236 | ||
237 | idi48gpio->chip.label = name; | |
238 | idi48gpio->chip.parent = dev; | |
239 | idi48gpio->chip.owner = THIS_MODULE; | |
240 | idi48gpio->chip.base = -1; | |
241 | idi48gpio->chip.ngpio = 48; | |
242 | idi48gpio->chip.get_direction = idi_48_gpio_get_direction; | |
243 | idi48gpio->chip.direction_input = idi_48_gpio_direction_input; | |
244 | idi48gpio->chip.get = idi_48_gpio_get; | |
245 | idi48gpio->base = base; | |
246 | idi48gpio->extent = extent; | |
247 | idi48gpio->irq = irq; | |
248 | ||
249 | spin_lock_init(&idi48gpio->lock); | |
250 | ||
251 | dev_set_drvdata(dev, idi48gpio); | |
252 | ||
1f36bec5 | 253 | err = gpiochip_add_data(&idi48gpio->chip, idi48gpio); |
6ddcf9b4 WBG |
254 | if (err) { |
255 | dev_err(dev, "GPIO registering failed (%d)\n", err); | |
256 | goto err_gpio_register; | |
257 | } | |
258 | ||
259 | /* Disable IRQ by default */ | |
260 | outb(0, base + 7); | |
261 | inb(base + 7); | |
262 | ||
263 | err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0, | |
264 | handle_edge_irq, IRQ_TYPE_NONE); | |
265 | if (err) { | |
266 | dev_err(dev, "Could not add irqchip (%d)\n", err); | |
267 | goto err_gpiochip_irqchip_add; | |
268 | } | |
269 | ||
270 | err = request_irq(irq, idi_48_irq_handler, 0, name, idi48gpio); | |
271 | if (err) { | |
272 | dev_err(dev, "IRQ handler registering failed (%d)\n", err); | |
273 | goto err_request_irq; | |
274 | } | |
275 | ||
276 | return 0; | |
277 | ||
278 | err_request_irq: | |
279 | err_gpiochip_irqchip_add: | |
280 | gpiochip_remove(&idi48gpio->chip); | |
281 | err_gpio_register: | |
282 | release_region(base, extent); | |
283 | err_lock_io_port: | |
284 | return err; | |
285 | } | |
286 | ||
287 | static int idi_48_remove(struct platform_device *pdev) | |
288 | { | |
289 | struct idi_48_gpio *const idi48gpio = platform_get_drvdata(pdev); | |
290 | ||
291 | free_irq(idi48gpio->irq, idi48gpio); | |
292 | gpiochip_remove(&idi48gpio->chip); | |
293 | release_region(idi48gpio->base, idi48gpio->extent); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static struct platform_device *idi_48_device; | |
299 | ||
300 | static struct platform_driver idi_48_driver = { | |
301 | .driver = { | |
302 | .name = "104-idi-48" | |
303 | }, | |
304 | .remove = idi_48_remove | |
305 | }; | |
306 | ||
307 | static void __exit idi_48_exit(void) | |
308 | { | |
309 | platform_device_unregister(idi_48_device); | |
310 | platform_driver_unregister(&idi_48_driver); | |
311 | } | |
312 | ||
313 | static int __init idi_48_init(void) | |
314 | { | |
315 | int err; | |
316 | ||
317 | idi_48_device = platform_device_alloc(idi_48_driver.driver.name, -1); | |
318 | if (!idi_48_device) | |
319 | return -ENOMEM; | |
320 | ||
321 | err = platform_device_add(idi_48_device); | |
322 | if (err) | |
323 | goto err_platform_device; | |
324 | ||
325 | err = platform_driver_probe(&idi_48_driver, idi_48_probe); | |
326 | if (err) | |
327 | goto err_platform_driver; | |
328 | ||
329 | return 0; | |
330 | ||
331 | err_platform_driver: | |
332 | platform_device_del(idi_48_device); | |
333 | err_platform_device: | |
334 | platform_device_put(idi_48_device); | |
335 | return err; | |
336 | } | |
337 | ||
338 | module_init(idi_48_init); | |
339 | module_exit(idi_48_exit); | |
340 | ||
341 | MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); | |
342 | MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver"); | |
343 | MODULE_LICENSE("GPL"); |