[deliverable/linux.git] / drivers / gpio / gpio-bcm-kona.c

/*
 * Copyright (C) 2012-2013 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>

#define BCM_GPIO_PASSWD				0x00a5a501
#define GPIO_PER_BANK				32
#define GPIO_MAX_BANK_NUM			8

#define GPIO_BANK(gpio)				((gpio) >> 5)
#define GPIO_BIT(gpio)				((gpio) & (GPIO_PER_BANK - 1))

#define GPIO_OUT_STATUS(bank)			(0x00000000 + ((bank) << 2))
#define GPIO_IN_STATUS(bank)			(0x00000020 + ((bank) << 2))
#define GPIO_OUT_SET(bank)			(0x00000040 + ((bank) << 2))
#define GPIO_OUT_CLEAR(bank)			(0x00000060 + ((bank) << 2))
#define GPIO_INT_STATUS(bank)			(0x00000080 + ((bank) << 2))
#define GPIO_INT_MASK(bank)			(0x000000a0 + ((bank) << 2))
#define GPIO_INT_MSKCLR(bank)			(0x000000c0 + ((bank) << 2))
#define GPIO_CONTROL(bank)			(0x00000100 + ((bank) << 2))
#define GPIO_PWD_STATUS(bank)			(0x00000500 + ((bank) << 2))

#define GPIO_GPPWR_OFFSET			0x00000520

#define GPIO_GPCTR0_DBR_SHIFT			5
#define GPIO_GPCTR0_DBR_MASK			0x000001e0

#define GPIO_GPCTR0_ITR_SHIFT			3
#define GPIO_GPCTR0_ITR_MASK			0x00000018
#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE		0x00000001
#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE	0x00000002
#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE		0x00000003

#define GPIO_GPCTR0_IOTR_MASK			0x00000001
#define GPIO_GPCTR0_IOTR_CMD_0UTPUT		0x00000000
#define GPIO_GPCTR0_IOTR_CMD_INPUT		0x00000001

#define GPIO_GPCTR0_DB_ENABLE_MASK		0x00000100

#define LOCK_CODE				0xffffffff
#define UNLOCK_CODE				0x00000000

struct bcm_kona_gpio {
	void __iomem *reg_base;
	int num_bank;
	spinlock_t lock;
	struct gpio_chip gpio_chip;
	struct irq_domain *irq_domain;
	struct bcm_kona_gpio_bank *banks;
	struct platform_device *pdev;
};

struct bcm_kona_gpio_bank {
	int id;
	int irq;
	/* Used in the interrupt handler */
	struct bcm_kona_gpio *kona_gpio;
};

static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct bcm_kona_gpio, gpio_chip);
}

static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
					    int bank_id, int lockcode)
{
	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
}

static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
{
	bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
}

static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
					     int bank_id)
{
	bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
}

static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val, reg_offset;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	/* determine the GPIO pin direction */
	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= GPIO_GPCTR0_IOTR_MASK;

	/* this function only applies to output pin */
	if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
		goto out;

	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);

	val = readl(reg_base + reg_offset);
	val |= BIT(bit);
	writel(val, reg_base + reg_offset);

out:
	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val, reg_offset;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	/* determine the GPIO pin direction */
	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= GPIO_GPCTR0_IOTR_MASK;

	/* read the GPIO bank status */
	reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
	    GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
	val = readl(reg_base + reg_offset);

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	/* return the specified bit status */
	return !!(val & bit);
}

static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	u32 val;
	unsigned long flags;
	int bank_id = GPIO_BANK(gpio);

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_IOTR_MASK;
	val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
	writel(val, reg_base + GPIO_CONTROL(gpio));

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
					  unsigned gpio, int value)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val, reg_offset;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_IOTR_MASK;
	val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
	writel(val, reg_base + GPIO_CONTROL(gpio));
	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);

	val = readl(reg_base + reg_offset);
	val |= BIT(bit);
	writel(val, reg_base + reg_offset);

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio;

	kona_gpio = to_kona_gpio(chip);
	if (gpio >= kona_gpio->gpio_chip.ngpio)
		return -ENXIO;
	return irq_create_mapping(kona_gpio->irq_domain, gpio);
}

static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
				      unsigned debounce)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	u32 val, res;
	unsigned long flags;
	int bank_id = GPIO_BANK(gpio);

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	/* debounce must be 1-128ms (or 0) */
	if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
		dev_err(chip->dev, "Debounce value %u not in range\n",
			debounce);
		return -EINVAL;
	}

	/* calculate debounce bit value */
	if (debounce != 0) {
		/* Convert to ms */
		debounce /= 1000;
		/* find the MSB */
		res = fls(debounce) - 1;
		/* Check if MSB-1 is set (round up or down) */
		if (res > 0 && (debounce & BIT(res - 1)))
			res++;
	}

	/* spin lock for read-modify-write of the GPIO register */
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_DBR_MASK;

	if (debounce == 0) {
		/* disable debounce */
		val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
	} else {
		val |= GPIO_GPCTR0_DB_ENABLE_MASK |
		    (res << GPIO_GPCTR0_DBR_SHIFT);
	}

	writel(val, reg_base + GPIO_CONTROL(gpio));

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static struct gpio_chip template_chip = {
	.label = "bcm-kona-gpio",
	.direction_input = bcm_kona_gpio_direction_input,
	.get = bcm_kona_gpio_get,
	.direction_output = bcm_kona_gpio_direction_output,
	.set = bcm_kona_gpio_set,
	.set_debounce = bcm_kona_gpio_set_debounce,
	.to_irq = bcm_kona_gpio_to_irq,
	.base = 0,
};

static void bcm_kona_gpio_irq_ack(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int gpio = d->hwirq;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
	val |= BIT(bit);
	writel(val, reg_base + GPIO_INT_STATUS(bank_id));

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static void bcm_kona_gpio_irq_mask(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int gpio = d->hwirq;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_INT_MASK(bank_id));
	val |= BIT(bit);
	writel(val, reg_base + GPIO_INT_MASK(bank_id));

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int gpio = d->hwirq;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
	val |= BIT(bit);
	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int gpio = d->hwirq;
	u32 lvl_type;
	u32 val;
	unsigned long flags;
	int bank_id = GPIO_BANK(gpio);

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
	case IRQ_TYPE_LEVEL_LOW:
		/* BCM GPIO doesn't support level triggering */
	default:
		dev_err(kona_gpio->gpio_chip.dev,
			"Invalid BCM GPIO irq type 0x%x\n", type);
		return -EINVAL;
	}

	spin_lock_irqsave(&kona_gpio->lock, flags);
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_ITR_MASK;
	val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
	writel(val, reg_base + GPIO_CONTROL(gpio));

	bcm_kona_gpio_lock_bank(reg_base, bank_id);
	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	void __iomem *reg_base;
	int bit, bank_id;
	unsigned long sta;
	struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	/*
	 * For bank interrupts, we can't use chip_data to store the kona_gpio
	 * pointer, since GIC needs it for its own purposes. Therefore, we get
	 * our pointer from the bank structure.
	 */
	reg_base = bank->kona_gpio->reg_base;
	bank_id = bank->id;
	bcm_kona_gpio_unlock_bank(reg_base, bank_id);

	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
		for_each_set_bit(bit, &sta, 32) {
			int gpio = GPIO_PER_BANK * bank_id + bit;
			int virq = irq_find_mapping(bank->kona_gpio->irq_domain,
						    gpio);
			/*
			 * Clear interrupt before handler is called so we don't
			 * miss any interrupt occurred during executing them.
			 */
			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
			/* Invoke interrupt handler */
			generic_handle_irq(virq);
		}
	}

	bcm_kona_gpio_lock_bank(reg_base, bank_id);

	chained_irq_exit(chip, desc);
}

static struct irq_chip bcm_gpio_irq_chip = {
	.name = "bcm-kona-gpio",
	.irq_ack = bcm_kona_gpio_irq_ack,
	.irq_mask = bcm_kona_gpio_irq_mask,
	.irq_unmask = bcm_kona_gpio_irq_unmask,
	.irq_set_type = bcm_kona_gpio_irq_set_type,
};

static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
	{ .compatible = "brcm,kona-gpio" },
	{}
};

MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);

/*
 * This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int virq,
				 irq_hw_number_t hwirq)
{
	int ret;

	ret = irq_set_chip_data(virq, d->host_data);
	if (ret < 0)
		return ret;
	irq_set_lockdep_class(virq, &gpio_lock_class);
	irq_set_chip_and_handler(virq, &bcm_gpio_irq_chip, handle_simple_irq);
	irq_set_nested_thread(virq, 1);
	set_irq_flags(virq, IRQF_VALID);

	return 0;
}

static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
{
	irq_set_chip_and_handler(virq, NULL, NULL);
	irq_set_chip_data(virq, NULL);
}

static struct irq_domain_ops bcm_kona_irq_ops = {
	.map = bcm_kona_gpio_irq_map,
	.unmap = bcm_kona_gpio_irq_unmap,
	.xlate = irq_domain_xlate_twocell,
};

static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
{
	void __iomem *reg_base;
	int i;

	reg_base = kona_gpio->reg_base;
	/* disable interrupts and clear status */
	for (i = 0; i < kona_gpio->num_bank; i++) {
		bcm_kona_gpio_unlock_bank(reg_base, i);
		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
		bcm_kona_gpio_lock_bank(reg_base, i);
	}
}

static int bcm_kona_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *match;
	struct resource *res;
	struct bcm_kona_gpio_bank *bank;
	struct bcm_kona_gpio *kona_gpio;
	struct gpio_chip *chip;
	int ret;
	int i;

	match = of_match_device(bcm_kona_gpio_of_match, dev);
	if (!match) {
		dev_err(dev, "Failed to find gpio controller\n");
		return -ENODEV;
	}

	kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
	if (!kona_gpio)
		return -ENOMEM;

	kona_gpio->gpio_chip = template_chip;
	chip = &kona_gpio->gpio_chip;
	kona_gpio->num_bank = of_irq_count(dev->of_node);
	if (kona_gpio->num_bank == 0) {
		dev_err(dev, "Couldn't determine # GPIO banks\n");
		return -ENOENT;
	}
	if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
		dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
			GPIO_MAX_BANK_NUM);
		return -ENXIO;
	}
	kona_gpio->banks = devm_kzalloc(dev,
					kona_gpio->num_bank *
					sizeof(*kona_gpio->banks), GFP_KERNEL);
	if (!kona_gpio->banks)
		return -ENOMEM;

	kona_gpio->pdev = pdev;
	platform_set_drvdata(pdev, kona_gpio);
	chip->of_node = dev->of_node;
	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;

	kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
						      chip->ngpio,
						      &bcm_kona_irq_ops,
						      kona_gpio);
	if (!kona_gpio->irq_domain) {
		dev_err(dev, "Couldn't allocate IRQ domain\n");
		return -ENXIO;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	kona_gpio->reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(kona_gpio->reg_base)) {
		ret = -ENXIO;
		goto err_irq_domain;
	}

	for (i = 0; i < kona_gpio->num_bank; i++) {
		bank = &kona_gpio->banks[i];
		bank->id = i;
		bank->irq = platform_get_irq(pdev, i);
		bank->kona_gpio = kona_gpio;
		if (bank->irq < 0) {
			dev_err(dev, "Couldn't get IRQ for bank %d", i);
			ret = -ENOENT;
			goto err_irq_domain;
		}
	}

	dev_info(&pdev->dev, "Setting up Kona GPIO at 0x%p (phys %#x)\n",
		 kona_gpio->reg_base, res->start);

	bcm_kona_gpio_reset(kona_gpio);

	ret = gpiochip_add(chip);
	if (ret < 0) {
		dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
		goto err_irq_domain;
	}
	for (i = 0; i < chip->ngpio; i++) {
		int irq = bcm_kona_gpio_to_irq(chip, i);
		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	for (i = 0; i < kona_gpio->num_bank; i++) {
		bank = &kona_gpio->banks[i];
		irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);
	}

	spin_lock_init(&kona_gpio->lock);

	return 0;

err_irq_domain:
	irq_domain_remove(kona_gpio->irq_domain);

	return ret;
}

static struct platform_driver bcm_kona_gpio_driver = {
	.driver = {
			.name = "bcm-kona-gpio",
			.owner = THIS_MODULE,
			.of_match_table = bcm_kona_gpio_of_match,
	},
	.probe = bcm_kona_gpio_probe,
};

module_platform_driver(bcm_kona_gpio_driver);

MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
757651e3 MM	1	/*
	2	* Copyright (C) 2012-2013 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation version 2.
	7	*
	8	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	9	* kind, whether express or implied; without even the implied warranty
	10	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/err.h>
	16	#include <linux/io.h>
	17	#include <linux/gpio.h>
	18	#include <linux/of_device.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/module.h>
	21	#include <linux/irqdomain.h>
	22	#include <linux/irqchip/chained_irq.h>
	23
	24	#define BCM_GPIO_PASSWD 0x00a5a501
	25	#define GPIO_PER_BANK 32
	26	#define GPIO_MAX_BANK_NUM 8
	27
	28	#define GPIO_BANK(gpio) ((gpio) >> 5)
	29	#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
	30
	31	#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
	32	#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
	33	#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
	34	#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
	35	#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
	36	#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
	37	#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
	38	#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
	39	#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
	40
	41	#define GPIO_GPPWR_OFFSET 0x00000520
	42
	43	#define GPIO_GPCTR0_DBR_SHIFT 5
	44	#define GPIO_GPCTR0_DBR_MASK 0x000001e0
	45
	46	#define GPIO_GPCTR0_ITR_SHIFT 3
	47	#define GPIO_GPCTR0_ITR_MASK 0x00000018
	48	#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
	49	#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
	50	#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
	51
	52	#define GPIO_GPCTR0_IOTR_MASK 0x00000001
	53	#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
	54	#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
	55
	56	#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
	57
	58	#define LOCK_CODE 0xffffffff
	59	#define UNLOCK_CODE 0x00000000
	60
	61	struct bcm_kona_gpio {
	62	void __iomem *reg_base;
	63	int num_bank;
	64	spinlock_t lock;
65	struct gpio_chip gpio_chip;
66	struct irq_domain *irq_domain;
67	struct bcm_kona_gpio_bank *banks;
68	struct platform_device *pdev;
69	};
70
71	struct bcm_kona_gpio_bank {
72	int id;
73	int irq;
74	/* Used in the interrupt handler */
75	struct bcm_kona_gpio *kona_gpio;
76	};
77
78	static inline struct bcm_kona_gpio to_kona_gpio(struct gpio_chip chip)
79	{
80	return container_of(chip, struct bcm_kona_gpio, gpio_chip);
81	}
82
83	static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
84	int bank_id, int lockcode)
85	{
86	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
87	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
88	}
89
90	static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
91	{
92	bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
93	}
94
95	static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
96	int bank_id)
97	{
98	bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
99	}
100
101	static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
102	{
103	struct bcm_kona_gpio *kona_gpio;
104	void __iomem *reg_base;
105	int bank_id = GPIO_BANK(gpio);
106	int bit = GPIO_BIT(gpio);
107	u32 val, reg_offset;
108	unsigned long flags;
109
110	kona_gpio = to_kona_gpio(chip);
111	reg_base = kona_gpio->reg_base;
112	spin_lock_irqsave(&kona_gpio->lock, flags);
113	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
114
115	/* determine the GPIO pin direction */
116	val = readl(reg_base + GPIO_CONTROL(gpio));
117	val &= GPIO_GPCTR0_IOTR_MASK;
118
119	/* this function only applies to output pin */
120	if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
121	goto out;
122
123	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
124
125	val = readl(reg_base + reg_offset);
126	val \|= BIT(bit);
127	writel(val, reg_base + reg_offset);
128
129	out:
130	bcm_kona_gpio_lock_bank(reg_base, bank_id);
131	spin_unlock_irqrestore(&kona_gpio->lock, flags);
132	}
133
134	static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
135	{
136	struct bcm_kona_gpio *kona_gpio;
137	void __iomem *reg_base;
138	int bank_id = GPIO_BANK(gpio);
139	int bit = GPIO_BIT(gpio);
140	u32 val, reg_offset;
141	unsigned long flags;
142
143	kona_gpio = to_kona_gpio(chip);
144	reg_base = kona_gpio->reg_base;
145	spin_lock_irqsave(&kona_gpio->lock, flags);
146	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
147
148	/* determine the GPIO pin direction */
149	val = readl(reg_base + GPIO_CONTROL(gpio));
150	val &= GPIO_GPCTR0_IOTR_MASK;
151
152	/* read the GPIO bank status */
153	reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
154	GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
155	val = readl(reg_base + reg_offset);
156
157	bcm_kona_gpio_lock_bank(reg_base, bank_id);
158	spin_unlock_irqrestore(&kona_gpio->lock, flags);
159
160	/* return the specified bit status */
161	return !!(val & bit);
162	}
163
164	static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
165	{
166	struct bcm_kona_gpio *kona_gpio;
167	void __iomem *reg_base;
168	u32 val;
169	unsigned long flags;
170	int bank_id = GPIO_BANK(gpio);
171
172	kona_gpio = to_kona_gpio(chip);
173	reg_base = kona_gpio->reg_base;
174	spin_lock_irqsave(&kona_gpio->lock, flags);
175	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
176
177	val = readl(reg_base + GPIO_CONTROL(gpio));
178	val &= ~GPIO_GPCTR0_IOTR_MASK;
179	val \|= GPIO_GPCTR0_IOTR_CMD_INPUT;
180	writel(val, reg_base + GPIO_CONTROL(gpio));
181
182	bcm_kona_gpio_lock_bank(reg_base, bank_id);
183	spin_unlock_irqrestore(&kona_gpio->lock, flags);
184
185	return 0;
186	}
187
188	static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
189	unsigned gpio, int value)
190	{
191	struct bcm_kona_gpio *kona_gpio;
192	void __iomem *reg_base;
193	int bank_id = GPIO_BANK(gpio);
194	int bit = GPIO_BIT(gpio);
195	u32 val, reg_offset;
196	unsigned long flags;
197
198	kona_gpio = to_kona_gpio(chip);
199	reg_base = kona_gpio->reg_base;
200	spin_lock_irqsave(&kona_gpio->lock, flags);
201	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
202
203	val = readl(reg_base + GPIO_CONTROL(gpio));
204	val &= ~GPIO_GPCTR0_IOTR_MASK;
205	val \|= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
206	writel(val, reg_base + GPIO_CONTROL(gpio));
207	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
208
209	val = readl(reg_base + reg_offset);
210	val \|= BIT(bit);
211	writel(val, reg_base + reg_offset);
212
213	bcm_kona_gpio_lock_bank(reg_base, bank_id);
214	spin_unlock_irqrestore(&kona_gpio->lock, flags);
215
216	return 0;
217	}
218
219	static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
220	{
221	struct bcm_kona_gpio *kona_gpio;
222
223	kona_gpio = to_kona_gpio(chip);
224	if (gpio >= kona_gpio->gpio_chip.ngpio)
225	return -ENXIO;
226	return irq_create_mapping(kona_gpio->irq_domain, gpio);
227	}
228
229	static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
230	unsigned debounce)
231	{
232	struct bcm_kona_gpio *kona_gpio;
233	void __iomem *reg_base;
234	u32 val, res;
235	unsigned long flags;
236	int bank_id = GPIO_BANK(gpio);
237
238	kona_gpio = to_kona_gpio(chip);
239	reg_base = kona_gpio->reg_base;
240	/* debounce must be 1-128ms (or 0) */
241	if ((debounce > 0 && debounce < 1000) \|\| debounce > 128000) {
242	dev_err(chip->dev, "Debounce value %u not in range\n",
243	debounce);
244	return -EINVAL;
245	}
246
247	/* calculate debounce bit value */
248	if (debounce != 0) {
249	/* Convert to ms */
250	debounce /= 1000;
251	/* find the MSB */
252	res = fls(debounce) - 1;
253	/* Check if MSB-1 is set (round up or down) */
254	if (res > 0 && (debounce & BIT(res - 1)))
255	res++;
256	}
257
258	/* spin lock for read-modify-write of the GPIO register */
259	spin_lock_irqsave(&kona_gpio->lock, flags);
260	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
261
262	val = readl(reg_base + GPIO_CONTROL(gpio));
263	val &= ~GPIO_GPCTR0_DBR_MASK;
264
265	if (debounce == 0) {
266	/* disable debounce */
267	val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
268	} else {
269	val \|= GPIO_GPCTR0_DB_ENABLE_MASK \|
270	(res << GPIO_GPCTR0_DBR_SHIFT);
271	}
272
273	writel(val, reg_base + GPIO_CONTROL(gpio));
274
275	bcm_kona_gpio_lock_bank(reg_base, bank_id);
276	spin_unlock_irqrestore(&kona_gpio->lock, flags);
277
278	return 0;
279	}
280
281	static struct gpio_chip template_chip = {
282	.label = "bcm-kona-gpio",
283	.direction_input = bcm_kona_gpio_direction_input,
284	.get = bcm_kona_gpio_get,
285	.direction_output = bcm_kona_gpio_direction_output,
286	.set = bcm_kona_gpio_set,
287	.set_debounce = bcm_kona_gpio_set_debounce,
288	.to_irq = bcm_kona_gpio_to_irq,
289	.base = 0,
290	};
291
292	static void bcm_kona_gpio_irq_ack(struct irq_data *d)
293	{
294	struct bcm_kona_gpio *kona_gpio;
295	void __iomem *reg_base;
296	int gpio = d->hwirq;
297	int bank_id = GPIO_BANK(gpio);
298	int bit = GPIO_BIT(gpio);
299	u32 val;
300	unsigned long flags;
301
302	kona_gpio = irq_data_get_irq_chip_data(d);
303	reg_base = kona_gpio->reg_base;
304	spin_lock_irqsave(&kona_gpio->lock, flags);
305	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
306
307	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
308	val \|= BIT(bit);
309	writel(val, reg_base + GPIO_INT_STATUS(bank_id));
310
311	bcm_kona_gpio_lock_bank(reg_base, bank_id);
312	spin_unlock_irqrestore(&kona_gpio->lock, flags);
313	}
314
315	static void bcm_kona_gpio_irq_mask(struct irq_data *d)
316	{
317	struct bcm_kona_gpio *kona_gpio;
318	void __iomem *reg_base;
319	int gpio = d->hwirq;
320	int bank_id = GPIO_BANK(gpio);
321	int bit = GPIO_BIT(gpio);
322	u32 val;
323	unsigned long flags;
324
325	kona_gpio = irq_data_get_irq_chip_data(d);
326	reg_base = kona_gpio->reg_base;
327	spin_lock_irqsave(&kona_gpio->lock, flags);
328	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
329
330	val = readl(reg_base + GPIO_INT_MASK(bank_id));
331	val \|= BIT(bit);
332	writel(val, reg_base + GPIO_INT_MASK(bank_id));
333
334	bcm_kona_gpio_lock_bank(reg_base, bank_id);
335	spin_unlock_irqrestore(&kona_gpio->lock, flags);
336	}
337
338	static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
339	{
340	struct bcm_kona_gpio *kona_gpio;
341	void __iomem *reg_base;
342	int gpio = d->hwirq;
343	int bank_id = GPIO_BANK(gpio);
344	int bit = GPIO_BIT(gpio);
345	u32 val;
346	unsigned long flags;
347
348	kona_gpio = irq_data_get_irq_chip_data(d);
349	reg_base = kona_gpio->reg_base;
350	spin_lock_irqsave(&kona_gpio->lock, flags);
351	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
352
353	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
354	val \|= BIT(bit);
355	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
356
357	bcm_kona_gpio_lock_bank(reg_base, bank_id);
358	spin_unlock_irqrestore(&kona_gpio->lock, flags);
359	}
360
361	static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
362	{
363	struct bcm_kona_gpio *kona_gpio;
364	void __iomem *reg_base;
365	int gpio = d->hwirq;
366	u32 lvl_type;
367	u32 val;
368	unsigned long flags;
369	int bank_id = GPIO_BANK(gpio);
370
371	kona_gpio = irq_data_get_irq_chip_data(d);
372	reg_base = kona_gpio->reg_base;
373	switch (type & IRQ_TYPE_SENSE_MASK) {
374	case IRQ_TYPE_EDGE_RISING:
375	lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
376	break;
377
378	case IRQ_TYPE_EDGE_FALLING:
379	lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
380	break;
381
382	case IRQ_TYPE_EDGE_BOTH:
383	lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
384	break;
385
386	case IRQ_TYPE_LEVEL_HIGH:
387	case IRQ_TYPE_LEVEL_LOW:
388	/* BCM GPIO doesn't support level triggering */
389	default:
390	dev_err(kona_gpio->gpio_chip.dev,
391	"Invalid BCM GPIO irq type 0x%x\n", type);
392	return -EINVAL;
393	}
394
395	spin_lock_irqsave(&kona_gpio->lock, flags);
396	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
397
398	val = readl(reg_base + GPIO_CONTROL(gpio));
399	val &= ~GPIO_GPCTR0_ITR_MASK;
400	val \|= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
401	writel(val, reg_base + GPIO_CONTROL(gpio));
402
403	bcm_kona_gpio_lock_bank(reg_base, bank_id);
404	spin_unlock_irqrestore(&kona_gpio->lock, flags);
405
406	return 0;
407	}
408
409	static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
410	{
411	void __iomem *reg_base;
412	int bit, bank_id;
413	unsigned long sta;
414	struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
415	struct irq_chip *chip = irq_desc_get_chip(desc);
416
417	chained_irq_enter(chip, desc);
418
419	/*
420	* For bank interrupts, we can't use chip_data to store the kona_gpio
421	* pointer, since GIC needs it for its own purposes. Therefore, we get
422	* our pointer from the bank structure.
423	*/
424	reg_base = bank->kona_gpio->reg_base;
425	bank_id = bank->id;
426	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
427
428	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
429	(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
430	for_each_set_bit(bit, &sta, 32) {
431	int gpio = GPIO_PER_BANK * bank_id + bit;
432	int virq = irq_find_mapping(bank->kona_gpio->irq_domain,
433	gpio);
434	/*
435	* Clear interrupt before handler is called so we don't
436	* miss any interrupt occurred during executing them.
437	*/
438	writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) \|
439	BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
440	/* Invoke interrupt handler */
441	generic_handle_irq(virq);
442	}
443	}
444
445	bcm_kona_gpio_lock_bank(reg_base, bank_id);
446
447	chained_irq_exit(chip, desc);
448	}
449
450	static struct irq_chip bcm_gpio_irq_chip = {
451	.name = "bcm-kona-gpio",
452	.irq_ack = bcm_kona_gpio_irq_ack,
453	.irq_mask = bcm_kona_gpio_irq_mask,
454	.irq_unmask = bcm_kona_gpio_irq_unmask,
455	.irq_set_type = bcm_kona_gpio_irq_set_type,
456	};
457
458	static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
459	{ .compatible = "brcm,kona-gpio" },
460	{}
461	};
462
463	MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
464
465	/*
466	* This lock class tells lockdep that GPIO irqs are in a different
467	* category than their parents, so it won't report false recursion.
468	*/
469	static struct lock_class_key gpio_lock_class;
470
471	static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int virq,
472	irq_hw_number_t hwirq)
473	{
474	int ret;
475
476	ret = irq_set_chip_data(virq, d->host_data);
477	if (ret < 0)
478	return ret;
479	irq_set_lockdep_class(virq, &gpio_lock_class);
480	irq_set_chip_and_handler(virq, &bcm_gpio_irq_chip, handle_simple_irq);
481	irq_set_nested_thread(virq, 1);
482	set_irq_flags(virq, IRQF_VALID);
483
484	return 0;
485	}
486
487	static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
488	{
489	irq_set_chip_and_handler(virq, NULL, NULL);
490	irq_set_chip_data(virq, NULL);
491	}
492
493	static struct irq_domain_ops bcm_kona_irq_ops = {
494	.map = bcm_kona_gpio_irq_map,
495	.unmap = bcm_kona_gpio_irq_unmap,
496	.xlate = irq_domain_xlate_twocell,
497	};
498
499	static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
500	{
501	void __iomem *reg_base;
502	int i;
503
504	reg_base = kona_gpio->reg_base;
505	/* disable interrupts and clear status */
506	for (i = 0; i < kona_gpio->num_bank; i++) {
507	bcm_kona_gpio_unlock_bank(reg_base, i);
508	writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
509	writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
510	bcm_kona_gpio_lock_bank(reg_base, i);
511	}
512	}
513
514	static int bcm_kona_gpio_probe(struct platform_device *pdev)
515	{
516	struct device *dev = &pdev->dev;
517	const struct of_device_id *match;
518	struct resource *res;
519	struct bcm_kona_gpio_bank *bank;
520	struct bcm_kona_gpio *kona_gpio;
521	struct gpio_chip *chip;
522	int ret;
523	int i;
524
525	match = of_match_device(bcm_kona_gpio_of_match, dev);
526	if (!match) {
527	dev_err(dev, "Failed to find gpio controller\n");
528	return -ENODEV;
529	}
530
531	kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
532	if (!kona_gpio)
533	return -ENOMEM;
534
535	kona_gpio->gpio_chip = template_chip;
536	chip = &kona_gpio->gpio_chip;
537	kona_gpio->num_bank = of_irq_count(dev->of_node);
538	if (kona_gpio->num_bank == 0) {
539	dev_err(dev, "Couldn't determine # GPIO banks\n");
540	return -ENOENT;
541	}
542	if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
543	dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
544	GPIO_MAX_BANK_NUM);
545	return -ENXIO;
546	}
547	kona_gpio->banks = devm_kzalloc(dev,
548	kona_gpio->num_bank *
549	sizeof(*kona_gpio->banks), GFP_KERNEL);
550	if (!kona_gpio->banks)
551	return -ENOMEM;
552
553	kona_gpio->pdev = pdev;
554	platform_set_drvdata(pdev, kona_gpio);
555	chip->of_node = dev->of_node;
556	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
557
558	kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
559	chip->ngpio,
560	&bcm_kona_irq_ops,
561	kona_gpio);
562	if (!kona_gpio->irq_domain) {
563	dev_err(dev, "Couldn't allocate IRQ domain\n");
564	return -ENXIO;
565	}
566
567	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
568	kona_gpio->reg_base = devm_ioremap_resource(dev, res);
569	if (IS_ERR(kona_gpio->reg_base)) {
570	ret = -ENXIO;
571	goto err_irq_domain;
572	}
573
574	for (i = 0; i < kona_gpio->num_bank; i++) {
575	bank = &kona_gpio->banks[i];
576	bank->id = i;
577	bank->irq = platform_get_irq(pdev, i);
578	bank->kona_gpio = kona_gpio;
579	if (bank->irq < 0) {
580	dev_err(dev, "Couldn't get IRQ for bank %d", i);
581	ret = -ENOENT;
582	goto err_irq_domain;
583	}
584	}
585
586	dev_info(&pdev->dev, "Setting up Kona GPIO at 0x%p (phys %#x)\n",
587	kona_gpio->reg_base, res->start);
588
589	bcm_kona_gpio_reset(kona_gpio);
590
591	ret = gpiochip_add(chip);
592	if (ret < 0) {
593	dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
594	goto err_irq_domain;
595	}
596	for (i = 0; i < chip->ngpio; i++) {
597	int irq = bcm_kona_gpio_to_irq(chip, i);
598	irq_set_lockdep_class(irq, &gpio_lock_class);
599	irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
600	handle_simple_irq);
601	set_irq_flags(irq, IRQF_VALID);
602	}
603	for (i = 0; i < kona_gpio->num_bank; i++) {
604	bank = &kona_gpio->banks[i];
605	irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
606	irq_set_handler_data(bank->irq, bank);
607	}
608
609	spin_lock_init(&kona_gpio->lock);
610
611	return 0;
612
613	err_irq_domain:
614	irq_domain_remove(kona_gpio->irq_domain);
615
616	return ret;
617	}
618
619	static struct platform_driver bcm_kona_gpio_driver = {
620	.driver = {
621	.name = "bcm-kona-gpio",
622	.owner = THIS_MODULE,
623	.of_match_table = bcm_kona_gpio_of_match,
624	},
625	.probe = bcm_kona_gpio_probe,
626	};
627
628	module_platform_driver(bcm_kona_gpio_driver);
629
630	MODULE_AUTHOR("Broadcom");
631	MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
632	MODULE_LICENSE("GPL v2");