Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
2f8163ba | 12 | #include <linux/gpio.h> |
3d9edf09 VB |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
118150f2 | 18 | #include <linux/irq.h> |
9211ff31 | 19 | #include <linux/irqdomain.h> |
c770844c KS |
20 | #include <linux/module.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
118150f2 KS |
23 | #include <linux/platform_device.h> |
24 | #include <linux/platform_data/gpio-davinci.h> | |
3d9edf09 | 25 | |
c12f415a CC |
26 | struct davinci_gpio_regs { |
27 | u32 dir; | |
28 | u32 out_data; | |
29 | u32 set_data; | |
30 | u32 clr_data; | |
31 | u32 in_data; | |
32 | u32 set_rising; | |
33 | u32 clr_rising; | |
34 | u32 set_falling; | |
35 | u32 clr_falling; | |
36 | u32 intstat; | |
37 | }; | |
38 | ||
131a10a3 PA |
39 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
40 | ||
ba4a984e | 41 | #define chip2controller(chip) \ |
99e9e52d | 42 | container_of(chip, struct davinci_gpio_controller, chip) |
ba4a984e | 43 | |
b8d44293 | 44 | static void __iomem *gpio_base; |
3d9edf09 | 45 | |
118150f2 | 46 | static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) |
3d9edf09 | 47 | { |
c12f415a | 48 | void __iomem *ptr; |
c12f415a CC |
49 | |
50 | if (gpio < 32 * 1) | |
b8d44293 | 51 | ptr = gpio_base + 0x10; |
c12f415a | 52 | else if (gpio < 32 * 2) |
b8d44293 | 53 | ptr = gpio_base + 0x38; |
c12f415a | 54 | else if (gpio < 32 * 3) |
b8d44293 | 55 | ptr = gpio_base + 0x60; |
c12f415a | 56 | else if (gpio < 32 * 4) |
b8d44293 | 57 | ptr = gpio_base + 0x88; |
c12f415a | 58 | else if (gpio < 32 * 5) |
b8d44293 | 59 | ptr = gpio_base + 0xb0; |
c12f415a CC |
60 | else |
61 | ptr = NULL; | |
62 | return ptr; | |
3d9edf09 VB |
63 | } |
64 | ||
99e9e52d | 65 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
21ce873d | 66 | { |
99e9e52d | 67 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 68 | |
6845664a | 69 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
21ce873d KH |
70 | |
71 | return g; | |
72 | } | |
73 | ||
118150f2 | 74 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
75 | |
76 | /*--------------------------------------------------------------------------*/ | |
77 | ||
5b3a05ca | 78 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
79 | static inline int __davinci_direction(struct gpio_chip *chip, |
80 | unsigned offset, bool out, int value) | |
3d9edf09 | 81 | { |
99e9e52d CC |
82 | struct davinci_gpio_controller *d = chip2controller(chip); |
83 | struct davinci_gpio_regs __iomem *g = d->regs; | |
b27b6d03 | 84 | unsigned long flags; |
dce1115b | 85 | u32 temp; |
ba4a984e | 86 | u32 mask = 1 << offset; |
3d9edf09 | 87 | |
b27b6d03 | 88 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 89 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
90 | if (out) { |
91 | temp &= ~mask; | |
388291c3 | 92 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
93 | } else { |
94 | temp |= mask; | |
95 | } | |
388291c3 | 96 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 97 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 98 | |
dce1115b DB |
99 | return 0; |
100 | } | |
3d9edf09 | 101 | |
ba4a984e CC |
102 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
103 | { | |
104 | return __davinci_direction(chip, offset, false, 0); | |
105 | } | |
106 | ||
107 | static int | |
108 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
109 | { | |
110 | return __davinci_direction(chip, offset, true, value); | |
111 | } | |
112 | ||
3d9edf09 VB |
113 | /* |
114 | * Read the pin's value (works even if it's set up as output); | |
115 | * returns zero/nonzero. | |
116 | * | |
117 | * Note that changes are synched to the GPIO clock, so reading values back | |
118 | * right after you've set them may give old values. | |
119 | */ | |
dce1115b | 120 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 121 | { |
99e9e52d CC |
122 | struct davinci_gpio_controller *d = chip2controller(chip); |
123 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 124 | |
388291c3 | 125 | return (1 << offset) & readl_relaxed(&g->in_data); |
3d9edf09 | 126 | } |
3d9edf09 | 127 | |
dce1115b DB |
128 | /* |
129 | * Assuming the pin is muxed as a gpio output, set its output value. | |
130 | */ | |
131 | static void | |
132 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 133 | { |
99e9e52d CC |
134 | struct davinci_gpio_controller *d = chip2controller(chip); |
135 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 136 | |
388291c3 | 137 | writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); |
dce1115b DB |
138 | } |
139 | ||
c770844c KS |
140 | static struct davinci_gpio_platform_data * |
141 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
142 | { | |
143 | struct device_node *dn = pdev->dev.of_node; | |
144 | struct davinci_gpio_platform_data *pdata; | |
145 | int ret; | |
146 | u32 val; | |
147 | ||
148 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
149 | return pdev->dev.platform_data; | |
150 | ||
151 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
152 | if (!pdata) | |
153 | return NULL; | |
154 | ||
155 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
156 | if (ret) | |
157 | goto of_err; | |
158 | ||
159 | pdata->ngpio = val; | |
160 | ||
161 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
162 | if (ret) | |
163 | goto of_err; | |
164 | ||
165 | pdata->gpio_unbanked = val; | |
166 | ||
167 | return pdata; | |
168 | ||
169 | of_err: | |
170 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
171 | return NULL; | |
172 | } | |
173 | ||
118150f2 | 174 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b DB |
175 | { |
176 | int i, base; | |
a994955c | 177 | unsigned ngpio; |
118150f2 KS |
178 | struct davinci_gpio_controller *chips; |
179 | struct davinci_gpio_platform_data *pdata; | |
180 | struct davinci_gpio_regs __iomem *regs; | |
181 | struct device *dev = &pdev->dev; | |
182 | struct resource *res; | |
183 | ||
c770844c | 184 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
185 | if (!pdata) { |
186 | dev_err(dev, "No platform data found\n"); | |
187 | return -EINVAL; | |
188 | } | |
686b634a | 189 | |
c770844c KS |
190 | dev->platform_data = pdata; |
191 | ||
a994955c MG |
192 | /* |
193 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
194 | * and "ngpio" is one more than the largest zero-based |
195 | * bit index that's valid. | |
196 | */ | |
118150f2 | 197 | ngpio = pdata->ngpio; |
a994955c | 198 | if (ngpio == 0) { |
118150f2 | 199 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
200 | return -EINVAL; |
201 | } | |
202 | ||
c21d500b GS |
203 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
204 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 205 | |
118150f2 KS |
206 | chips = devm_kzalloc(dev, |
207 | ngpio * sizeof(struct davinci_gpio_controller), | |
208 | GFP_KERNEL); | |
209 | if (!chips) { | |
210 | dev_err(dev, "Memory allocation failed\n"); | |
b8d44293 | 211 | return -ENOMEM; |
118150f2 KS |
212 | } |
213 | ||
214 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
215 | if (!res) { | |
216 | dev_err(dev, "Invalid memory resource\n"); | |
217 | return -EBUSY; | |
218 | } | |
219 | ||
220 | gpio_base = devm_ioremap_resource(dev, res); | |
221 | if (IS_ERR(gpio_base)) | |
222 | return PTR_ERR(gpio_base); | |
b8d44293 | 223 | |
474dad54 | 224 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
dce1115b DB |
225 | chips[i].chip.label = "DaVinci"; |
226 | ||
227 | chips[i].chip.direction_input = davinci_direction_in; | |
228 | chips[i].chip.get = davinci_gpio_get; | |
229 | chips[i].chip.direction_output = davinci_direction_out; | |
230 | chips[i].chip.set = davinci_gpio_set; | |
231 | ||
232 | chips[i].chip.base = base; | |
474dad54 | 233 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
234 | if (chips[i].chip.ngpio > 32) |
235 | chips[i].chip.ngpio = 32; | |
236 | ||
c770844c KS |
237 | #ifdef CONFIG_OF_GPIO |
238 | chips[i].chip.of_node = dev->of_node; | |
239 | #endif | |
b27b6d03 CC |
240 | spin_lock_init(&chips[i].lock); |
241 | ||
c12f415a CC |
242 | regs = gpio2regs(base); |
243 | chips[i].regs = regs; | |
244 | chips[i].set_data = ®s->set_data; | |
245 | chips[i].clr_data = ®s->clr_data; | |
246 | chips[i].in_data = ®s->in_data; | |
dce1115b DB |
247 | |
248 | gpiochip_add(&chips[i].chip); | |
249 | } | |
3d9edf09 | 250 | |
118150f2 KS |
251 | platform_set_drvdata(pdev, chips); |
252 | davinci_gpio_irq_setup(pdev); | |
3d9edf09 VB |
253 | return 0; |
254 | } | |
3d9edf09 | 255 | |
dce1115b | 256 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
257 | /* |
258 | * We expect irqs will normally be set up as input pins, but they can also be | |
259 | * used as output pins ... which is convenient for testing. | |
260 | * | |
474dad54 | 261 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 262 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 263 | * |
474dad54 | 264 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
265 | * serve as EDMA event triggers. |
266 | */ | |
267 | ||
23265442 | 268 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 269 | { |
23265442 | 270 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 271 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
3d9edf09 | 272 | |
388291c3 LP |
273 | writel_relaxed(mask, &g->clr_falling); |
274 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
275 | } |
276 | ||
23265442 | 277 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 278 | { |
23265442 | 279 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 280 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
5093aec8 | 281 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 282 | |
df4aab46 DB |
283 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
284 | if (!status) | |
285 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
286 | ||
287 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 288 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 289 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 290 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
291 | } |
292 | ||
23265442 | 293 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 294 | { |
3d9edf09 VB |
295 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
296 | return -EINVAL; | |
297 | ||
3d9edf09 VB |
298 | return 0; |
299 | } | |
300 | ||
301 | static struct irq_chip gpio_irqchip = { | |
302 | .name = "GPIO", | |
23265442 LB |
303 | .irq_enable = gpio_irq_enable, |
304 | .irq_disable = gpio_irq_disable, | |
305 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 306 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
307 | }; |
308 | ||
309 | static void | |
310 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
311 | { | |
74164016 | 312 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 313 | u32 mask = 0xffff; |
f299bb95 | 314 | struct davinci_gpio_controller *d; |
3d9edf09 | 315 | |
f299bb95 IY |
316 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
317 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
74164016 | 318 | |
3d9edf09 VB |
319 | /* we only care about one bank */ |
320 | if (irq & 1) | |
321 | mask <<= 16; | |
322 | ||
323 | /* temporarily mask (level sensitive) parent IRQ */ | |
23265442 LB |
324 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
325 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
3d9edf09 VB |
326 | while (1) { |
327 | u32 status; | |
9211ff31 | 328 | int bit; |
3d9edf09 VB |
329 | |
330 | /* ack any irqs */ | |
388291c3 | 331 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
332 | if (!status) |
333 | break; | |
388291c3 | 334 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
335 | |
336 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 337 | |
3d9edf09 | 338 | while (status) { |
9211ff31 LP |
339 | bit = __ffs(status); |
340 | status &= ~BIT(bit); | |
341 | generic_handle_irq( | |
342 | irq_find_mapping(d->irq_domain, | |
343 | d->chip.base + bit)); | |
3d9edf09 VB |
344 | } |
345 | } | |
23265442 | 346 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
3d9edf09 VB |
347 | /* now it may re-trigger */ |
348 | } | |
349 | ||
7a36071e DB |
350 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
351 | { | |
99e9e52d | 352 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 353 | |
9211ff31 | 354 | return irq_create_mapping(d->irq_domain, d->chip.base + offset); |
7a36071e DB |
355 | } |
356 | ||
357 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
358 | { | |
118150f2 | 359 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 360 | |
131a10a3 PA |
361 | /* |
362 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
363 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
364 | */ | |
34af1ab4 | 365 | if (offset < d->gpio_unbanked) |
118150f2 | 366 | return d->gpio_irq + offset; |
7a36071e DB |
367 | else |
368 | return -ENODEV; | |
369 | } | |
370 | ||
ab2dde99 | 371 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 372 | { |
ab2dde99 SN |
373 | struct davinci_gpio_controller *d; |
374 | struct davinci_gpio_regs __iomem *g; | |
ab2dde99 SN |
375 | u32 mask; |
376 | ||
377 | d = (struct davinci_gpio_controller *)data->handler_data; | |
378 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
118150f2 | 379 | mask = __gpio_mask(data->irq - d->gpio_irq); |
7a36071e DB |
380 | |
381 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
382 | return -EINVAL; | |
383 | ||
388291c3 | 384 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 385 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 386 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
387 | ? &g->set_rising : &g->clr_rising); |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
9211ff31 LP |
392 | static int |
393 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
394 | irq_hw_number_t hw) | |
395 | { | |
396 | struct davinci_gpio_regs __iomem *g = gpio2regs(hw); | |
397 | ||
398 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
399 | "davinci_gpio"); | |
400 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
401 | irq_set_chip_data(irq, (__force void *)g); | |
402 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); | |
403 | set_irq_flags(irq, IRQF_VALID); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
409 | .map = davinci_gpio_irq_map, | |
410 | .xlate = irq_domain_xlate_onetwocell, | |
411 | }; | |
412 | ||
3d9edf09 | 413 | /* |
474dad54 DB |
414 | * NOTE: for suspend/resume, probably best to make a platform_device with |
415 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
416 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
417 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 418 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
419 | */ |
420 | ||
118150f2 | 421 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 VB |
422 | { |
423 | unsigned gpio, irq, bank; | |
424 | struct clk *clk; | |
474dad54 | 425 | u32 binten = 0; |
a994955c | 426 | unsigned ngpio, bank_irq; |
118150f2 KS |
427 | struct device *dev = &pdev->dev; |
428 | struct resource *res; | |
429 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); | |
430 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
431 | struct davinci_gpio_regs __iomem *g; | |
9211ff31 | 432 | struct irq_domain *irq_domain; |
a994955c | 433 | |
118150f2 KS |
434 | ngpio = pdata->ngpio; |
435 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
436 | if (!res) { | |
437 | dev_err(dev, "Invalid IRQ resource\n"); | |
438 | return -EBUSY; | |
439 | } | |
474dad54 | 440 | |
118150f2 KS |
441 | bank_irq = res->start; |
442 | ||
443 | if (!bank_irq) { | |
444 | dev_err(dev, "Invalid IRQ resource\n"); | |
445 | return -ENODEV; | |
474dad54 | 446 | } |
3d9edf09 | 447 | |
118150f2 | 448 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 VB |
449 | if (IS_ERR(clk)) { |
450 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
451 | PTR_ERR(clk)); | |
474dad54 | 452 | return PTR_ERR(clk); |
3d9edf09 | 453 | } |
ce6b658d | 454 | clk_prepare_enable(clk); |
3d9edf09 | 455 | |
9211ff31 LP |
456 | irq = irq_alloc_descs(-1, 0, ngpio, 0); |
457 | if (irq < 0) { | |
458 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
459 | return irq; | |
460 | } | |
461 | ||
462 | irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, | |
463 | &davinci_gpio_irq_ops, | |
464 | chips); | |
465 | if (!irq_domain) { | |
466 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
467 | return -ENODEV; | |
468 | } | |
469 | ||
131a10a3 PA |
470 | /* |
471 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
472 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
473 | * IRQs, while the others use banked IRQs, would need some setup | |
474 | * tweaks to recognize hardware which can do that. | |
475 | */ | |
476 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
477 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
9211ff31 LP |
478 | if (!pdata->gpio_unbanked) |
479 | chips[bank].irq_domain = irq_domain; | |
7a36071e DB |
480 | } |
481 | ||
482 | /* | |
483 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
484 | * controller only handling trigger modes. We currently assume no | |
485 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
486 | */ | |
118150f2 | 487 | if (pdata->gpio_unbanked) { |
81b279d8 | 488 | static struct irq_chip_type gpio_unbanked; |
7a36071e DB |
489 | |
490 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
491 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
34af1ab4 LP |
492 | chips[0].gpio_irq = bank_irq; |
493 | chips[0].gpio_unbanked = pdata->gpio_unbanked; | |
7a36071e DB |
494 | binten = BIT(0); |
495 | ||
496 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
497 | irq = bank_irq; | |
81b279d8 SN |
498 | gpio_unbanked = *container_of(irq_get_chip(irq), |
499 | struct irq_chip_type, chip); | |
500 | gpio_unbanked.chip.name = "GPIO-AINTC"; | |
501 | gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
502 | |
503 | /* default trigger: both edges */ | |
99e9e52d | 504 | g = gpio2regs(0); |
388291c3 LP |
505 | writel_relaxed(~0, &g->set_falling); |
506 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
507 | |
508 | /* set the direct IRQs up to use that irqchip */ | |
118150f2 | 509 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
81b279d8 | 510 | irq_set_chip(irq, &gpio_unbanked.chip); |
ab2dde99 | 511 | irq_set_handler_data(irq, &chips[gpio / 32]); |
5093aec8 | 512 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
7a36071e DB |
513 | } |
514 | ||
515 | goto done; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
520 | * then chain through our own handler. | |
521 | */ | |
9211ff31 | 522 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
7a36071e | 523 | /* disabled by default, enabled only as needed */ |
99e9e52d | 524 | g = gpio2regs(gpio); |
388291c3 LP |
525 | writel_relaxed(~0, &g->clr_falling); |
526 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 VB |
527 | |
528 | /* set up all irqs in this bank */ | |
6845664a | 529 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
f299bb95 IY |
530 | |
531 | /* | |
532 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
533 | * gpio irqs. Pass the irq bank's corresponding controller to | |
534 | * the chained irq handler. | |
535 | */ | |
536 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); | |
3d9edf09 | 537 | |
474dad54 | 538 | binten |= BIT(bank); |
3d9edf09 VB |
539 | } |
540 | ||
7a36071e | 541 | done: |
131a10a3 PA |
542 | /* |
543 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
544 | * bits be set/cleared dynamically. |
545 | */ | |
388291c3 | 546 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 547 | |
3d9edf09 VB |
548 | return 0; |
549 | } | |
118150f2 | 550 | |
c770844c KS |
551 | #if IS_ENABLED(CONFIG_OF) |
552 | static const struct of_device_id davinci_gpio_ids[] = { | |
553 | { .compatible = "ti,dm6441-gpio", }, | |
554 | { /* sentinel */ }, | |
555 | }; | |
556 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
557 | #endif | |
558 | ||
118150f2 KS |
559 | static struct platform_driver davinci_gpio_driver = { |
560 | .probe = davinci_gpio_probe, | |
561 | .driver = { | |
c770844c KS |
562 | .name = "davinci_gpio", |
563 | .owner = THIS_MODULE, | |
564 | .of_match_table = of_match_ptr(davinci_gpio_ids), | |
118150f2 KS |
565 | }, |
566 | }; | |
567 | ||
568 | /** | |
569 | * GPIO driver registration needs to be done before machine_init functions | |
570 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
571 | */ | |
572 | static int __init davinci_gpio_drv_reg(void) | |
573 | { | |
574 | return platform_driver_register(&davinci_gpio_driver); | |
575 | } | |
576 | postcore_initcall(davinci_gpio_drv_reg); |