[deliverable/linux.git] / drivers / gpio / gpio-dln2.c

/*
 * Driver for the Diolan DLN-2 USB-GPIO adapter
 *
 * Copyright (c) 2014 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation, version 2.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/mfd/dln2.h>

#define DLN2_GPIO_ID			0x01

#define DLN2_GPIO_GET_PIN_COUNT		DLN2_CMD(0x01, DLN2_GPIO_ID)
#define DLN2_GPIO_SET_DEBOUNCE		DLN2_CMD(0x04, DLN2_GPIO_ID)
#define DLN2_GPIO_GET_DEBOUNCE		DLN2_CMD(0x05, DLN2_GPIO_ID)
#define DLN2_GPIO_PORT_GET_VAL		DLN2_CMD(0x06, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_VAL		DLN2_CMD(0x0B, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_OUT_VAL	DLN2_CMD(0x0C, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_OUT_VAL	DLN2_CMD(0x0D, DLN2_GPIO_ID)
#define DLN2_GPIO_CONDITION_MET_EV	DLN2_CMD(0x0F, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_ENABLE		DLN2_CMD(0x10, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_DISABLE		DLN2_CMD(0x11, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_DIRECTION	DLN2_CMD(0x13, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_DIRECTION	DLN2_CMD(0x14, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_EVENT_CFG	DLN2_CMD(0x1E, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_EVENT_CFG	DLN2_CMD(0x1F, DLN2_GPIO_ID)

#define DLN2_GPIO_EVENT_NONE		0
#define DLN2_GPIO_EVENT_CHANGE		1
#define DLN2_GPIO_EVENT_LVL_HIGH	2
#define DLN2_GPIO_EVENT_LVL_LOW		3
#define DLN2_GPIO_EVENT_CHANGE_RISING	0x11
#define DLN2_GPIO_EVENT_CHANGE_FALLING  0x21
#define DLN2_GPIO_EVENT_MASK		0x0F

#define DLN2_GPIO_MAX_PINS 32

struct dln2_irq_work {
	struct work_struct work;
	struct dln2_gpio *dln2;
	int pin;
	int type;
};

struct dln2_gpio {
	struct platform_device *pdev;
	struct gpio_chip gpio;

	/*
	 * Cache pin direction to save us one transfer, since the hardware has
	 * separate commands to read the in and out values.
	 */
	DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);

	DECLARE_BITMAP(irqs_masked, DLN2_GPIO_MAX_PINS);
	DECLARE_BITMAP(irqs_enabled, DLN2_GPIO_MAX_PINS);
	DECLARE_BITMAP(irqs_pending, DLN2_GPIO_MAX_PINS);
	struct dln2_irq_work *irq_work;
};

struct dln2_gpio_pin {
	__le16 pin;
};

struct dln2_gpio_pin_val {
	__le16 pin __packed;
	u8 value;
};

static int dln2_gpio_get_pin_count(struct platform_device *pdev)
{
	int ret;
	__le16 count;
	int len = sizeof(count);

	ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
	if (ret < 0)
		return ret;
	if (len < sizeof(count))
		return -EPROTO;

	return le16_to_cpu(count);
}

static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
{
	struct dln2_gpio_pin req = {
		.pin = cpu_to_le16(pin),
	};

	return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
}

static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
{
	int ret;
	struct dln2_gpio_pin req = {
		.pin = cpu_to_le16(pin),
	};
	struct dln2_gpio_pin_val rsp;
	int len = sizeof(rsp);

	ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
	if (ret < 0)
		return ret;
	if (len < sizeof(rsp) || req.pin != rsp.pin)
		return -EPROTO;

	return rsp.value;
}

static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
{
	int ret;

	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
	if (ret < 0)
		return ret;
	return !!ret;
}

static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
{
	int ret;

	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
	if (ret < 0)
		return ret;
	return !!ret;
}

static void dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
				      unsigned int pin, int value)
{
	struct dln2_gpio_pin_val req = {
		.pin = cpu_to_le16(pin),
		.value = value,
	};

	dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
			 sizeof(req));
}

#define DLN2_GPIO_DIRECTION_IN		0
#define DLN2_GPIO_DIRECTION_OUT		1

static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	struct dln2_gpio_pin req = {
		.pin = cpu_to_le16(offset),
	};
	struct dln2_gpio_pin_val rsp;
	int len = sizeof(rsp);
	int ret;

	ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
	if (ret < 0)
		return ret;

	/* cache the pin direction */
	ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
			    &req, sizeof(req), &rsp, &len);
	if (ret < 0)
		return ret;
	if (len < sizeof(rsp) || req.pin != rsp.pin) {
		ret = -EPROTO;
		goto out_disable;
	}

	switch (rsp.value) {
	case DLN2_GPIO_DIRECTION_IN:
		clear_bit(offset, dln2->output_enabled);
		return 0;
	case DLN2_GPIO_DIRECTION_OUT:
		set_bit(offset, dln2->output_enabled);
		return 0;
	default:
		ret = -EPROTO;
		goto out_disable;
	}

out_disable:
	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
	return ret;
}

static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);

	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
}

static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);

	if (test_bit(offset, dln2->output_enabled))
		return GPIOF_DIR_OUT;

	return GPIOF_DIR_IN;
}

static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	int dir;

	dir = dln2_gpio_get_direction(chip, offset);
	if (dir < 0)
		return dir;

	if (dir == GPIOF_DIR_IN)
		return dln2_gpio_pin_get_in_val(dln2, offset);

	return dln2_gpio_pin_get_out_val(dln2, offset);
}

static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);

	dln2_gpio_pin_set_out_val(dln2, offset, value);
}

static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
				   unsigned dir)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	struct dln2_gpio_pin_val req = {
		.pin = cpu_to_le16(offset),
		.value = dir,
	};
	int ret;

	ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
			       &req, sizeof(req));
	if (ret < 0)
		return ret;

	if (dir == DLN2_GPIO_DIRECTION_OUT)
		set_bit(offset, dln2->output_enabled);
	else
		clear_bit(offset, dln2->output_enabled);

	return ret;
}

static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
}

static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
}

static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
				  unsigned debounce)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	__le32 duration = cpu_to_le32(debounce);

	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
				&duration, sizeof(duration));
}

static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
				   unsigned type, unsigned period)
{
	struct {
		__le16 pin;
		u8 type;
		__le16 period;
	} __packed req = {
		.pin = cpu_to_le16(pin),
		.type = type,
		.period = cpu_to_le16(period),
	};

	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
				&req, sizeof(req));
}

static void dln2_irq_work(struct work_struct *w)
{
	struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
	struct dln2_gpio *dln2 = iw->dln2;
	u8 type = iw->type & DLN2_GPIO_EVENT_MASK;

	if (test_bit(iw->pin, dln2->irqs_enabled))
		dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
	else
		dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
}

static void dln2_irq_enable(struct irq_data *irqd)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	set_bit(pin, dln2->irqs_enabled);
	schedule_work(&dln2->irq_work[pin].work);
}

static void dln2_irq_disable(struct irq_data *irqd)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	clear_bit(pin, dln2->irqs_enabled);
	schedule_work(&dln2->irq_work[pin].work);
}

static void dln2_irq_mask(struct irq_data *irqd)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	set_bit(pin, dln2->irqs_masked);
}

static void dln2_irq_unmask(struct irq_data *irqd)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	struct device *dev = dln2->gpio.dev;
	int pin = irqd_to_hwirq(irqd);

	if (test_and_clear_bit(pin, dln2->irqs_pending)) {
		int irq;

		irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
		if (!irq) {
			dev_err(dev, "pin %d not mapped to IRQ\n", pin);
			return;
		}

		generic_handle_irq(irq);
	}
}

static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip dln2_gpio_irqchip = {
	.name = "dln2-irq",
	.irq_enable = dln2_irq_enable,
	.irq_disable = dln2_irq_disable,
	.irq_mask = dln2_irq_mask,
	.irq_unmask = dln2_irq_unmask,
	.irq_set_type = dln2_irq_set_type,
};

static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
			    const void *data, int len)
{
	int pin, irq;
	const struct {
		__le16 count;
		__u8 type;
		__le16 pin;
		__u8 value;
	} __packed *event = data;
	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);

	if (len < sizeof(*event)) {
		dev_err(dln2->gpio.dev, "short event message\n");
		return;
	}

	pin = le16_to_cpu(event->pin);
	if (pin >= dln2->gpio.ngpio) {
		dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
		return;
	}

	irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
	if (!irq) {
		dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
		return;
	}

	if (!test_bit(pin, dln2->irqs_enabled))
		return;
	if (test_bit(pin, dln2->irqs_masked)) {
		set_bit(pin, dln2->irqs_pending);
		return;
	}

	switch (dln2->irq_work[pin].type) {
	case DLN2_GPIO_EVENT_CHANGE_RISING:
		if (event->value)
			generic_handle_irq(irq);
		break;
	case DLN2_GPIO_EVENT_CHANGE_FALLING:
		if (!event->value)
			generic_handle_irq(irq);
		break;
	default:
		generic_handle_irq(irq);
	}
}

static int dln2_gpio_probe(struct platform_device *pdev)
{
	struct dln2_gpio *dln2;
	struct device *dev = &pdev->dev;
	int pins;
	int i, ret;

	pins = dln2_gpio_get_pin_count(pdev);
	if (pins < 0) {
		dev_err(dev, "failed to get pin count: %d\n", pins);
		return pins;
	}
	if (pins > DLN2_GPIO_MAX_PINS) {
		pins = DLN2_GPIO_MAX_PINS;
		dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
	}

	dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
	if (!dln2)
		return -ENOMEM;

	dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
				      sizeof(struct dln2_irq_work), GFP_KERNEL);
	if (!dln2->irq_work)
		return -ENOMEM;
	for (i = 0; i < pins; i++) {
		INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
		dln2->irq_work[i].pin = i;
		dln2->irq_work[i].dln2 = dln2;
	}

	dln2->pdev = pdev;

	dln2->gpio.label = "dln2";
	dln2->gpio.dev = dev;
	dln2->gpio.owner = THIS_MODULE;
	dln2->gpio.base = -1;
	dln2->gpio.ngpio = pins;
	dln2->gpio.exported = true;
	dln2->gpio.can_sleep = true;
	dln2->gpio.irq_not_threaded = true;
	dln2->gpio.set = dln2_gpio_set;
	dln2->gpio.get = dln2_gpio_get;
	dln2->gpio.request = dln2_gpio_request;
	dln2->gpio.free = dln2_gpio_free;
	dln2->gpio.get_direction = dln2_gpio_get_direction;
	dln2->gpio.direction_input = dln2_gpio_direction_input;
	dln2->gpio.direction_output = dln2_gpio_direction_output;
	dln2->gpio.set_debounce = dln2_gpio_set_debounce;

	platform_set_drvdata(pdev, dln2);

	ret = gpiochip_add(&dln2->gpio);
	if (ret < 0) {
		dev_err(dev, "failed to add gpio chip: %d\n", ret);
		goto out;
	}

	ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
				   handle_simple_irq, IRQ_TYPE_NONE);
	if (ret < 0) {
		dev_err(dev, "failed to add irq chip: %d\n", ret);
		goto out_gpiochip_remove;
	}

	ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
				     dln2_gpio_event);
	if (ret) {
		dev_err(dev, "failed to register event cb: %d\n", ret);
		goto out_gpiochip_remove;
	}

	return 0;

out_gpiochip_remove:
	gpiochip_remove(&dln2->gpio);
out:
	return ret;
}

static int dln2_gpio_remove(struct platform_device *pdev)
{
	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
	int i;

	dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
	for (i = 0; i < dln2->gpio.ngpio; i++)
		flush_work(&dln2->irq_work[i].work);
	gpiochip_remove(&dln2->gpio);

	return 0;
}

static struct platform_driver dln2_gpio_driver = {
	.driver.name	= "dln2-gpio",
	.probe		= dln2_gpio_probe,
	.remove		= dln2_gpio_remove,
};

module_platform_driver(dln2_gpio_driver);

MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dln2-gpio");
Commit	Line	Data
6732127f DB	1	/*
	2	* Driver for the Diolan DLN-2 USB-GPIO adapter
	3	*
	4	* Copyright (c) 2014 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation, version 2.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/slab.h>
	14	#include <linux/types.h>
	15	#include <linux/irqdomain.h>
	16	#include <linux/irq.h>
	17	#include <linux/irqchip/chained_irq.h>
	18	#include <linux/gpio.h>
	19	#include <linux/gpio/driver.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/mfd/dln2.h>
	22
	23	#define DLN2_GPIO_ID 0x01
	24
	25	#define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
	26	#define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
	27	#define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
	28	#define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
	29	#define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
	30	#define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
	31	#define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
	32	#define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
	33	#define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
	34	#define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
	35	#define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
	36	#define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
	37	#define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
	38	#define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
	39
	40	#define DLN2_GPIO_EVENT_NONE 0
	41	#define DLN2_GPIO_EVENT_CHANGE 1
	42	#define DLN2_GPIO_EVENT_LVL_HIGH 2
	43	#define DLN2_GPIO_EVENT_LVL_LOW 3
	44	#define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
	45	#define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
	46	#define DLN2_GPIO_EVENT_MASK 0x0F
	47
	48	#define DLN2_GPIO_MAX_PINS 32
	49
	50	struct dln2_irq_work {
	51	struct work_struct work;
	52	struct dln2_gpio *dln2;
	53	int pin;
	54	int type;
	55	};
	56
	57	struct dln2_gpio {
	58	struct platform_device *pdev;
	59	struct gpio_chip gpio;
	60
	61	/*
	62	* Cache pin direction to save us one transfer, since the hardware has
	63	* separate commands to read the in and out values.
	64	*/
65	DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
66
67	DECLARE_BITMAP(irqs_masked, DLN2_GPIO_MAX_PINS);
68	DECLARE_BITMAP(irqs_enabled, DLN2_GPIO_MAX_PINS);
69	DECLARE_BITMAP(irqs_pending, DLN2_GPIO_MAX_PINS);
70	struct dln2_irq_work *irq_work;
71	};
72
73	struct dln2_gpio_pin {
74	__le16 pin;
75	};
76
77	struct dln2_gpio_pin_val {
78	__le16 pin __packed;
79	u8 value;
80	};
81
82	static int dln2_gpio_get_pin_count(struct platform_device *pdev)
83	{
84	int ret;
85	__le16 count;
86	int len = sizeof(count);
87
88	ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
89	if (ret < 0)
90	return ret;
91	if (len < sizeof(count))
92	return -EPROTO;
93
94	return le16_to_cpu(count);
95	}
96
97	static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
98	{
99	struct dln2_gpio_pin req = {
100	.pin = cpu_to_le16(pin),
101	};
102
103	return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
104	}
105
106	static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
107	{
108	int ret;
109	struct dln2_gpio_pin req = {
110	.pin = cpu_to_le16(pin),
111	};
112	struct dln2_gpio_pin_val rsp;
113	int len = sizeof(rsp);
114
115	ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
116	if (ret < 0)
117	return ret;
118	if (len < sizeof(rsp) \|\| req.pin != rsp.pin)
119	return -EPROTO;
120
121	return rsp.value;
122	}
123
124	static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
125	{
126	int ret;
127
128	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
129	if (ret < 0)
130	return ret;
131	return !!ret;
132	}
133
134	static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
135	{
136	int ret;
137
138	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
139	if (ret < 0)
140	return ret;
141	return !!ret;
142	}
143
144	static void dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
145	unsigned int pin, int value)
146	{
147	struct dln2_gpio_pin_val req = {
148	.pin = cpu_to_le16(pin),
149	.value = value,
150	};
151
152	dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
153	sizeof(req));
154	}
155
156	#define DLN2_GPIO_DIRECTION_IN 0
157	#define DLN2_GPIO_DIRECTION_OUT 1
158
159	static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
160	{
161	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
162	struct dln2_gpio_pin req = {
163	.pin = cpu_to_le16(offset),
164	};
165	struct dln2_gpio_pin_val rsp;
166	int len = sizeof(rsp);
167	int ret;
168
169	ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
170	if (ret < 0)
171	return ret;
172
173	/* cache the pin direction */
174	ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
175	&req, sizeof(req), &rsp, &len);
176	if (ret < 0)
177	return ret;
178	if (len < sizeof(rsp) \|\| req.pin != rsp.pin) {
179	ret = -EPROTO;
180	goto out_disable;
181	}
182
183	switch (rsp.value) {
184	case DLN2_GPIO_DIRECTION_IN:
185	clear_bit(offset, dln2->output_enabled);
186	return 0;
187	case DLN2_GPIO_DIRECTION_OUT:
188	set_bit(offset, dln2->output_enabled);
189	return 0;
190	default:
191	ret = -EPROTO;
192	goto out_disable;
193	}
194
195	out_disable:
196	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
197	return ret;
198	}
199
200	static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
201	{
202	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
203
204	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
205	}
206
207	static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
208	{
209	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
210
211	if (test_bit(offset, dln2->output_enabled))
212	return GPIOF_DIR_OUT;
213
214	return GPIOF_DIR_IN;
215	}
216
217	static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
218	{
219	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
220	int dir;
221
222	dir = dln2_gpio_get_direction(chip, offset);
223	if (dir < 0)
224	return dir;
225
226	if (dir == GPIOF_DIR_IN)
227	return dln2_gpio_pin_get_in_val(dln2, offset);
228
229	return dln2_gpio_pin_get_out_val(dln2, offset);
230	}
231
232	static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
233	{
234	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
235
236	dln2_gpio_pin_set_out_val(dln2, offset, value);
237	}
238
239	static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
240	unsigned dir)
241	{
242	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
243	struct dln2_gpio_pin_val req = {
244	.pin = cpu_to_le16(offset),
245	.value = dir,
246	};
247	int ret;
248
249	ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
250	&req, sizeof(req));
251	if (ret < 0)
252	return ret;
253
254	if (dir == DLN2_GPIO_DIRECTION_OUT)
255	set_bit(offset, dln2->output_enabled);
256	else
257	clear_bit(offset, dln2->output_enabled);
258
259	return ret;
260	}
261
262	static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
263	{
264	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
265	}
266
267	static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
268	int value)
269	{
270	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
271	}
272
273	static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
274	unsigned debounce)
275	{
276	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
277	__le32 duration = cpu_to_le32(debounce);
278
279	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
280	&duration, sizeof(duration));
281	}
282
283	static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
284	unsigned type, unsigned period)
285	{
286	struct {
287	__le16 pin;
288	u8 type;
289	__le16 period;
290	} __packed req = {
291	.pin = cpu_to_le16(pin),
292	.type = type,
293	.period = cpu_to_le16(period),
294	};
295
296	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
297	&req, sizeof(req));
298	}
299
300	static void dln2_irq_work(struct work_struct *w)
301	{
302	struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
303	struct dln2_gpio *dln2 = iw->dln2;
304	u8 type = iw->type & DLN2_GPIO_EVENT_MASK;
305
306	if (test_bit(iw->pin, dln2->irqs_enabled))
307	dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
308	else
309	dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
310	}
311
312	static void dln2_irq_enable(struct irq_data *irqd)
313	{
314	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
315	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
316	int pin = irqd_to_hwirq(irqd);
317
318	set_bit(pin, dln2->irqs_enabled);
319	schedule_work(&dln2->irq_work[pin].work);
320	}
321
322	static void dln2_irq_disable(struct irq_data *irqd)
323	{
324	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
325	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
326	int pin = irqd_to_hwirq(irqd);
327
328	clear_bit(pin, dln2->irqs_enabled);
329	schedule_work(&dln2->irq_work[pin].work);
330	}
331
332	static void dln2_irq_mask(struct irq_data *irqd)
333	{
334	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
335	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
336	int pin = irqd_to_hwirq(irqd);
337
338	set_bit(pin, dln2->irqs_masked);
339	}
340
341	static void dln2_irq_unmask(struct irq_data *irqd)
342	{
343	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
344	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
345	struct device *dev = dln2->gpio.dev;
346	int pin = irqd_to_hwirq(irqd);
347
348	if (test_and_clear_bit(pin, dln2->irqs_pending)) {
349	int irq;
350
351	irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
352	if (!irq) {
353	dev_err(dev, "pin %d not mapped to IRQ\n", pin);
354	return;
355	}
356
357	generic_handle_irq(irq);
358	}
359	}
360
361	static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
362	{
363	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
364	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
365	int pin = irqd_to_hwirq(irqd);
366
367	switch (type) {
368	case IRQ_TYPE_LEVEL_HIGH:
369	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
370	break;
371	case IRQ_TYPE_LEVEL_LOW:
372	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
373	break;
374	case IRQ_TYPE_EDGE_BOTH:
375	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
376	break;
377	case IRQ_TYPE_EDGE_RISING:
378	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
379	break;
380	case IRQ_TYPE_EDGE_FALLING:
381	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
382	break;
383	default:
384	return -EINVAL;
385	}
386
387	return 0;
388	}
389
390	static struct irq_chip dln2_gpio_irqchip = {
391	.name = "dln2-irq",
392	.irq_enable = dln2_irq_enable,
393	.irq_disable = dln2_irq_disable,
394	.irq_mask = dln2_irq_mask,
395	.irq_unmask = dln2_irq_unmask,
396	.irq_set_type = dln2_irq_set_type,
397	};
398
399	static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
400	const void *data, int len)
401	{
402	int pin, irq;
403	const struct {
404	__le16 count;
405	__u8 type;
406	__le16 pin;
407	__u8 value;
408	} __packed *event = data;
409	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
410
411	if (len < sizeof(*event)) {
412	dev_err(dln2->gpio.dev, "short event message\n");
413	return;
414	}
415
416	pin = le16_to_cpu(event->pin);
417	if (pin >= dln2->gpio.ngpio) {
418	dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
419	return;
420	}
421
422	irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
423	if (!irq) {
424	dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
425	return;
426	}
427
428	if (!test_bit(pin, dln2->irqs_enabled))
429	return;
430	if (test_bit(pin, dln2->irqs_masked)) {
431	set_bit(pin, dln2->irqs_pending);
432	return;
433	}
434
435	switch (dln2->irq_work[pin].type) {
436	case DLN2_GPIO_EVENT_CHANGE_RISING:
437	if (event->value)
438	generic_handle_irq(irq);
439	break;
440	case DLN2_GPIO_EVENT_CHANGE_FALLING:
441	if (!event->value)
442	generic_handle_irq(irq);
443	break;
444	default:
445	generic_handle_irq(irq);
446	}
447	}
448
449	static int dln2_gpio_probe(struct platform_device *pdev)
450	{
451	struct dln2_gpio *dln2;
452	struct device *dev = &pdev->dev;
453	int pins;
454	int i, ret;
455
456	pins = dln2_gpio_get_pin_count(pdev);
457	if (pins < 0) {
458	dev_err(dev, "failed to get pin count: %d\n", pins);
459	return pins;
460	}
461	if (pins > DLN2_GPIO_MAX_PINS) {
462	pins = DLN2_GPIO_MAX_PINS;
463	dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
464	}
465
466	dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
467	if (!dln2)
468	return -ENOMEM;
469
470	dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
471	sizeof(struct dln2_irq_work), GFP_KERNEL);
472	if (!dln2->irq_work)
473	return -ENOMEM;
474	for (i = 0; i < pins; i++) {
475	INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
476	dln2->irq_work[i].pin = i;
477	dln2->irq_work[i].dln2 = dln2;
478	}
479
480	dln2->pdev = pdev;
481
482	dln2->gpio.label = "dln2";
483	dln2->gpio.dev = dev;
484	dln2->gpio.owner = THIS_MODULE;
485	dln2->gpio.base = -1;
486	dln2->gpio.ngpio = pins;
487	dln2->gpio.exported = true;
488	dln2->gpio.can_sleep = true;
489	dln2->gpio.irq_not_threaded = true;
490	dln2->gpio.set = dln2_gpio_set;
491	dln2->gpio.get = dln2_gpio_get;
492	dln2->gpio.request = dln2_gpio_request;
493	dln2->gpio.free = dln2_gpio_free;
494	dln2->gpio.get_direction = dln2_gpio_get_direction;
495	dln2->gpio.direction_input = dln2_gpio_direction_input;
496	dln2->gpio.direction_output = dln2_gpio_direction_output;
497	dln2->gpio.set_debounce = dln2_gpio_set_debounce;
498
499	platform_set_drvdata(pdev, dln2);
500
501	ret = gpiochip_add(&dln2->gpio);
502	if (ret < 0) {
503	dev_err(dev, "failed to add gpio chip: %d\n", ret);
504	goto out;
505	}
506
507	ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
508	handle_simple_irq, IRQ_TYPE_NONE);
509	if (ret < 0) {
510	dev_err(dev, "failed to add irq chip: %d\n", ret);
511	goto out_gpiochip_remove;
512	}
513
514	ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
515	dln2_gpio_event);
516	if (ret) {
517	dev_err(dev, "failed to register event cb: %d\n", ret);
518	goto out_gpiochip_remove;
519	}
520
521	return 0;
522
523	out_gpiochip_remove:
524	gpiochip_remove(&dln2->gpio);
525	out:
526	return ret;
527	}
528
529	static int dln2_gpio_remove(struct platform_device *pdev)
530	{
531	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
532	int i;
533
534	dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
535	for (i = 0; i < dln2->gpio.ngpio; i++)
536	flush_work(&dln2->irq_work[i].work);
537	gpiochip_remove(&dln2->gpio);
538
539	return 0;
540	}
541
542	static struct platform_driver dln2_gpio_driver = {
543	.driver.name = "dln2-gpio",
544	.probe = dln2_gpio_probe,
545	.remove = dln2_gpio_remove,
546	};
547
548	module_platform_driver(dln2_gpio_driver);
549
550	MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
551	MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
552	MODULE_LICENSE("GPL v2");
553	MODULE_ALIAS("platform:dln2-gpio");