Commit | Line | Data |
---|---|---|
6c17aa01 | 1 | /* |
7e960363 | 2 | * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882 and F71889 |
6c17aa01 SG |
3 | * |
4 | * Copyright (C) 2010-2013 LaCie | |
5 | * | |
6 | * Author: Simon Guinot <simon.guinot@sequanux.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/gpio.h> | |
19 | ||
20 | #define DRVNAME "gpio-f7188x" | |
21 | ||
22 | /* | |
23 | * Super-I/O registers | |
24 | */ | |
25 | #define SIO_LDSEL 0x07 /* Logical device select */ | |
26 | #define SIO_DEVID 0x20 /* Device ID (2 bytes) */ | |
27 | #define SIO_DEVREV 0x22 /* Device revision */ | |
28 | #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */ | |
29 | ||
30 | #define SIO_LD_GPIO 0x06 /* GPIO logical device */ | |
31 | #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */ | |
32 | #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ | |
33 | ||
34 | #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */ | |
24ccef35 | 35 | #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */ |
7e960363 | 36 | #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */ |
6c17aa01 SG |
37 | #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */ |
38 | #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */ | |
39 | ||
7e960363 | 40 | enum chips { f71869, f71869a, f71882fg, f71889f }; |
6c17aa01 SG |
41 | |
42 | static const char * const f7188x_names[] = { | |
24ccef35 | 43 | "f71869", |
7e960363 | 44 | "f71869a", |
6c17aa01 SG |
45 | "f71882fg", |
46 | "f71889f", | |
47 | }; | |
48 | ||
49 | struct f7188x_sio { | |
50 | int addr; | |
51 | enum chips type; | |
52 | }; | |
53 | ||
54 | struct f7188x_gpio_bank { | |
55 | struct gpio_chip chip; | |
56 | unsigned int regbase; | |
57 | struct f7188x_gpio_data *data; | |
58 | }; | |
59 | ||
60 | struct f7188x_gpio_data { | |
61 | struct f7188x_sio *sio; | |
62 | int nr_bank; | |
63 | struct f7188x_gpio_bank *bank; | |
64 | }; | |
65 | ||
66 | /* | |
67 | * Super-I/O functions. | |
68 | */ | |
69 | ||
70 | static inline int superio_inb(int base, int reg) | |
71 | { | |
72 | outb(reg, base); | |
73 | return inb(base + 1); | |
74 | } | |
75 | ||
76 | static int superio_inw(int base, int reg) | |
77 | { | |
78 | int val; | |
79 | ||
80 | outb(reg++, base); | |
81 | val = inb(base + 1) << 8; | |
82 | outb(reg, base); | |
83 | val |= inb(base + 1); | |
84 | ||
85 | return val; | |
86 | } | |
87 | ||
88 | static inline void superio_outb(int base, int reg, int val) | |
89 | { | |
90 | outb(reg, base); | |
91 | outb(val, base + 1); | |
92 | } | |
93 | ||
94 | static inline int superio_enter(int base) | |
95 | { | |
96 | /* Don't step on other drivers' I/O space by accident. */ | |
97 | if (!request_muxed_region(base, 2, DRVNAME)) { | |
98 | pr_err(DRVNAME "I/O address 0x%04x already in use\n", base); | |
99 | return -EBUSY; | |
100 | } | |
101 | ||
102 | /* According to the datasheet the key must be send twice. */ | |
103 | outb(SIO_UNLOCK_KEY, base); | |
104 | outb(SIO_UNLOCK_KEY, base); | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
109 | static inline void superio_select(int base, int ld) | |
110 | { | |
111 | outb(SIO_LDSEL, base); | |
112 | outb(ld, base + 1); | |
113 | } | |
114 | ||
115 | static inline void superio_exit(int base) | |
116 | { | |
117 | outb(SIO_LOCK_KEY, base); | |
118 | release_region(base, 2); | |
119 | } | |
120 | ||
121 | /* | |
122 | * GPIO chip. | |
123 | */ | |
124 | ||
125 | static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset); | |
126 | static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset); | |
127 | static int f7188x_gpio_direction_out(struct gpio_chip *chip, | |
128 | unsigned offset, int value); | |
129 | static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value); | |
130 | ||
131 | #define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \ | |
132 | { \ | |
133 | .chip = { \ | |
134 | .label = DRVNAME, \ | |
135 | .owner = THIS_MODULE, \ | |
136 | .direction_input = f7188x_gpio_direction_in, \ | |
137 | .get = f7188x_gpio_get, \ | |
138 | .direction_output = f7188x_gpio_direction_out, \ | |
139 | .set = f7188x_gpio_set, \ | |
140 | .base = _base, \ | |
141 | .ngpio = _ngpio, \ | |
aeccc1b4 | 142 | .can_sleep = true, \ |
6c17aa01 SG |
143 | }, \ |
144 | .regbase = _regbase, \ | |
145 | } | |
146 | ||
147 | #define gpio_dir(base) (base + 0) | |
148 | #define gpio_data_out(base) (base + 1) | |
149 | #define gpio_data_in(base) (base + 2) | |
150 | /* Output mode register (0:open drain 1:push-pull). */ | |
151 | #define gpio_out_mode(base) (base + 3) | |
152 | ||
24ccef35 AB |
153 | static struct f7188x_gpio_bank f71869_gpio_bank[] = { |
154 | F7188X_GPIO_BANK(0, 6, 0xF0), | |
155 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
156 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
157 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
158 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
159 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
160 | F7188X_GPIO_BANK(60, 6, 0x90), | |
161 | }; | |
162 | ||
7e960363 AB |
163 | static struct f7188x_gpio_bank f71869a_gpio_bank[] = { |
164 | F7188X_GPIO_BANK(0, 6, 0xF0), | |
165 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
166 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
167 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
168 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
169 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
170 | F7188X_GPIO_BANK(60, 8, 0x90), | |
171 | F7188X_GPIO_BANK(70, 8, 0x80), | |
172 | }; | |
173 | ||
6c17aa01 | 174 | static struct f7188x_gpio_bank f71882_gpio_bank[] = { |
38e003f4 | 175 | F7188X_GPIO_BANK(0, 8, 0xF0), |
6c17aa01 SG |
176 | F7188X_GPIO_BANK(10, 8, 0xE0), |
177 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
178 | F7188X_GPIO_BANK(30, 4, 0xC0), | |
179 | F7188X_GPIO_BANK(40, 4, 0xB0), | |
180 | }; | |
181 | ||
182 | static struct f7188x_gpio_bank f71889_gpio_bank[] = { | |
38e003f4 | 183 | F7188X_GPIO_BANK(0, 7, 0xF0), |
6c17aa01 SG |
184 | F7188X_GPIO_BANK(10, 7, 0xE0), |
185 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
186 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
187 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
188 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
189 | F7188X_GPIO_BANK(60, 8, 0x90), | |
190 | F7188X_GPIO_BANK(70, 8, 0x80), | |
191 | }; | |
192 | ||
193 | static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset) | |
194 | { | |
195 | int err; | |
196 | struct f7188x_gpio_bank *bank = | |
197 | container_of(chip, struct f7188x_gpio_bank, chip); | |
198 | struct f7188x_sio *sio = bank->data->sio; | |
199 | u8 dir; | |
200 | ||
201 | err = superio_enter(sio->addr); | |
202 | if (err) | |
203 | return err; | |
204 | superio_select(sio->addr, SIO_LD_GPIO); | |
205 | ||
206 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
207 | dir &= ~(1 << offset); | |
208 | superio_outb(sio->addr, gpio_dir(bank->regbase), dir); | |
209 | ||
210 | superio_exit(sio->addr); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset) | |
216 | { | |
217 | int err; | |
218 | struct f7188x_gpio_bank *bank = | |
219 | container_of(chip, struct f7188x_gpio_bank, chip); | |
220 | struct f7188x_sio *sio = bank->data->sio; | |
221 | u8 dir, data; | |
222 | ||
223 | err = superio_enter(sio->addr); | |
224 | if (err) | |
225 | return err; | |
226 | superio_select(sio->addr, SIO_LD_GPIO); | |
227 | ||
228 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
229 | dir = !!(dir & (1 << offset)); | |
230 | if (dir) | |
231 | data = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
232 | else | |
233 | data = superio_inb(sio->addr, gpio_data_in(bank->regbase)); | |
234 | ||
235 | superio_exit(sio->addr); | |
236 | ||
237 | return !!(data & 1 << offset); | |
238 | } | |
239 | ||
240 | static int f7188x_gpio_direction_out(struct gpio_chip *chip, | |
241 | unsigned offset, int value) | |
242 | { | |
243 | int err; | |
244 | struct f7188x_gpio_bank *bank = | |
245 | container_of(chip, struct f7188x_gpio_bank, chip); | |
246 | struct f7188x_sio *sio = bank->data->sio; | |
247 | u8 dir, data_out; | |
248 | ||
249 | err = superio_enter(sio->addr); | |
250 | if (err) | |
251 | return err; | |
252 | superio_select(sio->addr, SIO_LD_GPIO); | |
253 | ||
254 | data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
255 | if (value) | |
256 | data_out |= (1 << offset); | |
257 | else | |
258 | data_out &= ~(1 << offset); | |
259 | superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); | |
260 | ||
261 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
262 | dir |= (1 << offset); | |
263 | superio_outb(sio->addr, gpio_dir(bank->regbase), dir); | |
264 | ||
265 | superio_exit(sio->addr); | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
271 | { | |
272 | int err; | |
273 | struct f7188x_gpio_bank *bank = | |
274 | container_of(chip, struct f7188x_gpio_bank, chip); | |
275 | struct f7188x_sio *sio = bank->data->sio; | |
276 | u8 data_out; | |
277 | ||
278 | err = superio_enter(sio->addr); | |
279 | if (err) | |
280 | return; | |
281 | superio_select(sio->addr, SIO_LD_GPIO); | |
282 | ||
283 | data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
284 | if (value) | |
285 | data_out |= (1 << offset); | |
286 | else | |
287 | data_out &= ~(1 << offset); | |
288 | superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); | |
289 | ||
290 | superio_exit(sio->addr); | |
291 | } | |
292 | ||
293 | /* | |
294 | * Platform device and driver. | |
295 | */ | |
296 | ||
297 | static int f7188x_gpio_probe(struct platform_device *pdev) | |
298 | { | |
299 | int err; | |
300 | int i; | |
301 | struct f7188x_sio *sio = pdev->dev.platform_data; | |
302 | struct f7188x_gpio_data *data; | |
303 | ||
304 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
305 | if (!data) | |
306 | return -ENOMEM; | |
307 | ||
308 | switch (sio->type) { | |
24ccef35 AB |
309 | case f71869: |
310 | data->nr_bank = ARRAY_SIZE(f71869_gpio_bank); | |
311 | data->bank = f71869_gpio_bank; | |
312 | break; | |
7e960363 AB |
313 | case f71869a: |
314 | data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank); | |
315 | data->bank = f71869a_gpio_bank; | |
316 | break; | |
6c17aa01 SG |
317 | case f71882fg: |
318 | data->nr_bank = ARRAY_SIZE(f71882_gpio_bank); | |
319 | data->bank = f71882_gpio_bank; | |
320 | break; | |
321 | case f71889f: | |
322 | data->nr_bank = ARRAY_SIZE(f71889_gpio_bank); | |
323 | data->bank = f71889_gpio_bank; | |
324 | break; | |
325 | default: | |
326 | return -ENODEV; | |
327 | } | |
328 | data->sio = sio; | |
329 | ||
330 | platform_set_drvdata(pdev, data); | |
331 | ||
332 | /* For each GPIO bank, register a GPIO chip. */ | |
333 | for (i = 0; i < data->nr_bank; i++) { | |
334 | struct f7188x_gpio_bank *bank = &data->bank[i]; | |
335 | ||
336 | bank->chip.dev = &pdev->dev; | |
337 | bank->data = data; | |
338 | ||
339 | err = gpiochip_add(&bank->chip); | |
340 | if (err) { | |
341 | dev_err(&pdev->dev, | |
342 | "Failed to register gpiochip %d: %d\n", | |
343 | i, err); | |
344 | goto err_gpiochip; | |
345 | } | |
346 | } | |
347 | ||
348 | return 0; | |
349 | ||
350 | err_gpiochip: | |
351 | for (i = i - 1; i >= 0; i--) { | |
352 | struct f7188x_gpio_bank *bank = &data->bank[i]; | |
9f5132ae | 353 | gpiochip_remove(&bank->chip); |
6c17aa01 SG |
354 | } |
355 | ||
356 | return err; | |
357 | } | |
358 | ||
359 | static int f7188x_gpio_remove(struct platform_device *pdev) | |
360 | { | |
6c17aa01 SG |
361 | int i; |
362 | struct f7188x_gpio_data *data = platform_get_drvdata(pdev); | |
363 | ||
364 | for (i = 0; i < data->nr_bank; i++) { | |
365 | struct f7188x_gpio_bank *bank = &data->bank[i]; | |
9f5132ae | 366 | gpiochip_remove(&bank->chip); |
6c17aa01 SG |
367 | } |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static int __init f7188x_find(int addr, struct f7188x_sio *sio) | |
373 | { | |
374 | int err; | |
375 | u16 devid; | |
376 | ||
377 | err = superio_enter(addr); | |
378 | if (err) | |
379 | return err; | |
380 | ||
381 | err = -ENODEV; | |
382 | devid = superio_inw(addr, SIO_MANID); | |
383 | if (devid != SIO_FINTEK_ID) { | |
384 | pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr); | |
385 | goto err; | |
386 | } | |
387 | ||
388 | devid = superio_inw(addr, SIO_DEVID); | |
389 | switch (devid) { | |
24ccef35 AB |
390 | case SIO_F71869_ID: |
391 | sio->type = f71869; | |
392 | break; | |
7e960363 AB |
393 | case SIO_F71869A_ID: |
394 | sio->type = f71869a; | |
395 | break; | |
6c17aa01 SG |
396 | case SIO_F71882_ID: |
397 | sio->type = f71882fg; | |
398 | break; | |
399 | case SIO_F71889_ID: | |
400 | sio->type = f71889f; | |
401 | break; | |
402 | default: | |
403 | pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid); | |
404 | goto err; | |
405 | } | |
406 | sio->addr = addr; | |
407 | err = 0; | |
408 | ||
409 | pr_info(DRVNAME ": Found %s at %#x, revision %d\n", | |
410 | f7188x_names[sio->type], | |
411 | (unsigned int) addr, | |
412 | (int) superio_inb(addr, SIO_DEVREV)); | |
413 | ||
414 | err: | |
415 | superio_exit(addr); | |
416 | return err; | |
417 | } | |
418 | ||
419 | static struct platform_device *f7188x_gpio_pdev; | |
420 | ||
421 | static int __init | |
422 | f7188x_gpio_device_add(const struct f7188x_sio *sio) | |
423 | { | |
424 | int err; | |
425 | ||
426 | f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1); | |
427 | if (!f7188x_gpio_pdev) | |
428 | return -ENOMEM; | |
429 | ||
430 | err = platform_device_add_data(f7188x_gpio_pdev, | |
431 | sio, sizeof(*sio)); | |
432 | if (err) { | |
433 | pr_err(DRVNAME "Platform data allocation failed\n"); | |
434 | goto err; | |
435 | } | |
436 | ||
437 | err = platform_device_add(f7188x_gpio_pdev); | |
438 | if (err) { | |
439 | pr_err(DRVNAME "Device addition failed\n"); | |
440 | goto err; | |
441 | } | |
442 | ||
443 | return 0; | |
444 | ||
445 | err: | |
446 | platform_device_put(f7188x_gpio_pdev); | |
447 | ||
448 | return err; | |
449 | } | |
450 | ||
451 | /* | |
3f8f4f19 | 452 | * Try to match a supported Fintek device by reading the (hard-wired) |
6c17aa01 SG |
453 | * configuration I/O ports. If available, then register both the platform |
454 | * device and driver to support the GPIOs. | |
455 | */ | |
456 | ||
457 | static struct platform_driver f7188x_gpio_driver = { | |
458 | .driver = { | |
6c17aa01 SG |
459 | .name = DRVNAME, |
460 | }, | |
461 | .probe = f7188x_gpio_probe, | |
462 | .remove = f7188x_gpio_remove, | |
463 | }; | |
464 | ||
465 | static int __init f7188x_gpio_init(void) | |
466 | { | |
467 | int err; | |
468 | struct f7188x_sio sio; | |
469 | ||
470 | if (f7188x_find(0x2e, &sio) && | |
471 | f7188x_find(0x4e, &sio)) | |
472 | return -ENODEV; | |
473 | ||
474 | err = platform_driver_register(&f7188x_gpio_driver); | |
475 | if (!err) { | |
476 | err = f7188x_gpio_device_add(&sio); | |
477 | if (err) | |
478 | platform_driver_unregister(&f7188x_gpio_driver); | |
479 | } | |
480 | ||
481 | return err; | |
482 | } | |
483 | subsys_initcall(f7188x_gpio_init); | |
484 | ||
485 | static void __exit f7188x_gpio_exit(void) | |
486 | { | |
487 | platform_device_unregister(f7188x_gpio_pdev); | |
488 | platform_driver_unregister(&f7188x_gpio_driver); | |
489 | } | |
490 | module_exit(f7188x_gpio_exit); | |
491 | ||
7e960363 | 492 | MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG and F71889F"); |
6c17aa01 SG |
493 | MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>"); |
494 | MODULE_LICENSE("GPL"); |