Commit | Line | Data |
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c4a0208f | 1 | /* |
da03d740 | 2 | * GPIO driver for LPC32xx SoC |
c4a0208f KW |
3 | * |
4 | * Author: Kevin Wells <kevin.wells@nxp.com> | |
5 | * | |
6 | * Copyright (C) 2010 NXP Semiconductors | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/gpio.h> | |
831cbd7a | 24 | #include <linux/of.h> |
e92935e1 RS |
25 | #include <linux/of_gpio.h> |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/module.h> | |
eef80f33 | 28 | #include <linux/platform_data/gpio-lpc32xx.h> |
c4a0208f KW |
29 | |
30 | #include <mach/hardware.h> | |
31 | #include <mach/platform.h> | |
0bdfeddc | 32 | #include <mach/irqs.h> |
c4a0208f KW |
33 | |
34 | #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) | |
35 | #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) | |
36 | #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) | |
37 | #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) | |
38 | #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) | |
39 | #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) | |
40 | #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) | |
41 | #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) | |
42 | #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) | |
43 | #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) | |
44 | #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) | |
45 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) | |
46 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) | |
47 | #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) | |
48 | #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) | |
49 | #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) | |
50 | #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) | |
51 | #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) | |
52 | #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) | |
53 | #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) | |
54 | #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) | |
55 | #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) | |
56 | #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) | |
57 | #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) | |
58 | #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) | |
59 | #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) | |
60 | #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) | |
61 | ||
62 | #define GPIO012_PIN_TO_BIT(x) (1 << (x)) | |
63 | #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) | |
64 | #define GPO3_PIN_TO_BIT(x) (1 << (x)) | |
65 | #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) | |
66 | #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) | |
8e5fb37b | 67 | #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) |
c4a0208f KW |
68 | #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) |
69 | #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) | |
46158aad | 70 | #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) |
c4a0208f KW |
71 | |
72 | struct gpio_regs { | |
73 | void __iomem *inp_state; | |
46158aad | 74 | void __iomem *outp_state; |
c4a0208f KW |
75 | void __iomem *outp_set; |
76 | void __iomem *outp_clr; | |
77 | void __iomem *dir_set; | |
78 | void __iomem *dir_clr; | |
79 | }; | |
80 | ||
81 | /* | |
82 | * GPIO names | |
83 | */ | |
84 | static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { | |
85 | "p0.0", "p0.1", "p0.2", "p0.3", | |
86 | "p0.4", "p0.5", "p0.6", "p0.7" | |
87 | }; | |
88 | ||
89 | static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { | |
90 | "p1.0", "p1.1", "p1.2", "p1.3", | |
91 | "p1.4", "p1.5", "p1.6", "p1.7", | |
92 | "p1.8", "p1.9", "p1.10", "p1.11", | |
93 | "p1.12", "p1.13", "p1.14", "p1.15", | |
94 | "p1.16", "p1.17", "p1.18", "p1.19", | |
95 | "p1.20", "p1.21", "p1.22", "p1.23", | |
96 | }; | |
97 | ||
98 | static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { | |
99 | "p2.0", "p2.1", "p2.2", "p2.3", | |
100 | "p2.4", "p2.5", "p2.6", "p2.7", | |
101 | "p2.8", "p2.9", "p2.10", "p2.11", | |
102 | "p2.12" | |
103 | }; | |
104 | ||
105 | static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { | |
95120d5d | 106 | "gpio00", "gpio01", "gpio02", "gpio03", |
c4a0208f KW |
107 | "gpio04", "gpio05" |
108 | }; | |
109 | ||
110 | static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { | |
111 | "gpi00", "gpi01", "gpi02", "gpi03", | |
112 | "gpi04", "gpi05", "gpi06", "gpi07", | |
113 | "gpi08", "gpi09", NULL, NULL, | |
114 | NULL, NULL, NULL, "gpi15", | |
115 | "gpi16", "gpi17", "gpi18", "gpi19", | |
116 | "gpi20", "gpi21", "gpi22", "gpi23", | |
71fde000 RS |
117 | "gpi24", "gpi25", "gpi26", "gpi27", |
118 | "gpi28" | |
c4a0208f KW |
119 | }; |
120 | ||
121 | static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { | |
122 | "gpo00", "gpo01", "gpo02", "gpo03", | |
123 | "gpo04", "gpo05", "gpo06", "gpo07", | |
124 | "gpo08", "gpo09", "gpo10", "gpo11", | |
125 | "gpo12", "gpo13", "gpo14", "gpo15", | |
126 | "gpo16", "gpo17", "gpo18", "gpo19", | |
127 | "gpo20", "gpo21", "gpo22", "gpo23" | |
128 | }; | |
129 | ||
130 | static struct gpio_regs gpio_grp_regs_p0 = { | |
131 | .inp_state = LPC32XX_GPIO_P0_INP_STATE, | |
132 | .outp_set = LPC32XX_GPIO_P0_OUTP_SET, | |
133 | .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, | |
134 | .dir_set = LPC32XX_GPIO_P0_DIR_SET, | |
135 | .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, | |
136 | }; | |
137 | ||
138 | static struct gpio_regs gpio_grp_regs_p1 = { | |
139 | .inp_state = LPC32XX_GPIO_P1_INP_STATE, | |
140 | .outp_set = LPC32XX_GPIO_P1_OUTP_SET, | |
141 | .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, | |
142 | .dir_set = LPC32XX_GPIO_P1_DIR_SET, | |
143 | .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, | |
144 | }; | |
145 | ||
146 | static struct gpio_regs gpio_grp_regs_p2 = { | |
147 | .inp_state = LPC32XX_GPIO_P2_INP_STATE, | |
148 | .outp_set = LPC32XX_GPIO_P2_OUTP_SET, | |
149 | .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, | |
150 | .dir_set = LPC32XX_GPIO_P2_DIR_SET, | |
151 | .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, | |
152 | }; | |
153 | ||
154 | static struct gpio_regs gpio_grp_regs_p3 = { | |
155 | .inp_state = LPC32XX_GPIO_P3_INP_STATE, | |
46158aad | 156 | .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, |
c4a0208f KW |
157 | .outp_set = LPC32XX_GPIO_P3_OUTP_SET, |
158 | .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, | |
159 | .dir_set = LPC32XX_GPIO_P2_DIR_SET, | |
160 | .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, | |
161 | }; | |
162 | ||
163 | struct lpc32xx_gpio_chip { | |
164 | struct gpio_chip chip; | |
165 | struct gpio_regs *gpio_grp; | |
166 | }; | |
167 | ||
c4a0208f KW |
168 | static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, |
169 | unsigned pin, int input) | |
170 | { | |
171 | if (input) | |
172 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | |
173 | group->gpio_grp->dir_clr); | |
174 | else | |
175 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | |
176 | group->gpio_grp->dir_set); | |
177 | } | |
178 | ||
179 | static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, | |
180 | unsigned pin, int input) | |
181 | { | |
182 | u32 u = GPIO3_PIN_TO_BIT(pin); | |
183 | ||
184 | if (input) | |
185 | __raw_writel(u, group->gpio_grp->dir_clr); | |
186 | else | |
187 | __raw_writel(u, group->gpio_grp->dir_set); | |
188 | } | |
189 | ||
190 | static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, | |
191 | unsigned pin, int high) | |
192 | { | |
193 | if (high) | |
194 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | |
195 | group->gpio_grp->outp_set); | |
196 | else | |
197 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | |
198 | group->gpio_grp->outp_clr); | |
199 | } | |
200 | ||
201 | static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, | |
202 | unsigned pin, int high) | |
203 | { | |
204 | u32 u = GPIO3_PIN_TO_BIT(pin); | |
205 | ||
206 | if (high) | |
207 | __raw_writel(u, group->gpio_grp->outp_set); | |
208 | else | |
209 | __raw_writel(u, group->gpio_grp->outp_clr); | |
210 | } | |
211 | ||
212 | static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, | |
213 | unsigned pin, int high) | |
214 | { | |
215 | if (high) | |
216 | __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); | |
217 | else | |
218 | __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); | |
219 | } | |
220 | ||
221 | static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, | |
222 | unsigned pin) | |
223 | { | |
224 | return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), | |
225 | pin); | |
226 | } | |
227 | ||
228 | static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, | |
229 | unsigned pin) | |
230 | { | |
231 | int state = __raw_readl(group->gpio_grp->inp_state); | |
232 | ||
233 | /* | |
234 | * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped | |
235 | * to bits 10..14, while GPIOP3-5 is mapped to bit 24. | |
236 | */ | |
237 | return GPIO3_PIN_IN_SEL(state, pin); | |
238 | } | |
239 | ||
240 | static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, | |
241 | unsigned pin) | |
242 | { | |
243 | return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); | |
244 | } | |
245 | ||
46158aad RS |
246 | static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, |
247 | unsigned pin) | |
248 | { | |
249 | return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); | |
250 | } | |
251 | ||
c4a0208f | 252 | /* |
7fd2bf3d | 253 | * GPIO primitives. |
c4a0208f KW |
254 | */ |
255 | static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, | |
256 | unsigned pin) | |
257 | { | |
a9bc97e4 | 258 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f KW |
259 | |
260 | __set_gpio_dir_p012(group, pin, 1); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, | |
266 | unsigned pin) | |
267 | { | |
a9bc97e4 | 268 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f KW |
269 | |
270 | __set_gpio_dir_p3(group, pin, 1); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, | |
276 | unsigned pin) | |
277 | { | |
278 | return 0; | |
279 | } | |
280 | ||
281 | static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) | |
282 | { | |
a9bc97e4 | 283 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f | 284 | |
2e6d8456 | 285 | return !!__get_gpio_state_p012(group, pin); |
c4a0208f KW |
286 | } |
287 | ||
288 | static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) | |
289 | { | |
a9bc97e4 | 290 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f | 291 | |
2e6d8456 | 292 | return !!__get_gpio_state_p3(group, pin); |
c4a0208f KW |
293 | } |
294 | ||
295 | static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) | |
296 | { | |
a9bc97e4 | 297 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f | 298 | |
2e6d8456 | 299 | return !!__get_gpi_state_p3(group, pin); |
c4a0208f KW |
300 | } |
301 | ||
302 | static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, | |
303 | int value) | |
304 | { | |
a9bc97e4 | 305 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f | 306 | |
b1268d37 | 307 | __set_gpio_level_p012(group, pin, value); |
c4a0208f KW |
308 | __set_gpio_dir_p012(group, pin, 0); |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, | |
314 | int value) | |
315 | { | |
a9bc97e4 | 316 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f | 317 | |
b1268d37 | 318 | __set_gpio_level_p3(group, pin, value); |
c4a0208f KW |
319 | __set_gpio_dir_p3(group, pin, 0); |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, | |
325 | int value) | |
326 | { | |
a9bc97e4 | 327 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
b1268d37 RS |
328 | |
329 | __set_gpo_level_p3(group, pin, value); | |
c4a0208f KW |
330 | return 0; |
331 | } | |
332 | ||
333 | static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, | |
334 | int value) | |
335 | { | |
a9bc97e4 | 336 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f KW |
337 | |
338 | __set_gpio_level_p012(group, pin, value); | |
339 | } | |
340 | ||
341 | static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, | |
342 | int value) | |
343 | { | |
a9bc97e4 | 344 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f KW |
345 | |
346 | __set_gpio_level_p3(group, pin, value); | |
347 | } | |
348 | ||
349 | static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, | |
350 | int value) | |
351 | { | |
a9bc97e4 | 352 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
c4a0208f KW |
353 | |
354 | __set_gpo_level_p3(group, pin, value); | |
355 | } | |
356 | ||
46158aad RS |
357 | static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) |
358 | { | |
a9bc97e4 | 359 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
46158aad | 360 | |
2e6d8456 | 361 | return !!__get_gpo_state_p3(group, pin); |
46158aad RS |
362 | } |
363 | ||
c4a0208f KW |
364 | static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) |
365 | { | |
366 | if (pin < chip->ngpio) | |
367 | return 0; | |
368 | ||
369 | return -EINVAL; | |
370 | } | |
371 | ||
0bdfeddc RS |
372 | static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset) |
373 | { | |
374 | return IRQ_LPC32XX_P0_P1_IRQ; | |
375 | } | |
376 | ||
377 | static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = { | |
378 | IRQ_LPC32XX_GPIO_00, | |
379 | IRQ_LPC32XX_GPIO_01, | |
380 | IRQ_LPC32XX_GPIO_02, | |
381 | IRQ_LPC32XX_GPIO_03, | |
382 | IRQ_LPC32XX_GPIO_04, | |
383 | IRQ_LPC32XX_GPIO_05, | |
384 | }; | |
385 | ||
386 | static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset) | |
387 | { | |
388 | if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table)) | |
389 | return lpc32xx_gpio_to_irq_gpio_p3_table[offset]; | |
390 | return -ENXIO; | |
391 | } | |
392 | ||
393 | static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = { | |
394 | IRQ_LPC32XX_GPI_00, | |
395 | IRQ_LPC32XX_GPI_01, | |
396 | IRQ_LPC32XX_GPI_02, | |
397 | IRQ_LPC32XX_GPI_03, | |
398 | IRQ_LPC32XX_GPI_04, | |
399 | IRQ_LPC32XX_GPI_05, | |
400 | IRQ_LPC32XX_GPI_06, | |
401 | IRQ_LPC32XX_GPI_07, | |
402 | IRQ_LPC32XX_GPI_08, | |
403 | IRQ_LPC32XX_GPI_09, | |
404 | -ENXIO, /* 10 */ | |
405 | -ENXIO, /* 11 */ | |
406 | -ENXIO, /* 12 */ | |
407 | -ENXIO, /* 13 */ | |
408 | -ENXIO, /* 14 */ | |
409 | -ENXIO, /* 15 */ | |
410 | -ENXIO, /* 16 */ | |
411 | -ENXIO, /* 17 */ | |
412 | -ENXIO, /* 18 */ | |
413 | IRQ_LPC32XX_GPI_19, | |
414 | -ENXIO, /* 20 */ | |
415 | -ENXIO, /* 21 */ | |
416 | -ENXIO, /* 22 */ | |
417 | -ENXIO, /* 23 */ | |
418 | -ENXIO, /* 24 */ | |
419 | -ENXIO, /* 25 */ | |
420 | -ENXIO, /* 26 */ | |
421 | -ENXIO, /* 27 */ | |
422 | IRQ_LPC32XX_GPI_28, | |
423 | }; | |
424 | ||
425 | static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset) | |
426 | { | |
427 | if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table)) | |
428 | return lpc32xx_gpio_to_irq_gpi_p3_table[offset]; | |
429 | return -ENXIO; | |
430 | } | |
431 | ||
c4a0208f KW |
432 | static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { |
433 | { | |
434 | .chip = { | |
435 | .label = "gpio_p0", | |
436 | .direction_input = lpc32xx_gpio_dir_input_p012, | |
437 | .get = lpc32xx_gpio_get_value_p012, | |
438 | .direction_output = lpc32xx_gpio_dir_output_p012, | |
439 | .set = lpc32xx_gpio_set_value_p012, | |
440 | .request = lpc32xx_gpio_request, | |
0bdfeddc | 441 | .to_irq = lpc32xx_gpio_to_irq_p01, |
c4a0208f KW |
442 | .base = LPC32XX_GPIO_P0_GRP, |
443 | .ngpio = LPC32XX_GPIO_P0_MAX, | |
444 | .names = gpio_p0_names, | |
9fb1f39e | 445 | .can_sleep = false, |
c4a0208f KW |
446 | }, |
447 | .gpio_grp = &gpio_grp_regs_p0, | |
448 | }, | |
449 | { | |
450 | .chip = { | |
451 | .label = "gpio_p1", | |
452 | .direction_input = lpc32xx_gpio_dir_input_p012, | |
453 | .get = lpc32xx_gpio_get_value_p012, | |
454 | .direction_output = lpc32xx_gpio_dir_output_p012, | |
455 | .set = lpc32xx_gpio_set_value_p012, | |
456 | .request = lpc32xx_gpio_request, | |
0bdfeddc | 457 | .to_irq = lpc32xx_gpio_to_irq_p01, |
c4a0208f KW |
458 | .base = LPC32XX_GPIO_P1_GRP, |
459 | .ngpio = LPC32XX_GPIO_P1_MAX, | |
460 | .names = gpio_p1_names, | |
9fb1f39e | 461 | .can_sleep = false, |
c4a0208f KW |
462 | }, |
463 | .gpio_grp = &gpio_grp_regs_p1, | |
464 | }, | |
465 | { | |
466 | .chip = { | |
467 | .label = "gpio_p2", | |
468 | .direction_input = lpc32xx_gpio_dir_input_p012, | |
469 | .get = lpc32xx_gpio_get_value_p012, | |
470 | .direction_output = lpc32xx_gpio_dir_output_p012, | |
471 | .set = lpc32xx_gpio_set_value_p012, | |
472 | .request = lpc32xx_gpio_request, | |
473 | .base = LPC32XX_GPIO_P2_GRP, | |
474 | .ngpio = LPC32XX_GPIO_P2_MAX, | |
475 | .names = gpio_p2_names, | |
9fb1f39e | 476 | .can_sleep = false, |
c4a0208f KW |
477 | }, |
478 | .gpio_grp = &gpio_grp_regs_p2, | |
479 | }, | |
480 | { | |
481 | .chip = { | |
482 | .label = "gpio_p3", | |
483 | .direction_input = lpc32xx_gpio_dir_input_p3, | |
484 | .get = lpc32xx_gpio_get_value_p3, | |
485 | .direction_output = lpc32xx_gpio_dir_output_p3, | |
486 | .set = lpc32xx_gpio_set_value_p3, | |
487 | .request = lpc32xx_gpio_request, | |
0bdfeddc | 488 | .to_irq = lpc32xx_gpio_to_irq_gpio_p3, |
c4a0208f KW |
489 | .base = LPC32XX_GPIO_P3_GRP, |
490 | .ngpio = LPC32XX_GPIO_P3_MAX, | |
491 | .names = gpio_p3_names, | |
9fb1f39e | 492 | .can_sleep = false, |
c4a0208f KW |
493 | }, |
494 | .gpio_grp = &gpio_grp_regs_p3, | |
495 | }, | |
496 | { | |
497 | .chip = { | |
498 | .label = "gpi_p3", | |
499 | .direction_input = lpc32xx_gpio_dir_in_always, | |
500 | .get = lpc32xx_gpi_get_value, | |
501 | .request = lpc32xx_gpio_request, | |
0bdfeddc | 502 | .to_irq = lpc32xx_gpio_to_irq_gpi_p3, |
c4a0208f KW |
503 | .base = LPC32XX_GPI_P3_GRP, |
504 | .ngpio = LPC32XX_GPI_P3_MAX, | |
505 | .names = gpi_p3_names, | |
9fb1f39e | 506 | .can_sleep = false, |
c4a0208f KW |
507 | }, |
508 | .gpio_grp = &gpio_grp_regs_p3, | |
509 | }, | |
510 | { | |
511 | .chip = { | |
512 | .label = "gpo_p3", | |
513 | .direction_output = lpc32xx_gpio_dir_out_always, | |
514 | .set = lpc32xx_gpo_set_value, | |
46158aad | 515 | .get = lpc32xx_gpo_get_value, |
c4a0208f KW |
516 | .request = lpc32xx_gpio_request, |
517 | .base = LPC32XX_GPO_P3_GRP, | |
518 | .ngpio = LPC32XX_GPO_P3_MAX, | |
519 | .names = gpo_p3_names, | |
9fb1f39e | 520 | .can_sleep = false, |
c4a0208f KW |
521 | }, |
522 | .gpio_grp = &gpio_grp_regs_p3, | |
523 | }, | |
524 | }; | |
525 | ||
e92935e1 RS |
526 | static int lpc32xx_of_xlate(struct gpio_chip *gc, |
527 | const struct of_phandle_args *gpiospec, u32 *flags) | |
528 | { | |
529 | /* Is this the correct bank? */ | |
530 | u32 bank = gpiospec->args[0]; | |
fdc7a9f8 | 531 | if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) || |
e92935e1 RS |
532 | (gc != &lpc32xx_gpiochip[bank].chip))) |
533 | return -EINVAL; | |
534 | ||
535 | if (flags) | |
536 | *flags = gpiospec->args[2]; | |
537 | return gpiospec->args[1]; | |
538 | } | |
539 | ||
3836309d | 540 | static int lpc32xx_gpio_probe(struct platform_device *pdev) |
c4a0208f KW |
541 | { |
542 | int i; | |
543 | ||
e92935e1 RS |
544 | for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { |
545 | if (pdev->dev.of_node) { | |
546 | lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; | |
547 | lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; | |
548 | lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; | |
549 | } | |
69c0a0a5 | 550 | devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, |
a9bc97e4 | 551 | &lpc32xx_gpiochip[i]); |
e92935e1 RS |
552 | } |
553 | ||
554 | return 0; | |
c4a0208f | 555 | } |
e92935e1 RS |
556 | |
557 | #ifdef CONFIG_OF | |
e95c7c45 | 558 | static const struct of_device_id lpc32xx_gpio_of_match[] = { |
e92935e1 RS |
559 | { .compatible = "nxp,lpc3220-gpio", }, |
560 | { }, | |
561 | }; | |
562 | #endif | |
563 | ||
564 | static struct platform_driver lpc32xx_gpio_driver = { | |
565 | .driver = { | |
566 | .name = "lpc32xx-gpio", | |
e92935e1 RS |
567 | .of_match_table = of_match_ptr(lpc32xx_gpio_of_match), |
568 | }, | |
569 | .probe = lpc32xx_gpio_probe, | |
570 | }; | |
571 | ||
572 | module_platform_driver(lpc32xx_gpio_driver); |