Commit | Line | Data |
---|---|---|
1e16dfc1 | 1 | /* |
e39d5ef6 | 2 | * GPIOs on MPC512x/8349/8572/8610 and compatible |
1e16dfc1 PK |
3 | * |
4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_gpio.h> | |
5af50730 | 17 | #include <linux/of_irq.h> |
1e16dfc1 | 18 | #include <linux/gpio.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
345e5c8a | 20 | #include <linux/irq.h> |
1e16dfc1 PK |
21 | |
22 | #define MPC8XXX_GPIO_PINS 32 | |
23 | ||
24 | #define GPIO_DIR 0x00 | |
25 | #define GPIO_ODR 0x04 | |
26 | #define GPIO_DAT 0x08 | |
27 | #define GPIO_IER 0x0c | |
28 | #define GPIO_IMR 0x10 | |
29 | #define GPIO_ICR 0x14 | |
e39d5ef6 | 30 | #define GPIO_ICR2 0x18 |
1e16dfc1 PK |
31 | |
32 | struct mpc8xxx_gpio_chip { | |
33 | struct of_mm_gpio_chip mm_gc; | |
34 | spinlock_t lock; | |
35 | ||
36 | /* | |
37 | * shadowed data register to be able to clear/set output pins in | |
38 | * open drain mode safely | |
39 | */ | |
40 | u32 data; | |
bae1d8f1 | 41 | struct irq_domain *irq; |
01a04ddc | 42 | const void *of_dev_id_data; |
1e16dfc1 PK |
43 | }; |
44 | ||
45 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) | |
46 | { | |
47 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); | |
48 | } | |
49 | ||
50 | static inline struct mpc8xxx_gpio_chip * | |
51 | to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) | |
52 | { | |
53 | return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); | |
54 | } | |
55 | ||
56 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) | |
57 | { | |
58 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
59 | ||
60 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); | |
61 | } | |
62 | ||
c1a676df FR |
63 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
64 | * defined as output cannot be determined by reading GPDAT register, | |
65 | * so we use shadow data register instead. The status of input pins | |
66 | * is determined by reading GPDAT register. | |
67 | */ | |
68 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) | |
69 | { | |
70 | u32 val; | |
71 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
72 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
1aeef303 | 73 | u32 out_mask, out_shadow; |
c1a676df | 74 | |
1aeef303 | 75 | out_mask = in_be32(mm->regs + GPIO_DIR); |
c1a676df | 76 | |
1aeef303 LG |
77 | val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; |
78 | out_shadow = mpc8xxx_gc->data & out_mask; | |
79 | ||
80 | return (val | out_shadow) & mpc8xxx_gpio2mask(gpio); | |
c1a676df FR |
81 | } |
82 | ||
1e16dfc1 PK |
83 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
84 | { | |
85 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
86 | ||
87 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); | |
88 | } | |
89 | ||
90 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
91 | { | |
92 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
93 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
94 | unsigned long flags; | |
95 | ||
96 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
97 | ||
98 | if (val) | |
99 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); | |
100 | else | |
101 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); | |
102 | ||
103 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); | |
104 | ||
105 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
106 | } | |
107 | ||
e5db3b33 RI |
108 | static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc, |
109 | unsigned long *mask, unsigned long *bits) | |
110 | { | |
111 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
112 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
113 | unsigned long flags; | |
114 | int i; | |
115 | ||
116 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
117 | ||
118 | for (i = 0; i < gc->ngpio; i++) { | |
119 | if (*mask == 0) | |
120 | break; | |
121 | if (__test_and_clear_bit(i, mask)) { | |
122 | if (test_bit(i, bits)) | |
123 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i); | |
124 | else | |
125 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i); | |
126 | } | |
127 | } | |
128 | ||
129 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); | |
130 | ||
131 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
132 | } | |
133 | ||
1e16dfc1 PK |
134 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
135 | { | |
136 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
137 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
141 | ||
142 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
143 | ||
144 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
150 | { | |
151 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
152 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
153 | unsigned long flags; | |
154 | ||
155 | mpc8xxx_gpio_set(gc, gpio, val); | |
156 | ||
157 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
158 | ||
159 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
160 | ||
161 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
28538df0 WS |
166 | static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
167 | { | |
168 | /* GPIO 28..31 are input only on MPC5121 */ | |
169 | if (gpio >= 28) | |
170 | return -EINVAL; | |
171 | ||
172 | return mpc8xxx_gpio_dir_out(gc, gpio, val); | |
173 | } | |
174 | ||
345e5c8a PK |
175 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
176 | { | |
177 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
178 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
179 | ||
180 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) | |
181 | return irq_create_mapping(mpc8xxx_gc->irq, offset); | |
182 | else | |
183 | return -ENXIO; | |
184 | } | |
185 | ||
186 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | |
187 | { | |
ec775d0e | 188 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
cfadd838 | 189 | struct irq_chip *chip = irq_desc_get_chip(desc); |
345e5c8a PK |
190 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
191 | unsigned int mask; | |
192 | ||
193 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); | |
194 | if (mask) | |
195 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, | |
196 | 32 - ffs(mask))); | |
d6de85e8 TG |
197 | if (chip->irq_eoi) |
198 | chip->irq_eoi(&desc->irq_data); | |
345e5c8a PK |
199 | } |
200 | ||
94347cb3 | 201 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
345e5c8a | 202 | { |
94347cb3 | 203 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
204 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
205 | unsigned long flags; | |
206 | ||
207 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
208 | ||
476eb491 | 209 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
210 | |
211 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
212 | } | |
213 | ||
94347cb3 | 214 | static void mpc8xxx_irq_mask(struct irq_data *d) |
345e5c8a | 215 | { |
94347cb3 | 216 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
217 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
218 | unsigned long flags; | |
219 | ||
220 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
221 | ||
476eb491 | 222 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
223 | |
224 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
225 | } | |
226 | ||
94347cb3 | 227 | static void mpc8xxx_irq_ack(struct irq_data *d) |
345e5c8a | 228 | { |
94347cb3 | 229 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
230 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
231 | ||
476eb491 | 232 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
233 | } |
234 | ||
94347cb3 | 235 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
345e5c8a | 236 | { |
94347cb3 | 237 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
238 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
239 | unsigned long flags; | |
240 | ||
241 | switch (flow_type) { | |
242 | case IRQ_TYPE_EDGE_FALLING: | |
243 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
244 | setbits32(mm->regs + GPIO_ICR, | |
476eb491 | 245 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
246 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
247 | break; | |
248 | ||
249 | case IRQ_TYPE_EDGE_BOTH: | |
250 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
251 | clrbits32(mm->regs + GPIO_ICR, | |
476eb491 | 252 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
253 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
254 | break; | |
255 | ||
256 | default: | |
257 | return -EINVAL; | |
258 | } | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
94347cb3 | 263 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
e39d5ef6 | 264 | { |
94347cb3 | 265 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
e39d5ef6 | 266 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
476eb491 | 267 | unsigned long gpio = irqd_to_hwirq(d); |
e39d5ef6 AG |
268 | void __iomem *reg; |
269 | unsigned int shift; | |
270 | unsigned long flags; | |
271 | ||
272 | if (gpio < 16) { | |
273 | reg = mm->regs + GPIO_ICR; | |
274 | shift = (15 - gpio) * 2; | |
275 | } else { | |
276 | reg = mm->regs + GPIO_ICR2; | |
277 | shift = (15 - (gpio % 16)) * 2; | |
278 | } | |
279 | ||
280 | switch (flow_type) { | |
281 | case IRQ_TYPE_EDGE_FALLING: | |
282 | case IRQ_TYPE_LEVEL_LOW: | |
283 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
284 | clrsetbits_be32(reg, 3 << shift, 2 << shift); | |
285 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
286 | break; | |
287 | ||
288 | case IRQ_TYPE_EDGE_RISING: | |
289 | case IRQ_TYPE_LEVEL_HIGH: | |
290 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
291 | clrsetbits_be32(reg, 3 << shift, 1 << shift); | |
292 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
293 | break; | |
294 | ||
295 | case IRQ_TYPE_EDGE_BOTH: | |
296 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
297 | clrbits32(reg, 3 << shift); | |
298 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
299 | break; | |
300 | ||
301 | default: | |
302 | return -EINVAL; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
345e5c8a PK |
308 | static struct irq_chip mpc8xxx_irq_chip = { |
309 | .name = "mpc8xxx-gpio", | |
94347cb3 LB |
310 | .irq_unmask = mpc8xxx_irq_unmask, |
311 | .irq_mask = mpc8xxx_irq_mask, | |
312 | .irq_ack = mpc8xxx_irq_ack, | |
313 | .irq_set_type = mpc8xxx_irq_set_type, | |
345e5c8a PK |
314 | }; |
315 | ||
5ba17ae9 LW |
316 | static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, |
317 | irq_hw_number_t hwirq) | |
345e5c8a | 318 | { |
e39d5ef6 AG |
319 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; |
320 | ||
321 | if (mpc8xxx_gc->of_dev_id_data) | |
94347cb3 | 322 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
e39d5ef6 | 323 | |
5ba17ae9 LW |
324 | irq_set_chip_data(irq, h->host_data); |
325 | irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq); | |
345e5c8a PK |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
bae1d8f1 | 330 | static struct irq_domain_ops mpc8xxx_gpio_irq_ops = { |
345e5c8a | 331 | .map = mpc8xxx_gpio_irq_map, |
ff8c3ab8 | 332 | .xlate = irq_domain_xlate_twocell, |
345e5c8a PK |
333 | }; |
334 | ||
e39d5ef6 AG |
335 | static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { |
336 | { .compatible = "fsl,mpc8349-gpio", }, | |
337 | { .compatible = "fsl,mpc8572-gpio", }, | |
338 | { .compatible = "fsl,mpc8610-gpio", }, | |
339 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, | |
15a5148c | 340 | { .compatible = "fsl,pq3-gpio", }, |
d1dcfbbb | 341 | { .compatible = "fsl,qoriq-gpio", }, |
e39d5ef6 AG |
342 | {} |
343 | }; | |
344 | ||
1e16dfc1 PK |
345 | static void __init mpc8xxx_add_controller(struct device_node *np) |
346 | { | |
347 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; | |
348 | struct of_mm_gpio_chip *mm_gc; | |
1e16dfc1 | 349 | struct gpio_chip *gc; |
e39d5ef6 | 350 | const struct of_device_id *id; |
345e5c8a | 351 | unsigned hwirq; |
1e16dfc1 PK |
352 | int ret; |
353 | ||
354 | mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); | |
355 | if (!mpc8xxx_gc) { | |
356 | ret = -ENOMEM; | |
357 | goto err; | |
358 | } | |
359 | ||
360 | spin_lock_init(&mpc8xxx_gc->lock); | |
361 | ||
362 | mm_gc = &mpc8xxx_gc->mm_gc; | |
a19e3da5 | 363 | gc = &mm_gc->gc; |
1e16dfc1 PK |
364 | |
365 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; | |
1e16dfc1 PK |
366 | gc->ngpio = MPC8XXX_GPIO_PINS; |
367 | gc->direction_input = mpc8xxx_gpio_dir_in; | |
28538df0 WS |
368 | gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ? |
369 | mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out; | |
370 | gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ? | |
371 | mpc8572_gpio_get : mpc8xxx_gpio_get; | |
1e16dfc1 | 372 | gc->set = mpc8xxx_gpio_set; |
e5db3b33 | 373 | gc->set_multiple = mpc8xxx_gpio_set_multiple; |
345e5c8a | 374 | gc->to_irq = mpc8xxx_gpio_to_irq; |
1e16dfc1 PK |
375 | |
376 | ret = of_mm_gpiochip_add(np, mm_gc); | |
377 | if (ret) | |
378 | goto err; | |
379 | ||
345e5c8a PK |
380 | hwirq = irq_of_parse_and_map(np, 0); |
381 | if (hwirq == NO_IRQ) | |
382 | goto skip_irq; | |
383 | ||
a8db8cf0 GL |
384 | mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, |
385 | &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); | |
345e5c8a PK |
386 | if (!mpc8xxx_gc->irq) |
387 | goto skip_irq; | |
388 | ||
e39d5ef6 AG |
389 | id = of_match_node(mpc8xxx_gpio_ids, np); |
390 | if (id) | |
391 | mpc8xxx_gc->of_dev_id_data = id->data; | |
392 | ||
345e5c8a PK |
393 | /* ack and mask all irqs */ |
394 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); | |
395 | out_be32(mm_gc->regs + GPIO_IMR, 0); | |
396 | ||
ec775d0e TG |
397 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
398 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); | |
345e5c8a PK |
399 | |
400 | skip_irq: | |
1e16dfc1 PK |
401 | return; |
402 | ||
403 | err: | |
404 | pr_err("%s: registration failed with status %d\n", | |
405 | np->full_name, ret); | |
406 | kfree(mpc8xxx_gc); | |
407 | ||
408 | return; | |
409 | } | |
410 | ||
411 | static int __init mpc8xxx_add_gpiochips(void) | |
412 | { | |
413 | struct device_node *np; | |
414 | ||
e39d5ef6 | 415 | for_each_matching_node(np, mpc8xxx_gpio_ids) |
1e16dfc1 PK |
416 | mpc8xxx_add_controller(np); |
417 | ||
418 | return 0; | |
419 | } | |
420 | arch_initcall(mpc8xxx_add_gpiochips); |