[deliverable/linux.git] / drivers / gpio / gpio-mpc8xxx.c

/*
 * GPIOs on MPC512x/8349/8572/8610 and compatible
 *
 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/irq.h>

#define MPC8XXX_GPIO_PINS	32

#define GPIO_DIR		0x00
#define GPIO_ODR		0x04
#define GPIO_DAT		0x08
#define GPIO_IER		0x0c
#define GPIO_IMR		0x10
#define GPIO_ICR		0x14
#define GPIO_ICR2		0x18

struct mpc8xxx_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	raw_spinlock_t lock;

	/*
	 * shadowed data register to be able to clear/set output pins in
	 * open drain mode safely
	 */
	u32 data;
	struct irq_domain *irq;
	unsigned int irqn;
	const void *of_dev_id_data;
};

static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
{
	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
}

static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc =
		container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);

	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
}

/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 * defined as output cannot be determined by reading GPDAT register,
 * so we use shadow data register instead. The status of input pins
 * is determined by reading GPDAT register.
 */
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	u32 val;
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	u32 out_mask, out_shadow;

	out_mask = in_be32(mm->regs + GPIO_DIR);

	val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
	out_shadow = mpc8xxx_gc->data & out_mask;

	return !!((val | out_shadow) & mpc8xxx_gpio2mask(gpio));
}

static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);

	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
}

static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	if (val)
		mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
	else
		mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);

	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
				      unsigned long *mask, unsigned long *bits)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	unsigned long flags;
	int i;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	for (i = 0; i < gc->ngpio; i++) {
		if (*mask == 0)
			break;
		if (__test_and_clear_bit(i, mask)) {
			if (test_bit(i, bits))
				mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
			else
				mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
		}
	}

	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);

	return 0;
}

static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	unsigned long flags;

	mpc8xxx_gpio_set(gc, gpio, val);

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);

	return 0;
}

static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	/* GPIO 28..31 are input only on MPC5121 */
	if (gpio >= 28)
		return -EINVAL;

	return mpc8xxx_gpio_dir_out(gc, gpio, val);
}

static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	/* GPIO 0..3 are input only on MPC5125 */
	if (gpio <= 3)
		return -EINVAL;

	return mpc8xxx_gpio_dir_out(gc, gpio, val);
}

static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);

	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
		return irq_create_mapping(mpc8xxx_gc->irq, offset);
	else
		return -ENXIO;
}

static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned int mask;

	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
	if (mask)
		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
						     32 - ffs(mask)));
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
}

static void mpc8xxx_irq_unmask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_mask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_ack(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;

	out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
}

static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		setbits32(mm->regs + GPIO_ICR,
			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		clrbits32(mm->regs + GPIO_ICR,
			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long gpio = irqd_to_hwirq(d);
	void __iomem *reg;
	unsigned int shift;
	unsigned long flags;

	if (gpio < 16) {
		reg = mm->regs + GPIO_ICR;
		shift = (15 - gpio) * 2;
	} else {
		reg = mm->regs + GPIO_ICR2;
		shift = (15 - (gpio % 16)) * 2;
	}

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		clrsetbits_be32(reg, 3 << shift, 2 << shift);
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_LEVEL_HIGH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		clrsetbits_be32(reg, 3 << shift, 1 << shift);
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		clrbits32(reg, 3 << shift);
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip mpc8xxx_irq_chip = {
	.name		= "mpc8xxx-gpio",
	.irq_unmask	= mpc8xxx_irq_unmask,
	.irq_mask	= mpc8xxx_irq_mask,
	.irq_ack	= mpc8xxx_irq_ack,
	/* this might get overwritten in mpc8xxx_probe() */
	.irq_set_type	= mpc8xxx_irq_set_type,
};

static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
	.map	= mpc8xxx_gpio_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

struct mpc8xxx_gpio_devtype {
	int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
	int (*gpio_get)(struct gpio_chip *, unsigned int);
	int (*irq_set_type)(struct irq_data *, unsigned int);
};

static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	.gpio_dir_out = mpc5121_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	.gpio_dir_out = mpc5125_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	.gpio_get = mpc8572_gpio_get,
};

static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
	.gpio_dir_out = mpc8xxx_gpio_dir_out,
	.gpio_get = mpc8xxx_gpio_get,
	.irq_set_type = mpc8xxx_irq_set_type,
};

static const struct of_device_id mpc8xxx_gpio_ids[] = {
	{ .compatible = "fsl,mpc8349-gpio", },
	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
	{ .compatible = "fsl,mpc8610-gpio", },
	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
	{ .compatible = "fsl,pq3-gpio",     },
	{ .compatible = "fsl,qoriq-gpio",   },
	{}
};

static int mpc8xxx_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
	struct of_mm_gpio_chip *mm_gc;
	struct gpio_chip *gc;
	const struct of_device_id *id;
	const struct mpc8xxx_gpio_devtype *devtype =
		of_device_get_match_data(&pdev->dev);
	int ret;

	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	if (!mpc8xxx_gc)
		return -ENOMEM;

	platform_set_drvdata(pdev, mpc8xxx_gc);

	raw_spin_lock_init(&mpc8xxx_gc->lock);

	mm_gc = &mpc8xxx_gc->mm_gc;
	gc = &mm_gc->gc;

	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
	gc->ngpio = MPC8XXX_GPIO_PINS;
	gc->direction_input = mpc8xxx_gpio_dir_in;

	if (!devtype)
		devtype = &mpc8xxx_gpio_devtype_default;

	/*
	 * It's assumed that only a single type of gpio controller is available
	 * on the current machine, so overwriting global data is fine.
	 */
	mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;

	gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
	gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
	gc->set = mpc8xxx_gpio_set;
	gc->set_multiple = mpc8xxx_gpio_set_multiple;
	gc->to_irq = mpc8xxx_gpio_to_irq;

	ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc);
	if (ret)
		return ret;

	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
	if (mpc8xxx_gc->irqn == NO_IRQ)
		return 0;

	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
					&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
	if (!mpc8xxx_gc->irq)
		return 0;

	id = of_match_node(mpc8xxx_gpio_ids, np);
	if (id)
		mpc8xxx_gc->of_dev_id_data = id->data;

	/* ack and mask all irqs */
	out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
	out_be32(mm_gc->regs + GPIO_IMR, 0);

	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
					 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);

	return 0;
}

static int mpc8xxx_remove(struct platform_device *pdev)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);

	if (mpc8xxx_gc->irq) {
		irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
		irq_domain_remove(mpc8xxx_gc->irq);
	}

	of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);

	return 0;
}

static struct platform_driver mpc8xxx_plat_driver = {
	.probe		= mpc8xxx_probe,
	.remove		= mpc8xxx_remove,
	.driver		= {
		.name = "gpio-mpc8xxx",
		.of_match_table	= mpc8xxx_gpio_ids,
	},
};

static int __init mpc8xxx_init(void)
{
	return platform_driver_register(&mpc8xxx_plat_driver);
}

arch_initcall(mpc8xxx_init);
Commit	Line	Data
1e16dfc1	1	/*
e39d5ef6	2	* GPIOs on MPC512x/8349/8572/8610 and compatible
1e16dfc1 PK	3	*
	4	* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16	#include <linux/of_gpio.h>
5af50730	17	#include <linux/of_irq.h>
98686d9a	18	#include <linux/of_platform.h>
1e16dfc1	19	#include <linux/gpio.h>
5a0e3ad6	20	#include <linux/slab.h>
345e5c8a	21	#include <linux/irq.h>
1e16dfc1 PK	22
	23	#define MPC8XXX_GPIO_PINS 32
	24
	25	#define GPIO_DIR 0x00
	26	#define GPIO_ODR 0x04
	27	#define GPIO_DAT 0x08
	28	#define GPIO_IER 0x0c
	29	#define GPIO_IMR 0x10
	30	#define GPIO_ICR 0x14
e39d5ef6	31	#define GPIO_ICR2 0x18
1e16dfc1 PK	32
	33	struct mpc8xxx_gpio_chip {
	34	struct of_mm_gpio_chip mm_gc;
50593613	35	raw_spinlock_t lock;
1e16dfc1 PK	36
	37	/*
	38	* shadowed data register to be able to clear/set output pins in
	39	* open drain mode safely
	40	*/
	41	u32 data;
bae1d8f1	42	struct irq_domain *irq;
257e1075	43	unsigned int irqn;
01a04ddc	44	const void *of_dev_id_data;
1e16dfc1 PK	45	};
	46
	47	static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
	48	{
	49	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
	50	}
	51
1e16dfc1 PK	52	static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
1e16dfc1 PK	53	{
78179989 GR	54	struct mpc8xxx_gpio_chip *mpc8xxx_gc =
78179989 GR	55	container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
1e16dfc1 PK	56
	57	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
	58	}
	59
c1a676df FR	60	/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
	61	* defined as output cannot be determined by reading GPDAT register,
	62	* so we use shadow data register instead. The status of input pins
	63	* is determined by reading GPDAT register.
	64	*/
	65	static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	66	{
	67	u32 val;
	68	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
709d71a1	69	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1aeef303	70	u32 out_mask, out_shadow;
c1a676df	71
1aeef303	72	out_mask = in_be32(mm->regs + GPIO_DIR);
c1a676df	73
1aeef303 LG	74	val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
	75	out_shadow = mpc8xxx_gc->data & out_mask;
	76
c759174e	77	return !!((val \| out_shadow) & mpc8xxx_gpio2mask(gpio));
c1a676df FR	78	}
c1a676df FR	79
1e16dfc1 PK	80	static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	81	{
	82	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	83
	84	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
	85	}
	86
	87	static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	88	{
	89	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
709d71a1	90	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1e16dfc1 PK	91	unsigned long flags;
1e16dfc1 PK	92
50593613	93	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
1e16dfc1 PK	94
	95	if (val)
	96	mpc8xxx_gc->data \|= mpc8xxx_gpio2mask(gpio);
	97	else
	98	mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
	99
	100	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
	101
50593613	102	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
1e16dfc1 PK	103	}
1e16dfc1 PK	104
e5db3b33 RI	105	static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
	106	unsigned long mask, unsigned long bits)
	107	{
	108	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
709d71a1	109	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
e5db3b33 RI	110	unsigned long flags;
	111	int i;
	112
50593613	113	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
e5db3b33 RI	114
	115	for (i = 0; i < gc->ngpio; i++) {
	116	if (*mask == 0)
	117	break;
	118	if (__test_and_clear_bit(i, mask)) {
	119	if (test_bit(i, bits))
	120	mpc8xxx_gc->data \|= mpc8xxx_gpio2mask(i);
	121	else
	122	mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
	123	}
	124	}
	125
	126	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
	127
50593613	128	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e5db3b33 RI	129	}
e5db3b33 RI	130
1e16dfc1 PK	131	static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	132	{
	133	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
709d71a1	134	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1e16dfc1 PK	135	unsigned long flags;
1e16dfc1 PK	136
50593613	137	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
1e16dfc1 PK	138
	139	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
	140
50593613	141	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
1e16dfc1 PK	142
	143	return 0;
	144	}
	145
	146	static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	147	{
	148	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
709d71a1	149	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1e16dfc1 PK	150	unsigned long flags;
	151
	152	mpc8xxx_gpio_set(gc, gpio, val);
	153
50593613	154	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
1e16dfc1 PK	155
	156	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
	157
50593613	158	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
1e16dfc1 PK	159
	160	return 0;
	161	}
	162
28538df0 WS	163	static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	164	{
	165	/* GPIO 28..31 are input only on MPC5121 */
	166	if (gpio >= 28)
	167	return -EINVAL;
	168
	169	return mpc8xxx_gpio_dir_out(gc, gpio, val);
	170	}
	171
0ba69e08 UKK	172	static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	173	{
	174	/* GPIO 0..3 are input only on MPC5125 */
	175	if (gpio <= 3)
	176	return -EINVAL;
	177
	178	return mpc8xxx_gpio_dir_out(gc, gpio, val);
	179	}
	180
345e5c8a PK	181	static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
345e5c8a PK	182	{
709d71a1	183	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
345e5c8a PK	184
	185	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
	186	return irq_create_mapping(mpc8xxx_gc->irq, offset);
	187	else
	188	return -ENXIO;
	189	}
	190
bd0b9ac4	191	static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
345e5c8a	192	{
ec775d0e	193	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
cfadd838	194	struct irq_chip *chip = irq_desc_get_chip(desc);
345e5c8a PK	195	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	196	unsigned int mask;
	197
	198	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
	199	if (mask)
	200	generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
	201	32 - ffs(mask)));
d6de85e8 TG	202	if (chip->irq_eoi)
d6de85e8 TG	203	chip->irq_eoi(&desc->irq_data);
345e5c8a PK	204	}
345e5c8a PK	205
94347cb3	206	static void mpc8xxx_irq_unmask(struct irq_data *d)
345e5c8a	207	{
94347cb3	208	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
345e5c8a PK	209	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	210	unsigned long flags;
	211
50593613	212	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	213
476eb491	214	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
345e5c8a	215
50593613	216	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	217	}
345e5c8a PK	218
94347cb3	219	static void mpc8xxx_irq_mask(struct irq_data *d)
345e5c8a	220	{
94347cb3	221	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
345e5c8a PK	222	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	223	unsigned long flags;
	224
50593613	225	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	226
476eb491	227	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
345e5c8a	228
50593613	229	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	230	}
345e5c8a PK	231
94347cb3	232	static void mpc8xxx_irq_ack(struct irq_data *d)
345e5c8a	233	{
94347cb3	234	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
345e5c8a PK	235	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
345e5c8a PK	236
476eb491	237	out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
345e5c8a PK	238	}
345e5c8a PK	239
94347cb3	240	static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
345e5c8a	241	{
94347cb3	242	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
345e5c8a PK	243	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	244	unsigned long flags;
	245
	246	switch (flow_type) {
	247	case IRQ_TYPE_EDGE_FALLING:
50593613	248	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	249	setbits32(mm->regs + GPIO_ICR,
476eb491	250	mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
50593613	251	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	252	break;
	253
	254	case IRQ_TYPE_EDGE_BOTH:
50593613	255	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	256	clrbits32(mm->regs + GPIO_ICR,
476eb491	257	mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
50593613	258	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	259	break;
	260
	261	default:
	262	return -EINVAL;
	263	}
	264
	265	return 0;
	266	}
	267
94347cb3	268	static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
e39d5ef6	269	{
94347cb3	270	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
e39d5ef6	271	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
476eb491	272	unsigned long gpio = irqd_to_hwirq(d);
e39d5ef6 AG	273	void __iomem *reg;
	274	unsigned int shift;
	275	unsigned long flags;
	276
	277	if (gpio < 16) {
	278	reg = mm->regs + GPIO_ICR;
	279	shift = (15 - gpio) * 2;
	280	} else {
	281	reg = mm->regs + GPIO_ICR2;
	282	shift = (15 - (gpio % 16)) * 2;
	283	}
	284
	285	switch (flow_type) {
	286	case IRQ_TYPE_EDGE_FALLING:
	287	case IRQ_TYPE_LEVEL_LOW:
50593613	288	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
e39d5ef6	289	clrsetbits_be32(reg, 3 << shift, 2 << shift);
50593613	290	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	291	break;
	292
	293	case IRQ_TYPE_EDGE_RISING:
	294	case IRQ_TYPE_LEVEL_HIGH:
50593613	295	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
e39d5ef6	296	clrsetbits_be32(reg, 3 << shift, 1 << shift);
50593613	297	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	298	break;
	299
	300	case IRQ_TYPE_EDGE_BOTH:
50593613	301	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
e39d5ef6	302	clrbits32(reg, 3 << shift);
50593613	303	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	304	break;
	305
	306	default:
	307	return -EINVAL;
	308	}
	309
	310	return 0;
	311	}
	312
345e5c8a PK	313	static struct irq_chip mpc8xxx_irq_chip = {
345e5c8a PK	314	.name = "mpc8xxx-gpio",
94347cb3 LB	315	.irq_unmask = mpc8xxx_irq_unmask,
	316	.irq_mask = mpc8xxx_irq_mask,
	317	.irq_ack = mpc8xxx_irq_ack,
82e39b0d	318	/* this might get overwritten in mpc8xxx_probe() */
94347cb3	319	.irq_set_type = mpc8xxx_irq_set_type,
345e5c8a PK	320	};
345e5c8a PK	321
5ba17ae9 LW	322	static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
5ba17ae9 LW	323	irq_hw_number_t hwirq)
345e5c8a	324	{
5ba17ae9 LW	325	irq_set_chip_data(irq, h->host_data);
5ba17ae9 LW	326	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
345e5c8a PK	327
	328	return 0;
	329	}
	330
0b354dc4	331	static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
345e5c8a	332	.map = mpc8xxx_gpio_irq_map,
ff8c3ab8	333	.xlate = irq_domain_xlate_twocell,
345e5c8a PK	334	};
345e5c8a PK	335
82e39b0d UKK	336	struct mpc8xxx_gpio_devtype {
	337	int (gpio_dir_out)(struct gpio_chip , unsigned int, int);
	338	int (gpio_get)(struct gpio_chip , unsigned int);
	339	int (irq_set_type)(struct irq_data , unsigned int);
	340	};
	341
	342	static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	343	.gpio_dir_out = mpc5121_gpio_dir_out,
	344	.irq_set_type = mpc512x_irq_set_type,
	345	};
	346
0ba69e08 UKK	347	static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	348	.gpio_dir_out = mpc5125_gpio_dir_out,
	349	.irq_set_type = mpc512x_irq_set_type,
	350	};
	351
82e39b0d UKK	352	static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	353	.gpio_get = mpc8572_gpio_get,
	354	};
	355
	356	static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
	357	.gpio_dir_out = mpc8xxx_gpio_dir_out,
	358	.gpio_get = mpc8xxx_gpio_get,
	359	.irq_set_type = mpc8xxx_irq_set_type,
	360	};
	361
4183afef	362	static const struct of_device_id mpc8xxx_gpio_ids[] = {
e39d5ef6	363	{ .compatible = "fsl,mpc8349-gpio", },
82e39b0d	364	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
e39d5ef6	365	{ .compatible = "fsl,mpc8610-gpio", },
82e39b0d	366	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
0ba69e08	367	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
15a5148c	368	{ .compatible = "fsl,pq3-gpio", },
d1dcfbbb	369	{ .compatible = "fsl,qoriq-gpio", },
e39d5ef6 AG	370	{}
	371	};
	372
98686d9a	373	static int mpc8xxx_probe(struct platform_device *pdev)
1e16dfc1	374	{
98686d9a	375	struct device_node *np = pdev->dev.of_node;
1e16dfc1 PK	376	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
1e16dfc1 PK	377	struct of_mm_gpio_chip *mm_gc;
1e16dfc1	378	struct gpio_chip *gc;
e39d5ef6	379	const struct of_device_id *id;
82e39b0d UKK	380	const struct mpc8xxx_gpio_devtype *devtype =
82e39b0d UKK	381	of_device_get_match_data(&pdev->dev);
1e16dfc1 PK	382	int ret;
1e16dfc1 PK	383
98686d9a RRD	384	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	385	if (!mpc8xxx_gc)
	386	return -ENOMEM;
1e16dfc1	387
257e1075 RRD	388	platform_set_drvdata(pdev, mpc8xxx_gc);
257e1075 RRD	389
50593613	390	raw_spin_lock_init(&mpc8xxx_gc->lock);
1e16dfc1 PK	391
1e16dfc1 PK	392	mm_gc = &mpc8xxx_gc->mm_gc;
a19e3da5	393	gc = &mm_gc->gc;
1e16dfc1 PK	394
1e16dfc1 PK	395	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
1e16dfc1 PK	396	gc->ngpio = MPC8XXX_GPIO_PINS;
1e16dfc1 PK	397	gc->direction_input = mpc8xxx_gpio_dir_in;
82e39b0d UKK	398
	399	if (!devtype)
	400	devtype = &mpc8xxx_gpio_devtype_default;
	401
	402	/*
	403	* It's assumed that only a single type of gpio controller is available
	404	* on the current machine, so overwriting global data is fine.
	405	*/
	406	mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
	407
	408	gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
	409	gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
1e16dfc1	410	gc->set = mpc8xxx_gpio_set;
e5db3b33	411	gc->set_multiple = mpc8xxx_gpio_set_multiple;
345e5c8a	412	gc->to_irq = mpc8xxx_gpio_to_irq;
1e16dfc1	413
709d71a1	414	ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc);
1e16dfc1	415	if (ret)
98686d9a	416	return ret;
1e16dfc1	417
257e1075 RRD	418	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
257e1075 RRD	419	if (mpc8xxx_gc->irqn == NO_IRQ)
98686d9a	420	return 0;
345e5c8a	421
a8db8cf0 GL	422	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
a8db8cf0 GL	423	&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
345e5c8a	424	if (!mpc8xxx_gc->irq)
98686d9a	425	return 0;
345e5c8a	426
e39d5ef6 AG	427	id = of_match_node(mpc8xxx_gpio_ids, np);
	428	if (id)
	429	mpc8xxx_gc->of_dev_id_data = id->data;
	430
345e5c8a PK	431	/* ack and mask all irqs */
	432	out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
	433	out_be32(mm_gc->regs + GPIO_IMR, 0);
	434
05379818 TG	435	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
05379818 TG	436	mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
257e1075 RRD	437
	438	return 0;
	439	}
	440
	441	static int mpc8xxx_remove(struct platform_device *pdev)
	442	{
	443	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
	444
	445	if (mpc8xxx_gc->irq) {
05379818	446	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
257e1075 RRD	447	irq_domain_remove(mpc8xxx_gc->irq);
	448	}
	449
	450	of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
345e5c8a	451
98686d9a	452	return 0;
1e16dfc1 PK	453	}
1e16dfc1 PK	454
98686d9a RRD	455	static struct platform_driver mpc8xxx_plat_driver = {
98686d9a RRD	456	.probe = mpc8xxx_probe,
257e1075	457	.remove = mpc8xxx_remove,
98686d9a RRD	458	.driver = {
	459	.name = "gpio-mpc8xxx",
	460	.of_match_table = mpc8xxx_gpio_ids,
	461	},
	462	};
1e16dfc1	463
98686d9a RRD	464	static int __init mpc8xxx_init(void)
	465	{
	466	return platform_driver_register(&mpc8xxx_plat_driver);
1e16dfc1	467	}
98686d9a RRD	468
98686d9a RRD	469	arch_initcall(mpc8xxx_init);