Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 TKD |
31 | #define OFF_MODE 1 |
32 | ||
03e128ca C |
33 | static LIST_HEAD(omap_gpio_list); |
34 | ||
6d62e216 C |
35 | struct gpio_regs { |
36 | u32 irqenable1; | |
37 | u32 irqenable2; | |
38 | u32 wake_en; | |
39 | u32 ctrl; | |
40 | u32 oe; | |
41 | u32 leveldetect0; | |
42 | u32 leveldetect1; | |
43 | u32 risingdetect; | |
44 | u32 fallingdetect; | |
45 | u32 dataout; | |
ae547354 NM |
46 | u32 debounce; |
47 | u32 debounce_en; | |
6d62e216 C |
48 | }; |
49 | ||
5e1c5ff4 | 50 | struct gpio_bank { |
03e128ca | 51 | struct list_head node; |
92105bb7 | 52 | void __iomem *base; |
5e1c5ff4 | 53 | u16 irq; |
3ac4fa99 JY |
54 | u32 non_wakeup_gpios; |
55 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 56 | struct gpio_regs context; |
3ac4fa99 | 57 | u32 saved_datain; |
b144ff6f | 58 | u32 level_mask; |
4318f36b | 59 | u32 toggle_mask; |
5e1c5ff4 | 60 | spinlock_t lock; |
52e31344 | 61 | struct gpio_chip chip; |
89db9482 | 62 | struct clk *dbck; |
058af1ea | 63 | u32 mod_usage; |
fa365e4d | 64 | u32 irq_usage; |
8865b9b6 | 65 | u32 dbck_enable_mask; |
72f83af9 | 66 | bool dbck_enabled; |
77640aab | 67 | struct device *dev; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
2dc983c5 TKD |
75 | int power_mode; |
76 | bool workaround_enabled; | |
fa87931a | 77 | |
04ebcbd8 | 78 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 79 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
80 | |
81 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
82 | }; |
83 | ||
c8eef65a | 84 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 85 | |
fa365e4d | 86 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 87 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 88 | |
3d009c8c TL |
89 | static void omap_gpio_unmask_irq(struct irq_data *d); |
90 | ||
a0e827c6 | 91 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 92 | { |
fb655f57 JMC |
93 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
94 | return container_of(chip, struct gpio_bank, chip); | |
25db711d BC |
95 | } |
96 | ||
a0e827c6 JMC |
97 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
98 | int is_input) | |
5e1c5ff4 | 99 | { |
92105bb7 | 100 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
101 | u32 l; |
102 | ||
fa87931a | 103 | reg += bank->regs->direction; |
661553b9 | 104 | l = readl_relaxed(reg); |
5e1c5ff4 | 105 | if (is_input) |
b1e9fec2 | 106 | l |= BIT(gpio); |
5e1c5ff4 | 107 | else |
b1e9fec2 | 108 | l &= ~(BIT(gpio)); |
661553b9 | 109 | writel_relaxed(l, reg); |
41d87cbd | 110 | bank->context.oe = l; |
5e1c5ff4 TL |
111 | } |
112 | ||
fa87931a KH |
113 | |
114 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 115 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 116 | int enable) |
5e1c5ff4 | 117 | { |
92105bb7 | 118 | void __iomem *reg = bank->base; |
04ebcbd8 | 119 | u32 l = BIT(offset); |
5e1c5ff4 | 120 | |
2c836f7e | 121 | if (enable) { |
fa87931a | 122 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
123 | bank->context.dataout |= l; |
124 | } else { | |
fa87931a | 125 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
126 | bank->context.dataout &= ~l; |
127 | } | |
5e1c5ff4 | 128 | |
661553b9 | 129 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
130 | } |
131 | ||
fa87931a | 132 | /* set data out value using mask register */ |
04ebcbd8 | 133 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 134 | int enable) |
5e1c5ff4 | 135 | { |
fa87931a | 136 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 137 | u32 gpio_bit = BIT(offset); |
fa87931a | 138 | u32 l; |
5e1c5ff4 | 139 | |
661553b9 | 140 | l = readl_relaxed(reg); |
fa87931a KH |
141 | if (enable) |
142 | l |= gpio_bit; | |
143 | else | |
144 | l &= ~gpio_bit; | |
661553b9 | 145 | writel_relaxed(l, reg); |
41d87cbd | 146 | bank->context.dataout = l; |
5e1c5ff4 TL |
147 | } |
148 | ||
a0e827c6 | 149 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 150 | { |
fa87931a | 151 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 152 | |
b1e9fec2 | 153 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 154 | } |
b37c45b8 | 155 | |
a0e827c6 | 156 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 157 | { |
fa87931a | 158 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 159 | |
b1e9fec2 | 160 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
161 | } |
162 | ||
a0e827c6 | 163 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 164 | { |
661553b9 | 165 | int l = readl_relaxed(base + reg); |
ece9528e | 166 | |
862ff640 | 167 | if (set) |
ece9528e KH |
168 | l |= mask; |
169 | else | |
170 | l &= ~mask; | |
171 | ||
661553b9 | 172 | writel_relaxed(l, base + reg); |
ece9528e | 173 | } |
92105bb7 | 174 | |
a0e827c6 | 175 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
176 | { |
177 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
345477ff | 178 | clk_prepare_enable(bank->dbck); |
72f83af9 | 179 | bank->dbck_enabled = true; |
9e303f22 | 180 | |
661553b9 | 181 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 182 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
183 | } |
184 | } | |
185 | ||
a0e827c6 | 186 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
187 | { |
188 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
189 | /* |
190 | * Disable debounce before cutting it's clock. If debounce is | |
191 | * enabled but the clock is not, GPIO module seems to be unable | |
192 | * to detect events and generate interrupts at least on OMAP3. | |
193 | */ | |
661553b9 | 194 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 195 | |
345477ff | 196 | clk_disable_unprepare(bank->dbck); |
72f83af9 TKD |
197 | bank->dbck_enabled = false; |
198 | } | |
199 | } | |
200 | ||
168ef3d9 | 201 | /** |
a0e827c6 | 202 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 203 | * @bank: the gpio bank we're acting upon |
4a58d229 | 204 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
205 | * @debounce: debounce time to use |
206 | * | |
207 | * OMAP's debounce time is in 31us steps so we need | |
208 | * to convert and round up to the closest unit. | |
209 | */ | |
4a58d229 | 210 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 211 | unsigned debounce) |
168ef3d9 | 212 | { |
9942da0e | 213 | void __iomem *reg; |
168ef3d9 FB |
214 | u32 val; |
215 | u32 l; | |
216 | ||
77640aab VC |
217 | if (!bank->dbck_flag) |
218 | return; | |
219 | ||
168ef3d9 FB |
220 | if (debounce < 32) |
221 | debounce = 0x01; | |
222 | else if (debounce > 7936) | |
223 | debounce = 0xff; | |
224 | else | |
225 | debounce = (debounce / 0x1f) - 1; | |
226 | ||
4a58d229 | 227 | l = BIT(offset); |
168ef3d9 | 228 | |
345477ff | 229 | clk_prepare_enable(bank->dbck); |
9942da0e | 230 | reg = bank->base + bank->regs->debounce; |
661553b9 | 231 | writel_relaxed(debounce, reg); |
168ef3d9 | 232 | |
9942da0e | 233 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 234 | val = readl_relaxed(reg); |
168ef3d9 | 235 | |
6fd9c421 | 236 | if (debounce) |
168ef3d9 | 237 | val |= l; |
6fd9c421 | 238 | else |
168ef3d9 | 239 | val &= ~l; |
f7ec0b0b | 240 | bank->dbck_enable_mask = val; |
168ef3d9 | 241 | |
661553b9 | 242 | writel_relaxed(val, reg); |
345477ff | 243 | clk_disable_unprepare(bank->dbck); |
6fd9c421 TKD |
244 | /* |
245 | * Enable debounce clock per module. | |
246 | * This call is mandatory because in omap_gpio_request() when | |
247 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
248 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
249 | * used within _gpio_dbck_enable() is still not initialized at | |
250 | * that point. Therefore we have to enable dbck here. | |
251 | */ | |
a0e827c6 | 252 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
253 | if (bank->dbck_enable_mask) { |
254 | bank->context.debounce = debounce; | |
255 | bank->context.debounce_en = val; | |
256 | } | |
168ef3d9 FB |
257 | } |
258 | ||
c9c55d92 | 259 | /** |
a0e827c6 | 260 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 261 | * @bank: the gpio bank we're acting upon |
4a58d229 | 262 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
263 | * |
264 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
265 | * this is the only gpio in this bank using debounce, then clear the debounce | |
266 | * time too. The debounce clock will also be disabled when calling this function | |
267 | * if this is the only gpio in the bank using debounce. | |
268 | */ | |
4a58d229 | 269 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 270 | { |
4a58d229 | 271 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
272 | |
273 | if (!bank->dbck_flag) | |
274 | return; | |
275 | ||
276 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
277 | return; | |
278 | ||
279 | bank->dbck_enable_mask &= ~gpio_bit; | |
280 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 281 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
282 | bank->base + bank->regs->debounce_en); |
283 | ||
284 | if (!bank->dbck_enable_mask) { | |
285 | bank->context.debounce = 0; | |
661553b9 | 286 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 287 | bank->regs->debounce); |
345477ff | 288 | clk_disable_unprepare(bank->dbck); |
c9c55d92 JH |
289 | bank->dbck_enabled = false; |
290 | } | |
291 | } | |
292 | ||
a0e827c6 | 293 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 294 | unsigned trigger) |
5e1c5ff4 | 295 | { |
3ac4fa99 | 296 | void __iomem *base = bank->base; |
b1e9fec2 | 297 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 298 | |
a0e827c6 JMC |
299 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
300 | trigger & IRQ_TYPE_LEVEL_LOW); | |
301 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
302 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
303 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
304 | trigger & IRQ_TYPE_EDGE_RISING); | |
305 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
306 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 307 | |
41d87cbd | 308 | bank->context.leveldetect0 = |
661553b9 | 309 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 310 | bank->context.leveldetect1 = |
661553b9 | 311 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 312 | bank->context.risingdetect = |
661553b9 | 313 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 314 | bank->context.fallingdetect = |
661553b9 | 315 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
316 | |
317 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 318 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 319 | bank->context.wake_en = |
661553b9 | 320 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 321 | } |
5e571f38 | 322 | |
55b220ca | 323 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
324 | if (!bank->regs->irqctrl) { |
325 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
326 | if (bank->non_wakeup_gpios) { | |
327 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
328 | goto exit; | |
329 | } | |
330 | ||
699117a6 CW |
331 | /* |
332 | * Log the edge gpio and manually trigger the IRQ | |
333 | * after resume if the input level changes | |
334 | * to avoid irq lost during PER RET/OFF mode | |
335 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
336 | */ | |
337 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
338 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
339 | else | |
340 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
341 | } | |
5eb3bb9c | 342 | |
5e571f38 | 343 | exit: |
9ea14d8c | 344 | bank->level_mask = |
661553b9 VK |
345 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
346 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
347 | } |
348 | ||
9198bcd3 | 349 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
350 | /* |
351 | * This only applies to chips that can't do both rising and falling edge | |
352 | * detection at once. For all other chips, this function is a noop. | |
353 | */ | |
a0e827c6 | 354 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
355 | { |
356 | void __iomem *reg = bank->base; | |
357 | u32 l = 0; | |
358 | ||
5e571f38 | 359 | if (!bank->regs->irqctrl) |
4318f36b | 360 | return; |
5e571f38 TKD |
361 | |
362 | reg += bank->regs->irqctrl; | |
4318f36b | 363 | |
661553b9 | 364 | l = readl_relaxed(reg); |
4318f36b | 365 | if ((l >> gpio) & 1) |
b1e9fec2 | 366 | l &= ~(BIT(gpio)); |
4318f36b | 367 | else |
b1e9fec2 | 368 | l |= BIT(gpio); |
4318f36b | 369 | |
661553b9 | 370 | writel_relaxed(l, reg); |
4318f36b | 371 | } |
5e571f38 | 372 | #else |
a0e827c6 | 373 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 374 | #endif |
4318f36b | 375 | |
a0e827c6 JMC |
376 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
377 | unsigned trigger) | |
92105bb7 TL |
378 | { |
379 | void __iomem *reg = bank->base; | |
5e571f38 | 380 | void __iomem *base = bank->base; |
92105bb7 | 381 | u32 l = 0; |
5e1c5ff4 | 382 | |
5e571f38 | 383 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 384 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
385 | } else if (bank->regs->irqctrl) { |
386 | reg += bank->regs->irqctrl; | |
387 | ||
661553b9 | 388 | l = readl_relaxed(reg); |
29501577 | 389 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 390 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 391 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 392 | l |= BIT(gpio); |
6cab4860 | 393 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 394 | l &= ~(BIT(gpio)); |
92105bb7 | 395 | else |
5e571f38 TKD |
396 | return -EINVAL; |
397 | ||
661553b9 | 398 | writel_relaxed(l, reg); |
5e571f38 | 399 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 400 | if (gpio & 0x08) |
5e571f38 | 401 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 402 | else |
5e571f38 TKD |
403 | reg += bank->regs->edgectrl1; |
404 | ||
5e1c5ff4 | 405 | gpio &= 0x07; |
661553b9 | 406 | l = readl_relaxed(reg); |
5e1c5ff4 | 407 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 408 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 409 | l |= 2 << (gpio << 1); |
6cab4860 | 410 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 411 | l |= BIT(gpio << 1); |
5e571f38 TKD |
412 | |
413 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 414 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 415 | bank->context.wake_en = |
661553b9 VK |
416 | readl_relaxed(bank->base + bank->regs->wkup_en); |
417 | writel_relaxed(l, reg); | |
5e1c5ff4 | 418 | } |
92105bb7 | 419 | return 0; |
5e1c5ff4 TL |
420 | } |
421 | ||
a0e827c6 | 422 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
423 | { |
424 | if (bank->regs->pinctrl) { | |
425 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
426 | ||
427 | /* Claim the pin for MPU */ | |
b1e9fec2 | 428 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
429 | } |
430 | ||
431 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
432 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
433 | u32 ctrl; | |
434 | ||
661553b9 | 435 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
436 | /* Module is enabled, clocks are not gated */ |
437 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 438 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
439 | bank->context.ctrl = ctrl; |
440 | } | |
441 | } | |
442 | ||
a0e827c6 | 443 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
444 | { |
445 | void __iomem *base = bank->base; | |
446 | ||
447 | if (bank->regs->wkup_en && | |
448 | !LINE_USED(bank->mod_usage, offset) && | |
449 | !LINE_USED(bank->irq_usage, offset)) { | |
450 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 451 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 452 | bank->context.wake_en = |
661553b9 | 453 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
454 | } |
455 | ||
456 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
457 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
458 | u32 ctrl; | |
459 | ||
661553b9 | 460 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
461 | /* Module is disabled, clocks are gated */ |
462 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 463 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
464 | bank->context.ctrl = ctrl; |
465 | } | |
466 | } | |
467 | ||
b2b20045 | 468 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
469 | { |
470 | void __iomem *reg = bank->base + bank->regs->direction; | |
471 | ||
b2b20045 | 472 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
473 | } |
474 | ||
37e14ecf | 475 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
476 | { |
477 | if (!LINE_USED(bank->mod_usage, offset)) { | |
478 | omap_enable_gpio_module(bank, offset); | |
479 | omap_set_gpio_direction(bank, offset, 1); | |
480 | } | |
37e14ecf | 481 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
482 | } |
483 | ||
a0e827c6 | 484 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 485 | { |
a0e827c6 | 486 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 487 | int retval; |
a6472533 | 488 | unsigned long flags; |
ea5fbe8d | 489 | unsigned offset = d->hwirq; |
92105bb7 | 490 | |
e5c56ed3 | 491 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 492 | return -EINVAL; |
e5c56ed3 | 493 | |
9ea14d8c TKD |
494 | if (!bank->regs->leveldetect0 && |
495 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
496 | return -EINVAL; |
497 | ||
1562e461 GS |
498 | if (!BANK_USED(bank)) |
499 | pm_runtime_get_sync(bank->dev); | |
500 | ||
a6472533 | 501 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 502 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 GS |
503 | if (retval) { |
504 | spin_unlock_irqrestore(&bank->lock, flags); | |
1562e461 | 505 | goto error; |
977bd8a9 | 506 | } |
37e14ecf | 507 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 508 | if (!omap_gpio_is_input(bank, offset)) { |
fac7fa16 | 509 | spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
510 | retval = -EINVAL; |
511 | goto error; | |
fac7fa16 | 512 | } |
a6472533 | 513 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
514 | |
515 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 516 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 517 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 518 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 519 | |
1562e461 GS |
520 | return 0; |
521 | ||
522 | error: | |
523 | if (!BANK_USED(bank)) | |
524 | pm_runtime_put(bank->dev); | |
92105bb7 | 525 | return retval; |
5e1c5ff4 TL |
526 | } |
527 | ||
a0e827c6 | 528 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 529 | { |
92105bb7 | 530 | void __iomem *reg = bank->base; |
5e1c5ff4 | 531 | |
eef4bec7 | 532 | reg += bank->regs->irqstatus; |
661553b9 | 533 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
534 | |
535 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
536 | if (bank->regs->irqstatus2) { |
537 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 538 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 539 | } |
bedfd154 RQ |
540 | |
541 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 542 | readl_relaxed(reg); |
5e1c5ff4 TL |
543 | } |
544 | ||
9943f261 GS |
545 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
546 | unsigned offset) | |
5e1c5ff4 | 547 | { |
9943f261 | 548 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
549 | } |
550 | ||
a0e827c6 | 551 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
552 | { |
553 | void __iomem *reg = bank->base; | |
99c47707 | 554 | u32 l; |
b1e9fec2 | 555 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 556 | |
28f3b5a0 | 557 | reg += bank->regs->irqenable; |
661553b9 | 558 | l = readl_relaxed(reg); |
28f3b5a0 | 559 | if (bank->regs->irqenable_inv) |
99c47707 ID |
560 | l = ~l; |
561 | l &= mask; | |
562 | return l; | |
ea6dedd7 ID |
563 | } |
564 | ||
a0e827c6 | 565 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 566 | { |
92105bb7 | 567 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
568 | u32 l; |
569 | ||
28f3b5a0 KH |
570 | if (bank->regs->set_irqenable) { |
571 | reg += bank->regs->set_irqenable; | |
572 | l = gpio_mask; | |
2a900eb7 | 573 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
574 | } else { |
575 | reg += bank->regs->irqenable; | |
661553b9 | 576 | l = readl_relaxed(reg); |
28f3b5a0 KH |
577 | if (bank->regs->irqenable_inv) |
578 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
579 | else |
580 | l |= gpio_mask; | |
2a900eb7 | 581 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
582 | } |
583 | ||
661553b9 | 584 | writel_relaxed(l, reg); |
28f3b5a0 KH |
585 | } |
586 | ||
a0e827c6 | 587 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
588 | { |
589 | void __iomem *reg = bank->base; | |
590 | u32 l; | |
591 | ||
592 | if (bank->regs->clr_irqenable) { | |
593 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 594 | l = gpio_mask; |
2a900eb7 | 595 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
596 | } else { |
597 | reg += bank->regs->irqenable; | |
661553b9 | 598 | l = readl_relaxed(reg); |
28f3b5a0 | 599 | if (bank->regs->irqenable_inv) |
56739a69 | 600 | l |= gpio_mask; |
92105bb7 | 601 | else |
28f3b5a0 | 602 | l &= ~gpio_mask; |
2a900eb7 | 603 | bank->context.irqenable1 = l; |
5e1c5ff4 | 604 | } |
28f3b5a0 | 605 | |
661553b9 | 606 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
607 | } |
608 | ||
9943f261 GS |
609 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
610 | unsigned offset, int enable) | |
5e1c5ff4 | 611 | { |
8276536c | 612 | if (enable) |
9943f261 | 613 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 614 | else |
9943f261 | 615 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
616 | } |
617 | ||
92105bb7 TL |
618 | /* |
619 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
620 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
621 | * to the target, system will wake up always on GPIO events. While | |
622 | * system is running all registered GPIO interrupts need to have wake-up | |
623 | * enabled. When system is suspended, only selected GPIO interrupts need | |
624 | * to have wake-up enabled. | |
625 | */ | |
9943f261 GS |
626 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, |
627 | int enable) | |
92105bb7 | 628 | { |
9943f261 | 629 | u32 gpio_bit = BIT(offset); |
f64ad1a0 | 630 | unsigned long flags; |
a6472533 | 631 | |
f64ad1a0 | 632 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 633 | dev_err(bank->dev, |
9943f261 GS |
634 | "Unable to modify wakeup on non-wakeup GPIO%d\n", |
635 | offset); | |
92105bb7 TL |
636 | return -EINVAL; |
637 | } | |
f64ad1a0 KH |
638 | |
639 | spin_lock_irqsave(&bank->lock, flags); | |
640 | if (enable) | |
0aa27273 | 641 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 642 | else |
0aa27273 | 643 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 644 | |
661553b9 | 645 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
646 | spin_unlock_irqrestore(&bank->lock, flags); |
647 | ||
648 | return 0; | |
92105bb7 TL |
649 | } |
650 | ||
651 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ | |
a0e827c6 | 652 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 653 | { |
a0e827c6 | 654 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 655 | unsigned offset = d->hwirq; |
92105bb7 | 656 | |
9943f261 | 657 | return omap_set_gpio_wakeup(bank, offset, enable); |
92105bb7 TL |
658 | } |
659 | ||
3ff164e1 | 660 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 661 | { |
3ff164e1 | 662 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 663 | unsigned long flags; |
52e31344 | 664 | |
55b93c32 TKD |
665 | /* |
666 | * If this is the first gpio_request for the bank, | |
667 | * enable the bank module. | |
668 | */ | |
fa365e4d | 669 | if (!BANK_USED(bank)) |
55b93c32 | 670 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 671 | |
55b93c32 | 672 | spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 673 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 674 | bank->mod_usage |= BIT(offset); |
a6472533 | 675 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
676 | |
677 | return 0; | |
678 | } | |
679 | ||
3ff164e1 | 680 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 681 | { |
3ff164e1 | 682 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 683 | unsigned long flags; |
5e1c5ff4 | 684 | |
a6472533 | 685 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 686 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
687 | if (!LINE_USED(bank->irq_usage, offset)) { |
688 | omap_set_gpio_direction(bank, offset, 1); | |
689 | omap_clear_gpio_debounce(bank, offset); | |
690 | } | |
a0e827c6 | 691 | omap_disable_gpio_module(bank, offset); |
a6472533 | 692 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
693 | |
694 | /* | |
695 | * If this is the last gpio to be freed in the bank, | |
696 | * disable the bank module. | |
697 | */ | |
fa365e4d | 698 | if (!BANK_USED(bank)) |
55b93c32 | 699 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
700 | } |
701 | ||
702 | /* | |
703 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
704 | * avoid missing GPIO interrupts for other lines in the bank. | |
705 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
706 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
707 | * If we wait to unmask individual GPIO lines in the bank after the | |
708 | * line's interrupt handler has been run, we may miss some nested | |
709 | * interrupts. | |
710 | */ | |
a0e827c6 | 711 | static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 712 | { |
92105bb7 | 713 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 714 | u32 isr; |
3513cdec | 715 | unsigned int bit; |
5e1c5ff4 | 716 | struct gpio_bank *bank; |
ea6dedd7 | 717 | int unmasked = 0; |
fb655f57 JMC |
718 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
719 | struct gpio_chip *chip = irq_get_handler_data(irq); | |
5e1c5ff4 | 720 | |
fb655f57 | 721 | chained_irq_enter(irqchip, desc); |
5e1c5ff4 | 722 | |
fb655f57 | 723 | bank = container_of(chip, struct gpio_bank, chip); |
eef4bec7 | 724 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 725 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
726 | |
727 | if (WARN_ON(!isr_reg)) | |
728 | goto exit; | |
729 | ||
e83507b7 | 730 | while (1) { |
6e60e79a | 731 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 732 | u32 enabled; |
6e60e79a | 733 | |
a0e827c6 | 734 | enabled = omap_get_gpio_irqbank_mask(bank); |
661553b9 | 735 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 736 | |
9ea14d8c | 737 | if (bank->level_mask) |
b144ff6f | 738 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
739 | |
740 | /* clear edge sensitive interrupts before handler(s) are | |
741 | called so that we don't miss any interrupt occurred while | |
742 | executing them */ | |
a0e827c6 JMC |
743 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
744 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
745 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); | |
6e60e79a TL |
746 | |
747 | /* if there is only edge sensitive GPIO pin interrupts | |
748 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
749 | if (!level_mask && !unmasked) { |
750 | unmasked = 1; | |
fb655f57 | 751 | chained_irq_exit(irqchip, desc); |
ea6dedd7 | 752 | } |
92105bb7 TL |
753 | |
754 | if (!isr) | |
755 | break; | |
756 | ||
3513cdec JH |
757 | while (isr) { |
758 | bit = __ffs(isr); | |
b1e9fec2 | 759 | isr &= ~(BIT(bit)); |
25db711d | 760 | |
4318f36b CM |
761 | /* |
762 | * Some chips can't respond to both rising and falling | |
763 | * at the same time. If this irq was requested with | |
764 | * both flags, we need to flip the ICR data for the IRQ | |
765 | * to respond to the IRQ for the opposite direction. | |
766 | * This will be indicated in the bank toggle_mask. | |
767 | */ | |
b1e9fec2 | 768 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 769 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 770 | |
fb655f57 JMC |
771 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
772 | bit)); | |
92105bb7 | 773 | } |
1a8bfa1e | 774 | } |
ea6dedd7 ID |
775 | /* if bank has any level sensitive GPIO pin interrupt |
776 | configured, we must unmask the bank interrupt only after | |
777 | handler(s) are executed in order to avoid spurious bank | |
778 | interrupt */ | |
b1cc4c55 | 779 | exit: |
ea6dedd7 | 780 | if (!unmasked) |
fb655f57 | 781 | chained_irq_exit(irqchip, desc); |
55b93c32 | 782 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
783 | } |
784 | ||
3d009c8c TL |
785 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
786 | { | |
787 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 788 | unsigned long flags; |
37e14ecf | 789 | unsigned offset = d->hwirq; |
3d009c8c TL |
790 | |
791 | if (!BANK_USED(bank)) | |
792 | pm_runtime_get_sync(bank->dev); | |
793 | ||
794 | spin_lock_irqsave(&bank->lock, flags); | |
121dcb76 GS |
795 | |
796 | if (!LINE_USED(bank->mod_usage, offset)) | |
797 | omap_set_gpio_direction(bank, offset, 1); | |
798 | else if (!omap_gpio_is_input(bank, offset)) | |
799 | goto err; | |
800 | omap_enable_gpio_module(bank, offset); | |
801 | bank->irq_usage |= BIT(offset); | |
802 | ||
3d009c8c TL |
803 | spin_unlock_irqrestore(&bank->lock, flags); |
804 | omap_gpio_unmask_irq(d); | |
805 | ||
806 | return 0; | |
121dcb76 GS |
807 | err: |
808 | spin_unlock_irqrestore(&bank->lock, flags); | |
809 | if (!BANK_USED(bank)) | |
810 | pm_runtime_put(bank->dev); | |
811 | return -EINVAL; | |
3d009c8c TL |
812 | } |
813 | ||
a0e827c6 | 814 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 815 | { |
a0e827c6 | 816 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 817 | unsigned long flags; |
9943f261 | 818 | unsigned offset = d->hwirq; |
4196dd6b | 819 | |
85ec7b97 | 820 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 821 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
822 | omap_set_gpio_irqenable(bank, offset, 0); |
823 | omap_clear_gpio_irqstatus(bank, offset); | |
824 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
825 | if (!LINE_USED(bank->mod_usage, offset)) | |
826 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 827 | omap_disable_gpio_module(bank, offset); |
85ec7b97 | 828 | spin_unlock_irqrestore(&bank->lock, flags); |
fac7fa16 JMC |
829 | |
830 | /* | |
831 | * If this is the last IRQ to be freed in the bank, | |
832 | * disable the bank module. | |
833 | */ | |
834 | if (!BANK_USED(bank)) | |
835 | pm_runtime_put(bank->dev); | |
4196dd6b TL |
836 | } |
837 | ||
a0e827c6 | 838 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 839 | { |
a0e827c6 | 840 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 841 | unsigned offset = d->hwirq; |
5e1c5ff4 | 842 | |
9943f261 | 843 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
844 | } |
845 | ||
a0e827c6 | 846 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 847 | { |
a0e827c6 | 848 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 849 | unsigned offset = d->hwirq; |
85ec7b97 | 850 | unsigned long flags; |
5e1c5ff4 | 851 | |
85ec7b97 | 852 | spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
853 | omap_set_gpio_irqenable(bank, offset, 0); |
854 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
85ec7b97 | 855 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
856 | } |
857 | ||
a0e827c6 | 858 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 859 | { |
a0e827c6 | 860 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 861 | unsigned offset = d->hwirq; |
8c04a176 | 862 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 863 | unsigned long flags; |
55b6019a | 864 | |
85ec7b97 | 865 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 866 | if (trigger) |
9943f261 | 867 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f KH |
868 | |
869 | /* For level-triggered GPIOs, the clearing must be done after | |
870 | * the HW source is cleared, thus after the handler has run */ | |
9943f261 GS |
871 | if (bank->level_mask & BIT(offset)) { |
872 | omap_set_gpio_irqenable(bank, offset, 0); | |
873 | omap_clear_gpio_irqstatus(bank, offset); | |
b144ff6f | 874 | } |
5e1c5ff4 | 875 | |
9943f261 | 876 | omap_set_gpio_irqenable(bank, offset, 1); |
85ec7b97 | 877 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
878 | } |
879 | ||
e5c56ed3 DB |
880 | /*---------------------------------------------------------------------*/ |
881 | ||
79ee031f | 882 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 883 | { |
79ee031f | 884 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 885 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
886 | void __iomem *mask_reg = bank->base + |
887 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 888 | unsigned long flags; |
11a78b79 | 889 | |
a6472533 | 890 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 891 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 892 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
893 | |
894 | return 0; | |
895 | } | |
896 | ||
79ee031f | 897 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 898 | { |
79ee031f | 899 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 900 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
901 | void __iomem *mask_reg = bank->base + |
902 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 903 | unsigned long flags; |
11a78b79 | 904 | |
a6472533 | 905 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 906 | writel_relaxed(bank->context.wake_en, mask_reg); |
a6472533 | 907 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
908 | |
909 | return 0; | |
910 | } | |
911 | ||
47145210 | 912 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
913 | .suspend_noirq = omap_mpuio_suspend_noirq, |
914 | .resume_noirq = omap_mpuio_resume_noirq, | |
915 | }; | |
916 | ||
3c437ffd | 917 | /* use platform_driver for this. */ |
11a78b79 | 918 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
919 | .driver = { |
920 | .name = "mpuio", | |
79ee031f | 921 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
922 | }, |
923 | }; | |
924 | ||
925 | static struct platform_device omap_mpuio_device = { | |
926 | .name = "mpuio", | |
927 | .id = -1, | |
928 | .dev = { | |
929 | .driver = &omap_mpuio_driver.driver, | |
930 | } | |
931 | /* could list the /proc/iomem resources */ | |
932 | }; | |
933 | ||
a0e827c6 | 934 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 935 | { |
77640aab | 936 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 937 | |
11a78b79 DB |
938 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
939 | (void) platform_device_register(&omap_mpuio_device); | |
940 | } | |
941 | ||
e5c56ed3 | 942 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 943 | |
a0e827c6 | 944 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
945 | { |
946 | struct gpio_bank *bank; | |
947 | unsigned long flags; | |
948 | void __iomem *reg; | |
949 | int dir; | |
950 | ||
951 | bank = container_of(chip, struct gpio_bank, chip); | |
952 | reg = bank->base + bank->regs->direction; | |
953 | spin_lock_irqsave(&bank->lock, flags); | |
954 | dir = !!(readl_relaxed(reg) & BIT(offset)); | |
955 | spin_unlock_irqrestore(&bank->lock, flags); | |
956 | return dir; | |
957 | } | |
958 | ||
a0e827c6 | 959 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
960 | { |
961 | struct gpio_bank *bank; | |
962 | unsigned long flags; | |
963 | ||
964 | bank = container_of(chip, struct gpio_bank, chip); | |
965 | spin_lock_irqsave(&bank->lock, flags); | |
a0e827c6 | 966 | omap_set_gpio_direction(bank, offset, 1); |
52e31344 DB |
967 | spin_unlock_irqrestore(&bank->lock, flags); |
968 | return 0; | |
969 | } | |
970 | ||
a0e827c6 | 971 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 972 | { |
b37c45b8 | 973 | struct gpio_bank *bank; |
b37c45b8 | 974 | |
a8be8daf | 975 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 976 | |
b2b20045 | 977 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 978 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 979 | else |
a0e827c6 | 980 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
981 | } |
982 | ||
a0e827c6 | 983 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
984 | { |
985 | struct gpio_bank *bank; | |
986 | unsigned long flags; | |
987 | ||
988 | bank = container_of(chip, struct gpio_bank, chip); | |
989 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 990 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 991 | omap_set_gpio_direction(bank, offset, 0); |
52e31344 | 992 | spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 993 | return 0; |
52e31344 DB |
994 | } |
995 | ||
a0e827c6 JMC |
996 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
997 | unsigned debounce) | |
168ef3d9 FB |
998 | { |
999 | struct gpio_bank *bank; | |
1000 | unsigned long flags; | |
1001 | ||
1002 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 1003 | |
168ef3d9 | 1004 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 1005 | omap2_set_gpio_debounce(bank, offset, debounce); |
168ef3d9 FB |
1006 | spin_unlock_irqrestore(&bank->lock, flags); |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
a0e827c6 | 1011 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1012 | { |
1013 | struct gpio_bank *bank; | |
1014 | unsigned long flags; | |
1015 | ||
1016 | bank = container_of(chip, struct gpio_bank, chip); | |
1017 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1018 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1019 | spin_unlock_irqrestore(&bank->lock, flags); |
1020 | } | |
1021 | ||
1022 | /*---------------------------------------------------------------------*/ | |
1023 | ||
9a748053 | 1024 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1025 | { |
e5ff4440 | 1026 | static bool called; |
9f7065da TL |
1027 | u32 rev; |
1028 | ||
e5ff4440 | 1029 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1030 | return; |
1031 | ||
661553b9 | 1032 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1033 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1034 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1035 | |
1036 | called = true; | |
9f7065da TL |
1037 | } |
1038 | ||
03e128ca | 1039 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1040 | { |
ab985f0f TKD |
1041 | void __iomem *base = bank->base; |
1042 | u32 l = 0xffffffff; | |
2fae7fbe | 1043 | |
ab985f0f TKD |
1044 | if (bank->width == 16) |
1045 | l = 0xffff; | |
1046 | ||
d0d665a8 | 1047 | if (bank->is_mpuio) { |
661553b9 | 1048 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1049 | return; |
2fae7fbe | 1050 | } |
ab985f0f | 1051 | |
a0e827c6 JMC |
1052 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1053 | bank->regs->irqenable_inv); | |
1054 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1055 | !bank->regs->irqenable_inv); | |
ab985f0f | 1056 | if (bank->regs->debounce_en) |
661553b9 | 1057 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1058 | |
2dc983c5 | 1059 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1060 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1061 | /* Initialize interface clk ungated, module enabled */ |
1062 | if (bank->regs->ctrl) | |
661553b9 | 1063 | writel_relaxed(0, base + bank->regs->ctrl); |
34672013 TKD |
1064 | |
1065 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1066 | if (IS_ERR(bank->dbck)) | |
1067 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1068 | } |
1069 | ||
46824e22 | 1070 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1071 | { |
2fae7fbe | 1072 | static int gpio; |
fb655f57 | 1073 | int irq_base = 0; |
6ef7f385 | 1074 | int ret; |
2fae7fbe | 1075 | |
2fae7fbe VC |
1076 | /* |
1077 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1078 | * over to the generic ones | |
1079 | */ | |
1080 | bank->chip.request = omap_gpio_request; | |
1081 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1082 | bank->chip.get_direction = omap_gpio_get_direction; |
1083 | bank->chip.direction_input = omap_gpio_input; | |
1084 | bank->chip.get = omap_gpio_get; | |
1085 | bank->chip.direction_output = omap_gpio_output; | |
1086 | bank->chip.set_debounce = omap_gpio_debounce; | |
1087 | bank->chip.set = omap_gpio_set; | |
d0d665a8 | 1088 | if (bank->is_mpuio) { |
2fae7fbe | 1089 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1090 | if (bank->regs->wkup_en) |
1091 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1092 | bank->chip.base = OMAP_MPUIO(0); |
1093 | } else { | |
1094 | bank->chip.label = "gpio"; | |
1095 | bank->chip.base = gpio; | |
d5f46247 | 1096 | gpio += bank->width; |
2fae7fbe | 1097 | } |
d5f46247 | 1098 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1099 | |
6ef7f385 JMC |
1100 | ret = gpiochip_add(&bank->chip); |
1101 | if (ret) { | |
fb655f57 | 1102 | dev_err(bank->dev, "Could not register gpio chip %d\n", ret); |
6ef7f385 JMC |
1103 | return ret; |
1104 | } | |
2fae7fbe | 1105 | |
fb655f57 JMC |
1106 | #ifdef CONFIG_ARCH_OMAP1 |
1107 | /* | |
1108 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1109 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1110 | */ | |
1111 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1112 | if (irq_base < 0) { | |
1113 | dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); | |
1114 | return -ENODEV; | |
1115 | } | |
1116 | #endif | |
1117 | ||
d2d05c65 TL |
1118 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1119 | if (bank->is_mpuio) { | |
1120 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
1121 | irqc->irq_mask = irq_gc_mask_set_bit; | |
1122 | irqc->irq_unmask = irq_gc_mask_clr_bit; | |
1123 | if (!bank->regs->wkup_en) | |
1124 | irqc->irq_set_wake = NULL; | |
1125 | } | |
1126 | ||
46824e22 | 1127 | ret = gpiochip_irqchip_add(&bank->chip, irqc, |
a0e827c6 | 1128 | irq_base, omap_gpio_irq_handler, |
fb655f57 JMC |
1129 | IRQ_TYPE_NONE); |
1130 | ||
1131 | if (ret) { | |
1132 | dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); | |
da26d5d8 | 1133 | gpiochip_remove(&bank->chip); |
fb655f57 JMC |
1134 | return -ENODEV; |
1135 | } | |
1136 | ||
46824e22 | 1137 | gpiochip_set_chained_irqchip(&bank->chip, irqc, |
a0e827c6 | 1138 | bank->irq, omap_gpio_irq_handler); |
fb655f57 | 1139 | |
fb655f57 | 1140 | return 0; |
2fae7fbe VC |
1141 | } |
1142 | ||
384ebe1c BC |
1143 | static const struct of_device_id omap_gpio_match[]; |
1144 | ||
3836309d | 1145 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1146 | { |
862ff640 | 1147 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1148 | struct device_node *node = dev->of_node; |
1149 | const struct of_device_id *match; | |
f6817a2c | 1150 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1151 | struct resource *res; |
5e1c5ff4 | 1152 | struct gpio_bank *bank; |
46824e22 | 1153 | struct irq_chip *irqc; |
6ef7f385 | 1154 | int ret; |
5e1c5ff4 | 1155 | |
384ebe1c BC |
1156 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1157 | ||
e56aee18 | 1158 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1159 | if (!pdata) |
96751fcb | 1160 | return -EINVAL; |
5492fb1a | 1161 | |
086d585f | 1162 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1163 | if (!bank) { |
862ff640 | 1164 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1165 | return -ENOMEM; |
03e128ca | 1166 | } |
92105bb7 | 1167 | |
46824e22 NM |
1168 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1169 | if (!irqc) | |
1170 | return -ENOMEM; | |
1171 | ||
3d009c8c | 1172 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1173 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1174 | irqc->irq_ack = omap_gpio_ack_irq, | |
1175 | irqc->irq_mask = omap_gpio_mask_irq, | |
1176 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1177 | irqc->irq_set_type = omap_gpio_irq_type, | |
1178 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1179 | irqc->name = dev_name(&pdev->dev); | |
1180 | ||
77640aab VC |
1181 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1182 | if (unlikely(!res)) { | |
862ff640 | 1183 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1184 | return -ENODEV; |
44169075 | 1185 | } |
5e1c5ff4 | 1186 | |
77640aab | 1187 | bank->irq = res->start; |
862ff640 | 1188 | bank->dev = dev; |
fb655f57 | 1189 | bank->chip.dev = dev; |
c23837ce | 1190 | bank->chip.owner = THIS_MODULE; |
77640aab | 1191 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1192 | bank->stride = pdata->bank_stride; |
d5f46247 | 1193 | bank->width = pdata->bank_width; |
d0d665a8 | 1194 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1195 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1196 | bank->regs = pdata->regs; |
384ebe1c BC |
1197 | #ifdef CONFIG_OF_GPIO |
1198 | bank->chip.of_node = of_node_get(node); | |
1199 | #endif | |
a2797bea JH |
1200 | if (node) { |
1201 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1202 | bank->loses_context = true; | |
1203 | } else { | |
1204 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1205 | |
1206 | if (bank->loses_context) | |
1207 | bank->get_context_loss_count = | |
1208 | pdata->get_context_loss_count; | |
384ebe1c BC |
1209 | } |
1210 | ||
fa87931a | 1211 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1212 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1213 | else |
a0e827c6 | 1214 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1215 | |
77640aab | 1216 | spin_lock_init(&bank->lock); |
9f7065da | 1217 | |
77640aab VC |
1218 | /* Static mapping, never released */ |
1219 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1220 | bank->base = devm_ioremap_resource(dev, res); |
1221 | if (IS_ERR(bank->base)) { | |
fb655f57 | 1222 | irq_domain_remove(bank->chip.irqdomain); |
717f70e3 | 1223 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1224 | } |
1225 | ||
065cd795 TKD |
1226 | platform_set_drvdata(pdev, bank); |
1227 | ||
77640aab | 1228 | pm_runtime_enable(bank->dev); |
55b93c32 | 1229 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1230 | pm_runtime_get_sync(bank->dev); |
1231 | ||
d0d665a8 | 1232 | if (bank->is_mpuio) |
a0e827c6 | 1233 | omap_mpuio_init(bank); |
ab985f0f | 1234 | |
03e128ca | 1235 | omap_gpio_mod_init(bank); |
6ef7f385 | 1236 | |
46824e22 | 1237 | ret = omap_gpio_chip_init(bank, irqc); |
6ef7f385 JMC |
1238 | if (ret) |
1239 | return ret; | |
1240 | ||
9a748053 | 1241 | omap_gpio_show_rev(bank); |
9f7065da | 1242 | |
55b93c32 TKD |
1243 | pm_runtime_put(bank->dev); |
1244 | ||
03e128ca | 1245 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1246 | |
879fe324 | 1247 | return 0; |
5e1c5ff4 TL |
1248 | } |
1249 | ||
cac089f9 TL |
1250 | static int omap_gpio_remove(struct platform_device *pdev) |
1251 | { | |
1252 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1253 | ||
1254 | list_del(&bank->node); | |
1255 | gpiochip_remove(&bank->chip); | |
1256 | pm_runtime_disable(bank->dev); | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
55b93c32 TKD |
1261 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1262 | ||
ecb2312f | 1263 | #if defined(CONFIG_PM) |
60a3437d | 1264 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1265 | |
2dc983c5 | 1266 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1267 | { |
2dc983c5 TKD |
1268 | struct platform_device *pdev = to_platform_device(dev); |
1269 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1270 | u32 l1 = 0, l2 = 0; | |
1271 | unsigned long flags; | |
68942edb | 1272 | u32 wake_low, wake_hi; |
8865b9b6 | 1273 | |
2dc983c5 | 1274 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1275 | |
1276 | /* | |
1277 | * Only edges can generate a wakeup event to the PRCM. | |
1278 | * | |
1279 | * Therefore, ensure any wake-up capable GPIOs have | |
1280 | * edge-detection enabled before going idle to ensure a wakeup | |
1281 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1282 | * NDA TRM 25.5.3.1) | |
1283 | * | |
1284 | * The normal values will be restored upon ->runtime_resume() | |
1285 | * by writing back the values saved in bank->context. | |
1286 | */ | |
1287 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1288 | if (wake_low) | |
661553b9 | 1289 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1290 | bank->base + bank->regs->fallingdetect); |
1291 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1292 | if (wake_hi) | |
661553b9 | 1293 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1294 | bank->base + bank->regs->risingdetect); |
1295 | ||
b3c64bc3 KH |
1296 | if (!bank->enabled_non_wakeup_gpios) |
1297 | goto update_gpio_context_count; | |
1298 | ||
2dc983c5 TKD |
1299 | if (bank->power_mode != OFF_MODE) { |
1300 | bank->power_mode = 0; | |
41d87cbd | 1301 | goto update_gpio_context_count; |
2dc983c5 TKD |
1302 | } |
1303 | /* | |
1304 | * If going to OFF, remove triggering for all | |
1305 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1306 | * generated. See OMAP2420 Errata item 1.101. | |
1307 | */ | |
661553b9 | 1308 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1309 | bank->regs->datain); |
c6f31c9e TKD |
1310 | l1 = bank->context.fallingdetect; |
1311 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1312 | |
2dc983c5 TKD |
1313 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1314 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1315 | |
661553b9 VK |
1316 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1317 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1318 | |
2dc983c5 | 1319 | bank->workaround_enabled = true; |
3f1686a9 | 1320 | |
41d87cbd | 1321 | update_gpio_context_count: |
2dc983c5 TKD |
1322 | if (bank->get_context_loss_count) |
1323 | bank->context_loss_count = | |
60a3437d TKD |
1324 | bank->get_context_loss_count(bank->dev); |
1325 | ||
a0e827c6 | 1326 | omap_gpio_dbck_disable(bank); |
2dc983c5 | 1327 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1328 | |
2dc983c5 | 1329 | return 0; |
3ac4fa99 JY |
1330 | } |
1331 | ||
352a2d5b JH |
1332 | static void omap_gpio_init_context(struct gpio_bank *p); |
1333 | ||
2dc983c5 | 1334 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1335 | { |
2dc983c5 TKD |
1336 | struct platform_device *pdev = to_platform_device(dev); |
1337 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1338 | u32 l = 0, gen, gen0, gen1; |
1339 | unsigned long flags; | |
a2797bea | 1340 | int c; |
8865b9b6 | 1341 | |
2dc983c5 | 1342 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1343 | |
1344 | /* | |
1345 | * On the first resume during the probe, the context has not | |
1346 | * been initialised and so initialise it now. Also initialise | |
1347 | * the context loss count. | |
1348 | */ | |
1349 | if (bank->loses_context && !bank->context_valid) { | |
1350 | omap_gpio_init_context(bank); | |
1351 | ||
1352 | if (bank->get_context_loss_count) | |
1353 | bank->context_loss_count = | |
1354 | bank->get_context_loss_count(bank->dev); | |
1355 | } | |
1356 | ||
a0e827c6 | 1357 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1358 | |
1359 | /* | |
1360 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1361 | * GPIOs were set to edge trigger also in order to be able to | |
1362 | * generate a PRCM wakeup. Here we restore the | |
1363 | * pre-runtime_suspend() values for edge triggering. | |
1364 | */ | |
661553b9 | 1365 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1366 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1367 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1368 | bank->base + bank->regs->risingdetect); |
1369 | ||
a2797bea JH |
1370 | if (bank->loses_context) { |
1371 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1372 | omap_gpio_restore_context(bank); |
1373 | } else { | |
a2797bea JH |
1374 | c = bank->get_context_loss_count(bank->dev); |
1375 | if (c != bank->context_loss_count) { | |
1376 | omap_gpio_restore_context(bank); | |
1377 | } else { | |
1378 | spin_unlock_irqrestore(&bank->lock, flags); | |
1379 | return 0; | |
1380 | } | |
60a3437d | 1381 | } |
2dc983c5 | 1382 | } |
43ffcd9a | 1383 | |
1b128703 TKD |
1384 | if (!bank->workaround_enabled) { |
1385 | spin_unlock_irqrestore(&bank->lock, flags); | |
1386 | return 0; | |
1387 | } | |
1388 | ||
661553b9 | 1389 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1390 | |
2dc983c5 TKD |
1391 | /* |
1392 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1393 | * state. If so, generate an IRQ by software. This is | |
1394 | * horribly racy, but it's the best we can do to work around | |
1395 | * this silicon bug. | |
1396 | */ | |
1397 | l ^= bank->saved_datain; | |
1398 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1399 | |
2dc983c5 TKD |
1400 | /* |
1401 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1402 | * configured with falling edge only; and vice versa. | |
1403 | */ | |
c6f31c9e | 1404 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1405 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1406 | |
c6f31c9e | 1407 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1408 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1409 | |
2dc983c5 | 1410 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1411 | gen = l & (~(bank->context.fallingdetect) & |
1412 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1413 | /* Consider all GPIO IRQs needed to be updated */ |
1414 | gen |= gen0 | gen1; | |
82dbb9d3 | 1415 | |
2dc983c5 TKD |
1416 | if (gen) { |
1417 | u32 old0, old1; | |
82dbb9d3 | 1418 | |
661553b9 VK |
1419 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1420 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1421 | |
4e962e89 | 1422 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1423 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1424 | bank->regs->leveldetect0); |
661553b9 | 1425 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1426 | bank->regs->leveldetect1); |
2dc983c5 | 1427 | } |
9ea14d8c | 1428 | |
4e962e89 | 1429 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1430 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1431 | bank->regs->leveldetect0); |
661553b9 | 1432 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1433 | bank->regs->leveldetect1); |
3ac4fa99 | 1434 | } |
661553b9 VK |
1435 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1436 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1437 | } |
1438 | ||
1439 | bank->workaround_enabled = false; | |
1440 | spin_unlock_irqrestore(&bank->lock, flags); | |
1441 | ||
1442 | return 0; | |
1443 | } | |
ecb2312f | 1444 | #endif /* CONFIG_PM */ |
2dc983c5 | 1445 | |
cac089f9 | 1446 | #if IS_BUILTIN(CONFIG_GPIO_OMAP) |
2dc983c5 TKD |
1447 | void omap2_gpio_prepare_for_idle(int pwr_mode) |
1448 | { | |
1449 | struct gpio_bank *bank; | |
1450 | ||
1451 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1452 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1453 | continue; |
1454 | ||
1455 | bank->power_mode = pwr_mode; | |
1456 | ||
2dc983c5 TKD |
1457 | pm_runtime_put_sync_suspend(bank->dev); |
1458 | } | |
1459 | } | |
1460 | ||
1461 | void omap2_gpio_resume_after_idle(void) | |
1462 | { | |
1463 | struct gpio_bank *bank; | |
1464 | ||
1465 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1466 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1467 | continue; |
1468 | ||
2dc983c5 | 1469 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1470 | } |
3ac4fa99 | 1471 | } |
cac089f9 | 1472 | #endif |
3ac4fa99 | 1473 | |
ecb2312f | 1474 | #if defined(CONFIG_PM) |
352a2d5b JH |
1475 | static void omap_gpio_init_context(struct gpio_bank *p) |
1476 | { | |
1477 | struct omap_gpio_reg_offs *regs = p->regs; | |
1478 | void __iomem *base = p->base; | |
1479 | ||
661553b9 VK |
1480 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1481 | p->context.oe = readl_relaxed(base + regs->direction); | |
1482 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1483 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1484 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1485 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1486 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1487 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1488 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1489 | |
1490 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1491 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1492 | else |
661553b9 | 1493 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1494 | |
1495 | p->context_valid = true; | |
1496 | } | |
1497 | ||
60a3437d | 1498 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1499 | { |
661553b9 | 1500 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1501 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1502 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1503 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1504 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1505 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1506 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1507 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1508 | bank->base + bank->regs->risingdetect); |
661553b9 | 1509 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1510 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1511 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1512 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1513 | bank->base + bank->regs->set_dataout); |
1514 | else | |
661553b9 | 1515 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1516 | bank->base + bank->regs->dataout); |
661553b9 | 1517 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1518 | |
ae547354 | 1519 | if (bank->dbck_enable_mask) { |
661553b9 | 1520 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1521 | bank->regs->debounce); |
661553b9 | 1522 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1523 | bank->base + bank->regs->debounce_en); |
1524 | } | |
ba805be5 | 1525 | |
661553b9 | 1526 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1527 | bank->base + bank->regs->irqenable); |
661553b9 | 1528 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1529 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1530 | } |
ecb2312f | 1531 | #endif /* CONFIG_PM */ |
55b93c32 | 1532 | #else |
2dc983c5 TKD |
1533 | #define omap_gpio_runtime_suspend NULL |
1534 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1535 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1536 | #endif |
1537 | ||
55b93c32 | 1538 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1539 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1540 | NULL) | |
55b93c32 TKD |
1541 | }; |
1542 | ||
384ebe1c BC |
1543 | #if defined(CONFIG_OF) |
1544 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1545 | .revision = OMAP24XX_GPIO_REVISION, | |
1546 | .direction = OMAP24XX_GPIO_OE, | |
1547 | .datain = OMAP24XX_GPIO_DATAIN, | |
1548 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1549 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1550 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1551 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1552 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1553 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1554 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1555 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1556 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1557 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1558 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1559 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1560 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1561 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1562 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1563 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1564 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1565 | }; | |
1566 | ||
1567 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1568 | .revision = OMAP4_GPIO_REVISION, | |
1569 | .direction = OMAP4_GPIO_OE, | |
1570 | .datain = OMAP4_GPIO_DATAIN, | |
1571 | .dataout = OMAP4_GPIO_DATAOUT, | |
1572 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1573 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1574 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1575 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1576 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1577 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1578 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1579 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1580 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1581 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1582 | .ctrl = OMAP4_GPIO_CTRL, | |
1583 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1584 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1585 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1586 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1587 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1588 | }; | |
1589 | ||
e9a65bb6 | 1590 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1591 | .regs = &omap2_gpio_regs, |
1592 | .bank_width = 32, | |
1593 | .dbck_flag = false, | |
1594 | }; | |
1595 | ||
e9a65bb6 | 1596 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1597 | .regs = &omap2_gpio_regs, |
1598 | .bank_width = 32, | |
1599 | .dbck_flag = true, | |
1600 | }; | |
1601 | ||
e9a65bb6 | 1602 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1603 | .regs = &omap4_gpio_regs, |
1604 | .bank_width = 32, | |
1605 | .dbck_flag = true, | |
1606 | }; | |
1607 | ||
1608 | static const struct of_device_id omap_gpio_match[] = { | |
1609 | { | |
1610 | .compatible = "ti,omap4-gpio", | |
1611 | .data = &omap4_pdata, | |
1612 | }, | |
1613 | { | |
1614 | .compatible = "ti,omap3-gpio", | |
1615 | .data = &omap3_pdata, | |
1616 | }, | |
1617 | { | |
1618 | .compatible = "ti,omap2-gpio", | |
1619 | .data = &omap2_pdata, | |
1620 | }, | |
1621 | { }, | |
1622 | }; | |
1623 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1624 | #endif | |
1625 | ||
77640aab VC |
1626 | static struct platform_driver omap_gpio_driver = { |
1627 | .probe = omap_gpio_probe, | |
cac089f9 | 1628 | .remove = omap_gpio_remove, |
77640aab VC |
1629 | .driver = { |
1630 | .name = "omap_gpio", | |
55b93c32 | 1631 | .pm = &gpio_pm_ops, |
384ebe1c | 1632 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1633 | }, |
1634 | }; | |
1635 | ||
5e1c5ff4 | 1636 | /* |
77640aab VC |
1637 | * gpio driver register needs to be done before |
1638 | * machine_init functions access gpio APIs. | |
1639 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1640 | */ |
77640aab | 1641 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1642 | { |
77640aab | 1643 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1644 | } |
77640aab | 1645 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1646 | |
1647 | static void __exit omap_gpio_exit(void) | |
1648 | { | |
1649 | platform_driver_unregister(&omap_gpio_driver); | |
1650 | } | |
1651 | module_exit(omap_gpio_exit); | |
1652 | ||
1653 | MODULE_DESCRIPTION("omap gpio driver"); | |
1654 | MODULE_ALIAS("platform:gpio-omap"); | |
1655 | MODULE_LICENSE("GPL v2"); |