Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 | 31 | struct gpio_bank { |
9f7065da | 32 | unsigned long pbase; |
92105bb7 | 33 | void __iomem *base; |
5e1c5ff4 TL |
34 | u16 irq; |
35 | u16 virtual_irq_start; | |
92105bb7 | 36 | int method; |
140455fa | 37 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
38 | u32 suspend_wakeup; |
39 | u32 saved_wakeup; | |
3ac4fa99 | 40 | #endif |
3ac4fa99 JY |
41 | u32 non_wakeup_gpios; |
42 | u32 enabled_non_wakeup_gpios; | |
43 | ||
44 | u32 saved_datain; | |
45 | u32 saved_fallingdetect; | |
46 | u32 saved_risingdetect; | |
b144ff6f | 47 | u32 level_mask; |
4318f36b | 48 | u32 toggle_mask; |
5e1c5ff4 | 49 | spinlock_t lock; |
52e31344 | 50 | struct gpio_chip chip; |
89db9482 | 51 | struct clk *dbck; |
058af1ea | 52 | u32 mod_usage; |
8865b9b6 | 53 | u32 dbck_enable_mask; |
77640aab VC |
54 | struct device *dev; |
55 | bool dbck_flag; | |
5de62b86 | 56 | int stride; |
5e1c5ff4 TL |
57 | }; |
58 | ||
a8eb7ca0 | 59 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 | 60 | struct omap3_gpio_regs { |
40c670f0 RN |
61 | u32 irqenable1; |
62 | u32 irqenable2; | |
63 | u32 wake_en; | |
64 | u32 ctrl; | |
65 | u32 oe; | |
66 | u32 leveldetect0; | |
67 | u32 leveldetect1; | |
68 | u32 risingdetect; | |
69 | u32 fallingdetect; | |
70 | u32 dataout; | |
5492fb1a SMK |
71 | }; |
72 | ||
40c670f0 | 73 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
74 | #endif |
75 | ||
77640aab VC |
76 | /* |
77 | * TODO: Cleanup gpio_bank usage as it is having information | |
78 | * related to all instances of the device | |
79 | */ | |
80 | static struct gpio_bank *gpio_bank; | |
44169075 | 81 | |
77640aab | 82 | static int bank_width; |
44169075 | 83 | |
c95d10bc VC |
84 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
85 | int gpio_bank_count; | |
5e1c5ff4 TL |
86 | |
87 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
88 | { | |
6e60e79a | 89 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
90 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
91 | return &gpio_bank[0]; | |
92 | return &gpio_bank[1]; | |
93 | } | |
5e1c5ff4 TL |
94 | if (cpu_is_omap16xx()) { |
95 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
96 | return &gpio_bank[0]; | |
97 | return &gpio_bank[1 + (gpio >> 4)]; | |
98 | } | |
56739a69 | 99 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
100 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
101 | return &gpio_bank[0]; | |
102 | return &gpio_bank[1 + (gpio >> 5)]; | |
103 | } | |
92105bb7 TL |
104 | if (cpu_is_omap24xx()) |
105 | return &gpio_bank[gpio >> 5]; | |
44169075 | 106 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 107 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
108 | BUG(); |
109 | return NULL; | |
5e1c5ff4 TL |
110 | } |
111 | ||
112 | static inline int get_gpio_index(int gpio) | |
113 | { | |
56739a69 | 114 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 115 | return gpio & 0x1f; |
92105bb7 TL |
116 | if (cpu_is_omap24xx()) |
117 | return gpio & 0x1f; | |
44169075 | 118 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 119 | return gpio & 0x1f; |
92105bb7 | 120 | return gpio & 0x0f; |
5e1c5ff4 TL |
121 | } |
122 | ||
123 | static inline int gpio_valid(int gpio) | |
124 | { | |
125 | if (gpio < 0) | |
126 | return -1; | |
d11ac979 | 127 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 128 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
129 | return -1; |
130 | return 0; | |
131 | } | |
6e60e79a | 132 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 133 | return 0; |
5e1c5ff4 TL |
134 | if ((cpu_is_omap16xx()) && gpio < 64) |
135 | return 0; | |
56739a69 | 136 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 137 | return 0; |
25d6f630 TL |
138 | if (cpu_is_omap2420() && gpio < 128) |
139 | return 0; | |
140 | if (cpu_is_omap2430() && gpio < 160) | |
92105bb7 | 141 | return 0; |
44169075 | 142 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 143 | return 0; |
5e1c5ff4 TL |
144 | return -1; |
145 | } | |
146 | ||
147 | static int check_gpio(int gpio) | |
148 | { | |
d32b20fc | 149 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
150 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
151 | dump_stack(); | |
152 | return -1; | |
153 | } | |
154 | return 0; | |
155 | } | |
156 | ||
157 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
158 | { | |
92105bb7 | 159 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
160 | u32 l; |
161 | ||
162 | switch (bank->method) { | |
e5c56ed3 | 163 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 164 | case METHOD_MPUIO: |
5de62b86 | 165 | reg += OMAP_MPUIO_IO_CNTL / bank->stride; |
5e1c5ff4 | 166 | break; |
e5c56ed3 DB |
167 | #endif |
168 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
169 | case METHOD_GPIO_1510: |
170 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
171 | break; | |
e5c56ed3 DB |
172 | #endif |
173 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
174 | case METHOD_GPIO_1610: |
175 | reg += OMAP1610_GPIO_DIRECTION; | |
176 | break; | |
e5c56ed3 | 177 | #endif |
b718aa81 | 178 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
179 | case METHOD_GPIO_7XX: |
180 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
181 | break; |
182 | #endif | |
a8eb7ca0 | 183 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
184 | case METHOD_GPIO_24XX: |
185 | reg += OMAP24XX_GPIO_OE; | |
186 | break; | |
78a1a6d3 SR |
187 | #endif |
188 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 189 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
190 | reg += OMAP4_GPIO_OE; |
191 | break; | |
e5c56ed3 DB |
192 | #endif |
193 | default: | |
194 | WARN_ON(1); | |
195 | return; | |
5e1c5ff4 TL |
196 | } |
197 | l = __raw_readl(reg); | |
198 | if (is_input) | |
199 | l |= 1 << gpio; | |
200 | else | |
201 | l &= ~(1 << gpio); | |
202 | __raw_writel(l, reg); | |
203 | } | |
204 | ||
5e1c5ff4 TL |
205 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
206 | { | |
92105bb7 | 207 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
208 | u32 l = 0; |
209 | ||
210 | switch (bank->method) { | |
e5c56ed3 | 211 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 212 | case METHOD_MPUIO: |
5de62b86 | 213 | reg += OMAP_MPUIO_OUTPUT / bank->stride; |
5e1c5ff4 TL |
214 | l = __raw_readl(reg); |
215 | if (enable) | |
216 | l |= 1 << gpio; | |
217 | else | |
218 | l &= ~(1 << gpio); | |
219 | break; | |
e5c56ed3 DB |
220 | #endif |
221 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
222 | case METHOD_GPIO_1510: |
223 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
224 | l = __raw_readl(reg); | |
225 | if (enable) | |
226 | l |= 1 << gpio; | |
227 | else | |
228 | l &= ~(1 << gpio); | |
229 | break; | |
e5c56ed3 DB |
230 | #endif |
231 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
232 | case METHOD_GPIO_1610: |
233 | if (enable) | |
234 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
235 | else | |
236 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
237 | l = 1 << gpio; | |
238 | break; | |
e5c56ed3 | 239 | #endif |
b718aa81 | 240 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
241 | case METHOD_GPIO_7XX: |
242 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
243 | l = __raw_readl(reg); |
244 | if (enable) | |
245 | l |= 1 << gpio; | |
246 | else | |
247 | l &= ~(1 << gpio); | |
248 | break; | |
249 | #endif | |
a8eb7ca0 | 250 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
251 | case METHOD_GPIO_24XX: |
252 | if (enable) | |
253 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
254 | else | |
255 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
256 | l = 1 << gpio; | |
257 | break; | |
78a1a6d3 SR |
258 | #endif |
259 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 260 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
261 | if (enable) |
262 | reg += OMAP4_GPIO_SETDATAOUT; | |
263 | else | |
264 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
265 | l = 1 << gpio; | |
266 | break; | |
e5c56ed3 | 267 | #endif |
5e1c5ff4 | 268 | default: |
e5c56ed3 | 269 | WARN_ON(1); |
5e1c5ff4 TL |
270 | return; |
271 | } | |
272 | __raw_writel(l, reg); | |
273 | } | |
274 | ||
b37c45b8 | 275 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 276 | { |
92105bb7 | 277 | void __iomem *reg; |
5e1c5ff4 TL |
278 | |
279 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 280 | return -EINVAL; |
5e1c5ff4 TL |
281 | reg = bank->base; |
282 | switch (bank->method) { | |
e5c56ed3 | 283 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 284 | case METHOD_MPUIO: |
5de62b86 | 285 | reg += OMAP_MPUIO_INPUT_LATCH / bank->stride; |
5e1c5ff4 | 286 | break; |
e5c56ed3 DB |
287 | #endif |
288 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
289 | case METHOD_GPIO_1510: |
290 | reg += OMAP1510_GPIO_DATA_INPUT; | |
291 | break; | |
e5c56ed3 DB |
292 | #endif |
293 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
294 | case METHOD_GPIO_1610: |
295 | reg += OMAP1610_GPIO_DATAIN; | |
296 | break; | |
e5c56ed3 | 297 | #endif |
b718aa81 | 298 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
299 | case METHOD_GPIO_7XX: |
300 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
301 | break; |
302 | #endif | |
a8eb7ca0 | 303 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
304 | case METHOD_GPIO_24XX: |
305 | reg += OMAP24XX_GPIO_DATAIN; | |
306 | break; | |
78a1a6d3 SR |
307 | #endif |
308 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 309 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
310 | reg += OMAP4_GPIO_DATAIN; |
311 | break; | |
e5c56ed3 | 312 | #endif |
5e1c5ff4 | 313 | default: |
e5c56ed3 | 314 | return -EINVAL; |
5e1c5ff4 | 315 | } |
92105bb7 TL |
316 | return (__raw_readl(reg) |
317 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
318 | } |
319 | ||
b37c45b8 RQ |
320 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
321 | { | |
322 | void __iomem *reg; | |
323 | ||
324 | if (check_gpio(gpio) < 0) | |
325 | return -EINVAL; | |
326 | reg = bank->base; | |
327 | ||
328 | switch (bank->method) { | |
329 | #ifdef CONFIG_ARCH_OMAP1 | |
330 | case METHOD_MPUIO: | |
5de62b86 | 331 | reg += OMAP_MPUIO_OUTPUT / bank->stride; |
b37c45b8 RQ |
332 | break; |
333 | #endif | |
334 | #ifdef CONFIG_ARCH_OMAP15XX | |
335 | case METHOD_GPIO_1510: | |
336 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
337 | break; | |
338 | #endif | |
339 | #ifdef CONFIG_ARCH_OMAP16XX | |
340 | case METHOD_GPIO_1610: | |
341 | reg += OMAP1610_GPIO_DATAOUT; | |
342 | break; | |
343 | #endif | |
b718aa81 | 344 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
345 | case METHOD_GPIO_7XX: |
346 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
347 | break; |
348 | #endif | |
9f096868 | 349 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
b37c45b8 RQ |
350 | case METHOD_GPIO_24XX: |
351 | reg += OMAP24XX_GPIO_DATAOUT; | |
352 | break; | |
9f096868 C |
353 | #endif |
354 | #ifdef CONFIG_ARCH_OMAP4 | |
355 | case METHOD_GPIO_44XX: | |
356 | reg += OMAP4_GPIO_DATAOUT; | |
357 | break; | |
b37c45b8 RQ |
358 | #endif |
359 | default: | |
360 | return -EINVAL; | |
361 | } | |
362 | ||
363 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
364 | } | |
365 | ||
92105bb7 TL |
366 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
367 | do { \ | |
368 | int l = __raw_readl(base + reg); \ | |
369 | if (set) l |= bit_mask; \ | |
370 | else l &= ~bit_mask; \ | |
371 | __raw_writel(l, base + reg); \ | |
372 | } while(0) | |
373 | ||
168ef3d9 FB |
374 | /** |
375 | * _set_gpio_debounce - low level gpio debounce time | |
376 | * @bank: the gpio bank we're acting upon | |
377 | * @gpio: the gpio number on this @gpio | |
378 | * @debounce: debounce time to use | |
379 | * | |
380 | * OMAP's debounce time is in 31us steps so we need | |
381 | * to convert and round up to the closest unit. | |
382 | */ | |
383 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
384 | unsigned debounce) | |
385 | { | |
386 | void __iomem *reg = bank->base; | |
387 | u32 val; | |
388 | u32 l; | |
389 | ||
77640aab VC |
390 | if (!bank->dbck_flag) |
391 | return; | |
392 | ||
168ef3d9 FB |
393 | if (debounce < 32) |
394 | debounce = 0x01; | |
395 | else if (debounce > 7936) | |
396 | debounce = 0xff; | |
397 | else | |
398 | debounce = (debounce / 0x1f) - 1; | |
399 | ||
400 | l = 1 << get_gpio_index(gpio); | |
401 | ||
77640aab | 402 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
403 | reg += OMAP4_GPIO_DEBOUNCINGTIME; |
404 | else | |
405 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
406 | ||
407 | __raw_writel(debounce, reg); | |
408 | ||
409 | reg = bank->base; | |
77640aab | 410 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
411 | reg += OMAP4_GPIO_DEBOUNCENABLE; |
412 | else | |
413 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
414 | ||
415 | val = __raw_readl(reg); | |
416 | ||
417 | if (debounce) { | |
418 | val |= l; | |
77640aab | 419 | clk_enable(bank->dbck); |
168ef3d9 FB |
420 | } else { |
421 | val &= ~l; | |
77640aab | 422 | clk_disable(bank->dbck); |
168ef3d9 | 423 | } |
f7ec0b0b | 424 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
425 | |
426 | __raw_writel(val, reg); | |
427 | } | |
428 | ||
140455fa | 429 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
430 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
431 | int trigger) | |
5e1c5ff4 | 432 | { |
3ac4fa99 | 433 | void __iomem *base = bank->base; |
92105bb7 TL |
434 | u32 gpio_bit = 1 << gpio; |
435 | ||
78a1a6d3 SR |
436 | if (cpu_is_omap44xx()) { |
437 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
438 | trigger & IRQ_TYPE_LEVEL_LOW); | |
439 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
440 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
441 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
442 | trigger & IRQ_TYPE_EDGE_RISING); | |
443 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
444 | trigger & IRQ_TYPE_EDGE_FALLING); | |
445 | } else { | |
446 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
447 | trigger & IRQ_TYPE_LEVEL_LOW); | |
448 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
449 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
450 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
451 | trigger & IRQ_TYPE_EDGE_RISING); | |
452 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
453 | trigger & IRQ_TYPE_EDGE_FALLING); | |
454 | } | |
3ac4fa99 | 455 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 | 456 | if (cpu_is_omap44xx()) { |
0622b25b CC |
457 | MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit, |
458 | trigger != 0); | |
78a1a6d3 | 459 | } else { |
699117a6 CW |
460 | /* |
461 | * GPIO wakeup request can only be generated on edge | |
462 | * transitions | |
463 | */ | |
464 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 465 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 466 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
467 | else |
468 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 469 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 470 | } |
a118b5f3 TK |
471 | } |
472 | /* This part needs to be executed always for OMAP34xx */ | |
473 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
474 | /* |
475 | * Log the edge gpio and manually trigger the IRQ | |
476 | * after resume if the input level changes | |
477 | * to avoid irq lost during PER RET/OFF mode | |
478 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
479 | */ | |
480 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
481 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
482 | else | |
483 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
484 | } | |
5eb3bb9c | 485 | |
78a1a6d3 SR |
486 | if (cpu_is_omap44xx()) { |
487 | bank->level_mask = | |
488 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
489 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
490 | } else { | |
491 | bank->level_mask = | |
492 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
493 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
494 | } | |
92105bb7 | 495 | } |
3ac4fa99 | 496 | #endif |
92105bb7 | 497 | |
9198bcd3 | 498 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
499 | /* |
500 | * This only applies to chips that can't do both rising and falling edge | |
501 | * detection at once. For all other chips, this function is a noop. | |
502 | */ | |
503 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
504 | { | |
505 | void __iomem *reg = bank->base; | |
506 | u32 l = 0; | |
507 | ||
508 | switch (bank->method) { | |
4318f36b | 509 | case METHOD_MPUIO: |
5de62b86 | 510 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
4318f36b | 511 | break; |
4318f36b CM |
512 | #ifdef CONFIG_ARCH_OMAP15XX |
513 | case METHOD_GPIO_1510: | |
514 | reg += OMAP1510_GPIO_INT_CONTROL; | |
515 | break; | |
516 | #endif | |
517 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
518 | case METHOD_GPIO_7XX: | |
519 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
520 | break; | |
521 | #endif | |
522 | default: | |
523 | return; | |
524 | } | |
525 | ||
526 | l = __raw_readl(reg); | |
527 | if ((l >> gpio) & 1) | |
528 | l &= ~(1 << gpio); | |
529 | else | |
530 | l |= 1 << gpio; | |
531 | ||
532 | __raw_writel(l, reg); | |
533 | } | |
9198bcd3 | 534 | #endif |
4318f36b | 535 | |
92105bb7 TL |
536 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
537 | { | |
538 | void __iomem *reg = bank->base; | |
539 | u32 l = 0; | |
5e1c5ff4 TL |
540 | |
541 | switch (bank->method) { | |
e5c56ed3 | 542 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 543 | case METHOD_MPUIO: |
5de62b86 | 544 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
5e1c5ff4 | 545 | l = __raw_readl(reg); |
29501577 | 546 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 547 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 548 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 549 | l |= 1 << gpio; |
6cab4860 | 550 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 551 | l &= ~(1 << gpio); |
92105bb7 TL |
552 | else |
553 | goto bad; | |
5e1c5ff4 | 554 | break; |
e5c56ed3 DB |
555 | #endif |
556 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
557 | case METHOD_GPIO_1510: |
558 | reg += OMAP1510_GPIO_INT_CONTROL; | |
559 | l = __raw_readl(reg); | |
29501577 | 560 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 561 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 562 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 563 | l |= 1 << gpio; |
6cab4860 | 564 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 565 | l &= ~(1 << gpio); |
92105bb7 TL |
566 | else |
567 | goto bad; | |
5e1c5ff4 | 568 | break; |
e5c56ed3 | 569 | #endif |
3ac4fa99 | 570 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 571 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
572 | if (gpio & 0x08) |
573 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
574 | else | |
575 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
576 | gpio &= 0x07; | |
577 | l = __raw_readl(reg); | |
578 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 579 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 580 | l |= 2 << (gpio << 1); |
6cab4860 | 581 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 582 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
583 | if (trigger) |
584 | /* Enable wake-up during idle for dynamic tick */ | |
585 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
586 | else | |
587 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 588 | break; |
3ac4fa99 | 589 | #endif |
b718aa81 | 590 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
591 | case METHOD_GPIO_7XX: |
592 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 593 | l = __raw_readl(reg); |
29501577 | 594 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 595 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
596 | if (trigger & IRQ_TYPE_EDGE_RISING) |
597 | l |= 1 << gpio; | |
598 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
599 | l &= ~(1 << gpio); | |
600 | else | |
601 | goto bad; | |
602 | break; | |
603 | #endif | |
140455fa | 604 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 605 | case METHOD_GPIO_24XX: |
3f1686a9 | 606 | case METHOD_GPIO_44XX: |
3ac4fa99 | 607 | set_24xx_gpio_triggering(bank, gpio, trigger); |
f7c5cc45 | 608 | return 0; |
3ac4fa99 | 609 | #endif |
5e1c5ff4 | 610 | default: |
92105bb7 | 611 | goto bad; |
5e1c5ff4 | 612 | } |
92105bb7 TL |
613 | __raw_writel(l, reg); |
614 | return 0; | |
615 | bad: | |
616 | return -EINVAL; | |
5e1c5ff4 TL |
617 | } |
618 | ||
e9191028 | 619 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
620 | { |
621 | struct gpio_bank *bank; | |
92105bb7 TL |
622 | unsigned gpio; |
623 | int retval; | |
a6472533 | 624 | unsigned long flags; |
92105bb7 | 625 | |
e9191028 LB |
626 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
627 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 628 | else |
e9191028 | 629 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 TL |
630 | |
631 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
632 | return -EINVAL; |
633 | ||
e5c56ed3 | 634 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 635 | return -EINVAL; |
e5c56ed3 DB |
636 | |
637 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 638 | if (!cpu_class_is_omap2() |
e5c56ed3 | 639 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
640 | return -EINVAL; |
641 | ||
e9191028 | 642 | bank = irq_data_get_irq_chip_data(d); |
a6472533 | 643 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 644 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
a6472533 | 645 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
646 | |
647 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 648 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 649 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 650 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 651 | |
92105bb7 | 652 | return retval; |
5e1c5ff4 TL |
653 | } |
654 | ||
655 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
656 | { | |
92105bb7 | 657 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
658 | |
659 | switch (bank->method) { | |
e5c56ed3 | 660 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
661 | case METHOD_MPUIO: |
662 | /* MPUIO irqstatus is reset by reading the status register, | |
663 | * so do nothing here */ | |
664 | return; | |
e5c56ed3 DB |
665 | #endif |
666 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
667 | case METHOD_GPIO_1510: |
668 | reg += OMAP1510_GPIO_INT_STATUS; | |
669 | break; | |
e5c56ed3 DB |
670 | #endif |
671 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
672 | case METHOD_GPIO_1610: |
673 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
674 | break; | |
e5c56ed3 | 675 | #endif |
b718aa81 | 676 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
677 | case METHOD_GPIO_7XX: |
678 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
679 | break; |
680 | #endif | |
a8eb7ca0 | 681 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
682 | case METHOD_GPIO_24XX: |
683 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
684 | break; | |
78a1a6d3 SR |
685 | #endif |
686 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 687 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
688 | reg += OMAP4_GPIO_IRQSTATUS0; |
689 | break; | |
e5c56ed3 | 690 | #endif |
5e1c5ff4 | 691 | default: |
e5c56ed3 | 692 | WARN_ON(1); |
5e1c5ff4 TL |
693 | return; |
694 | } | |
695 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
696 | |
697 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
698 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
699 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
700 | else if (cpu_is_omap44xx()) | |
701 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
702 | ||
78a1a6d3 | 703 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
bedfd154 RQ |
704 | __raw_writel(gpio_mask, reg); |
705 | ||
706 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
707 | __raw_readl(reg); | |
78a1a6d3 | 708 | } |
5e1c5ff4 TL |
709 | } |
710 | ||
711 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
712 | { | |
713 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
714 | } | |
715 | ||
ea6dedd7 ID |
716 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
717 | { | |
718 | void __iomem *reg = bank->base; | |
99c47707 ID |
719 | int inv = 0; |
720 | u32 l; | |
721 | u32 mask; | |
ea6dedd7 ID |
722 | |
723 | switch (bank->method) { | |
e5c56ed3 | 724 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 | 725 | case METHOD_MPUIO: |
5de62b86 | 726 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
99c47707 ID |
727 | mask = 0xffff; |
728 | inv = 1; | |
ea6dedd7 | 729 | break; |
e5c56ed3 DB |
730 | #endif |
731 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
732 | case METHOD_GPIO_1510: |
733 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
734 | mask = 0xffff; |
735 | inv = 1; | |
ea6dedd7 | 736 | break; |
e5c56ed3 DB |
737 | #endif |
738 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
739 | case METHOD_GPIO_1610: |
740 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 741 | mask = 0xffff; |
ea6dedd7 | 742 | break; |
e5c56ed3 | 743 | #endif |
b718aa81 | 744 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
745 | case METHOD_GPIO_7XX: |
746 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
747 | mask = 0xffffffff; |
748 | inv = 1; | |
749 | break; | |
750 | #endif | |
a8eb7ca0 | 751 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
752 | case METHOD_GPIO_24XX: |
753 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 754 | mask = 0xffffffff; |
ea6dedd7 | 755 | break; |
78a1a6d3 SR |
756 | #endif |
757 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 758 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
759 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
760 | mask = 0xffffffff; | |
761 | break; | |
e5c56ed3 | 762 | #endif |
ea6dedd7 | 763 | default: |
e5c56ed3 | 764 | WARN_ON(1); |
ea6dedd7 ID |
765 | return 0; |
766 | } | |
767 | ||
99c47707 ID |
768 | l = __raw_readl(reg); |
769 | if (inv) | |
770 | l = ~l; | |
771 | l &= mask; | |
772 | return l; | |
ea6dedd7 ID |
773 | } |
774 | ||
5e1c5ff4 TL |
775 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
776 | { | |
92105bb7 | 777 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
778 | u32 l; |
779 | ||
780 | switch (bank->method) { | |
e5c56ed3 | 781 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 782 | case METHOD_MPUIO: |
5de62b86 | 783 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
5e1c5ff4 TL |
784 | l = __raw_readl(reg); |
785 | if (enable) | |
786 | l &= ~(gpio_mask); | |
787 | else | |
788 | l |= gpio_mask; | |
789 | break; | |
e5c56ed3 DB |
790 | #endif |
791 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
792 | case METHOD_GPIO_1510: |
793 | reg += OMAP1510_GPIO_INT_MASK; | |
794 | l = __raw_readl(reg); | |
795 | if (enable) | |
796 | l &= ~(gpio_mask); | |
797 | else | |
798 | l |= gpio_mask; | |
799 | break; | |
e5c56ed3 DB |
800 | #endif |
801 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
802 | case METHOD_GPIO_1610: |
803 | if (enable) | |
804 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
805 | else | |
806 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
807 | l = gpio_mask; | |
808 | break; | |
e5c56ed3 | 809 | #endif |
b718aa81 | 810 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
811 | case METHOD_GPIO_7XX: |
812 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
813 | l = __raw_readl(reg); |
814 | if (enable) | |
815 | l &= ~(gpio_mask); | |
816 | else | |
817 | l |= gpio_mask; | |
818 | break; | |
819 | #endif | |
a8eb7ca0 | 820 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
821 | case METHOD_GPIO_24XX: |
822 | if (enable) | |
823 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
824 | else | |
825 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
826 | l = gpio_mask; | |
827 | break; | |
78a1a6d3 SR |
828 | #endif |
829 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 830 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
831 | if (enable) |
832 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
833 | else | |
834 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
835 | l = gpio_mask; | |
836 | break; | |
e5c56ed3 | 837 | #endif |
5e1c5ff4 | 838 | default: |
e5c56ed3 | 839 | WARN_ON(1); |
5e1c5ff4 TL |
840 | return; |
841 | } | |
842 | __raw_writel(l, reg); | |
843 | } | |
844 | ||
845 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
846 | { | |
847 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
848 | } | |
849 | ||
92105bb7 TL |
850 | /* |
851 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
852 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
853 | * to the target, system will wake up always on GPIO events. While | |
854 | * system is running all registered GPIO interrupts need to have wake-up | |
855 | * enabled. When system is suspended, only selected GPIO interrupts need | |
856 | * to have wake-up enabled. | |
857 | */ | |
858 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
859 | { | |
4cc6420c | 860 | unsigned long uninitialized_var(flags); |
a6472533 | 861 | |
92105bb7 | 862 | switch (bank->method) { |
3ac4fa99 | 863 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 864 | case METHOD_MPUIO: |
92105bb7 | 865 | case METHOD_GPIO_1610: |
a6472533 | 866 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 867 | if (enable) |
92105bb7 | 868 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 869 | else |
92105bb7 | 870 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 871 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 872 | return 0; |
3ac4fa99 | 873 | #endif |
140455fa | 874 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 875 | case METHOD_GPIO_24XX: |
3f1686a9 | 876 | case METHOD_GPIO_44XX: |
11a78b79 DB |
877 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
878 | printk(KERN_ERR "Unable to modify wakeup on " | |
879 | "non-wakeup GPIO%d\n", | |
880 | (bank - gpio_bank) * 32 + gpio); | |
881 | return -EINVAL; | |
882 | } | |
a6472533 | 883 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 884 | if (enable) |
3ac4fa99 | 885 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 886 | else |
3ac4fa99 | 887 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 888 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
889 | return 0; |
890 | #endif | |
92105bb7 TL |
891 | default: |
892 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
893 | bank->method); | |
894 | return -EINVAL; | |
895 | } | |
896 | } | |
897 | ||
4196dd6b TL |
898 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
899 | { | |
900 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
901 | _set_gpio_irqenable(bank, gpio, 0); | |
902 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 903 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
904 | } |
905 | ||
92105bb7 | 906 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 907 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 908 | { |
e9191028 | 909 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
910 | struct gpio_bank *bank; |
911 | int retval; | |
912 | ||
913 | if (check_gpio(gpio) < 0) | |
914 | return -ENODEV; | |
e9191028 | 915 | bank = irq_data_get_irq_chip_data(d); |
92105bb7 | 916 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
917 | |
918 | return retval; | |
919 | } | |
920 | ||
3ff164e1 | 921 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 922 | { |
3ff164e1 | 923 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 924 | unsigned long flags; |
52e31344 | 925 | |
a6472533 | 926 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 927 | |
4196dd6b TL |
928 | /* Set trigger to none. You need to enable the desired trigger with |
929 | * request_irq() or set_irq_type(). | |
930 | */ | |
3ff164e1 | 931 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 932 | |
1a8bfa1e | 933 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 934 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 935 | void __iomem *reg; |
5e1c5ff4 | 936 | |
92105bb7 | 937 | /* Claim the pin for MPU */ |
5e1c5ff4 | 938 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 939 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
940 | } |
941 | #endif | |
058af1ea C |
942 | if (!cpu_class_is_omap1()) { |
943 | if (!bank->mod_usage) { | |
9f096868 | 944 | void __iomem *reg = bank->base; |
058af1ea | 945 | u32 ctrl; |
9f096868 C |
946 | |
947 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
948 | reg += OMAP24XX_GPIO_CTRL; | |
949 | else if (cpu_is_omap44xx()) | |
950 | reg += OMAP4_GPIO_CTRL; | |
951 | ctrl = __raw_readl(reg); | |
058af1ea | 952 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
953 | ctrl &= 0xFFFFFFFE; |
954 | __raw_writel(ctrl, reg); | |
058af1ea C |
955 | } |
956 | bank->mod_usage |= 1 << offset; | |
957 | } | |
a6472533 | 958 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
959 | |
960 | return 0; | |
961 | } | |
962 | ||
3ff164e1 | 963 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 964 | { |
3ff164e1 | 965 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 966 | unsigned long flags; |
5e1c5ff4 | 967 | |
a6472533 | 968 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
969 | #ifdef CONFIG_ARCH_OMAP16XX |
970 | if (bank->method == METHOD_GPIO_1610) { | |
971 | /* Disable wake-up during idle for dynamic tick */ | |
972 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 973 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
974 | } |
975 | #endif | |
9f096868 C |
976 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
977 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
978 | /* Disable wake-up during idle for dynamic tick */ |
979 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 980 | __raw_writel(1 << offset, reg); |
92105bb7 | 981 | } |
9f096868 C |
982 | #endif |
983 | #ifdef CONFIG_ARCH_OMAP4 | |
984 | if (bank->method == METHOD_GPIO_44XX) { | |
985 | /* Disable wake-up during idle for dynamic tick */ | |
986 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
987 | __raw_writel(1 << offset, reg); | |
988 | } | |
92105bb7 | 989 | #endif |
058af1ea C |
990 | if (!cpu_class_is_omap1()) { |
991 | bank->mod_usage &= ~(1 << offset); | |
992 | if (!bank->mod_usage) { | |
9f096868 | 993 | void __iomem *reg = bank->base; |
058af1ea | 994 | u32 ctrl; |
9f096868 C |
995 | |
996 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
997 | reg += OMAP24XX_GPIO_CTRL; | |
998 | else if (cpu_is_omap44xx()) | |
999 | reg += OMAP4_GPIO_CTRL; | |
1000 | ctrl = __raw_readl(reg); | |
058af1ea C |
1001 | /* Module is disabled, clocks are gated */ |
1002 | ctrl |= 1; | |
9f096868 | 1003 | __raw_writel(ctrl, reg); |
058af1ea C |
1004 | } |
1005 | } | |
3ff164e1 | 1006 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1007 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1008 | } |
1009 | ||
1010 | /* | |
1011 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1012 | * avoid missing GPIO interrupts for other lines in the bank. | |
1013 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1014 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1015 | * If we wait to unmask individual GPIO lines in the bank after the | |
1016 | * line's interrupt handler has been run, we may miss some nested | |
1017 | * interrupts. | |
1018 | */ | |
10dd5ce2 | 1019 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1020 | { |
92105bb7 | 1021 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 1022 | u32 isr; |
4318f36b | 1023 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 1024 | struct gpio_bank *bank; |
ea6dedd7 ID |
1025 | u32 retrigger = 0; |
1026 | int unmasked = 0; | |
ee144182 | 1027 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 1028 | |
ee144182 | 1029 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 1030 | |
6845664a | 1031 | bank = irq_get_handler_data(irq); |
e5c56ed3 | 1032 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 1033 | if (bank->method == METHOD_MPUIO) |
5de62b86 TL |
1034 | isr_reg = bank->base + |
1035 | OMAP_MPUIO_GPIO_INT / bank->stride; | |
e5c56ed3 | 1036 | #endif |
1a8bfa1e | 1037 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1038 | if (bank->method == METHOD_GPIO_1510) |
1039 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1040 | #endif | |
1041 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1042 | if (bank->method == METHOD_GPIO_1610) | |
1043 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1044 | #endif | |
b718aa81 | 1045 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1046 | if (bank->method == METHOD_GPIO_7XX) |
1047 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1048 | #endif |
a8eb7ca0 | 1049 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1050 | if (bank->method == METHOD_GPIO_24XX) |
1051 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1052 | #endif |
1053 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1054 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 1055 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 1056 | #endif |
b1cc4c55 EK |
1057 | |
1058 | if (WARN_ON(!isr_reg)) | |
1059 | goto exit; | |
1060 | ||
92105bb7 | 1061 | while(1) { |
6e60e79a | 1062 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1063 | u32 enabled; |
6e60e79a | 1064 | |
ea6dedd7 ID |
1065 | enabled = _get_gpio_irqbank_mask(bank); |
1066 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1067 | |
1068 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1069 | isr &= 0x0000ffff; | |
1070 | ||
5492fb1a | 1071 | if (cpu_class_is_omap2()) { |
b144ff6f | 1072 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1073 | } |
6e60e79a TL |
1074 | |
1075 | /* clear edge sensitive interrupts before handler(s) are | |
1076 | called so that we don't miss any interrupt occurred while | |
1077 | executing them */ | |
1078 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1079 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1080 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1081 | ||
1082 | /* if there is only edge sensitive GPIO pin interrupts | |
1083 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1084 | if (!level_mask && !unmasked) { |
1085 | unmasked = 1; | |
ee144182 | 1086 | chained_irq_exit(chip, desc); |
ea6dedd7 | 1087 | } |
92105bb7 | 1088 | |
ea6dedd7 ID |
1089 | isr |= retrigger; |
1090 | retrigger = 0; | |
92105bb7 TL |
1091 | if (!isr) |
1092 | break; | |
1093 | ||
1094 | gpio_irq = bank->virtual_irq_start; | |
1095 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
4318f36b CM |
1096 | gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); |
1097 | ||
92105bb7 TL |
1098 | if (!(isr & 1)) |
1099 | continue; | |
29454dde | 1100 | |
4318f36b CM |
1101 | #ifdef CONFIG_ARCH_OMAP1 |
1102 | /* | |
1103 | * Some chips can't respond to both rising and falling | |
1104 | * at the same time. If this irq was requested with | |
1105 | * both flags, we need to flip the ICR data for the IRQ | |
1106 | * to respond to the IRQ for the opposite direction. | |
1107 | * This will be indicated in the bank toggle_mask. | |
1108 | */ | |
1109 | if (bank->toggle_mask & (1 << gpio_index)) | |
1110 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
1111 | #endif | |
1112 | ||
d8aa0251 | 1113 | generic_handle_irq(gpio_irq); |
92105bb7 | 1114 | } |
1a8bfa1e | 1115 | } |
ea6dedd7 ID |
1116 | /* if bank has any level sensitive GPIO pin interrupt |
1117 | configured, we must unmask the bank interrupt only after | |
1118 | handler(s) are executed in order to avoid spurious bank | |
1119 | interrupt */ | |
b1cc4c55 | 1120 | exit: |
ea6dedd7 | 1121 | if (!unmasked) |
ee144182 | 1122 | chained_irq_exit(chip, desc); |
5e1c5ff4 TL |
1123 | } |
1124 | ||
e9191028 | 1125 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 1126 | { |
e9191028 LB |
1127 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1128 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 1129 | unsigned long flags; |
4196dd6b | 1130 | |
85ec7b97 | 1131 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 1132 | _reset_gpio(bank, gpio); |
85ec7b97 | 1133 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
1134 | } |
1135 | ||
e9191028 | 1136 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 1137 | { |
e9191028 LB |
1138 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1139 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1140 | |
1141 | _clear_gpio_irqstatus(bank, gpio); | |
1142 | } | |
1143 | ||
e9191028 | 1144 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 1145 | { |
e9191028 LB |
1146 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1147 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 1148 | unsigned long flags; |
5e1c5ff4 | 1149 | |
85ec7b97 | 1150 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 1151 | _set_gpio_irqenable(bank, gpio, 0); |
55b6019a | 1152 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
85ec7b97 | 1153 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1154 | } |
1155 | ||
e9191028 | 1156 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 1157 | { |
e9191028 LB |
1158 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1159 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
b144ff6f | 1160 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
8c04a176 | 1161 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 1162 | unsigned long flags; |
55b6019a | 1163 | |
85ec7b97 | 1164 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a KH |
1165 | if (trigger) |
1166 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1167 | |
1168 | /* For level-triggered GPIOs, the clearing must be done after | |
1169 | * the HW source is cleared, thus after the handler has run */ | |
1170 | if (bank->level_mask & irq_mask) { | |
1171 | _set_gpio_irqenable(bank, gpio, 0); | |
1172 | _clear_gpio_irqstatus(bank, gpio); | |
1173 | } | |
5e1c5ff4 | 1174 | |
4de8c75b | 1175 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 1176 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1177 | } |
1178 | ||
e5c56ed3 DB |
1179 | static struct irq_chip gpio_irq_chip = { |
1180 | .name = "GPIO", | |
e9191028 LB |
1181 | .irq_shutdown = gpio_irq_shutdown, |
1182 | .irq_ack = gpio_ack_irq, | |
1183 | .irq_mask = gpio_mask_irq, | |
1184 | .irq_unmask = gpio_unmask_irq, | |
1185 | .irq_set_type = gpio_irq_type, | |
1186 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
1187 | }; |
1188 | ||
1189 | /*---------------------------------------------------------------------*/ | |
1190 | ||
1191 | #ifdef CONFIG_ARCH_OMAP1 | |
1192 | ||
1193 | /* MPUIO uses the always-on 32k clock */ | |
1194 | ||
e9191028 | 1195 | static void mpuio_ack_irq(struct irq_data *d) |
5e1c5ff4 TL |
1196 | { |
1197 | /* The ISR is reset automatically, so do nothing here. */ | |
1198 | } | |
1199 | ||
e9191028 | 1200 | static void mpuio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 1201 | { |
e9191028 LB |
1202 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
1203 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1204 | |
1205 | _set_gpio_irqenable(bank, gpio, 0); | |
1206 | } | |
1207 | ||
e9191028 | 1208 | static void mpuio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 1209 | { |
e9191028 LB |
1210 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
1211 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1212 | |
1213 | _set_gpio_irqenable(bank, gpio, 1); | |
1214 | } | |
1215 | ||
e5c56ed3 DB |
1216 | static struct irq_chip mpuio_irq_chip = { |
1217 | .name = "MPUIO", | |
e9191028 LB |
1218 | .irq_ack = mpuio_ack_irq, |
1219 | .irq_mask = mpuio_mask_irq, | |
1220 | .irq_unmask = mpuio_unmask_irq, | |
1221 | .irq_set_type = gpio_irq_type, | |
11a78b79 DB |
1222 | #ifdef CONFIG_ARCH_OMAP16XX |
1223 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
e9191028 | 1224 | .irq_set_wake = gpio_wake_enable, |
11a78b79 | 1225 | #endif |
5e1c5ff4 TL |
1226 | }; |
1227 | ||
e5c56ed3 DB |
1228 | |
1229 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1230 | ||
11a78b79 DB |
1231 | |
1232 | #ifdef CONFIG_ARCH_OMAP16XX | |
1233 | ||
1234 | #include <linux/platform_device.h> | |
1235 | ||
79ee031f | 1236 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1237 | { |
79ee031f | 1238 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1239 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1240 | void __iomem *mask_reg = bank->base + |
1241 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1242 | unsigned long flags; |
11a78b79 | 1243 | |
a6472533 | 1244 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1245 | bank->saved_wakeup = __raw_readl(mask_reg); |
1246 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1247 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1248 | |
1249 | return 0; | |
1250 | } | |
1251 | ||
79ee031f | 1252 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1253 | { |
79ee031f | 1254 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1255 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1256 | void __iomem *mask_reg = bank->base + |
1257 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1258 | unsigned long flags; |
11a78b79 | 1259 | |
a6472533 | 1260 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1261 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1262 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1263 | |
1264 | return 0; | |
1265 | } | |
1266 | ||
47145210 | 1267 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1268 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1269 | .resume_noirq = omap_mpuio_resume_noirq, | |
1270 | }; | |
1271 | ||
3c437ffd | 1272 | /* use platform_driver for this. */ |
11a78b79 | 1273 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
1274 | .driver = { |
1275 | .name = "mpuio", | |
79ee031f | 1276 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1277 | }, |
1278 | }; | |
1279 | ||
1280 | static struct platform_device omap_mpuio_device = { | |
1281 | .name = "mpuio", | |
1282 | .id = -1, | |
1283 | .dev = { | |
1284 | .driver = &omap_mpuio_driver.driver, | |
1285 | } | |
1286 | /* could list the /proc/iomem resources */ | |
1287 | }; | |
1288 | ||
1289 | static inline void mpuio_init(void) | |
1290 | { | |
77640aab VC |
1291 | struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); |
1292 | platform_set_drvdata(&omap_mpuio_device, bank); | |
fcf126d8 | 1293 | |
11a78b79 DB |
1294 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1295 | (void) platform_device_register(&omap_mpuio_device); | |
1296 | } | |
1297 | ||
1298 | #else | |
1299 | static inline void mpuio_init(void) {} | |
1300 | #endif /* 16xx */ | |
1301 | ||
e5c56ed3 DB |
1302 | #else |
1303 | ||
1304 | extern struct irq_chip mpuio_irq_chip; | |
1305 | ||
1306 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1307 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1308 | |
1309 | #endif | |
1310 | ||
1311 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1312 | |
52e31344 DB |
1313 | /* REVISIT these are stupid implementations! replace by ones that |
1314 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1315 | */ | |
1316 | ||
1317 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1318 | { | |
1319 | struct gpio_bank *bank; | |
1320 | unsigned long flags; | |
1321 | ||
1322 | bank = container_of(chip, struct gpio_bank, chip); | |
1323 | spin_lock_irqsave(&bank->lock, flags); | |
1324 | _set_gpio_direction(bank, offset, 1); | |
1325 | spin_unlock_irqrestore(&bank->lock, flags); | |
1326 | return 0; | |
1327 | } | |
1328 | ||
b37c45b8 RQ |
1329 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1330 | { | |
1331 | void __iomem *reg = bank->base; | |
1332 | ||
1333 | switch (bank->method) { | |
1334 | case METHOD_MPUIO: | |
5de62b86 | 1335 | reg += OMAP_MPUIO_IO_CNTL / bank->stride; |
b37c45b8 RQ |
1336 | break; |
1337 | case METHOD_GPIO_1510: | |
1338 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1339 | break; | |
1340 | case METHOD_GPIO_1610: | |
1341 | reg += OMAP1610_GPIO_DIRECTION; | |
1342 | break; | |
7c006926 AB |
1343 | case METHOD_GPIO_7XX: |
1344 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1345 | break; |
1346 | case METHOD_GPIO_24XX: | |
1347 | reg += OMAP24XX_GPIO_OE; | |
1348 | break; | |
9f096868 C |
1349 | case METHOD_GPIO_44XX: |
1350 | reg += OMAP4_GPIO_OE; | |
1351 | break; | |
1352 | default: | |
1353 | WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); | |
1354 | return -EINVAL; | |
b37c45b8 RQ |
1355 | } |
1356 | return __raw_readl(reg) & mask; | |
1357 | } | |
1358 | ||
52e31344 DB |
1359 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1360 | { | |
b37c45b8 RQ |
1361 | struct gpio_bank *bank; |
1362 | void __iomem *reg; | |
1363 | int gpio; | |
1364 | u32 mask; | |
1365 | ||
1366 | gpio = chip->base + offset; | |
1367 | bank = get_gpio_bank(gpio); | |
1368 | reg = bank->base; | |
1369 | mask = 1 << get_gpio_index(gpio); | |
1370 | ||
1371 | if (gpio_is_input(bank, mask)) | |
1372 | return _get_gpio_datain(bank, gpio); | |
1373 | else | |
1374 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1375 | } |
1376 | ||
1377 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1378 | { | |
1379 | struct gpio_bank *bank; | |
1380 | unsigned long flags; | |
1381 | ||
1382 | bank = container_of(chip, struct gpio_bank, chip); | |
1383 | spin_lock_irqsave(&bank->lock, flags); | |
1384 | _set_gpio_dataout(bank, offset, value); | |
1385 | _set_gpio_direction(bank, offset, 0); | |
1386 | spin_unlock_irqrestore(&bank->lock, flags); | |
1387 | return 0; | |
1388 | } | |
1389 | ||
168ef3d9 FB |
1390 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1391 | unsigned debounce) | |
1392 | { | |
1393 | struct gpio_bank *bank; | |
1394 | unsigned long flags; | |
1395 | ||
1396 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
1397 | |
1398 | if (!bank->dbck) { | |
1399 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1400 | if (IS_ERR(bank->dbck)) | |
1401 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
1402 | } | |
1403 | ||
168ef3d9 FB |
1404 | spin_lock_irqsave(&bank->lock, flags); |
1405 | _set_gpio_debounce(bank, offset, debounce); | |
1406 | spin_unlock_irqrestore(&bank->lock, flags); | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
52e31344 DB |
1411 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1412 | { | |
1413 | struct gpio_bank *bank; | |
1414 | unsigned long flags; | |
1415 | ||
1416 | bank = container_of(chip, struct gpio_bank, chip); | |
1417 | spin_lock_irqsave(&bank->lock, flags); | |
1418 | _set_gpio_dataout(bank, offset, value); | |
1419 | spin_unlock_irqrestore(&bank->lock, flags); | |
1420 | } | |
1421 | ||
a007b709 DB |
1422 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1423 | { | |
1424 | struct gpio_bank *bank; | |
1425 | ||
1426 | bank = container_of(chip, struct gpio_bank, chip); | |
1427 | return bank->virtual_irq_start + offset; | |
1428 | } | |
1429 | ||
52e31344 DB |
1430 | /*---------------------------------------------------------------------*/ |
1431 | ||
9a748053 | 1432 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da TL |
1433 | { |
1434 | u32 rev; | |
1435 | ||
9a748053 TL |
1436 | if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) |
1437 | rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION); | |
9f7065da | 1438 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
9a748053 | 1439 | rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION); |
9f7065da | 1440 | else if (cpu_is_omap44xx()) |
9a748053 | 1441 | rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION); |
9f7065da TL |
1442 | else |
1443 | return; | |
1444 | ||
1445 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1446 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1447 | } | |
1448 | ||
8ba55c5c DB |
1449 | /* This lock class tells lockdep that GPIO irqs are in a different |
1450 | * category than their parents, so it won't report false recursion. | |
1451 | */ | |
1452 | static struct lock_class_key gpio_lock_class; | |
1453 | ||
77640aab VC |
1454 | static inline int init_gpio_info(struct platform_device *pdev) |
1455 | { | |
1456 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ | |
1457 | gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), | |
1458 | GFP_KERNEL); | |
1459 | if (!gpio_bank) { | |
1460 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1461 | return -ENOMEM; | |
1462 | } | |
1463 | return 0; | |
1464 | } | |
1465 | ||
1466 | /* TODO: Cleanup cpu_is_* checks */ | |
2fae7fbe VC |
1467 | static void omap_gpio_mod_init(struct gpio_bank *bank, int id) |
1468 | { | |
1469 | if (cpu_class_is_omap2()) { | |
1470 | if (cpu_is_omap44xx()) { | |
1471 | __raw_writel(0xffffffff, bank->base + | |
1472 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1473 | __raw_writel(0x00000000, bank->base + | |
1474 | OMAP4_GPIO_DEBOUNCENABLE); | |
1475 | /* Initialize interface clk ungated, module enabled */ | |
1476 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1477 | } else if (cpu_is_omap34xx()) { | |
1478 | __raw_writel(0x00000000, bank->base + | |
1479 | OMAP24XX_GPIO_IRQENABLE1); | |
1480 | __raw_writel(0xffffffff, bank->base + | |
1481 | OMAP24XX_GPIO_IRQSTATUS1); | |
1482 | __raw_writel(0x00000000, bank->base + | |
1483 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1484 | ||
1485 | /* Initialize interface clk ungated, module enabled */ | |
1486 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
1487 | } else if (cpu_is_omap24xx()) { | |
1488 | static const u32 non_wakeup_gpios[] = { | |
1489 | 0xe203ffc0, 0x08700040 | |
1490 | }; | |
1491 | if (id < ARRAY_SIZE(non_wakeup_gpios)) | |
1492 | bank->non_wakeup_gpios = non_wakeup_gpios[id]; | |
1493 | } | |
1494 | } else if (cpu_class_is_omap1()) { | |
1495 | if (bank_is_mpuio(bank)) | |
5de62b86 TL |
1496 | __raw_writew(0xffff, bank->base + |
1497 | OMAP_MPUIO_GPIO_MASKIT / bank->stride); | |
2fae7fbe VC |
1498 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
1499 | __raw_writew(0xffff, bank->base | |
1500 | + OMAP1510_GPIO_INT_MASK); | |
1501 | __raw_writew(0x0000, bank->base | |
1502 | + OMAP1510_GPIO_INT_STATUS); | |
1503 | } | |
1504 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | |
1505 | __raw_writew(0x0000, bank->base | |
1506 | + OMAP1610_GPIO_IRQENABLE1); | |
1507 | __raw_writew(0xffff, bank->base | |
1508 | + OMAP1610_GPIO_IRQSTATUS1); | |
1509 | __raw_writew(0x0014, bank->base | |
1510 | + OMAP1610_GPIO_SYSCONFIG); | |
1511 | ||
1512 | /* | |
1513 | * Enable system clock for GPIO module. | |
1514 | * The CAM_CLK_CTRL *is* really the right place. | |
1515 | */ | |
1516 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | |
1517 | ULPD_CAM_CLK_CTRL); | |
1518 | } | |
1519 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | |
1520 | __raw_writel(0xffffffff, bank->base | |
1521 | + OMAP7XX_GPIO_INT_MASK); | |
1522 | __raw_writel(0x00000000, bank->base | |
1523 | + OMAP7XX_GPIO_INT_STATUS); | |
1524 | } | |
1525 | } | |
1526 | } | |
1527 | ||
d52b31de | 1528 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1529 | { |
77640aab | 1530 | int j; |
2fae7fbe VC |
1531 | static int gpio; |
1532 | ||
2fae7fbe VC |
1533 | bank->mod_usage = 0; |
1534 | /* | |
1535 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1536 | * over to the generic ones | |
1537 | */ | |
1538 | bank->chip.request = omap_gpio_request; | |
1539 | bank->chip.free = omap_gpio_free; | |
1540 | bank->chip.direction_input = gpio_input; | |
1541 | bank->chip.get = gpio_get; | |
1542 | bank->chip.direction_output = gpio_output; | |
1543 | bank->chip.set_debounce = gpio_debounce; | |
1544 | bank->chip.set = gpio_set; | |
1545 | bank->chip.to_irq = gpio_2irq; | |
1546 | if (bank_is_mpuio(bank)) { | |
1547 | bank->chip.label = "mpuio"; | |
1548 | #ifdef CONFIG_ARCH_OMAP16XX | |
1549 | bank->chip.dev = &omap_mpuio_device.dev; | |
1550 | #endif | |
1551 | bank->chip.base = OMAP_MPUIO(0); | |
1552 | } else { | |
1553 | bank->chip.label = "gpio"; | |
1554 | bank->chip.base = gpio; | |
1555 | gpio += bank_width; | |
1556 | } | |
1557 | bank->chip.ngpio = bank_width; | |
1558 | ||
1559 | gpiochip_add(&bank->chip); | |
1560 | ||
1561 | for (j = bank->virtual_irq_start; | |
1562 | j < bank->virtual_irq_start + bank_width; j++) { | |
1475b85d | 1563 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1564 | irq_set_chip_data(j, bank); |
2fae7fbe | 1565 | if (bank_is_mpuio(bank)) |
6845664a | 1566 | irq_set_chip(j, &mpuio_irq_chip); |
2fae7fbe | 1567 | else |
6845664a TG |
1568 | irq_set_chip(j, &gpio_irq_chip); |
1569 | irq_set_handler(j, handle_simple_irq); | |
2fae7fbe VC |
1570 | set_irq_flags(j, IRQF_VALID); |
1571 | } | |
6845664a TG |
1572 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1573 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1574 | } |
1575 | ||
77640aab | 1576 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1577 | { |
77640aab VC |
1578 | static int gpio_init_done; |
1579 | struct omap_gpio_platform_data *pdata; | |
1580 | struct resource *res; | |
1581 | int id; | |
5e1c5ff4 TL |
1582 | struct gpio_bank *bank; |
1583 | ||
77640aab VC |
1584 | if (!pdev->dev.platform_data) |
1585 | return -EINVAL; | |
5e1c5ff4 | 1586 | |
77640aab | 1587 | pdata = pdev->dev.platform_data; |
56a25641 | 1588 | |
77640aab VC |
1589 | if (!gpio_init_done) { |
1590 | int ret; | |
5492fb1a | 1591 | |
77640aab VC |
1592 | ret = init_gpio_info(pdev); |
1593 | if (ret) | |
1594 | return ret; | |
5492fb1a | 1595 | } |
5492fb1a | 1596 | |
77640aab VC |
1597 | id = pdev->id; |
1598 | bank = &gpio_bank[id]; | |
92105bb7 | 1599 | |
77640aab VC |
1600 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1601 | if (unlikely(!res)) { | |
1602 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); | |
1603 | return -ENODEV; | |
44169075 | 1604 | } |
5e1c5ff4 | 1605 | |
77640aab VC |
1606 | bank->irq = res->start; |
1607 | bank->virtual_irq_start = pdata->virtual_irq_start; | |
1608 | bank->method = pdata->bank_type; | |
1609 | bank->dev = &pdev->dev; | |
1610 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1611 | bank->stride = pdata->bank_stride; |
77640aab | 1612 | bank_width = pdata->bank_width; |
9f7065da | 1613 | |
77640aab | 1614 | spin_lock_init(&bank->lock); |
9f7065da | 1615 | |
77640aab VC |
1616 | /* Static mapping, never released */ |
1617 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1618 | if (unlikely(!res)) { | |
1619 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); | |
1620 | return -ENODEV; | |
1621 | } | |
89db9482 | 1622 | |
77640aab VC |
1623 | bank->base = ioremap(res->start, resource_size(res)); |
1624 | if (!bank->base) { | |
1625 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); | |
1626 | return -ENOMEM; | |
5e1c5ff4 TL |
1627 | } |
1628 | ||
77640aab VC |
1629 | pm_runtime_enable(bank->dev); |
1630 | pm_runtime_get_sync(bank->dev); | |
1631 | ||
1632 | omap_gpio_mod_init(bank, id); | |
1633 | omap_gpio_chip_init(bank); | |
9a748053 | 1634 | omap_gpio_show_rev(bank); |
9f7065da | 1635 | |
77640aab VC |
1636 | if (!gpio_init_done) |
1637 | gpio_init_done = 1; | |
1638 | ||
5e1c5ff4 TL |
1639 | return 0; |
1640 | } | |
1641 | ||
140455fa | 1642 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd | 1643 | static int omap_gpio_suspend(void) |
92105bb7 TL |
1644 | { |
1645 | int i; | |
1646 | ||
5492fb1a | 1647 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1648 | return 0; |
1649 | ||
1650 | for (i = 0; i < gpio_bank_count; i++) { | |
1651 | struct gpio_bank *bank = &gpio_bank[i]; | |
1652 | void __iomem *wake_status; | |
1653 | void __iomem *wake_clear; | |
1654 | void __iomem *wake_set; | |
a6472533 | 1655 | unsigned long flags; |
92105bb7 TL |
1656 | |
1657 | switch (bank->method) { | |
e5c56ed3 | 1658 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1659 | case METHOD_GPIO_1610: |
1660 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1661 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1662 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1663 | break; | |
e5c56ed3 | 1664 | #endif |
a8eb7ca0 | 1665 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1666 | case METHOD_GPIO_24XX: |
723fdb78 | 1667 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1668 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1669 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1670 | break; | |
78a1a6d3 SR |
1671 | #endif |
1672 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1673 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1674 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1675 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1676 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1677 | break; | |
e5c56ed3 | 1678 | #endif |
92105bb7 TL |
1679 | default: |
1680 | continue; | |
1681 | } | |
1682 | ||
a6472533 | 1683 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1684 | bank->saved_wakeup = __raw_readl(wake_status); |
1685 | __raw_writel(0xffffffff, wake_clear); | |
1686 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1687 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1688 | } |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
3c437ffd | 1693 | static void omap_gpio_resume(void) |
92105bb7 TL |
1694 | { |
1695 | int i; | |
1696 | ||
723fdb78 | 1697 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
3c437ffd | 1698 | return; |
92105bb7 TL |
1699 | |
1700 | for (i = 0; i < gpio_bank_count; i++) { | |
1701 | struct gpio_bank *bank = &gpio_bank[i]; | |
1702 | void __iomem *wake_clear; | |
1703 | void __iomem *wake_set; | |
a6472533 | 1704 | unsigned long flags; |
92105bb7 TL |
1705 | |
1706 | switch (bank->method) { | |
e5c56ed3 | 1707 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1708 | case METHOD_GPIO_1610: |
1709 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1710 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1711 | break; | |
e5c56ed3 | 1712 | #endif |
a8eb7ca0 | 1713 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1714 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1715 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1716 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1717 | break; |
78a1a6d3 SR |
1718 | #endif |
1719 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1720 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1721 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1722 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1723 | break; | |
e5c56ed3 | 1724 | #endif |
92105bb7 TL |
1725 | default: |
1726 | continue; | |
1727 | } | |
1728 | ||
a6472533 | 1729 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1730 | __raw_writel(0xffffffff, wake_clear); |
1731 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1732 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1733 | } |
92105bb7 TL |
1734 | } |
1735 | ||
3c437ffd | 1736 | static struct syscore_ops omap_gpio_syscore_ops = { |
92105bb7 TL |
1737 | .suspend = omap_gpio_suspend, |
1738 | .resume = omap_gpio_resume, | |
1739 | }; | |
1740 | ||
3ac4fa99 JY |
1741 | #endif |
1742 | ||
140455fa | 1743 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
1744 | |
1745 | static int workaround_enabled; | |
1746 | ||
72e06d08 | 1747 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 JY |
1748 | { |
1749 | int i, c = 0; | |
a118b5f3 | 1750 | int min = 0; |
3ac4fa99 | 1751 | |
a118b5f3 TK |
1752 | if (cpu_is_omap34xx()) |
1753 | min = 1; | |
43ffcd9a | 1754 | |
a118b5f3 | 1755 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 | 1756 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1757 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1758 | int j; |
3ac4fa99 | 1759 | |
0aed0435 | 1760 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1761 | clk_disable(bank->dbck); |
1762 | ||
72e06d08 | 1763 | if (!off_mode) |
43ffcd9a KH |
1764 | continue; |
1765 | ||
1766 | /* If going to OFF, remove triggering for all | |
1767 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1768 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
1769 | if (!(bank->enabled_non_wakeup_gpios)) |
1770 | continue; | |
3f1686a9 TL |
1771 | |
1772 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1773 | bank->saved_datain = __raw_readl(bank->base + | |
1774 | OMAP24XX_GPIO_DATAIN); | |
1775 | l1 = __raw_readl(bank->base + | |
1776 | OMAP24XX_GPIO_FALLINGDETECT); | |
1777 | l2 = __raw_readl(bank->base + | |
1778 | OMAP24XX_GPIO_RISINGDETECT); | |
1779 | } | |
1780 | ||
1781 | if (cpu_is_omap44xx()) { | |
1782 | bank->saved_datain = __raw_readl(bank->base + | |
1783 | OMAP4_GPIO_DATAIN); | |
1784 | l1 = __raw_readl(bank->base + | |
1785 | OMAP4_GPIO_FALLINGDETECT); | |
1786 | l2 = __raw_readl(bank->base + | |
1787 | OMAP4_GPIO_RISINGDETECT); | |
1788 | } | |
1789 | ||
3ac4fa99 JY |
1790 | bank->saved_fallingdetect = l1; |
1791 | bank->saved_risingdetect = l2; | |
1792 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1793 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
1794 | |
1795 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1796 | __raw_writel(l1, bank->base + | |
1797 | OMAP24XX_GPIO_FALLINGDETECT); | |
1798 | __raw_writel(l2, bank->base + | |
1799 | OMAP24XX_GPIO_RISINGDETECT); | |
1800 | } | |
1801 | ||
1802 | if (cpu_is_omap44xx()) { | |
1803 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1804 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
1805 | } | |
1806 | ||
3ac4fa99 JY |
1807 | c++; |
1808 | } | |
1809 | if (!c) { | |
1810 | workaround_enabled = 0; | |
1811 | return; | |
1812 | } | |
1813 | workaround_enabled = 1; | |
1814 | } | |
1815 | ||
43ffcd9a | 1816 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
1817 | { |
1818 | int i; | |
a118b5f3 | 1819 | int min = 0; |
3ac4fa99 | 1820 | |
a118b5f3 TK |
1821 | if (cpu_is_omap34xx()) |
1822 | min = 1; | |
1823 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 1824 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1825 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1826 | int j; |
3ac4fa99 | 1827 | |
0aed0435 | 1828 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1829 | clk_enable(bank->dbck); |
1830 | ||
43ffcd9a KH |
1831 | if (!workaround_enabled) |
1832 | continue; | |
1833 | ||
3ac4fa99 JY |
1834 | if (!(bank->enabled_non_wakeup_gpios)) |
1835 | continue; | |
3f1686a9 TL |
1836 | |
1837 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1838 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 1839 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 1840 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 1841 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
1842 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1843 | } | |
1844 | ||
1845 | if (cpu_is_omap44xx()) { | |
1846 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 1847 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 1848 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 1849 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
1850 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
1851 | } | |
1852 | ||
3ac4fa99 JY |
1853 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1854 | * state. If so, generate an IRQ by software. This is | |
1855 | * horribly racy, but it's the best we can do to work around | |
1856 | * this silicon bug. */ | |
3ac4fa99 | 1857 | l ^= bank->saved_datain; |
a118b5f3 | 1858 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1859 | |
1860 | /* | |
1861 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1862 | * configured with falling edge only; and vice versa. | |
1863 | */ | |
1864 | gen0 = l & bank->saved_fallingdetect; | |
1865 | gen0 &= bank->saved_datain; | |
1866 | ||
1867 | gen1 = l & bank->saved_risingdetect; | |
1868 | gen1 &= ~(bank->saved_datain); | |
1869 | ||
1870 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1871 | gen = l & (~(bank->saved_fallingdetect) & | |
1872 | ~(bank->saved_risingdetect)); | |
1873 | /* Consider all GPIO IRQs needed to be updated */ | |
1874 | gen |= gen0 | gen1; | |
1875 | ||
1876 | if (gen) { | |
3ac4fa99 | 1877 | u32 old0, old1; |
3f1686a9 | 1878 | |
f00d6497 | 1879 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
1880 | old0 = __raw_readl(bank->base + |
1881 | OMAP24XX_GPIO_LEVELDETECT0); | |
1882 | old1 = __raw_readl(bank->base + | |
1883 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 1884 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 1885 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1886 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 1887 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 1888 | __raw_writel(old0, bank->base + |
3f1686a9 | 1889 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1890 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
1891 | OMAP24XX_GPIO_LEVELDETECT1); |
1892 | } | |
1893 | ||
1894 | if (cpu_is_omap44xx()) { | |
1895 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 1896 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1897 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 1898 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1899 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 1900 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1901 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 1902 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1903 | __raw_writel(old0, bank->base + |
78a1a6d3 | 1904 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1905 | __raw_writel(old1, bank->base + |
78a1a6d3 | 1906 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1907 | } |
3ac4fa99 JY |
1908 | } |
1909 | } | |
1910 | ||
1911 | } | |
1912 | ||
92105bb7 TL |
1913 | #endif |
1914 | ||
a8eb7ca0 | 1915 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
1916 | /* save the registers of bank 2-6 */ |
1917 | void omap_gpio_save_context(void) | |
1918 | { | |
1919 | int i; | |
1920 | ||
1921 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
1922 | for (i = 1; i < gpio_bank_count; i++) { | |
1923 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1924 | gpio_context[i].irqenable1 = |
1925 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1926 | gpio_context[i].irqenable2 = | |
1927 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1928 | gpio_context[i].wake_en = | |
1929 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1930 | gpio_context[i].ctrl = | |
1931 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1932 | gpio_context[i].oe = | |
1933 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
1934 | gpio_context[i].leveldetect0 = | |
1935 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1936 | gpio_context[i].leveldetect1 = | |
1937 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1938 | gpio_context[i].risingdetect = | |
1939 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1940 | gpio_context[i].fallingdetect = | |
1941 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1942 | gpio_context[i].dataout = | |
1943 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1944 | } |
1945 | } | |
1946 | ||
1947 | /* restore the required registers of bank 2-6 */ | |
1948 | void omap_gpio_restore_context(void) | |
1949 | { | |
1950 | int i; | |
1951 | ||
1952 | for (i = 1; i < gpio_bank_count; i++) { | |
1953 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1954 | __raw_writel(gpio_context[i].irqenable1, |
1955 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1956 | __raw_writel(gpio_context[i].irqenable2, | |
1957 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1958 | __raw_writel(gpio_context[i].wake_en, | |
1959 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1960 | __raw_writel(gpio_context[i].ctrl, | |
1961 | bank->base + OMAP24XX_GPIO_CTRL); | |
1962 | __raw_writel(gpio_context[i].oe, | |
1963 | bank->base + OMAP24XX_GPIO_OE); | |
1964 | __raw_writel(gpio_context[i].leveldetect0, | |
1965 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1966 | __raw_writel(gpio_context[i].leveldetect1, | |
1967 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1968 | __raw_writel(gpio_context[i].risingdetect, | |
1969 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1970 | __raw_writel(gpio_context[i].fallingdetect, | |
1971 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1972 | __raw_writel(gpio_context[i].dataout, | |
1973 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1974 | } |
1975 | } | |
1976 | #endif | |
1977 | ||
77640aab VC |
1978 | static struct platform_driver omap_gpio_driver = { |
1979 | .probe = omap_gpio_probe, | |
1980 | .driver = { | |
1981 | .name = "omap_gpio", | |
1982 | }, | |
1983 | }; | |
1984 | ||
5e1c5ff4 | 1985 | /* |
77640aab VC |
1986 | * gpio driver register needs to be done before |
1987 | * machine_init functions access gpio APIs. | |
1988 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1989 | */ |
77640aab | 1990 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1991 | { |
77640aab | 1992 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1993 | } |
77640aab | 1994 | postcore_initcall(omap_gpio_drv_reg); |
5e1c5ff4 | 1995 | |
92105bb7 TL |
1996 | static int __init omap_gpio_sysinit(void) |
1997 | { | |
11a78b79 DB |
1998 | mpuio_init(); |
1999 | ||
140455fa | 2000 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd RW |
2001 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) |
2002 | register_syscore_ops(&omap_gpio_syscore_ops); | |
92105bb7 TL |
2003 | #endif |
2004 | ||
3c437ffd | 2005 | return 0; |
92105bb7 TL |
2006 | } |
2007 | ||
92105bb7 | 2008 | arch_initcall(omap_gpio_sysinit); |