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gpio/omap: handle save/restore context in GPIO driver
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb 27#include <mach/irqs.h>
1bc857f7 28#include <asm/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
03e128ca
C		 31static LIST_HEAD(omap_gpio_list);
32
6d62e216
C		 33struct gpio_regs {
34 u32 irqenable1;
35 u32 irqenable2;
36 u32 wake_en;
37 u32 ctrl;
38 u32 oe;
39 u32 leveldetect0;
40 u32 leveldetect1;
41 u32 risingdetect;
42 u32 fallingdetect;
43 u32 dataout;
44};
45
5e1c5ff4 46struct gpio_bank {
03e128ca 47 struct list_head node;
9f7065da 48 unsigned long pbase;
92105bb7 49 void __iomem *base;
5e1c5ff4
TL		 50 u16 irq;
51 u16 virtual_irq_start;
92105bb7 52 int method;
92105bb7 53 u32 suspend_wakeup;
78a43158 54#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7 55 u32 saved_wakeup;
3ac4fa99 56#endif
3ac4fa99
JY		 57 u32 non_wakeup_gpios;
58 u32 enabled_non_wakeup_gpios;
6d62e216 59 struct gpio_regs context;
3ac4fa99
JY		 60 u32 saved_datain;
61 u32 saved_fallingdetect;
62 u32 saved_risingdetect;
b144ff6f 63 u32 level_mask;
4318f36b 64 u32 toggle_mask;
5e1c5ff4 65 spinlock_t lock;
52e31344 66 struct gpio_chip chip;
89db9482 67 struct clk *dbck;
058af1ea 68 u32 mod_usage;
8865b9b6 69 u32 dbck_enable_mask;
77640aab
VC		 70 struct device *dev;
71 bool dbck_flag;
0cde8d03 72 bool loses_context;
5de62b86 73 int stride;
d5f46247 74 u32 width;
60a3437d 75 int context_loss_count;
03e128ca 76 u16 id;
fa87931a
KH		 77
78 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60a3437d 79 int (*get_context_loss_count)(struct device *dev);
fa87931a
KH		 80
81 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 82};
83
129fd223
KH		 84#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
5e1c5ff4
TL		 86
87static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
88{
92105bb7 89 void __iomem *reg = bank->base;
5e1c5ff4
TL		 90 u32 l;
91
fa87931a 92 reg += bank->regs->direction;
5e1c5ff4
TL		 93 l = __raw_readl(reg);
94 if (is_input)
95 l |= 1 << gpio;
96 else
97 l &= ~(1 << gpio);
98 __raw_writel(l, reg);
99}
100
fa87931a
KH		 101
102/* set data out value using dedicate set/clear register */
103static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 104{
92105bb7 105 void __iomem *reg = bank->base;
fa87931a 106 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 107
fa87931a
KH		 108 if (enable)
109 reg += bank->regs->set_dataout;
110 else
111 reg += bank->regs->clr_dataout;
5e1c5ff4 112
5e1c5ff4
TL		 113 __raw_writel(l, reg);
114}
115
fa87931a
KH		 116/* set data out value using mask register */
117static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 118{
fa87931a
KH		 119 void __iomem *reg = bank->base + bank->regs->dataout;
120 u32 gpio_bit = GPIO_BIT(bank, gpio);
121 u32 l;
5e1c5ff4 122
fa87931a
KH		 123 l = __raw_readl(reg);
124 if (enable)
125 l |= gpio_bit;
126 else
127 l &= ~gpio_bit;
5e1c5ff4 128 __raw_writel(l, reg);
5e1c5ff4
TL		 129}
130
b37c45b8 131static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
b37c45b8 132{
fa87931a 133 void __iomem *reg = bank->base + bank->regs->datain;
b37c45b8 134
fa87931a 135 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
5e1c5ff4 136}
b37c45b8 137
b37c45b8
RQ		 138static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
139{
fa87931a 140 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8 141
129fd223 142 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
b37c45b8
RQ		 143}
144
ece9528e
KH		 145static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
146{
147 int l = __raw_readl(base + reg);
148
149 if (set)
150 l |= mask;
151 else
152 l &= ~mask;
153
154 __raw_writel(l, base + reg);
155}
92105bb7 156
168ef3d9
FB		 157/**
158 * _set_gpio_debounce - low level gpio debounce time
159 * @bank: the gpio bank we're acting upon
160 * @gpio: the gpio number on this @gpio
161 * @debounce: debounce time to use
162 *
163 * OMAP's debounce time is in 31us steps so we need
164 * to convert and round up to the closest unit.
165 */
166static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
167 unsigned debounce)
168{
9942da0e 169 void __iomem *reg;
168ef3d9
FB		 170 u32 val;
171 u32 l;
172
77640aab
VC		 173 if (!bank->dbck_flag)
174 return;
175
168ef3d9
FB		 176 if (debounce < 32)
177 debounce = 0x01;
178 else if (debounce > 7936)
179 debounce = 0xff;
180 else
181 debounce = (debounce / 0x1f) - 1;
182
129fd223 183 l = GPIO_BIT(bank, gpio);
168ef3d9 184
9942da0e 185 reg = bank->base + bank->regs->debounce;
168ef3d9
FB		 186 __raw_writel(debounce, reg);
187
9942da0e 188 reg = bank->base + bank->regs->debounce_en;
168ef3d9
FB		 189 val = __raw_readl(reg);
190
191 if (debounce) {
192 val |= l;
77640aab 193 clk_enable(bank->dbck);
168ef3d9
FB		 194 } else {
195 val &= ~l;
77640aab 196 clk_disable(bank->dbck);
168ef3d9 197 }
f7ec0b0b 198 bank->dbck_enable_mask = val;
168ef3d9
FB		 199
200 __raw_writel(val, reg);
201}
202
140455fa 203#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 204static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
205 int trigger)
5e1c5ff4 206{
3ac4fa99 207 void __iomem *base = bank->base;
92105bb7
TL		 208 u32 gpio_bit = 1 << gpio;
209
78a1a6d3 210 if (cpu_is_omap44xx()) {
ece9528e
KH		 211 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
212 trigger & IRQ_TYPE_LEVEL_LOW);
213 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
214 trigger & IRQ_TYPE_LEVEL_HIGH);
215 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
216 trigger & IRQ_TYPE_EDGE_RISING);
217 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
218 trigger & IRQ_TYPE_EDGE_FALLING);
78a1a6d3 219 } else {
ece9528e
KH		 220 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
221 trigger & IRQ_TYPE_LEVEL_LOW);
222 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
223 trigger & IRQ_TYPE_LEVEL_HIGH);
224 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
225 trigger & IRQ_TYPE_EDGE_RISING);
226 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
227 trigger & IRQ_TYPE_EDGE_FALLING);
78a1a6d3 228 }
3ac4fa99 229 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 230 if (cpu_is_omap44xx()) {
ece9528e
KH		 231 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
232 trigger != 0);
78a1a6d3 233 } else {
699117a6
CW		 234 /*
235 * GPIO wakeup request can only be generated on edge
236 * transitions
237 */
238 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 239 __raw_writel(1 << gpio, bank->base
5eb3bb9c 240 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 241 else
242 __raw_writel(1 << gpio, bank->base
5eb3bb9c 243 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 244 }
a118b5f3 245 }
55b220ca
A		 246 /* This part needs to be executed always for OMAP{34xx, 44xx} */
247 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
248 (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 249 /*
250 * Log the edge gpio and manually trigger the IRQ
251 * after resume if the input level changes
252 * to avoid irq lost during PER RET/OFF mode
253 * Applies for omap2 non-wakeup gpio and all omap3 gpios
254 */
255 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 256 bank->enabled_non_wakeup_gpios |= gpio_bit;
257 else
258 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
259 }
5eb3bb9c 260
78a1a6d3
SR		 261 if (cpu_is_omap44xx()) {
262 bank->level_mask =
263 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
264 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
265 } else {
266 bank->level_mask =
267 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
268 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
269 }
92105bb7 270}
3ac4fa99 271#endif
92105bb7 272
9198bcd3 273#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 274/*
275 * This only applies to chips that can't do both rising and falling edge
276 * detection at once. For all other chips, this function is a noop.
277 */
278static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
279{
280 void __iomem *reg = bank->base;
281 u32 l = 0;
282
283 switch (bank->method) {
4318f36b 284 case METHOD_MPUIO:
5de62b86 285 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 286 break;
4318f36b
CM		 287#ifdef CONFIG_ARCH_OMAP15XX
288 case METHOD_GPIO_1510:
289 reg += OMAP1510_GPIO_INT_CONTROL;
290 break;
291#endif
292#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
293 case METHOD_GPIO_7XX:
294 reg += OMAP7XX_GPIO_INT_CONTROL;
295 break;
296#endif
297 default:
298 return;
299 }
300
301 l = __raw_readl(reg);
302 if ((l >> gpio) & 1)
303 l &= ~(1 << gpio);
304 else
305 l |= 1 << gpio;
306
307 __raw_writel(l, reg);
308}
9198bcd3 309#endif
4318f36b 310
92105bb7
TL		 311static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
312{
313 void __iomem *reg = bank->base;
314 u32 l = 0;
5e1c5ff4
TL		 315
316 switch (bank->method) {
e5c56ed3 317#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 318 case METHOD_MPUIO:
5de62b86 319 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 320 l = __raw_readl(reg);
29501577 321 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 322 bank->toggle_mask |= 1 << gpio;
6cab4860 323 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 324 l |= 1 << gpio;
6cab4860 325 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 326 l &= ~(1 << gpio);
92105bb7
TL		 327 else
328 goto bad;
5e1c5ff4 329 break;
e5c56ed3
DB		 330#endif
331#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 332 case METHOD_GPIO_1510:
333 reg += OMAP1510_GPIO_INT_CONTROL;
334 l = __raw_readl(reg);
29501577 335 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 336 bank->toggle_mask |= 1 << gpio;
6cab4860 337 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 338 l |= 1 << gpio;
6cab4860 339 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 340 l &= ~(1 << gpio);
92105bb7
TL		 341 else
342 goto bad;
5e1c5ff4 343 break;
e5c56ed3 344#endif
3ac4fa99 345#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 346 case METHOD_GPIO_1610:
5e1c5ff4
TL		 347 if (gpio & 0x08)
348 reg += OMAP1610_GPIO_EDGE_CTRL2;
349 else
350 reg += OMAP1610_GPIO_EDGE_CTRL1;
351 gpio &= 0x07;
352 l = __raw_readl(reg);
353 l &= ~(3 << (gpio << 1));
6cab4860 354 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 355 l |= 2 << (gpio << 1);
6cab4860 356 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 357 l |= 1 << (gpio << 1);
3ac4fa99
JY		 358 if (trigger)
359 /* Enable wake-up during idle for dynamic tick */
360 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
361 else
362 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 363 break;
3ac4fa99 364#endif
b718aa81 365#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 366 case METHOD_GPIO_7XX:
367 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 368 l = __raw_readl(reg);
29501577 369 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 370 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 371 if (trigger & IRQ_TYPE_EDGE_RISING)
372 l |= 1 << gpio;
373 else if (trigger & IRQ_TYPE_EDGE_FALLING)
374 l &= ~(1 << gpio);
375 else
376 goto bad;
377 break;
378#endif
140455fa 379#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 380 case METHOD_GPIO_24XX:
3f1686a9 381 case METHOD_GPIO_44XX:
3ac4fa99 382 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 383 return 0;
3ac4fa99 384#endif
5e1c5ff4 385 default:
92105bb7 386 goto bad;
5e1c5ff4 387 }
92105bb7
TL		 388 __raw_writel(l, reg);
389 return 0;
390bad:
391 return -EINVAL;
5e1c5ff4
TL		 392}
393
e9191028 394static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 395{
396 struct gpio_bank *bank;
92105bb7
TL		 397 unsigned gpio;
398 int retval;
a6472533 399 unsigned long flags;
92105bb7 400
e9191028
LB		 401 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
402 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 403 else
e9191028 404 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4 405
e5c56ed3 406 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 407 return -EINVAL;
e5c56ed3
DB		 408
409 /* OMAP1 allows only only edge triggering */
5492fb1a 410 if (!cpu_class_is_omap2()
e5c56ed3 411 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 412 return -EINVAL;
413
e9191028 414 bank = irq_data_get_irq_chip_data(d);
a6472533 415 spin_lock_irqsave(&bank->lock, flags);
129fd223 416 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 417 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 418
419 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 420 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 421 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 422 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 423
92105bb7 424 return retval;
5e1c5ff4
TL		 425}
426
427static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
428{
92105bb7 429 void __iomem *reg = bank->base;
5e1c5ff4 430
eef4bec7 431 reg += bank->regs->irqstatus;
5e1c5ff4 432 __raw_writel(gpio_mask, reg);
bee7930f
HD		 433
434 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 435 if (bank->regs->irqstatus2) {
436 reg = bank->base + bank->regs->irqstatus2;
bedfd154 437 __raw_writel(gpio_mask, reg);
eef4bec7 438 }
bedfd154
RQ		 439
440 /* Flush posted write for the irq status to avoid spurious interrupts */
441 __raw_readl(reg);
5e1c5ff4
TL		 442}
443
444static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
445{
129fd223 446 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 447}
448
ea6dedd7
ID		 449static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
450{
451 void __iomem *reg = bank->base;
99c47707 452 u32 l;
c390aad0 453 u32 mask = (1 << bank->width) - 1;
ea6dedd7 454
28f3b5a0 455 reg += bank->regs->irqenable;
99c47707 456 l = __raw_readl(reg);
28f3b5a0 457 if (bank->regs->irqenable_inv)
99c47707
ID		 458 l = ~l;
459 l &= mask;
460 return l;
ea6dedd7
ID		 461}
462
28f3b5a0 463static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
5e1c5ff4 464{
92105bb7 465 void __iomem *reg = bank->base;
5e1c5ff4
TL		 466 u32 l;
467
28f3b5a0
KH		 468 if (bank->regs->set_irqenable) {
469 reg += bank->regs->set_irqenable;
470 l = gpio_mask;
471 } else {
472 reg += bank->regs->irqenable;
5e1c5ff4 473 l = __raw_readl(reg);
28f3b5a0
KH		 474 if (bank->regs->irqenable_inv)
475 l &= ~gpio_mask;
5e1c5ff4
TL		 476 else
477 l |= gpio_mask;
28f3b5a0
KH		 478 }
479
480 __raw_writel(l, reg);
481}
482
483static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
484{
485 void __iomem *reg = bank->base;
486 u32 l;
487
488 if (bank->regs->clr_irqenable) {
489 reg += bank->regs->clr_irqenable;
5e1c5ff4 490 l = gpio_mask;
28f3b5a0
KH		 491 } else {
492 reg += bank->regs->irqenable;
56739a69 493 l = __raw_readl(reg);
28f3b5a0 494 if (bank->regs->irqenable_inv)
56739a69 495 l |= gpio_mask;
92105bb7 496 else
28f3b5a0 497 l &= ~gpio_mask;
5e1c5ff4 498 }
28f3b5a0 499
5e1c5ff4
TL		 500 __raw_writel(l, reg);
501}
502
503static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
504{
28f3b5a0 505 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 506}
507
92105bb7
TL		 508/*
509 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
510 * 1510 does not seem to have a wake-up register. If JTAG is connected
511 * to the target, system will wake up always on GPIO events. While
512 * system is running all registered GPIO interrupts need to have wake-up
513 * enabled. When system is suspended, only selected GPIO interrupts need
514 * to have wake-up enabled.
515 */
516static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
517{
f64ad1a0
KH		 518 u32 gpio_bit = GPIO_BIT(bank, gpio);
519 unsigned long flags;
a6472533 520
f64ad1a0
KH		 521 if (bank->non_wakeup_gpios & gpio_bit) {
522 dev_err(bank->dev,
523 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
92105bb7
TL		 524 return -EINVAL;
525 }
f64ad1a0
KH		 526
527 spin_lock_irqsave(&bank->lock, flags);
528 if (enable)
529 bank->suspend_wakeup |= gpio_bit;
530 else
531 bank->suspend_wakeup &= ~gpio_bit;
532
533 spin_unlock_irqrestore(&bank->lock, flags);
534
535 return 0;
92105bb7
TL		 536}
537
4196dd6b
TL		 538static void _reset_gpio(struct gpio_bank *bank, int gpio)
539{
129fd223 540 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 541 _set_gpio_irqenable(bank, gpio, 0);
542 _clear_gpio_irqstatus(bank, gpio);
129fd223 543 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 544}
545
92105bb7 546/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 547static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 548{
e9191028 549 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 550 struct gpio_bank *bank;
551 int retval;
552
e9191028 553 bank = irq_data_get_irq_chip_data(d);
f64ad1a0 554 retval = _set_gpio_wakeup(bank, gpio, enable);
92105bb7
TL		 555
556 return retval;
557}
558
3ff164e1 559static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 560{
3ff164e1 561 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 562 unsigned long flags;
52e31344 563
a6472533 564 spin_lock_irqsave(&bank->lock, flags);
92105bb7 565
4196dd6b
TL		 566 /* Set trigger to none. You need to enable the desired trigger with
567 * request_irq() or set_irq_type().
568 */
3ff164e1 569 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 570
1a8bfa1e 571#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 572 if (bank->method == METHOD_GPIO_1510) {
92105bb7 573 void __iomem *reg;
5e1c5ff4 574
92105bb7 575 /* Claim the pin for MPU */
5e1c5ff4 576 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 577 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 578 }
579#endif
058af1ea
C		 580 if (!cpu_class_is_omap1()) {
581 if (!bank->mod_usage) {
9f096868 582 void __iomem *reg = bank->base;
058af1ea 583 u32 ctrl;
9f096868
C		 584
585 if (cpu_is_omap24xx() || cpu_is_omap34xx())
586 reg += OMAP24XX_GPIO_CTRL;
587 else if (cpu_is_omap44xx())
588 reg += OMAP4_GPIO_CTRL;
589 ctrl = __raw_readl(reg);
058af1ea 590 /* Module is enabled, clocks are not gated */
9f096868
C		 591 ctrl &= 0xFFFFFFFE;
592 __raw_writel(ctrl, reg);
058af1ea
C		 593 }
594 bank->mod_usage |= 1 << offset;
595 }
a6472533 596 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 597
598 return 0;
599}
600
3ff164e1 601static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 602{
3ff164e1 603 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 604 unsigned long flags;
5e1c5ff4 605
a6472533 606 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 607#ifdef CONFIG_ARCH_OMAP16XX
608 if (bank->method == METHOD_GPIO_1610) {
609 /* Disable wake-up during idle for dynamic tick */
610 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 611 __raw_writel(1 << offset, reg);
92105bb7
TL		 612 }
613#endif
9f096868
C		 614#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
615 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 616 /* Disable wake-up during idle for dynamic tick */
617 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 618 __raw_writel(1 << offset, reg);
92105bb7 619 }
9f096868
C		 620#endif
621#ifdef CONFIG_ARCH_OMAP4
622 if (bank->method == METHOD_GPIO_44XX) {
623 /* Disable wake-up during idle for dynamic tick */
624 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
625 __raw_writel(1 << offset, reg);
626 }
92105bb7 627#endif
058af1ea
C		 628 if (!cpu_class_is_omap1()) {
629 bank->mod_usage &= ~(1 << offset);
630 if (!bank->mod_usage) {
9f096868 631 void __iomem *reg = bank->base;
058af1ea 632 u32 ctrl;
9f096868
C		 633
634 if (cpu_is_omap24xx() || cpu_is_omap34xx())
635 reg += OMAP24XX_GPIO_CTRL;
636 else if (cpu_is_omap44xx())
637 reg += OMAP4_GPIO_CTRL;
638 ctrl = __raw_readl(reg);
058af1ea
C		 639 /* Module is disabled, clocks are gated */
640 ctrl |= 1;
9f096868 641 __raw_writel(ctrl, reg);
058af1ea
C		 642 }
643 }
3ff164e1 644 _reset_gpio(bank, bank->chip.base + offset);
a6472533 645 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 646}
647
648/*
649 * We need to unmask the GPIO bank interrupt as soon as possible to
650 * avoid missing GPIO interrupts for other lines in the bank.
651 * Then we need to mask-read-clear-unmask the triggered GPIO lines
652 * in the bank to avoid missing nested interrupts for a GPIO line.
653 * If we wait to unmask individual GPIO lines in the bank after the
654 * line's interrupt handler has been run, we may miss some nested
655 * interrupts.
656 */
10dd5ce2 657static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 658{
92105bb7 659 void __iomem *isr_reg = NULL;
5e1c5ff4 660 u32 isr;
4318f36b 661 unsigned int gpio_irq, gpio_index;
5e1c5ff4 662 struct gpio_bank *bank;
ea6dedd7
ID		 663 u32 retrigger = 0;
664 int unmasked = 0;
ee144182 665 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 666
ee144182 667 chained_irq_enter(chip, desc);
5e1c5ff4 668
6845664a 669 bank = irq_get_handler_data(irq);
eef4bec7 670 isr_reg = bank->base + bank->regs->irqstatus;
b1cc4c55
EK		 671
672 if (WARN_ON(!isr_reg))
673 goto exit;
674
92105bb7 675 while(1) {
6e60e79a 676 u32 isr_saved, level_mask = 0;
ea6dedd7 677 u32 enabled;
6e60e79a 678
ea6dedd7
ID		 679 enabled = _get_gpio_irqbank_mask(bank);
680 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 681
682 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
683 isr &= 0x0000ffff;
684
5492fb1a 685 if (cpu_class_is_omap2()) {
b144ff6f 686 level_mask = bank->level_mask & enabled;
ea6dedd7 687 }
6e60e79a
TL		 688
689 /* clear edge sensitive interrupts before handler(s) are
690 called so that we don't miss any interrupt occurred while
691 executing them */
28f3b5a0 692 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a 693 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
28f3b5a0 694 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a
TL		 695
696 /* if there is only edge sensitive GPIO pin interrupts
697 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 698 if (!level_mask && !unmasked) {
699 unmasked = 1;
ee144182 700 chained_irq_exit(chip, desc);
ea6dedd7 701 }
92105bb7 702
ea6dedd7
ID		 703 isr |= retrigger;
704 retrigger = 0;
92105bb7
TL		 705 if (!isr)
706 break;
707
708 gpio_irq = bank->virtual_irq_start;
709 for (; isr != 0; isr >>= 1, gpio_irq++) {
129fd223 710 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
4318f36b 711
92105bb7
TL		 712 if (!(isr & 1))
713 continue;
29454dde 714
4318f36b
CM		 715#ifdef CONFIG_ARCH_OMAP1
716 /*
717 * Some chips can't respond to both rising and falling
718 * at the same time. If this irq was requested with
719 * both flags, we need to flip the ICR data for the IRQ
720 * to respond to the IRQ for the opposite direction.
721 * This will be indicated in the bank toggle_mask.
722 */
723 if (bank->toggle_mask & (1 << gpio_index))
724 _toggle_gpio_edge_triggering(bank, gpio_index);
725#endif
726
d8aa0251 727 generic_handle_irq(gpio_irq);
92105bb7 728 }
1a8bfa1e 729 }
ea6dedd7
ID		 730 /* if bank has any level sensitive GPIO pin interrupt
731 configured, we must unmask the bank interrupt only after
732 handler(s) are executed in order to avoid spurious bank
733 interrupt */
b1cc4c55 734exit:
ea6dedd7 735 if (!unmasked)
ee144182 736 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 737}
738
e9191028 739static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 740{
e9191028
LB		 741 unsigned int gpio = d->irq - IH_GPIO_BASE;
742 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 743 unsigned long flags;
4196dd6b 744
85ec7b97 745 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 746 _reset_gpio(bank, gpio);
85ec7b97 747 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 748}
749
e9191028 750static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 751{
e9191028
LB		 752 unsigned int gpio = d->irq - IH_GPIO_BASE;
753 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 754
755 _clear_gpio_irqstatus(bank, gpio);
756}
757
e9191028 758static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 759{
e9191028
LB		 760 unsigned int gpio = d->irq - IH_GPIO_BASE;
761 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 762 unsigned long flags;
5e1c5ff4 763
85ec7b97 764 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 765 _set_gpio_irqenable(bank, gpio, 0);
129fd223 766 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 767 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 768}
769
e9191028 770static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 771{
e9191028
LB		 772 unsigned int gpio = d->irq - IH_GPIO_BASE;
773 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
129fd223 774 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 775 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 776 unsigned long flags;
55b6019a 777
85ec7b97 778 spin_lock_irqsave(&bank->lock, flags);
55b6019a 779 if (trigger)
129fd223 780 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 781
782 /* For level-triggered GPIOs, the clearing must be done after
783 * the HW source is cleared, thus after the handler has run */
784 if (bank->level_mask & irq_mask) {
785 _set_gpio_irqenable(bank, gpio, 0);
786 _clear_gpio_irqstatus(bank, gpio);
787 }
5e1c5ff4 788
4de8c75b 789 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 790 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 791}
792
e5c56ed3
DB		 793static struct irq_chip gpio_irq_chip = {
794 .name = "GPIO",
e9191028
LB		 795 .irq_shutdown = gpio_irq_shutdown,
796 .irq_ack = gpio_ack_irq,
797 .irq_mask = gpio_mask_irq,
798 .irq_unmask = gpio_unmask_irq,
799 .irq_set_type = gpio_irq_type,
800 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 801};
802
803/*---------------------------------------------------------------------*/
804
805#ifdef CONFIG_ARCH_OMAP1
806
e5c56ed3
DB		 807#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
808
11a78b79
DB		 809#ifdef CONFIG_ARCH_OMAP16XX
810
811#include <linux/platform_device.h>
812
79ee031f 813static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 814{
79ee031f 815 struct platform_device *pdev = to_platform_device(dev);
11a78b79 816 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 817 void __iomem *mask_reg = bank->base +
818 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 819 unsigned long flags;
11a78b79 820
a6472533 821 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 822 bank->saved_wakeup = __raw_readl(mask_reg);
823 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 824 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 825
826 return 0;
827}
828
79ee031f 829static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 830{
79ee031f 831 struct platform_device *pdev = to_platform_device(dev);
11a78b79 832 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 833 void __iomem *mask_reg = bank->base +
834 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 835 unsigned long flags;
11a78b79 836
a6472533 837 spin_lock_irqsave(&bank->lock, flags);
11a78b79 838 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 839 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 840
841 return 0;
842}
843
47145210 844static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 845 .suspend_noirq = omap_mpuio_suspend_noirq,
846 .resume_noirq = omap_mpuio_resume_noirq,
847};
848
3c437ffd 849/* use platform_driver for this. */
11a78b79 850static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 851 .driver = {
852 .name = "mpuio",
79ee031f 853 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 854 },
855};
856
857static struct platform_device omap_mpuio_device = {
858 .name = "mpuio",
859 .id = -1,
860 .dev = {
861 .driver = &omap_mpuio_driver.driver,
862 }
863 /* could list the /proc/iomem resources */
864};
865
03e128ca 866static inline void mpuio_init(struct gpio_bank *bank)
11a78b79 867{
77640aab 868 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 869
11a78b79
DB		 870 if (platform_driver_register(&omap_mpuio_driver) == 0)
871 (void) platform_device_register(&omap_mpuio_device);
872}
873
874#else
03e128ca 875static inline void mpuio_init(struct gpio_bank *bank) {}
11a78b79
DB		 876#endif /* 16xx */
877
e5c56ed3
DB		 878#else
879
e5c56ed3 880#define bank_is_mpuio(bank) 0
03e128ca 881static inline void mpuio_init(struct gpio_bank *bank) {}
e5c56ed3
DB		 882
883#endif
884
885/*---------------------------------------------------------------------*/
5e1c5ff4 886
52e31344
DB		 887/* REVISIT these are stupid implementations! replace by ones that
888 * don't switch on METHOD_* and which mostly avoid spinlocks
889 */
890
891static int gpio_input(struct gpio_chip *chip, unsigned offset)
892{
893 struct gpio_bank *bank;
894 unsigned long flags;
895
896 bank = container_of(chip, struct gpio_bank, chip);
897 spin_lock_irqsave(&bank->lock, flags);
898 _set_gpio_direction(bank, offset, 1);
899 spin_unlock_irqrestore(&bank->lock, flags);
900 return 0;
901}
902
b37c45b8
RQ		 903static int gpio_is_input(struct gpio_bank *bank, int mask)
904{
fa87931a 905 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 906
b37c45b8
RQ		 907 return __raw_readl(reg) & mask;
908}
909
52e31344
DB		 910static int gpio_get(struct gpio_chip *chip, unsigned offset)
911{
b37c45b8
RQ		 912 struct gpio_bank *bank;
913 void __iomem *reg;
914 int gpio;
915 u32 mask;
916
917 gpio = chip->base + offset;
a8be8daf 918 bank = container_of(chip, struct gpio_bank, chip);
b37c45b8 919 reg = bank->base;
129fd223 920 mask = GPIO_BIT(bank, gpio);
b37c45b8
RQ		 921
922 if (gpio_is_input(bank, mask))
923 return _get_gpio_datain(bank, gpio);
924 else
925 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 926}
927
928static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
929{
930 struct gpio_bank *bank;
931 unsigned long flags;
932
933 bank = container_of(chip, struct gpio_bank, chip);
934 spin_lock_irqsave(&bank->lock, flags);
fa87931a 935 bank->set_dataout(bank, offset, value);
52e31344
DB		 936 _set_gpio_direction(bank, offset, 0);
937 spin_unlock_irqrestore(&bank->lock, flags);
938 return 0;
939}
940
168ef3d9
FB		 941static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
942 unsigned debounce)
943{
944 struct gpio_bank *bank;
945 unsigned long flags;
946
947 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 948
949 if (!bank->dbck) {
950 bank->dbck = clk_get(bank->dev, "dbclk");
951 if (IS_ERR(bank->dbck))
952 dev_err(bank->dev, "Could not get gpio dbck\n");
953 }
954
168ef3d9
FB		 955 spin_lock_irqsave(&bank->lock, flags);
956 _set_gpio_debounce(bank, offset, debounce);
957 spin_unlock_irqrestore(&bank->lock, flags);
958
959 return 0;
960}
961
52e31344
DB		 962static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
963{
964 struct gpio_bank *bank;
965 unsigned long flags;
966
967 bank = container_of(chip, struct gpio_bank, chip);
968 spin_lock_irqsave(&bank->lock, flags);
fa87931a 969 bank->set_dataout(bank, offset, value);
52e31344
DB		 970 spin_unlock_irqrestore(&bank->lock, flags);
971}
972
a007b709
DB		 973static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
974{
975 struct gpio_bank *bank;
976
977 bank = container_of(chip, struct gpio_bank, chip);
978 return bank->virtual_irq_start + offset;
979}
980
52e31344
DB		 981/*---------------------------------------------------------------------*/
982
9a748053 983static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da 984{
e5ff4440 985 static bool called;
9f7065da
TL		 986 u32 rev;
987
e5ff4440 988 if (called || bank->regs->revision == USHRT_MAX)
9f7065da
TL		 989 return;
990
e5ff4440
KH		 991 rev = __raw_readw(bank->base + bank->regs->revision);
992 pr_info("OMAP GPIO hardware version %d.%d\n",
9f7065da 993 (rev >> 4) & 0x0f, rev & 0x0f);
e5ff4440
KH		 994
995 called = true;
9f7065da
TL		 996}
997
8ba55c5c
DB		 998/* This lock class tells lockdep that GPIO irqs are in a different
999 * category than their parents, so it won't report false recursion.
1000 */
1001static struct lock_class_key gpio_lock_class;
1002
77640aab 1003/* TODO: Cleanup cpu_is_* checks */
03e128ca 1004static void omap_gpio_mod_init(struct gpio_bank *bank)
2fae7fbe
VC		 1005{
1006 if (cpu_class_is_omap2()) {
1007 if (cpu_is_omap44xx()) {
1008 __raw_writel(0xffffffff, bank->base +
1009 OMAP4_GPIO_IRQSTATUSCLR0);
1010 __raw_writel(0x00000000, bank->base +
1011 OMAP4_GPIO_DEBOUNCENABLE);
1012 /* Initialize interface clk ungated, module enabled */
1013 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1014 } else if (cpu_is_omap34xx()) {
1015 __raw_writel(0x00000000, bank->base +
1016 OMAP24XX_GPIO_IRQENABLE1);
1017 __raw_writel(0xffffffff, bank->base +
1018 OMAP24XX_GPIO_IRQSTATUS1);
1019 __raw_writel(0x00000000, bank->base +
1020 OMAP24XX_GPIO_DEBOUNCE_EN);
1021
1022 /* Initialize interface clk ungated, module enabled */
1023 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1024 } else if (cpu_is_omap24xx()) {
1025 static const u32 non_wakeup_gpios[] = {
1026 0xe203ffc0, 0x08700040
1027 };
03e128ca
C		 1028 if (bank->id < ARRAY_SIZE(non_wakeup_gpios))
1029 bank->non_wakeup_gpios =
1030 non_wakeup_gpios[bank->id];
2fae7fbe
VC		 1031 }
1032 } else if (cpu_class_is_omap1()) {
03e128ca 1033 if (bank_is_mpuio(bank)) {
5de62b86
TL		 1034 __raw_writew(0xffff, bank->base +
1035 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
03e128ca
C		 1036 mpuio_init(bank);
1037 }
2fae7fbe
VC		 1038 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1039 __raw_writew(0xffff, bank->base
1040 + OMAP1510_GPIO_INT_MASK);
1041 __raw_writew(0x0000, bank->base
1042 + OMAP1510_GPIO_INT_STATUS);
1043 }
1044 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1045 __raw_writew(0x0000, bank->base
1046 + OMAP1610_GPIO_IRQENABLE1);
1047 __raw_writew(0xffff, bank->base
1048 + OMAP1610_GPIO_IRQSTATUS1);
1049 __raw_writew(0x0014, bank->base
1050 + OMAP1610_GPIO_SYSCONFIG);
1051
1052 /*
1053 * Enable system clock for GPIO module.
1054 * The CAM_CLK_CTRL *is* really the right place.
1055 */
1056 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1057 ULPD_CAM_CLK_CTRL);
1058 }
1059 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1060 __raw_writel(0xffffffff, bank->base
1061 + OMAP7XX_GPIO_INT_MASK);
1062 __raw_writel(0x00000000, bank->base
1063 + OMAP7XX_GPIO_INT_STATUS);
1064 }
1065 }
1066}
1067
f8b46b58
KH		 1068static __init void
1069omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1070 unsigned int num)
1071{
1072 struct irq_chip_generic *gc;
1073 struct irq_chip_type *ct;
1074
1075 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1076 handle_simple_irq);
83233749
TP		 1077 if (!gc) {
1078 dev_err(bank->dev, "Memory alloc failed for gc\n");
1079 return;
1080 }
1081
f8b46b58
KH		 1082 ct = gc->chip_types;
1083
1084 /* NOTE: No ack required, reading IRQ status clears it. */
1085 ct->chip.irq_mask = irq_gc_mask_set_bit;
1086 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1087 ct->chip.irq_set_type = gpio_irq_type;
1088 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1089 if (cpu_is_omap16xx())
1090 ct->chip.irq_set_wake = gpio_wake_enable,
1091
1092 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1093 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1094 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1095}
1096
d52b31de 1097static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1098{
77640aab 1099 int j;
2fae7fbe
VC		 1100 static int gpio;
1101
2fae7fbe
VC		 1102 bank->mod_usage = 0;
1103 /*
1104 * REVISIT eventually switch from OMAP-specific gpio structs
1105 * over to the generic ones
1106 */
1107 bank->chip.request = omap_gpio_request;
1108 bank->chip.free = omap_gpio_free;
1109 bank->chip.direction_input = gpio_input;
1110 bank->chip.get = gpio_get;
1111 bank->chip.direction_output = gpio_output;
1112 bank->chip.set_debounce = gpio_debounce;
1113 bank->chip.set = gpio_set;
1114 bank->chip.to_irq = gpio_2irq;
1115 if (bank_is_mpuio(bank)) {
1116 bank->chip.label = "mpuio";
1117#ifdef CONFIG_ARCH_OMAP16XX
1118 bank->chip.dev = &omap_mpuio_device.dev;
1119#endif
1120 bank->chip.base = OMAP_MPUIO(0);
1121 } else {
1122 bank->chip.label = "gpio";
1123 bank->chip.base = gpio;
d5f46247 1124 gpio += bank->width;
2fae7fbe 1125 }
d5f46247 1126 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1127
1128 gpiochip_add(&bank->chip);
1129
1130 for (j = bank->virtual_irq_start;
d5f46247 1131 j < bank->virtual_irq_start + bank->width; j++) {
1475b85d 1132 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1133 irq_set_chip_data(j, bank);
f8b46b58
KH		 1134 if (bank_is_mpuio(bank)) {
1135 omap_mpuio_alloc_gc(bank, j, bank->width);
1136 } else {
6845664a 1137 irq_set_chip(j, &gpio_irq_chip);
f8b46b58
KH		 1138 irq_set_handler(j, handle_simple_irq);
1139 set_irq_flags(j, IRQF_VALID);
1140 }
2fae7fbe 1141 }
6845664a
TG		 1142 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1143 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1144}
1145
77640aab 1146static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1147{
77640aab
VC		 1148 struct omap_gpio_platform_data *pdata;
1149 struct resource *res;
5e1c5ff4 1150 struct gpio_bank *bank;
03e128ca 1151 int ret = 0;
5e1c5ff4 1152
03e128ca
C		 1153 if (!pdev->dev.platform_data) {
1154 ret = -EINVAL;
1155 goto err_exit;
5492fb1a 1156 }
5492fb1a 1157
03e128ca
C		 1158 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
1159 if (!bank) {
1160 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1161 ret = -ENOMEM;
1162 goto err_exit;
1163 }
92105bb7 1164
77640aab
VC		 1165 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1166 if (unlikely(!res)) {
03e128ca
C		 1167 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
1168 pdev->id);
1169 ret = -ENODEV;
1170 goto err_free;
44169075 1171 }
5e1c5ff4 1172
77640aab 1173 bank->irq = res->start;
03e128ca
C		 1174 bank->id = pdev->id;
1175
1176 pdata = pdev->dev.platform_data;
77640aab
VC		 1177 bank->virtual_irq_start = pdata->virtual_irq_start;
1178 bank->method = pdata->bank_type;
1179 bank->dev = &pdev->dev;
1180 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1181 bank->stride = pdata->bank_stride;
d5f46247 1182 bank->width = pdata->bank_width;
0cde8d03 1183 bank->loses_context = pdata->loses_context;
60a3437d 1184 bank->get_context_loss_count = pdata->get_context_loss_count;
fa87931a
KH		 1185 bank->regs = pdata->regs;
1186
1187 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1188 bank->set_dataout = _set_gpio_dataout_reg;
1189 else
1190 bank->set_dataout = _set_gpio_dataout_mask;
9f7065da 1191
77640aab 1192 spin_lock_init(&bank->lock);
9f7065da 1193
77640aab
VC		 1194 /* Static mapping, never released */
1195 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1196 if (unlikely(!res)) {
03e128ca
C		 1197 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1198 pdev->id);
1199 ret = -ENODEV;
1200 goto err_free;
77640aab 1201 }
89db9482 1202
77640aab
VC		 1203 bank->base = ioremap(res->start, resource_size(res));
1204 if (!bank->base) {
03e128ca
C		 1205 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1206 pdev->id);
1207 ret = -ENOMEM;
1208 goto err_free;
5e1c5ff4
TL		 1209 }
1210
77640aab
VC		 1211 pm_runtime_enable(bank->dev);
1212 pm_runtime_get_sync(bank->dev);
1213
03e128ca 1214 omap_gpio_mod_init(bank);
77640aab 1215 omap_gpio_chip_init(bank);
9a748053 1216 omap_gpio_show_rev(bank);
9f7065da 1217
03e128ca 1218 list_add_tail(&bank->node, &omap_gpio_list);
77640aab 1219
03e128ca
C		 1220 return ret;
1221
1222err_free:
1223 kfree(bank);
1224err_exit:
1225 return ret;
5e1c5ff4
TL		 1226}
1227
140455fa 1228#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1229static int omap_gpio_suspend(void)
92105bb7 1230{
03e128ca 1231 struct gpio_bank *bank;
92105bb7 1232
5492fb1a 1233 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1234 return 0;
1235
03e128ca 1236 list_for_each_entry(bank, &omap_gpio_list, node) {
92105bb7
TL		 1237 void __iomem *wake_status;
1238 void __iomem *wake_clear;
1239 void __iomem *wake_set;
a6472533 1240 unsigned long flags;
92105bb7
TL		 1241
1242 switch (bank->method) {
e5c56ed3 1243#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1244 case METHOD_GPIO_1610:
1245 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1246 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1247 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1248 break;
e5c56ed3 1249#endif
a8eb7ca0 1250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1251 case METHOD_GPIO_24XX:
723fdb78 1252 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1253 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1254 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1255 break;
78a1a6d3
SR		 1256#endif
1257#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1258 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1259 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1260 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1261 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1262 break;
e5c56ed3 1263#endif
92105bb7
TL		 1264 default:
1265 continue;
1266 }
1267
a6472533 1268 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1269 bank->saved_wakeup = __raw_readl(wake_status);
1270 __raw_writel(0xffffffff, wake_clear);
1271 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1272 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1273 }
1274
1275 return 0;
1276}
1277
3c437ffd 1278static void omap_gpio_resume(void)
92105bb7 1279{
03e128ca 1280 struct gpio_bank *bank;
92105bb7 1281
723fdb78 1282 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1283 return;
92105bb7 1284
03e128ca 1285 list_for_each_entry(bank, &omap_gpio_list, node) {
92105bb7
TL		 1286 void __iomem *wake_clear;
1287 void __iomem *wake_set;
a6472533 1288 unsigned long flags;
92105bb7
TL		 1289
1290 switch (bank->method) {
e5c56ed3 1291#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1292 case METHOD_GPIO_1610:
1293 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1294 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1295 break;
e5c56ed3 1296#endif
a8eb7ca0 1297#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1298 case METHOD_GPIO_24XX:
0d9356cb
TL		 1299 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1300 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1301 break;
78a1a6d3
SR		 1302#endif
1303#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1304 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1305 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1306 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1307 break;
e5c56ed3 1308#endif
92105bb7
TL		 1309 default:
1310 continue;
1311 }
1312
a6472533 1313 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1314 __raw_writel(0xffffffff, wake_clear);
1315 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1316 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1317 }
92105bb7
TL		 1318}
1319
3c437ffd 1320static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1321 .suspend = omap_gpio_suspend,
1322 .resume = omap_gpio_resume,
1323};
1324
3ac4fa99
JY		 1325#endif
1326
140455fa 1327#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 1328
60a3437d
TKD		 1329static void omap_gpio_save_context(struct gpio_bank *bank);
1330static void omap_gpio_restore_context(struct gpio_bank *bank);
3ac4fa99 1331
72e06d08 1332void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99 1333{
03e128ca 1334 struct gpio_bank *bank;
43ffcd9a 1335
03e128ca 1336 list_for_each_entry(bank, &omap_gpio_list, node) {
ca828760 1337 u32 l1 = 0, l2 = 0;
0aed0435 1338 int j;
3ac4fa99 1339
0cde8d03 1340 if (!bank->loses_context)
03e128ca
C		 1341 continue;
1342
0aed0435 1343 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1344 clk_disable(bank->dbck);
1345
72e06d08 1346 if (!off_mode)
43ffcd9a
KH		 1347 continue;
1348
1349 /* If going to OFF, remove triggering for all
1350 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1351 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99 1352 if (!(bank->enabled_non_wakeup_gpios))
60a3437d 1353 goto save_gpio_context;
3f1686a9
TL		 1354
1355 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1356 bank->saved_datain = __raw_readl(bank->base +
1357 OMAP24XX_GPIO_DATAIN);
1358 l1 = __raw_readl(bank->base +
1359 OMAP24XX_GPIO_FALLINGDETECT);
1360 l2 = __raw_readl(bank->base +
1361 OMAP24XX_GPIO_RISINGDETECT);
1362 }
1363
1364 if (cpu_is_omap44xx()) {
1365 bank->saved_datain = __raw_readl(bank->base +
1366 OMAP4_GPIO_DATAIN);
1367 l1 = __raw_readl(bank->base +
1368 OMAP4_GPIO_FALLINGDETECT);
1369 l2 = __raw_readl(bank->base +
1370 OMAP4_GPIO_RISINGDETECT);
1371 }
1372
3ac4fa99
JY		 1373 bank->saved_fallingdetect = l1;
1374 bank->saved_risingdetect = l2;
1375 l1 &= ~bank->enabled_non_wakeup_gpios;
1376 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1377
1378 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1379 __raw_writel(l1, bank->base +
1380 OMAP24XX_GPIO_FALLINGDETECT);
1381 __raw_writel(l2, bank->base +
1382 OMAP24XX_GPIO_RISINGDETECT);
1383 }
1384
1385 if (cpu_is_omap44xx()) {
1386 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1387 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1388 }
1389
60a3437d
TKD		 1390save_gpio_context:
1391 if (bank->get_context_loss_count)
1392 bank->context_loss_count =
1393 bank->get_context_loss_count(bank->dev);
1394
1395 omap_gpio_save_context(bank);
3ac4fa99 1396 }
3ac4fa99
JY		 1397}
1398
43ffcd9a 1399void omap2_gpio_resume_after_idle(void)
3ac4fa99 1400{
03e128ca 1401 struct gpio_bank *bank;
3ac4fa99 1402
03e128ca 1403 list_for_each_entry(bank, &omap_gpio_list, node) {
60a3437d 1404 int context_lost_cnt_after;
ca828760 1405 u32 l = 0, gen, gen0, gen1;
0aed0435 1406 int j;
3ac4fa99 1407
0cde8d03 1408 if (!bank->loses_context)
03e128ca
C		 1409 continue;
1410
0aed0435 1411 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1412 clk_enable(bank->dbck);
1413
60a3437d
TKD		 1414 if (bank->get_context_loss_count) {
1415 context_lost_cnt_after =
1416 bank->get_context_loss_count(bank->dev);
1417 if (context_lost_cnt_after != bank->context_loss_count
1418 || !context_lost_cnt_after)
1419 omap_gpio_restore_context(bank);
1420 }
43ffcd9a 1421
3ac4fa99
JY		 1422 if (!(bank->enabled_non_wakeup_gpios))
1423 continue;
3f1686a9
TL		 1424
1425 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1426 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1427 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1428 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1429 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1430 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1431 }
1432
1433 if (cpu_is_omap44xx()) {
1434 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1435 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1436 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1437 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1438 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1439 }
1440
3ac4fa99
JY		 1441 /* Check if any of the non-wakeup interrupt GPIOs have changed
1442 * state. If so, generate an IRQ by software. This is
1443 * horribly racy, but it's the best we can do to work around
1444 * this silicon bug. */
3ac4fa99 1445 l ^= bank->saved_datain;
a118b5f3 1446 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1447
1448 /*
1449 * No need to generate IRQs for the rising edge for gpio IRQs
1450 * configured with falling edge only; and vice versa.
1451 */
1452 gen0 = l & bank->saved_fallingdetect;
1453 gen0 &= bank->saved_datain;
1454
1455 gen1 = l & bank->saved_risingdetect;
1456 gen1 &= ~(bank->saved_datain);
1457
1458 /* FIXME: Consider GPIO IRQs with level detections properly! */
1459 gen = l & (~(bank->saved_fallingdetect) &
1460 ~(bank->saved_risingdetect));
1461 /* Consider all GPIO IRQs needed to be updated */
1462 gen |= gen0 | gen1;
1463
1464 if (gen) {
3ac4fa99 1465 u32 old0, old1;
3f1686a9 1466
f00d6497 1467 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1468 old0 = __raw_readl(bank->base +
1469 OMAP24XX_GPIO_LEVELDETECT0);
1470 old1 = __raw_readl(bank->base +
1471 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1472 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1473 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1474 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1475 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1476 __raw_writel(old0, bank->base +
3f1686a9 1477 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1478 __raw_writel(old1, bank->base +
3f1686a9
TL		 1479 OMAP24XX_GPIO_LEVELDETECT1);
1480 }
1481
1482 if (cpu_is_omap44xx()) {
1483 old0 = __raw_readl(bank->base +
78a1a6d3 1484 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1485 old1 = __raw_readl(bank->base +
78a1a6d3 1486 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1487 __raw_writel(old0 | l, bank->base +
78a1a6d3 1488 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1489 __raw_writel(old1 | l, bank->base +
78a1a6d3 1490 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1491 __raw_writel(old0, bank->base +
78a1a6d3 1492 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1493 __raw_writel(old1, bank->base +
78a1a6d3 1494 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1495 }
3ac4fa99
JY		 1496 }
1497 }
3ac4fa99
JY		 1498}
1499
60a3437d 1500static void omap_gpio_save_context(struct gpio_bank *bank)
40c670f0 1501{
60a3437d
TKD		 1502 bank->context.irqenable1 =
1503 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1504 bank->context.irqenable2 =
1505 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1506 bank->context.wake_en =
1507 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1508 bank->context.ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1509 bank->context.oe = __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1510 bank->context.leveldetect0 =
1511 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1512 bank->context.leveldetect1 =
1513 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1514 bank->context.risingdetect =
1515 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1516 bank->context.fallingdetect =
1517 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1518 bank->context.dataout =
1519 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1520}
1521
60a3437d 1522static void omap_gpio_restore_context(struct gpio_bank *bank)
40c670f0 1523{
60a3437d
TKD		 1524 __raw_writel(bank->context.irqenable1,
1525 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1526 __raw_writel(bank->context.irqenable2,
1527 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1528 __raw_writel(bank->context.wake_en,
1529 bank->base + OMAP24XX_GPIO_WAKE_EN);
1530 __raw_writel(bank->context.ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1531 __raw_writel(bank->context.oe, bank->base + OMAP24XX_GPIO_OE);
1532 __raw_writel(bank->context.leveldetect0,
1533 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1534 __raw_writel(bank->context.leveldetect1,
1535 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1536 __raw_writel(bank->context.risingdetect,
1537 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1538 __raw_writel(bank->context.fallingdetect,
1539 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1540 __raw_writel(bank->context.dataout,
1541 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1542}
1543#endif
1544
77640aab
VC		 1545static struct platform_driver omap_gpio_driver = {
1546 .probe = omap_gpio_probe,
1547 .driver = {
1548 .name = "omap_gpio",
1549 },
1550};
1551
5e1c5ff4 1552/*
77640aab
VC		 1553 * gpio driver register needs to be done before
1554 * machine_init functions access gpio APIs.
1555 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1556 */
77640aab 1557static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1558{
77640aab 1559 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1560}
77640aab 1561postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1562
92105bb7
TL		 1563static int __init omap_gpio_sysinit(void)
1564{
11a78b79 1565
140455fa 1566#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1567 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1568 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 1569#endif
1570
3c437ffd 1571 return 0;
92105bb7
TL		 1572}
1573
92105bb7 1574arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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