Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb | 27 | #include <mach/irqs.h> |
1bc857f7 | 28 | #include <asm/gpio.h> |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
03e128ca C |
31 | static LIST_HEAD(omap_gpio_list); |
32 | ||
6d62e216 C |
33 | struct gpio_regs { |
34 | u32 irqenable1; | |
35 | u32 irqenable2; | |
36 | u32 wake_en; | |
37 | u32 ctrl; | |
38 | u32 oe; | |
39 | u32 leveldetect0; | |
40 | u32 leveldetect1; | |
41 | u32 risingdetect; | |
42 | u32 fallingdetect; | |
43 | u32 dataout; | |
44 | }; | |
45 | ||
5e1c5ff4 | 46 | struct gpio_bank { |
03e128ca | 47 | struct list_head node; |
9f7065da | 48 | unsigned long pbase; |
92105bb7 | 49 | void __iomem *base; |
5e1c5ff4 TL |
50 | u16 irq; |
51 | u16 virtual_irq_start; | |
92105bb7 | 52 | int method; |
92105bb7 | 53 | u32 suspend_wakeup; |
78a43158 | 54 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 | 55 | u32 saved_wakeup; |
3ac4fa99 | 56 | #endif |
3ac4fa99 JY |
57 | u32 non_wakeup_gpios; |
58 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 59 | struct gpio_regs context; |
3ac4fa99 JY |
60 | u32 saved_datain; |
61 | u32 saved_fallingdetect; | |
62 | u32 saved_risingdetect; | |
b144ff6f | 63 | u32 level_mask; |
4318f36b | 64 | u32 toggle_mask; |
5e1c5ff4 | 65 | spinlock_t lock; |
52e31344 | 66 | struct gpio_chip chip; |
89db9482 | 67 | struct clk *dbck; |
058af1ea | 68 | u32 mod_usage; |
8865b9b6 | 69 | u32 dbck_enable_mask; |
77640aab VC |
70 | struct device *dev; |
71 | bool dbck_flag; | |
0cde8d03 | 72 | bool loses_context; |
5de62b86 | 73 | int stride; |
d5f46247 | 74 | u32 width; |
03e128ca | 75 | u16 id; |
fa87931a KH |
76 | |
77 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
78 | ||
79 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
80 | }; |
81 | ||
129fd223 KH |
82 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
83 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
5e1c5ff4 TL |
84 | |
85 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
86 | { | |
92105bb7 | 87 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
88 | u32 l; |
89 | ||
fa87931a | 90 | reg += bank->regs->direction; |
5e1c5ff4 TL |
91 | l = __raw_readl(reg); |
92 | if (is_input) | |
93 | l |= 1 << gpio; | |
94 | else | |
95 | l &= ~(1 << gpio); | |
96 | __raw_writel(l, reg); | |
97 | } | |
98 | ||
fa87931a KH |
99 | |
100 | /* set data out value using dedicate set/clear register */ | |
101 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 102 | { |
92105bb7 | 103 | void __iomem *reg = bank->base; |
fa87931a | 104 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 105 | |
fa87931a KH |
106 | if (enable) |
107 | reg += bank->regs->set_dataout; | |
108 | else | |
109 | reg += bank->regs->clr_dataout; | |
5e1c5ff4 | 110 | |
5e1c5ff4 TL |
111 | __raw_writel(l, reg); |
112 | } | |
113 | ||
fa87931a KH |
114 | /* set data out value using mask register */ |
115 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 116 | { |
fa87931a KH |
117 | void __iomem *reg = bank->base + bank->regs->dataout; |
118 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
119 | u32 l; | |
5e1c5ff4 | 120 | |
fa87931a KH |
121 | l = __raw_readl(reg); |
122 | if (enable) | |
123 | l |= gpio_bit; | |
124 | else | |
125 | l &= ~gpio_bit; | |
5e1c5ff4 | 126 | __raw_writel(l, reg); |
5e1c5ff4 TL |
127 | } |
128 | ||
b37c45b8 | 129 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
b37c45b8 | 130 | { |
fa87931a | 131 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 132 | |
fa87931a | 133 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
5e1c5ff4 | 134 | } |
b37c45b8 | 135 | |
b37c45b8 RQ |
136 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
137 | { | |
fa87931a | 138 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 139 | |
129fd223 | 140 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
141 | } |
142 | ||
ece9528e KH |
143 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
144 | { | |
145 | int l = __raw_readl(base + reg); | |
146 | ||
147 | if (set) | |
148 | l |= mask; | |
149 | else | |
150 | l &= ~mask; | |
151 | ||
152 | __raw_writel(l, base + reg); | |
153 | } | |
92105bb7 | 154 | |
168ef3d9 FB |
155 | /** |
156 | * _set_gpio_debounce - low level gpio debounce time | |
157 | * @bank: the gpio bank we're acting upon | |
158 | * @gpio: the gpio number on this @gpio | |
159 | * @debounce: debounce time to use | |
160 | * | |
161 | * OMAP's debounce time is in 31us steps so we need | |
162 | * to convert and round up to the closest unit. | |
163 | */ | |
164 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
165 | unsigned debounce) | |
166 | { | |
9942da0e | 167 | void __iomem *reg; |
168ef3d9 FB |
168 | u32 val; |
169 | u32 l; | |
170 | ||
77640aab VC |
171 | if (!bank->dbck_flag) |
172 | return; | |
173 | ||
168ef3d9 FB |
174 | if (debounce < 32) |
175 | debounce = 0x01; | |
176 | else if (debounce > 7936) | |
177 | debounce = 0xff; | |
178 | else | |
179 | debounce = (debounce / 0x1f) - 1; | |
180 | ||
129fd223 | 181 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 182 | |
9942da0e | 183 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
184 | __raw_writel(debounce, reg); |
185 | ||
9942da0e | 186 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
187 | val = __raw_readl(reg); |
188 | ||
189 | if (debounce) { | |
190 | val |= l; | |
77640aab | 191 | clk_enable(bank->dbck); |
168ef3d9 FB |
192 | } else { |
193 | val &= ~l; | |
77640aab | 194 | clk_disable(bank->dbck); |
168ef3d9 | 195 | } |
f7ec0b0b | 196 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
197 | |
198 | __raw_writel(val, reg); | |
199 | } | |
200 | ||
140455fa | 201 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
202 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
203 | int trigger) | |
5e1c5ff4 | 204 | { |
3ac4fa99 | 205 | void __iomem *base = bank->base; |
92105bb7 TL |
206 | u32 gpio_bit = 1 << gpio; |
207 | ||
78a1a6d3 | 208 | if (cpu_is_omap44xx()) { |
ece9528e KH |
209 | _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit, |
210 | trigger & IRQ_TYPE_LEVEL_LOW); | |
211 | _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
212 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
213 | _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
214 | trigger & IRQ_TYPE_EDGE_RISING); | |
215 | _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
216 | trigger & IRQ_TYPE_EDGE_FALLING); | |
78a1a6d3 | 217 | } else { |
ece9528e KH |
218 | _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, |
219 | trigger & IRQ_TYPE_LEVEL_LOW); | |
220 | _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
221 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
222 | _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
223 | trigger & IRQ_TYPE_EDGE_RISING); | |
224 | _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
225 | trigger & IRQ_TYPE_EDGE_FALLING); | |
78a1a6d3 | 226 | } |
3ac4fa99 | 227 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 | 228 | if (cpu_is_omap44xx()) { |
ece9528e KH |
229 | _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit, |
230 | trigger != 0); | |
78a1a6d3 | 231 | } else { |
699117a6 CW |
232 | /* |
233 | * GPIO wakeup request can only be generated on edge | |
234 | * transitions | |
235 | */ | |
236 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 237 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 238 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
239 | else |
240 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 241 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 242 | } |
a118b5f3 | 243 | } |
55b220ca A |
244 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
245 | if (cpu_is_omap34xx() || cpu_is_omap44xx() || | |
246 | (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
247 | /* |
248 | * Log the edge gpio and manually trigger the IRQ | |
249 | * after resume if the input level changes | |
250 | * to avoid irq lost during PER RET/OFF mode | |
251 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
252 | */ | |
253 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
254 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
255 | else | |
256 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
257 | } | |
5eb3bb9c | 258 | |
78a1a6d3 SR |
259 | if (cpu_is_omap44xx()) { |
260 | bank->level_mask = | |
261 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
262 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
263 | } else { | |
264 | bank->level_mask = | |
265 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
266 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
267 | } | |
92105bb7 | 268 | } |
3ac4fa99 | 269 | #endif |
92105bb7 | 270 | |
9198bcd3 | 271 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
272 | /* |
273 | * This only applies to chips that can't do both rising and falling edge | |
274 | * detection at once. For all other chips, this function is a noop. | |
275 | */ | |
276 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
277 | { | |
278 | void __iomem *reg = bank->base; | |
279 | u32 l = 0; | |
280 | ||
281 | switch (bank->method) { | |
4318f36b | 282 | case METHOD_MPUIO: |
5de62b86 | 283 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
4318f36b | 284 | break; |
4318f36b CM |
285 | #ifdef CONFIG_ARCH_OMAP15XX |
286 | case METHOD_GPIO_1510: | |
287 | reg += OMAP1510_GPIO_INT_CONTROL; | |
288 | break; | |
289 | #endif | |
290 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
291 | case METHOD_GPIO_7XX: | |
292 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
293 | break; | |
294 | #endif | |
295 | default: | |
296 | return; | |
297 | } | |
298 | ||
299 | l = __raw_readl(reg); | |
300 | if ((l >> gpio) & 1) | |
301 | l &= ~(1 << gpio); | |
302 | else | |
303 | l |= 1 << gpio; | |
304 | ||
305 | __raw_writel(l, reg); | |
306 | } | |
9198bcd3 | 307 | #endif |
4318f36b | 308 | |
92105bb7 TL |
309 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
310 | { | |
311 | void __iomem *reg = bank->base; | |
312 | u32 l = 0; | |
5e1c5ff4 TL |
313 | |
314 | switch (bank->method) { | |
e5c56ed3 | 315 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 316 | case METHOD_MPUIO: |
5de62b86 | 317 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
5e1c5ff4 | 318 | l = __raw_readl(reg); |
29501577 | 319 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 320 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 321 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 322 | l |= 1 << gpio; |
6cab4860 | 323 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 324 | l &= ~(1 << gpio); |
92105bb7 TL |
325 | else |
326 | goto bad; | |
5e1c5ff4 | 327 | break; |
e5c56ed3 DB |
328 | #endif |
329 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
330 | case METHOD_GPIO_1510: |
331 | reg += OMAP1510_GPIO_INT_CONTROL; | |
332 | l = __raw_readl(reg); | |
29501577 | 333 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 334 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 335 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 336 | l |= 1 << gpio; |
6cab4860 | 337 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 338 | l &= ~(1 << gpio); |
92105bb7 TL |
339 | else |
340 | goto bad; | |
5e1c5ff4 | 341 | break; |
e5c56ed3 | 342 | #endif |
3ac4fa99 | 343 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 344 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
345 | if (gpio & 0x08) |
346 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
347 | else | |
348 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
349 | gpio &= 0x07; | |
350 | l = __raw_readl(reg); | |
351 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 352 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 353 | l |= 2 << (gpio << 1); |
6cab4860 | 354 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 355 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
356 | if (trigger) |
357 | /* Enable wake-up during idle for dynamic tick */ | |
358 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
359 | else | |
360 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 361 | break; |
3ac4fa99 | 362 | #endif |
b718aa81 | 363 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
364 | case METHOD_GPIO_7XX: |
365 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 366 | l = __raw_readl(reg); |
29501577 | 367 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 368 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
369 | if (trigger & IRQ_TYPE_EDGE_RISING) |
370 | l |= 1 << gpio; | |
371 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
372 | l &= ~(1 << gpio); | |
373 | else | |
374 | goto bad; | |
375 | break; | |
376 | #endif | |
140455fa | 377 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 378 | case METHOD_GPIO_24XX: |
3f1686a9 | 379 | case METHOD_GPIO_44XX: |
3ac4fa99 | 380 | set_24xx_gpio_triggering(bank, gpio, trigger); |
f7c5cc45 | 381 | return 0; |
3ac4fa99 | 382 | #endif |
5e1c5ff4 | 383 | default: |
92105bb7 | 384 | goto bad; |
5e1c5ff4 | 385 | } |
92105bb7 TL |
386 | __raw_writel(l, reg); |
387 | return 0; | |
388 | bad: | |
389 | return -EINVAL; | |
5e1c5ff4 TL |
390 | } |
391 | ||
e9191028 | 392 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
393 | { |
394 | struct gpio_bank *bank; | |
92105bb7 TL |
395 | unsigned gpio; |
396 | int retval; | |
a6472533 | 397 | unsigned long flags; |
92105bb7 | 398 | |
e9191028 LB |
399 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
400 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 401 | else |
e9191028 | 402 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 | 403 | |
e5c56ed3 | 404 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 405 | return -EINVAL; |
e5c56ed3 DB |
406 | |
407 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 408 | if (!cpu_class_is_omap2() |
e5c56ed3 | 409 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
410 | return -EINVAL; |
411 | ||
e9191028 | 412 | bank = irq_data_get_irq_chip_data(d); |
a6472533 | 413 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 414 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 415 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
416 | |
417 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 418 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 419 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 420 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 421 | |
92105bb7 | 422 | return retval; |
5e1c5ff4 TL |
423 | } |
424 | ||
425 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
426 | { | |
92105bb7 | 427 | void __iomem *reg = bank->base; |
5e1c5ff4 | 428 | |
eef4bec7 | 429 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 430 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
431 | |
432 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
433 | if (bank->regs->irqstatus2) { |
434 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 435 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 436 | } |
bedfd154 RQ |
437 | |
438 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
439 | __raw_readl(reg); | |
5e1c5ff4 TL |
440 | } |
441 | ||
442 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
443 | { | |
129fd223 | 444 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
445 | } |
446 | ||
ea6dedd7 ID |
447 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
448 | { | |
449 | void __iomem *reg = bank->base; | |
99c47707 | 450 | u32 l; |
c390aad0 | 451 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 452 | |
28f3b5a0 | 453 | reg += bank->regs->irqenable; |
99c47707 | 454 | l = __raw_readl(reg); |
28f3b5a0 | 455 | if (bank->regs->irqenable_inv) |
99c47707 ID |
456 | l = ~l; |
457 | l &= mask; | |
458 | return l; | |
ea6dedd7 ID |
459 | } |
460 | ||
28f3b5a0 | 461 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 462 | { |
92105bb7 | 463 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
464 | u32 l; |
465 | ||
28f3b5a0 KH |
466 | if (bank->regs->set_irqenable) { |
467 | reg += bank->regs->set_irqenable; | |
468 | l = gpio_mask; | |
469 | } else { | |
470 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 471 | l = __raw_readl(reg); |
28f3b5a0 KH |
472 | if (bank->regs->irqenable_inv) |
473 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
474 | else |
475 | l |= gpio_mask; | |
28f3b5a0 KH |
476 | } |
477 | ||
478 | __raw_writel(l, reg); | |
479 | } | |
480 | ||
481 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
482 | { | |
483 | void __iomem *reg = bank->base; | |
484 | u32 l; | |
485 | ||
486 | if (bank->regs->clr_irqenable) { | |
487 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 488 | l = gpio_mask; |
28f3b5a0 KH |
489 | } else { |
490 | reg += bank->regs->irqenable; | |
56739a69 | 491 | l = __raw_readl(reg); |
28f3b5a0 | 492 | if (bank->regs->irqenable_inv) |
56739a69 | 493 | l |= gpio_mask; |
92105bb7 | 494 | else |
28f3b5a0 | 495 | l &= ~gpio_mask; |
5e1c5ff4 | 496 | } |
28f3b5a0 | 497 | |
5e1c5ff4 TL |
498 | __raw_writel(l, reg); |
499 | } | |
500 | ||
501 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
502 | { | |
28f3b5a0 | 503 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
504 | } |
505 | ||
92105bb7 TL |
506 | /* |
507 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
508 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
509 | * to the target, system will wake up always on GPIO events. While | |
510 | * system is running all registered GPIO interrupts need to have wake-up | |
511 | * enabled. When system is suspended, only selected GPIO interrupts need | |
512 | * to have wake-up enabled. | |
513 | */ | |
514 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
515 | { | |
f64ad1a0 KH |
516 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
517 | unsigned long flags; | |
a6472533 | 518 | |
f64ad1a0 KH |
519 | if (bank->non_wakeup_gpios & gpio_bit) { |
520 | dev_err(bank->dev, | |
521 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); | |
92105bb7 TL |
522 | return -EINVAL; |
523 | } | |
f64ad1a0 KH |
524 | |
525 | spin_lock_irqsave(&bank->lock, flags); | |
526 | if (enable) | |
527 | bank->suspend_wakeup |= gpio_bit; | |
528 | else | |
529 | bank->suspend_wakeup &= ~gpio_bit; | |
530 | ||
531 | spin_unlock_irqrestore(&bank->lock, flags); | |
532 | ||
533 | return 0; | |
92105bb7 TL |
534 | } |
535 | ||
4196dd6b TL |
536 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
537 | { | |
129fd223 | 538 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
539 | _set_gpio_irqenable(bank, gpio, 0); |
540 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 541 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
542 | } |
543 | ||
92105bb7 | 544 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 545 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 546 | { |
e9191028 | 547 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
548 | struct gpio_bank *bank; |
549 | int retval; | |
550 | ||
e9191028 | 551 | bank = irq_data_get_irq_chip_data(d); |
f64ad1a0 | 552 | retval = _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
553 | |
554 | return retval; | |
555 | } | |
556 | ||
3ff164e1 | 557 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 558 | { |
3ff164e1 | 559 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 560 | unsigned long flags; |
52e31344 | 561 | |
a6472533 | 562 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 563 | |
4196dd6b TL |
564 | /* Set trigger to none. You need to enable the desired trigger with |
565 | * request_irq() or set_irq_type(). | |
566 | */ | |
3ff164e1 | 567 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 568 | |
1a8bfa1e | 569 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 570 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 571 | void __iomem *reg; |
5e1c5ff4 | 572 | |
92105bb7 | 573 | /* Claim the pin for MPU */ |
5e1c5ff4 | 574 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 575 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
576 | } |
577 | #endif | |
058af1ea C |
578 | if (!cpu_class_is_omap1()) { |
579 | if (!bank->mod_usage) { | |
9f096868 | 580 | void __iomem *reg = bank->base; |
058af1ea | 581 | u32 ctrl; |
9f096868 C |
582 | |
583 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
584 | reg += OMAP24XX_GPIO_CTRL; | |
585 | else if (cpu_is_omap44xx()) | |
586 | reg += OMAP4_GPIO_CTRL; | |
587 | ctrl = __raw_readl(reg); | |
058af1ea | 588 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
589 | ctrl &= 0xFFFFFFFE; |
590 | __raw_writel(ctrl, reg); | |
058af1ea C |
591 | } |
592 | bank->mod_usage |= 1 << offset; | |
593 | } | |
a6472533 | 594 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
595 | |
596 | return 0; | |
597 | } | |
598 | ||
3ff164e1 | 599 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 600 | { |
3ff164e1 | 601 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 602 | unsigned long flags; |
5e1c5ff4 | 603 | |
a6472533 | 604 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
605 | #ifdef CONFIG_ARCH_OMAP16XX |
606 | if (bank->method == METHOD_GPIO_1610) { | |
607 | /* Disable wake-up during idle for dynamic tick */ | |
608 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 609 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
610 | } |
611 | #endif | |
9f096868 C |
612 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
613 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
614 | /* Disable wake-up during idle for dynamic tick */ |
615 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 616 | __raw_writel(1 << offset, reg); |
92105bb7 | 617 | } |
9f096868 C |
618 | #endif |
619 | #ifdef CONFIG_ARCH_OMAP4 | |
620 | if (bank->method == METHOD_GPIO_44XX) { | |
621 | /* Disable wake-up during idle for dynamic tick */ | |
622 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
623 | __raw_writel(1 << offset, reg); | |
624 | } | |
92105bb7 | 625 | #endif |
058af1ea C |
626 | if (!cpu_class_is_omap1()) { |
627 | bank->mod_usage &= ~(1 << offset); | |
628 | if (!bank->mod_usage) { | |
9f096868 | 629 | void __iomem *reg = bank->base; |
058af1ea | 630 | u32 ctrl; |
9f096868 C |
631 | |
632 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
633 | reg += OMAP24XX_GPIO_CTRL; | |
634 | else if (cpu_is_omap44xx()) | |
635 | reg += OMAP4_GPIO_CTRL; | |
636 | ctrl = __raw_readl(reg); | |
058af1ea C |
637 | /* Module is disabled, clocks are gated */ |
638 | ctrl |= 1; | |
9f096868 | 639 | __raw_writel(ctrl, reg); |
058af1ea C |
640 | } |
641 | } | |
3ff164e1 | 642 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 643 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
644 | } |
645 | ||
646 | /* | |
647 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
648 | * avoid missing GPIO interrupts for other lines in the bank. | |
649 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
650 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
651 | * If we wait to unmask individual GPIO lines in the bank after the | |
652 | * line's interrupt handler has been run, we may miss some nested | |
653 | * interrupts. | |
654 | */ | |
10dd5ce2 | 655 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 656 | { |
92105bb7 | 657 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 658 | u32 isr; |
4318f36b | 659 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 660 | struct gpio_bank *bank; |
ea6dedd7 ID |
661 | u32 retrigger = 0; |
662 | int unmasked = 0; | |
ee144182 | 663 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 664 | |
ee144182 | 665 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 666 | |
6845664a | 667 | bank = irq_get_handler_data(irq); |
eef4bec7 | 668 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
669 | |
670 | if (WARN_ON(!isr_reg)) | |
671 | goto exit; | |
672 | ||
92105bb7 | 673 | while(1) { |
6e60e79a | 674 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 675 | u32 enabled; |
6e60e79a | 676 | |
ea6dedd7 ID |
677 | enabled = _get_gpio_irqbank_mask(bank); |
678 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
679 | |
680 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
681 | isr &= 0x0000ffff; | |
682 | ||
5492fb1a | 683 | if (cpu_class_is_omap2()) { |
b144ff6f | 684 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 685 | } |
6e60e79a TL |
686 | |
687 | /* clear edge sensitive interrupts before handler(s) are | |
688 | called so that we don't miss any interrupt occurred while | |
689 | executing them */ | |
28f3b5a0 | 690 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 691 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 692 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
693 | |
694 | /* if there is only edge sensitive GPIO pin interrupts | |
695 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
696 | if (!level_mask && !unmasked) { |
697 | unmasked = 1; | |
ee144182 | 698 | chained_irq_exit(chip, desc); |
ea6dedd7 | 699 | } |
92105bb7 | 700 | |
ea6dedd7 ID |
701 | isr |= retrigger; |
702 | retrigger = 0; | |
92105bb7 TL |
703 | if (!isr) |
704 | break; | |
705 | ||
706 | gpio_irq = bank->virtual_irq_start; | |
707 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 708 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 709 | |
92105bb7 TL |
710 | if (!(isr & 1)) |
711 | continue; | |
29454dde | 712 | |
4318f36b CM |
713 | #ifdef CONFIG_ARCH_OMAP1 |
714 | /* | |
715 | * Some chips can't respond to both rising and falling | |
716 | * at the same time. If this irq was requested with | |
717 | * both flags, we need to flip the ICR data for the IRQ | |
718 | * to respond to the IRQ for the opposite direction. | |
719 | * This will be indicated in the bank toggle_mask. | |
720 | */ | |
721 | if (bank->toggle_mask & (1 << gpio_index)) | |
722 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
723 | #endif | |
724 | ||
d8aa0251 | 725 | generic_handle_irq(gpio_irq); |
92105bb7 | 726 | } |
1a8bfa1e | 727 | } |
ea6dedd7 ID |
728 | /* if bank has any level sensitive GPIO pin interrupt |
729 | configured, we must unmask the bank interrupt only after | |
730 | handler(s) are executed in order to avoid spurious bank | |
731 | interrupt */ | |
b1cc4c55 | 732 | exit: |
ea6dedd7 | 733 | if (!unmasked) |
ee144182 | 734 | chained_irq_exit(chip, desc); |
5e1c5ff4 TL |
735 | } |
736 | ||
e9191028 | 737 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 738 | { |
e9191028 LB |
739 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
740 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 741 | unsigned long flags; |
4196dd6b | 742 | |
85ec7b97 | 743 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 744 | _reset_gpio(bank, gpio); |
85ec7b97 | 745 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
746 | } |
747 | ||
e9191028 | 748 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 749 | { |
e9191028 LB |
750 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
751 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
752 | |
753 | _clear_gpio_irqstatus(bank, gpio); | |
754 | } | |
755 | ||
e9191028 | 756 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 757 | { |
e9191028 LB |
758 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
759 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 760 | unsigned long flags; |
5e1c5ff4 | 761 | |
85ec7b97 | 762 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 763 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 764 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 765 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
766 | } |
767 | ||
e9191028 | 768 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 769 | { |
e9191028 LB |
770 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
771 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 772 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 773 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 774 | unsigned long flags; |
55b6019a | 775 | |
85ec7b97 | 776 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 777 | if (trigger) |
129fd223 | 778 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
779 | |
780 | /* For level-triggered GPIOs, the clearing must be done after | |
781 | * the HW source is cleared, thus after the handler has run */ | |
782 | if (bank->level_mask & irq_mask) { | |
783 | _set_gpio_irqenable(bank, gpio, 0); | |
784 | _clear_gpio_irqstatus(bank, gpio); | |
785 | } | |
5e1c5ff4 | 786 | |
4de8c75b | 787 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 788 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
789 | } |
790 | ||
e5c56ed3 DB |
791 | static struct irq_chip gpio_irq_chip = { |
792 | .name = "GPIO", | |
e9191028 LB |
793 | .irq_shutdown = gpio_irq_shutdown, |
794 | .irq_ack = gpio_ack_irq, | |
795 | .irq_mask = gpio_mask_irq, | |
796 | .irq_unmask = gpio_unmask_irq, | |
797 | .irq_set_type = gpio_irq_type, | |
798 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
799 | }; |
800 | ||
801 | /*---------------------------------------------------------------------*/ | |
802 | ||
803 | #ifdef CONFIG_ARCH_OMAP1 | |
804 | ||
e5c56ed3 DB |
805 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) |
806 | ||
11a78b79 DB |
807 | #ifdef CONFIG_ARCH_OMAP16XX |
808 | ||
809 | #include <linux/platform_device.h> | |
810 | ||
79ee031f | 811 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 812 | { |
79ee031f | 813 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 814 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
815 | void __iomem *mask_reg = bank->base + |
816 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 817 | unsigned long flags; |
11a78b79 | 818 | |
a6472533 | 819 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
820 | bank->saved_wakeup = __raw_readl(mask_reg); |
821 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 822 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
823 | |
824 | return 0; | |
825 | } | |
826 | ||
79ee031f | 827 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 828 | { |
79ee031f | 829 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 830 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
831 | void __iomem *mask_reg = bank->base + |
832 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 833 | unsigned long flags; |
11a78b79 | 834 | |
a6472533 | 835 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 836 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 837 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
838 | |
839 | return 0; | |
840 | } | |
841 | ||
47145210 | 842 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
843 | .suspend_noirq = omap_mpuio_suspend_noirq, |
844 | .resume_noirq = omap_mpuio_resume_noirq, | |
845 | }; | |
846 | ||
3c437ffd | 847 | /* use platform_driver for this. */ |
11a78b79 | 848 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
849 | .driver = { |
850 | .name = "mpuio", | |
79ee031f | 851 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
852 | }, |
853 | }; | |
854 | ||
855 | static struct platform_device omap_mpuio_device = { | |
856 | .name = "mpuio", | |
857 | .id = -1, | |
858 | .dev = { | |
859 | .driver = &omap_mpuio_driver.driver, | |
860 | } | |
861 | /* could list the /proc/iomem resources */ | |
862 | }; | |
863 | ||
03e128ca | 864 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 865 | { |
77640aab | 866 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 867 | |
11a78b79 DB |
868 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
869 | (void) platform_device_register(&omap_mpuio_device); | |
870 | } | |
871 | ||
872 | #else | |
03e128ca | 873 | static inline void mpuio_init(struct gpio_bank *bank) {} |
11a78b79 DB |
874 | #endif /* 16xx */ |
875 | ||
e5c56ed3 DB |
876 | #else |
877 | ||
e5c56ed3 | 878 | #define bank_is_mpuio(bank) 0 |
03e128ca | 879 | static inline void mpuio_init(struct gpio_bank *bank) {} |
e5c56ed3 DB |
880 | |
881 | #endif | |
882 | ||
883 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 884 | |
52e31344 DB |
885 | /* REVISIT these are stupid implementations! replace by ones that |
886 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
887 | */ | |
888 | ||
889 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
890 | { | |
891 | struct gpio_bank *bank; | |
892 | unsigned long flags; | |
893 | ||
894 | bank = container_of(chip, struct gpio_bank, chip); | |
895 | spin_lock_irqsave(&bank->lock, flags); | |
896 | _set_gpio_direction(bank, offset, 1); | |
897 | spin_unlock_irqrestore(&bank->lock, flags); | |
898 | return 0; | |
899 | } | |
900 | ||
b37c45b8 RQ |
901 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
902 | { | |
fa87931a | 903 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 904 | |
b37c45b8 RQ |
905 | return __raw_readl(reg) & mask; |
906 | } | |
907 | ||
52e31344 DB |
908 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
909 | { | |
b37c45b8 RQ |
910 | struct gpio_bank *bank; |
911 | void __iomem *reg; | |
912 | int gpio; | |
913 | u32 mask; | |
914 | ||
915 | gpio = chip->base + offset; | |
a8be8daf | 916 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 917 | reg = bank->base; |
129fd223 | 918 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
919 | |
920 | if (gpio_is_input(bank, mask)) | |
921 | return _get_gpio_datain(bank, gpio); | |
922 | else | |
923 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
924 | } |
925 | ||
926 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
927 | { | |
928 | struct gpio_bank *bank; | |
929 | unsigned long flags; | |
930 | ||
931 | bank = container_of(chip, struct gpio_bank, chip); | |
932 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 933 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
934 | _set_gpio_direction(bank, offset, 0); |
935 | spin_unlock_irqrestore(&bank->lock, flags); | |
936 | return 0; | |
937 | } | |
938 | ||
168ef3d9 FB |
939 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
940 | unsigned debounce) | |
941 | { | |
942 | struct gpio_bank *bank; | |
943 | unsigned long flags; | |
944 | ||
945 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
946 | |
947 | if (!bank->dbck) { | |
948 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
949 | if (IS_ERR(bank->dbck)) | |
950 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
951 | } | |
952 | ||
168ef3d9 FB |
953 | spin_lock_irqsave(&bank->lock, flags); |
954 | _set_gpio_debounce(bank, offset, debounce); | |
955 | spin_unlock_irqrestore(&bank->lock, flags); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
52e31344 DB |
960 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
961 | { | |
962 | struct gpio_bank *bank; | |
963 | unsigned long flags; | |
964 | ||
965 | bank = container_of(chip, struct gpio_bank, chip); | |
966 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 967 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
968 | spin_unlock_irqrestore(&bank->lock, flags); |
969 | } | |
970 | ||
a007b709 DB |
971 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
972 | { | |
973 | struct gpio_bank *bank; | |
974 | ||
975 | bank = container_of(chip, struct gpio_bank, chip); | |
976 | return bank->virtual_irq_start + offset; | |
977 | } | |
978 | ||
52e31344 DB |
979 | /*---------------------------------------------------------------------*/ |
980 | ||
9a748053 | 981 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 982 | { |
e5ff4440 | 983 | static bool called; |
9f7065da TL |
984 | u32 rev; |
985 | ||
e5ff4440 | 986 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
987 | return; |
988 | ||
e5ff4440 KH |
989 | rev = __raw_readw(bank->base + bank->regs->revision); |
990 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 991 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
992 | |
993 | called = true; | |
9f7065da TL |
994 | } |
995 | ||
8ba55c5c DB |
996 | /* This lock class tells lockdep that GPIO irqs are in a different |
997 | * category than their parents, so it won't report false recursion. | |
998 | */ | |
999 | static struct lock_class_key gpio_lock_class; | |
1000 | ||
77640aab | 1001 | /* TODO: Cleanup cpu_is_* checks */ |
03e128ca | 1002 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe VC |
1003 | { |
1004 | if (cpu_class_is_omap2()) { | |
1005 | if (cpu_is_omap44xx()) { | |
1006 | __raw_writel(0xffffffff, bank->base + | |
1007 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1008 | __raw_writel(0x00000000, bank->base + | |
1009 | OMAP4_GPIO_DEBOUNCENABLE); | |
1010 | /* Initialize interface clk ungated, module enabled */ | |
1011 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1012 | } else if (cpu_is_omap34xx()) { | |
1013 | __raw_writel(0x00000000, bank->base + | |
1014 | OMAP24XX_GPIO_IRQENABLE1); | |
1015 | __raw_writel(0xffffffff, bank->base + | |
1016 | OMAP24XX_GPIO_IRQSTATUS1); | |
1017 | __raw_writel(0x00000000, bank->base + | |
1018 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1019 | ||
1020 | /* Initialize interface clk ungated, module enabled */ | |
1021 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
1022 | } else if (cpu_is_omap24xx()) { | |
1023 | static const u32 non_wakeup_gpios[] = { | |
1024 | 0xe203ffc0, 0x08700040 | |
1025 | }; | |
03e128ca C |
1026 | if (bank->id < ARRAY_SIZE(non_wakeup_gpios)) |
1027 | bank->non_wakeup_gpios = | |
1028 | non_wakeup_gpios[bank->id]; | |
2fae7fbe VC |
1029 | } |
1030 | } else if (cpu_class_is_omap1()) { | |
03e128ca | 1031 | if (bank_is_mpuio(bank)) { |
5de62b86 TL |
1032 | __raw_writew(0xffff, bank->base + |
1033 | OMAP_MPUIO_GPIO_MASKIT / bank->stride); | |
03e128ca C |
1034 | mpuio_init(bank); |
1035 | } | |
2fae7fbe VC |
1036 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
1037 | __raw_writew(0xffff, bank->base | |
1038 | + OMAP1510_GPIO_INT_MASK); | |
1039 | __raw_writew(0x0000, bank->base | |
1040 | + OMAP1510_GPIO_INT_STATUS); | |
1041 | } | |
1042 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | |
1043 | __raw_writew(0x0000, bank->base | |
1044 | + OMAP1610_GPIO_IRQENABLE1); | |
1045 | __raw_writew(0xffff, bank->base | |
1046 | + OMAP1610_GPIO_IRQSTATUS1); | |
1047 | __raw_writew(0x0014, bank->base | |
1048 | + OMAP1610_GPIO_SYSCONFIG); | |
1049 | ||
1050 | /* | |
1051 | * Enable system clock for GPIO module. | |
1052 | * The CAM_CLK_CTRL *is* really the right place. | |
1053 | */ | |
1054 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | |
1055 | ULPD_CAM_CLK_CTRL); | |
1056 | } | |
1057 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | |
1058 | __raw_writel(0xffffffff, bank->base | |
1059 | + OMAP7XX_GPIO_INT_MASK); | |
1060 | __raw_writel(0x00000000, bank->base | |
1061 | + OMAP7XX_GPIO_INT_STATUS); | |
1062 | } | |
1063 | } | |
1064 | } | |
1065 | ||
f8b46b58 KH |
1066 | static __init void |
1067 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |
1068 | unsigned int num) | |
1069 | { | |
1070 | struct irq_chip_generic *gc; | |
1071 | struct irq_chip_type *ct; | |
1072 | ||
1073 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1074 | handle_simple_irq); | |
83233749 TP |
1075 | if (!gc) { |
1076 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1077 | return; | |
1078 | } | |
1079 | ||
f8b46b58 KH |
1080 | ct = gc->chip_types; |
1081 | ||
1082 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1083 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1084 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
1085 | ct->chip.irq_set_type = gpio_irq_type; | |
1086 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1087 | if (cpu_is_omap16xx()) | |
1088 | ct->chip.irq_set_wake = gpio_wake_enable, | |
1089 | ||
1090 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1091 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1092 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1093 | } | |
1094 | ||
d52b31de | 1095 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1096 | { |
77640aab | 1097 | int j; |
2fae7fbe VC |
1098 | static int gpio; |
1099 | ||
2fae7fbe VC |
1100 | bank->mod_usage = 0; |
1101 | /* | |
1102 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1103 | * over to the generic ones | |
1104 | */ | |
1105 | bank->chip.request = omap_gpio_request; | |
1106 | bank->chip.free = omap_gpio_free; | |
1107 | bank->chip.direction_input = gpio_input; | |
1108 | bank->chip.get = gpio_get; | |
1109 | bank->chip.direction_output = gpio_output; | |
1110 | bank->chip.set_debounce = gpio_debounce; | |
1111 | bank->chip.set = gpio_set; | |
1112 | bank->chip.to_irq = gpio_2irq; | |
1113 | if (bank_is_mpuio(bank)) { | |
1114 | bank->chip.label = "mpuio"; | |
1115 | #ifdef CONFIG_ARCH_OMAP16XX | |
1116 | bank->chip.dev = &omap_mpuio_device.dev; | |
1117 | #endif | |
1118 | bank->chip.base = OMAP_MPUIO(0); | |
1119 | } else { | |
1120 | bank->chip.label = "gpio"; | |
1121 | bank->chip.base = gpio; | |
d5f46247 | 1122 | gpio += bank->width; |
2fae7fbe | 1123 | } |
d5f46247 | 1124 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1125 | |
1126 | gpiochip_add(&bank->chip); | |
1127 | ||
1128 | for (j = bank->virtual_irq_start; | |
d5f46247 | 1129 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 1130 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1131 | irq_set_chip_data(j, bank); |
f8b46b58 KH |
1132 | if (bank_is_mpuio(bank)) { |
1133 | omap_mpuio_alloc_gc(bank, j, bank->width); | |
1134 | } else { | |
6845664a | 1135 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
1136 | irq_set_handler(j, handle_simple_irq); |
1137 | set_irq_flags(j, IRQF_VALID); | |
1138 | } | |
2fae7fbe | 1139 | } |
6845664a TG |
1140 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1141 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1142 | } |
1143 | ||
77640aab | 1144 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1145 | { |
77640aab VC |
1146 | struct omap_gpio_platform_data *pdata; |
1147 | struct resource *res; | |
5e1c5ff4 | 1148 | struct gpio_bank *bank; |
03e128ca | 1149 | int ret = 0; |
5e1c5ff4 | 1150 | |
03e128ca C |
1151 | if (!pdev->dev.platform_data) { |
1152 | ret = -EINVAL; | |
1153 | goto err_exit; | |
5492fb1a | 1154 | } |
5492fb1a | 1155 | |
03e128ca C |
1156 | bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); |
1157 | if (!bank) { | |
1158 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1159 | ret = -ENOMEM; | |
1160 | goto err_exit; | |
1161 | } | |
92105bb7 | 1162 | |
77640aab VC |
1163 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1164 | if (unlikely(!res)) { | |
03e128ca C |
1165 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", |
1166 | pdev->id); | |
1167 | ret = -ENODEV; | |
1168 | goto err_free; | |
44169075 | 1169 | } |
5e1c5ff4 | 1170 | |
77640aab | 1171 | bank->irq = res->start; |
03e128ca C |
1172 | bank->id = pdev->id; |
1173 | ||
1174 | pdata = pdev->dev.platform_data; | |
77640aab VC |
1175 | bank->virtual_irq_start = pdata->virtual_irq_start; |
1176 | bank->method = pdata->bank_type; | |
1177 | bank->dev = &pdev->dev; | |
1178 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1179 | bank->stride = pdata->bank_stride; |
d5f46247 | 1180 | bank->width = pdata->bank_width; |
0cde8d03 | 1181 | bank->loses_context = pdata->loses_context; |
fa87931a KH |
1182 | bank->regs = pdata->regs; |
1183 | ||
1184 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1185 | bank->set_dataout = _set_gpio_dataout_reg; | |
1186 | else | |
1187 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1188 | |
77640aab | 1189 | spin_lock_init(&bank->lock); |
9f7065da | 1190 | |
77640aab VC |
1191 | /* Static mapping, never released */ |
1192 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1193 | if (unlikely(!res)) { | |
03e128ca C |
1194 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", |
1195 | pdev->id); | |
1196 | ret = -ENODEV; | |
1197 | goto err_free; | |
77640aab | 1198 | } |
89db9482 | 1199 | |
77640aab VC |
1200 | bank->base = ioremap(res->start, resource_size(res)); |
1201 | if (!bank->base) { | |
03e128ca C |
1202 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", |
1203 | pdev->id); | |
1204 | ret = -ENOMEM; | |
1205 | goto err_free; | |
5e1c5ff4 TL |
1206 | } |
1207 | ||
77640aab VC |
1208 | pm_runtime_enable(bank->dev); |
1209 | pm_runtime_get_sync(bank->dev); | |
1210 | ||
03e128ca | 1211 | omap_gpio_mod_init(bank); |
77640aab | 1212 | omap_gpio_chip_init(bank); |
9a748053 | 1213 | omap_gpio_show_rev(bank); |
9f7065da | 1214 | |
03e128ca | 1215 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1216 | |
03e128ca C |
1217 | return ret; |
1218 | ||
1219 | err_free: | |
1220 | kfree(bank); | |
1221 | err_exit: | |
1222 | return ret; | |
5e1c5ff4 TL |
1223 | } |
1224 | ||
140455fa | 1225 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd | 1226 | static int omap_gpio_suspend(void) |
92105bb7 | 1227 | { |
03e128ca | 1228 | struct gpio_bank *bank; |
92105bb7 | 1229 | |
5492fb1a | 1230 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1231 | return 0; |
1232 | ||
03e128ca | 1233 | list_for_each_entry(bank, &omap_gpio_list, node) { |
92105bb7 TL |
1234 | void __iomem *wake_status; |
1235 | void __iomem *wake_clear; | |
1236 | void __iomem *wake_set; | |
a6472533 | 1237 | unsigned long flags; |
92105bb7 TL |
1238 | |
1239 | switch (bank->method) { | |
e5c56ed3 | 1240 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1241 | case METHOD_GPIO_1610: |
1242 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1243 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1244 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1245 | break; | |
e5c56ed3 | 1246 | #endif |
a8eb7ca0 | 1247 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1248 | case METHOD_GPIO_24XX: |
723fdb78 | 1249 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1250 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1251 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1252 | break; | |
78a1a6d3 SR |
1253 | #endif |
1254 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1255 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1256 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1257 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1258 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1259 | break; | |
e5c56ed3 | 1260 | #endif |
92105bb7 TL |
1261 | default: |
1262 | continue; | |
1263 | } | |
1264 | ||
a6472533 | 1265 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1266 | bank->saved_wakeup = __raw_readl(wake_status); |
1267 | __raw_writel(0xffffffff, wake_clear); | |
1268 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1269 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1270 | } |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
3c437ffd | 1275 | static void omap_gpio_resume(void) |
92105bb7 | 1276 | { |
03e128ca | 1277 | struct gpio_bank *bank; |
92105bb7 | 1278 | |
723fdb78 | 1279 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
3c437ffd | 1280 | return; |
92105bb7 | 1281 | |
03e128ca | 1282 | list_for_each_entry(bank, &omap_gpio_list, node) { |
92105bb7 TL |
1283 | void __iomem *wake_clear; |
1284 | void __iomem *wake_set; | |
a6472533 | 1285 | unsigned long flags; |
92105bb7 TL |
1286 | |
1287 | switch (bank->method) { | |
e5c56ed3 | 1288 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1289 | case METHOD_GPIO_1610: |
1290 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1291 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1292 | break; | |
e5c56ed3 | 1293 | #endif |
a8eb7ca0 | 1294 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1295 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1296 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1297 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1298 | break; |
78a1a6d3 SR |
1299 | #endif |
1300 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1301 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1302 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1303 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1304 | break; | |
e5c56ed3 | 1305 | #endif |
92105bb7 TL |
1306 | default: |
1307 | continue; | |
1308 | } | |
1309 | ||
a6472533 | 1310 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1311 | __raw_writel(0xffffffff, wake_clear); |
1312 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1313 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1314 | } |
92105bb7 TL |
1315 | } |
1316 | ||
3c437ffd | 1317 | static struct syscore_ops omap_gpio_syscore_ops = { |
92105bb7 TL |
1318 | .suspend = omap_gpio_suspend, |
1319 | .resume = omap_gpio_resume, | |
1320 | }; | |
1321 | ||
3ac4fa99 JY |
1322 | #endif |
1323 | ||
140455fa | 1324 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
1325 | |
1326 | static int workaround_enabled; | |
1327 | ||
72e06d08 | 1328 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 | 1329 | { |
03e128ca C |
1330 | int c = 0; |
1331 | struct gpio_bank *bank; | |
43ffcd9a | 1332 | |
03e128ca | 1333 | list_for_each_entry(bank, &omap_gpio_list, node) { |
ca828760 | 1334 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1335 | int j; |
3ac4fa99 | 1336 | |
0cde8d03 | 1337 | if (!bank->loses_context) |
03e128ca C |
1338 | continue; |
1339 | ||
0aed0435 | 1340 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1341 | clk_disable(bank->dbck); |
1342 | ||
72e06d08 | 1343 | if (!off_mode) |
43ffcd9a KH |
1344 | continue; |
1345 | ||
1346 | /* If going to OFF, remove triggering for all | |
1347 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1348 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
1349 | if (!(bank->enabled_non_wakeup_gpios)) |
1350 | continue; | |
3f1686a9 TL |
1351 | |
1352 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1353 | bank->saved_datain = __raw_readl(bank->base + | |
1354 | OMAP24XX_GPIO_DATAIN); | |
1355 | l1 = __raw_readl(bank->base + | |
1356 | OMAP24XX_GPIO_FALLINGDETECT); | |
1357 | l2 = __raw_readl(bank->base + | |
1358 | OMAP24XX_GPIO_RISINGDETECT); | |
1359 | } | |
1360 | ||
1361 | if (cpu_is_omap44xx()) { | |
1362 | bank->saved_datain = __raw_readl(bank->base + | |
1363 | OMAP4_GPIO_DATAIN); | |
1364 | l1 = __raw_readl(bank->base + | |
1365 | OMAP4_GPIO_FALLINGDETECT); | |
1366 | l2 = __raw_readl(bank->base + | |
1367 | OMAP4_GPIO_RISINGDETECT); | |
1368 | } | |
1369 | ||
3ac4fa99 JY |
1370 | bank->saved_fallingdetect = l1; |
1371 | bank->saved_risingdetect = l2; | |
1372 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1373 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
1374 | |
1375 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1376 | __raw_writel(l1, bank->base + | |
1377 | OMAP24XX_GPIO_FALLINGDETECT); | |
1378 | __raw_writel(l2, bank->base + | |
1379 | OMAP24XX_GPIO_RISINGDETECT); | |
1380 | } | |
1381 | ||
1382 | if (cpu_is_omap44xx()) { | |
1383 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1384 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
1385 | } | |
1386 | ||
3ac4fa99 JY |
1387 | c++; |
1388 | } | |
1389 | if (!c) { | |
1390 | workaround_enabled = 0; | |
1391 | return; | |
1392 | } | |
1393 | workaround_enabled = 1; | |
1394 | } | |
1395 | ||
43ffcd9a | 1396 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 | 1397 | { |
03e128ca | 1398 | struct gpio_bank *bank; |
3ac4fa99 | 1399 | |
03e128ca | 1400 | list_for_each_entry(bank, &omap_gpio_list, node) { |
ca828760 | 1401 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1402 | int j; |
3ac4fa99 | 1403 | |
0cde8d03 | 1404 | if (!bank->loses_context) |
03e128ca C |
1405 | continue; |
1406 | ||
0aed0435 | 1407 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1408 | clk_enable(bank->dbck); |
1409 | ||
43ffcd9a KH |
1410 | if (!workaround_enabled) |
1411 | continue; | |
1412 | ||
3ac4fa99 JY |
1413 | if (!(bank->enabled_non_wakeup_gpios)) |
1414 | continue; | |
3f1686a9 TL |
1415 | |
1416 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1417 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 1418 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 1419 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 1420 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
1421 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1422 | } | |
1423 | ||
1424 | if (cpu_is_omap44xx()) { | |
1425 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 1426 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 1427 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 1428 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
1429 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
1430 | } | |
1431 | ||
3ac4fa99 JY |
1432 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1433 | * state. If so, generate an IRQ by software. This is | |
1434 | * horribly racy, but it's the best we can do to work around | |
1435 | * this silicon bug. */ | |
3ac4fa99 | 1436 | l ^= bank->saved_datain; |
a118b5f3 | 1437 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1438 | |
1439 | /* | |
1440 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1441 | * configured with falling edge only; and vice versa. | |
1442 | */ | |
1443 | gen0 = l & bank->saved_fallingdetect; | |
1444 | gen0 &= bank->saved_datain; | |
1445 | ||
1446 | gen1 = l & bank->saved_risingdetect; | |
1447 | gen1 &= ~(bank->saved_datain); | |
1448 | ||
1449 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1450 | gen = l & (~(bank->saved_fallingdetect) & | |
1451 | ~(bank->saved_risingdetect)); | |
1452 | /* Consider all GPIO IRQs needed to be updated */ | |
1453 | gen |= gen0 | gen1; | |
1454 | ||
1455 | if (gen) { | |
3ac4fa99 | 1456 | u32 old0, old1; |
3f1686a9 | 1457 | |
f00d6497 | 1458 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
1459 | old0 = __raw_readl(bank->base + |
1460 | OMAP24XX_GPIO_LEVELDETECT0); | |
1461 | old1 = __raw_readl(bank->base + | |
1462 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 1463 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 1464 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1465 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 1466 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 1467 | __raw_writel(old0, bank->base + |
3f1686a9 | 1468 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1469 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
1470 | OMAP24XX_GPIO_LEVELDETECT1); |
1471 | } | |
1472 | ||
1473 | if (cpu_is_omap44xx()) { | |
1474 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 1475 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1476 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 1477 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1478 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 1479 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1480 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 1481 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1482 | __raw_writel(old0, bank->base + |
78a1a6d3 | 1483 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1484 | __raw_writel(old1, bank->base + |
78a1a6d3 | 1485 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1486 | } |
3ac4fa99 JY |
1487 | } |
1488 | } | |
1489 | ||
1490 | } | |
1491 | ||
92105bb7 TL |
1492 | #endif |
1493 | ||
a8eb7ca0 | 1494 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
1495 | void omap_gpio_save_context(void) |
1496 | { | |
03e128ca | 1497 | struct gpio_bank *bank; |
03e128ca C |
1498 | |
1499 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
03e128ca | 1500 | |
0cde8d03 | 1501 | if (!bank->loses_context) |
03e128ca | 1502 | continue; |
40c670f0 | 1503 | |
6d62e216 | 1504 | bank->context.irqenable1 = |
40c670f0 | 1505 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); |
6d62e216 | 1506 | bank->context.irqenable2 = |
40c670f0 | 1507 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); |
6d62e216 | 1508 | bank->context.wake_en = |
40c670f0 | 1509 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); |
6d62e216 | 1510 | bank->context.ctrl = |
40c670f0 | 1511 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); |
6d62e216 | 1512 | bank->context.oe = |
40c670f0 | 1513 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); |
6d62e216 | 1514 | bank->context.leveldetect0 = |
40c670f0 | 1515 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
6d62e216 | 1516 | bank->context.leveldetect1 = |
40c670f0 | 1517 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); |
6d62e216 | 1518 | bank->context.risingdetect = |
40c670f0 | 1519 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); |
6d62e216 | 1520 | bank->context.fallingdetect = |
40c670f0 | 1521 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
6d62e216 | 1522 | bank->context.dataout = |
40c670f0 | 1523 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); |
40c670f0 RN |
1524 | } |
1525 | } | |
1526 | ||
40c670f0 RN |
1527 | void omap_gpio_restore_context(void) |
1528 | { | |
03e128ca | 1529 | struct gpio_bank *bank; |
03e128ca C |
1530 | |
1531 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
03e128ca | 1532 | |
0cde8d03 | 1533 | if (!bank->loses_context) |
03e128ca | 1534 | continue; |
40c670f0 | 1535 | |
6d62e216 | 1536 | __raw_writel(bank->context.irqenable1, |
40c670f0 | 1537 | bank->base + OMAP24XX_GPIO_IRQENABLE1); |
6d62e216 | 1538 | __raw_writel(bank->context.irqenable2, |
40c670f0 | 1539 | bank->base + OMAP24XX_GPIO_IRQENABLE2); |
6d62e216 | 1540 | __raw_writel(bank->context.wake_en, |
40c670f0 | 1541 | bank->base + OMAP24XX_GPIO_WAKE_EN); |
6d62e216 | 1542 | __raw_writel(bank->context.ctrl, |
40c670f0 | 1543 | bank->base + OMAP24XX_GPIO_CTRL); |
6d62e216 | 1544 | __raw_writel(bank->context.oe, |
40c670f0 | 1545 | bank->base + OMAP24XX_GPIO_OE); |
6d62e216 | 1546 | __raw_writel(bank->context.leveldetect0, |
40c670f0 | 1547 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
6d62e216 | 1548 | __raw_writel(bank->context.leveldetect1, |
40c670f0 | 1549 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); |
6d62e216 | 1550 | __raw_writel(bank->context.risingdetect, |
40c670f0 | 1551 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
6d62e216 | 1552 | __raw_writel(bank->context.fallingdetect, |
40c670f0 | 1553 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
6d62e216 | 1554 | __raw_writel(bank->context.dataout, |
40c670f0 | 1555 | bank->base + OMAP24XX_GPIO_DATAOUT); |
40c670f0 RN |
1556 | } |
1557 | } | |
1558 | #endif | |
1559 | ||
77640aab VC |
1560 | static struct platform_driver omap_gpio_driver = { |
1561 | .probe = omap_gpio_probe, | |
1562 | .driver = { | |
1563 | .name = "omap_gpio", | |
1564 | }, | |
1565 | }; | |
1566 | ||
5e1c5ff4 | 1567 | /* |
77640aab VC |
1568 | * gpio driver register needs to be done before |
1569 | * machine_init functions access gpio APIs. | |
1570 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1571 | */ |
77640aab | 1572 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1573 | { |
77640aab | 1574 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1575 | } |
77640aab | 1576 | postcore_initcall(omap_gpio_drv_reg); |
5e1c5ff4 | 1577 | |
92105bb7 TL |
1578 | static int __init omap_gpio_sysinit(void) |
1579 | { | |
11a78b79 | 1580 | |
140455fa | 1581 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd RW |
1582 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) |
1583 | register_syscore_ops(&omap_gpio_syscore_ops); | |
92105bb7 TL |
1584 | #endif |
1585 | ||
3c437ffd | 1586 | return 0; |
92105bb7 TL |
1587 | } |
1588 | ||
92105bb7 | 1589 | arch_initcall(omap_gpio_sysinit); |