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gpio/omap: remove MPUIO handling from _clear_gpio_irqbank()
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
140455fa 37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 38 u32 suspend_wakeup;
39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
5e1c5ff4
TL		 57};
58
a8eb7ca0 59#ifdef CONFIG_ARCH_OMAP3
40c670f0 60struct omap3_gpio_regs {
40c670f0
RN		 61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
5492fb1a
SMK		 71};
72
40c670f0 73static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 74#endif
75
77640aab
VC		 76/*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80static struct gpio_bank *gpio_bank;
44169075 81
77640aab 82static int bank_width;
44169075 83
c95d10bc
VC		 84/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count;
5e1c5ff4
TL		 86
87static inline struct gpio_bank *get_gpio_bank(int gpio)
88{
6e60e79a 89 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
5e1c5ff4
TL		 94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
56739a69 99 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
92105bb7
TL		 104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
44169075 106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 107 return &gpio_bank[gpio >> 5];
e031ab23
DB		 108 BUG();
109 return NULL;
5e1c5ff4
TL		 110}
111
112static inline int get_gpio_index(int gpio)
113{
56739a69 114 if (cpu_is_omap7xx())
5e1c5ff4 115 return gpio & 0x1f;
92105bb7
TL		 116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
44169075 118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 119 return gpio & 0x1f;
92105bb7 120 return gpio & 0x0f;
5e1c5ff4
TL		 121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
d11ac979 127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 129 return -1;
130 return 0;
131 }
6e60e79a 132 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 133 return 0;
5e1c5ff4
TL		 134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
56739a69 136 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 137 return 0;
25d6f630
TL		 138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
92105bb7 141 return 0;
44169075 142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 143 return 0;
5e1c5ff4
TL		 144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
d32b20fc 149 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{
92105bb7 159 void __iomem *reg = bank->base;
5e1c5ff4
TL		 160 u32 l;
161
162 switch (bank->method) {
e5c56ed3 163#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 164 case METHOD_MPUIO:
5de62b86 165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
5e1c5ff4 166 break;
e5c56ed3
DB		 167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
e5c56ed3
DB		 172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
e5c56ed3 177#endif
b718aa81 178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 181 break;
182#endif
a8eb7ca0 183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
78a1a6d3
SR		 187#endif
188#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 189 case METHOD_GPIO_44XX:
78a1a6d3
SR		 190 reg += OMAP4_GPIO_OE;
191 break;
e5c56ed3
DB		 192#endif
193 default:
194 WARN_ON(1);
195 return;
5e1c5ff4
TL		 196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203}
204
5e1c5ff4
TL		 205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206{
92105bb7 207 void __iomem *reg = bank->base;
5e1c5ff4
TL		 208 u32 l = 0;
209
210 switch (bank->method) {
e5c56ed3 211#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 212 case METHOD_MPUIO:
5de62b86 213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
5e1c5ff4
TL		 214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
e5c56ed3
DB		 220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
e5c56ed3
DB		 230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
e5c56ed3 239#endif
b718aa81 240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
a8eb7ca0 250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
78a1a6d3
SR		 258#endif
259#ifdef CONFIG_ARCH_OMAP4
3f1686a9 260 case METHOD_GPIO_44XX:
78a1a6d3
SR		 261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
e5c56ed3 267#endif
5e1c5ff4 268 default:
e5c56ed3 269 WARN_ON(1);
5e1c5ff4
TL		 270 return;
271 }
272 __raw_writel(l, reg);
273}
274
b37c45b8 275static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 276{
92105bb7 277 void __iomem *reg;
5e1c5ff4
TL		 278
279 if (check_gpio(gpio) < 0)
e5c56ed3 280 return -EINVAL;
5e1c5ff4
TL		 281 reg = bank->base;
282 switch (bank->method) {
e5c56ed3 283#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 284 case METHOD_MPUIO:
5de62b86 285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
5e1c5ff4 286 break;
e5c56ed3
DB		 287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
e5c56ed3
DB		 292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
e5c56ed3 297#endif
b718aa81 298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 301 break;
302#endif
a8eb7ca0 303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
78a1a6d3
SR		 307#endif
308#ifdef CONFIG_ARCH_OMAP4
3f1686a9 309 case METHOD_GPIO_44XX:
78a1a6d3
SR		 310 reg += OMAP4_GPIO_DATAIN;
311 break;
e5c56ed3 312#endif
5e1c5ff4 313 default:
e5c56ed3 314 return -EINVAL;
5e1c5ff4 315 }
92105bb7
TL		 316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 318}
319
b37c45b8
RQ		 320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321{
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329#ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
5de62b86 331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
b37c45b8
RQ		 332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
b718aa81 344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 347 break;
348#endif
9f096868 349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
9f096868
C		 353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
b37c45b8
RQ		 358#endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364}
365
92105bb7
TL		 366#define MOD_REG_BIT(reg, bit_mask, set) \
367do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372} while(0)
373
168ef3d9
FB		 374/**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385{
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
77640aab
VC		 390 if (!bank->dbck_flag)
391 return;
392
168ef3d9
FB		 393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
77640aab 402 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
77640aab 410 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
77640aab 419 clk_enable(bank->dbck);
168ef3d9
FB		 420 } else {
421 val &= ~l;
77640aab 422 clk_disable(bank->dbck);
168ef3d9 423 }
f7ec0b0b 424 bank->dbck_enable_mask = val;
168ef3d9
FB		 425
426 __raw_writel(val, reg);
427}
428
140455fa 429#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 430static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
5e1c5ff4 432{
3ac4fa99 433 void __iomem *base = bank->base;
92105bb7
TL		 434 u32 gpio_bit = 1 << gpio;
435
78a1a6d3
SR		 436 if (cpu_is_omap44xx()) {
437 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
438 trigger & IRQ_TYPE_LEVEL_LOW);
439 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
440 trigger & IRQ_TYPE_LEVEL_HIGH);
441 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
442 trigger & IRQ_TYPE_EDGE_RISING);
443 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
444 trigger & IRQ_TYPE_EDGE_FALLING);
445 } else {
446 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
447 trigger & IRQ_TYPE_LEVEL_LOW);
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
449 trigger & IRQ_TYPE_LEVEL_HIGH);
450 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
451 trigger & IRQ_TYPE_EDGE_RISING);
452 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
453 trigger & IRQ_TYPE_EDGE_FALLING);
454 }
3ac4fa99 455 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 456 if (cpu_is_omap44xx()) {
0622b25b
CC		 457 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
458 trigger != 0);
78a1a6d3 459 } else {
699117a6
CW		 460 /*
461 * GPIO wakeup request can only be generated on edge
462 * transitions
463 */
464 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 465 __raw_writel(1 << gpio, bank->base
5eb3bb9c 466 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 467 else
468 __raw_writel(1 << gpio, bank->base
5eb3bb9c 469 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 470 }
a118b5f3
TK		 471 }
472 /* This part needs to be executed always for OMAP34xx */
473 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 474 /*
475 * Log the edge gpio and manually trigger the IRQ
476 * after resume if the input level changes
477 * to avoid irq lost during PER RET/OFF mode
478 * Applies for omap2 non-wakeup gpio and all omap3 gpios
479 */
480 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 481 bank->enabled_non_wakeup_gpios |= gpio_bit;
482 else
483 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
484 }
5eb3bb9c 485
78a1a6d3
SR		 486 if (cpu_is_omap44xx()) {
487 bank->level_mask =
488 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
489 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
490 } else {
491 bank->level_mask =
492 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
493 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
494 }
92105bb7 495}
3ac4fa99 496#endif
92105bb7 497
9198bcd3 498#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 499/*
500 * This only applies to chips that can't do both rising and falling edge
501 * detection at once. For all other chips, this function is a noop.
502 */
503static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
504{
505 void __iomem *reg = bank->base;
506 u32 l = 0;
507
508 switch (bank->method) {
4318f36b 509 case METHOD_MPUIO:
5de62b86 510 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 511 break;
4318f36b
CM		 512#ifdef CONFIG_ARCH_OMAP15XX
513 case METHOD_GPIO_1510:
514 reg += OMAP1510_GPIO_INT_CONTROL;
515 break;
516#endif
517#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
518 case METHOD_GPIO_7XX:
519 reg += OMAP7XX_GPIO_INT_CONTROL;
520 break;
521#endif
522 default:
523 return;
524 }
525
526 l = __raw_readl(reg);
527 if ((l >> gpio) & 1)
528 l &= ~(1 << gpio);
529 else
530 l |= 1 << gpio;
531
532 __raw_writel(l, reg);
533}
9198bcd3 534#endif
4318f36b 535
92105bb7
TL		 536static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
537{
538 void __iomem *reg = bank->base;
539 u32 l = 0;
5e1c5ff4
TL		 540
541 switch (bank->method) {
e5c56ed3 542#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 543 case METHOD_MPUIO:
5de62b86 544 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 545 l = __raw_readl(reg);
29501577 546 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 547 bank->toggle_mask |= 1 << gpio;
6cab4860 548 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 549 l |= 1 << gpio;
6cab4860 550 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 551 l &= ~(1 << gpio);
92105bb7
TL		 552 else
553 goto bad;
5e1c5ff4 554 break;
e5c56ed3
DB		 555#endif
556#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 557 case METHOD_GPIO_1510:
558 reg += OMAP1510_GPIO_INT_CONTROL;
559 l = __raw_readl(reg);
29501577 560 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 561 bank->toggle_mask |= 1 << gpio;
6cab4860 562 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 563 l |= 1 << gpio;
6cab4860 564 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 565 l &= ~(1 << gpio);
92105bb7
TL		 566 else
567 goto bad;
5e1c5ff4 568 break;
e5c56ed3 569#endif
3ac4fa99 570#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 571 case METHOD_GPIO_1610:
5e1c5ff4
TL		 572 if (gpio & 0x08)
573 reg += OMAP1610_GPIO_EDGE_CTRL2;
574 else
575 reg += OMAP1610_GPIO_EDGE_CTRL1;
576 gpio &= 0x07;
577 l = __raw_readl(reg);
578 l &= ~(3 << (gpio << 1));
6cab4860 579 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 580 l |= 2 << (gpio << 1);
6cab4860 581 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 582 l |= 1 << (gpio << 1);
3ac4fa99
JY		 583 if (trigger)
584 /* Enable wake-up during idle for dynamic tick */
585 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
586 else
587 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 588 break;
3ac4fa99 589#endif
b718aa81 590#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 591 case METHOD_GPIO_7XX:
592 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 593 l = __raw_readl(reg);
29501577 594 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 595 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 596 if (trigger & IRQ_TYPE_EDGE_RISING)
597 l |= 1 << gpio;
598 else if (trigger & IRQ_TYPE_EDGE_FALLING)
599 l &= ~(1 << gpio);
600 else
601 goto bad;
602 break;
603#endif
140455fa 604#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 605 case METHOD_GPIO_24XX:
3f1686a9 606 case METHOD_GPIO_44XX:
3ac4fa99 607 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 608 return 0;
3ac4fa99 609#endif
5e1c5ff4 610 default:
92105bb7 611 goto bad;
5e1c5ff4 612 }
92105bb7
TL		 613 __raw_writel(l, reg);
614 return 0;
615bad:
616 return -EINVAL;
5e1c5ff4
TL		 617}
618
e9191028 619static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 620{
621 struct gpio_bank *bank;
92105bb7
TL		 622 unsigned gpio;
623 int retval;
a6472533 624 unsigned long flags;
92105bb7 625
e9191028
LB		 626 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
627 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 628 else
e9191028 629 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4
TL		 630
631 if (check_gpio(gpio) < 0)
92105bb7
TL		 632 return -EINVAL;
633
e5c56ed3 634 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 635 return -EINVAL;
e5c56ed3
DB		 636
637 /* OMAP1 allows only only edge triggering */
5492fb1a 638 if (!cpu_class_is_omap2()
e5c56ed3 639 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 640 return -EINVAL;
641
e9191028 642 bank = irq_data_get_irq_chip_data(d);
a6472533 643 spin_lock_irqsave(&bank->lock, flags);
92105bb7 644 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
a6472533 645 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 646
647 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 648 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 649 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 650 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 651
92105bb7 652 return retval;
5e1c5ff4
TL		 653}
654
655static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656{
92105bb7 657 void __iomem *reg = bank->base;
5e1c5ff4
TL		 658
659 switch (bank->method) {
e5c56ed3 660#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 661 case METHOD_GPIO_1510:
662 reg += OMAP1510_GPIO_INT_STATUS;
663 break;
e5c56ed3
DB		 664#endif
665#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 666 case METHOD_GPIO_1610:
667 reg += OMAP1610_GPIO_IRQSTATUS1;
668 break;
e5c56ed3 669#endif
b718aa81 670#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 671 case METHOD_GPIO_7XX:
672 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 673 break;
674#endif
a8eb7ca0 675#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 676 case METHOD_GPIO_24XX:
677 reg += OMAP24XX_GPIO_IRQSTATUS1;
678 break;
78a1a6d3
SR		 679#endif
680#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 681 case METHOD_GPIO_44XX:
78a1a6d3
SR		 682 reg += OMAP4_GPIO_IRQSTATUS0;
683 break;
e5c56ed3 684#endif
5e1c5ff4 685 default:
e5c56ed3 686 WARN_ON(1);
5e1c5ff4
TL		 687 return;
688 }
689 __raw_writel(gpio_mask, reg);
bee7930f
HD		 690
691 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 692 if (cpu_is_omap24xx() || cpu_is_omap34xx())
693 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
694 else if (cpu_is_omap44xx())
695 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
696
df3c8517 697 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx())
bedfd154
RQ		 698 __raw_writel(gpio_mask, reg);
699
700 /* Flush posted write for the irq status to avoid spurious interrupts */
701 __raw_readl(reg);
5e1c5ff4
TL		 702}
703
704static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
705{
706 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
707}
708
ea6dedd7
ID		 709static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
710{
711 void __iomem *reg = bank->base;
99c47707
ID		 712 int inv = 0;
713 u32 l;
714 u32 mask;
ea6dedd7
ID		 715
716 switch (bank->method) {
e5c56ed3 717#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 718 case METHOD_MPUIO:
5de62b86 719 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707
ID		 720 mask = 0xffff;
721 inv = 1;
ea6dedd7 722 break;
e5c56ed3
DB		 723#endif
724#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 725 case METHOD_GPIO_1510:
726 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 727 mask = 0xffff;
728 inv = 1;
ea6dedd7 729 break;
e5c56ed3
DB		 730#endif
731#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 732 case METHOD_GPIO_1610:
733 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 734 mask = 0xffff;
ea6dedd7 735 break;
e5c56ed3 736#endif
b718aa81 737#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 738 case METHOD_GPIO_7XX:
739 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 740 mask = 0xffffffff;
741 inv = 1;
742 break;
743#endif
a8eb7ca0 744#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 745 case METHOD_GPIO_24XX:
746 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 747 mask = 0xffffffff;
ea6dedd7 748 break;
78a1a6d3
SR		 749#endif
750#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 751 case METHOD_GPIO_44XX:
78a1a6d3
SR		 752 reg += OMAP4_GPIO_IRQSTATUSSET0;
753 mask = 0xffffffff;
754 break;
e5c56ed3 755#endif
ea6dedd7 756 default:
e5c56ed3 757 WARN_ON(1);
ea6dedd7
ID		 758 return 0;
759 }
760
99c47707
ID		 761 l = __raw_readl(reg);
762 if (inv)
763 l = ~l;
764 l &= mask;
765 return l;
ea6dedd7
ID		 766}
767
5e1c5ff4
TL		 768static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
769{
92105bb7 770 void __iomem *reg = bank->base;
5e1c5ff4
TL		 771 u32 l;
772
773 switch (bank->method) {
e5c56ed3 774#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 775 case METHOD_MPUIO:
5de62b86 776 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 777 l = __raw_readl(reg);
778 if (enable)
779 l &= ~(gpio_mask);
780 else
781 l |= gpio_mask;
782 break;
e5c56ed3
DB		 783#endif
784#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 785 case METHOD_GPIO_1510:
786 reg += OMAP1510_GPIO_INT_MASK;
787 l = __raw_readl(reg);
788 if (enable)
789 l &= ~(gpio_mask);
790 else
791 l |= gpio_mask;
792 break;
e5c56ed3
DB		 793#endif
794#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 795 case METHOD_GPIO_1610:
796 if (enable)
797 reg += OMAP1610_GPIO_SET_IRQENABLE1;
798 else
799 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
800 l = gpio_mask;
801 break;
e5c56ed3 802#endif
b718aa81 803#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 804 case METHOD_GPIO_7XX:
805 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 806 l = __raw_readl(reg);
807 if (enable)
808 l &= ~(gpio_mask);
809 else
810 l |= gpio_mask;
811 break;
812#endif
a8eb7ca0 813#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 814 case METHOD_GPIO_24XX:
815 if (enable)
816 reg += OMAP24XX_GPIO_SETIRQENABLE1;
817 else
818 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
819 l = gpio_mask;
820 break;
78a1a6d3
SR		 821#endif
822#ifdef CONFIG_ARCH_OMAP4
3f1686a9 823 case METHOD_GPIO_44XX:
78a1a6d3
SR		 824 if (enable)
825 reg += OMAP4_GPIO_IRQSTATUSSET0;
826 else
827 reg += OMAP4_GPIO_IRQSTATUSCLR0;
828 l = gpio_mask;
829 break;
e5c56ed3 830#endif
5e1c5ff4 831 default:
e5c56ed3 832 WARN_ON(1);
5e1c5ff4
TL		 833 return;
834 }
835 __raw_writel(l, reg);
836}
837
838static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
839{
840 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
841}
842
92105bb7
TL		 843/*
844 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
845 * 1510 does not seem to have a wake-up register. If JTAG is connected
846 * to the target, system will wake up always on GPIO events. While
847 * system is running all registered GPIO interrupts need to have wake-up
848 * enabled. When system is suspended, only selected GPIO interrupts need
849 * to have wake-up enabled.
850 */
851static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
852{
4cc6420c 853 unsigned long uninitialized_var(flags);
a6472533 854
92105bb7 855 switch (bank->method) {
3ac4fa99 856#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 857 case METHOD_MPUIO:
92105bb7 858 case METHOD_GPIO_1610:
a6472533 859 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 860 if (enable)
92105bb7 861 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 862 else
92105bb7 863 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 864 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 865 return 0;
3ac4fa99 866#endif
140455fa 867#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 868 case METHOD_GPIO_24XX:
3f1686a9 869 case METHOD_GPIO_44XX:
11a78b79
DB		 870 if (bank->non_wakeup_gpios & (1 << gpio)) {
871 printk(KERN_ERR "Unable to modify wakeup on "
872 "non-wakeup GPIO%d\n",
873 (bank - gpio_bank) * 32 + gpio);
874 return -EINVAL;
875 }
a6472533 876 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 877 if (enable)
3ac4fa99 878 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 879 else
3ac4fa99 880 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 881 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 882 return 0;
883#endif
92105bb7
TL		 884 default:
885 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
886 bank->method);
887 return -EINVAL;
888 }
889}
890
4196dd6b
TL		 891static void _reset_gpio(struct gpio_bank *bank, int gpio)
892{
893 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
894 _set_gpio_irqenable(bank, gpio, 0);
895 _clear_gpio_irqstatus(bank, gpio);
6cab4860 896 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 897}
898
92105bb7 899/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 900static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 901{
e9191028 902 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 903 struct gpio_bank *bank;
904 int retval;
905
906 if (check_gpio(gpio) < 0)
907 return -ENODEV;
e9191028 908 bank = irq_data_get_irq_chip_data(d);
92105bb7 909 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 910
911 return retval;
912}
913
3ff164e1 914static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 915{
3ff164e1 916 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 917 unsigned long flags;
52e31344 918
a6472533 919 spin_lock_irqsave(&bank->lock, flags);
92105bb7 920
4196dd6b
TL		 921 /* Set trigger to none. You need to enable the desired trigger with
922 * request_irq() or set_irq_type().
923 */
3ff164e1 924 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 925
1a8bfa1e 926#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 927 if (bank->method == METHOD_GPIO_1510) {
92105bb7 928 void __iomem *reg;
5e1c5ff4 929
92105bb7 930 /* Claim the pin for MPU */
5e1c5ff4 931 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 932 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 933 }
934#endif
058af1ea
C		 935 if (!cpu_class_is_omap1()) {
936 if (!bank->mod_usage) {
9f096868 937 void __iomem *reg = bank->base;
058af1ea 938 u32 ctrl;
9f096868
C		 939
940 if (cpu_is_omap24xx() || cpu_is_omap34xx())
941 reg += OMAP24XX_GPIO_CTRL;
942 else if (cpu_is_omap44xx())
943 reg += OMAP4_GPIO_CTRL;
944 ctrl = __raw_readl(reg);
058af1ea 945 /* Module is enabled, clocks are not gated */
9f096868
C		 946 ctrl &= 0xFFFFFFFE;
947 __raw_writel(ctrl, reg);
058af1ea
C		 948 }
949 bank->mod_usage |= 1 << offset;
950 }
a6472533 951 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 952
953 return 0;
954}
955
3ff164e1 956static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 957{
3ff164e1 958 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 959 unsigned long flags;
5e1c5ff4 960
a6472533 961 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 962#ifdef CONFIG_ARCH_OMAP16XX
963 if (bank->method == METHOD_GPIO_1610) {
964 /* Disable wake-up during idle for dynamic tick */
965 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 966 __raw_writel(1 << offset, reg);
92105bb7
TL		 967 }
968#endif
9f096868
C		 969#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
970 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 971 /* Disable wake-up during idle for dynamic tick */
972 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 973 __raw_writel(1 << offset, reg);
92105bb7 974 }
9f096868
C		 975#endif
976#ifdef CONFIG_ARCH_OMAP4
977 if (bank->method == METHOD_GPIO_44XX) {
978 /* Disable wake-up during idle for dynamic tick */
979 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
980 __raw_writel(1 << offset, reg);
981 }
92105bb7 982#endif
058af1ea
C		 983 if (!cpu_class_is_omap1()) {
984 bank->mod_usage &= ~(1 << offset);
985 if (!bank->mod_usage) {
9f096868 986 void __iomem *reg = bank->base;
058af1ea 987 u32 ctrl;
9f096868
C		 988
989 if (cpu_is_omap24xx() || cpu_is_omap34xx())
990 reg += OMAP24XX_GPIO_CTRL;
991 else if (cpu_is_omap44xx())
992 reg += OMAP4_GPIO_CTRL;
993 ctrl = __raw_readl(reg);
058af1ea
C		 994 /* Module is disabled, clocks are gated */
995 ctrl |= 1;
9f096868 996 __raw_writel(ctrl, reg);
058af1ea
C		 997 }
998 }
3ff164e1 999 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1000 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1001}
1002
1003/*
1004 * We need to unmask the GPIO bank interrupt as soon as possible to
1005 * avoid missing GPIO interrupts for other lines in the bank.
1006 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1007 * in the bank to avoid missing nested interrupts for a GPIO line.
1008 * If we wait to unmask individual GPIO lines in the bank after the
1009 * line's interrupt handler has been run, we may miss some nested
1010 * interrupts.
1011 */
10dd5ce2 1012static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1013{
92105bb7 1014 void __iomem *isr_reg = NULL;
5e1c5ff4 1015 u32 isr;
4318f36b 1016 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1017 struct gpio_bank *bank;
ea6dedd7
ID		 1018 u32 retrigger = 0;
1019 int unmasked = 0;
ee144182 1020 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 1021
ee144182 1022 chained_irq_enter(chip, desc);
5e1c5ff4 1023
6845664a 1024 bank = irq_get_handler_data(irq);
e5c56ed3 1025#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 1026 if (bank->method == METHOD_MPUIO)
5de62b86
TL		 1027 isr_reg = bank->base +
1028 OMAP_MPUIO_GPIO_INT / bank->stride;
e5c56ed3 1029#endif
1a8bfa1e 1030#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1031 if (bank->method == METHOD_GPIO_1510)
1032 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1033#endif
1034#if defined(CONFIG_ARCH_OMAP16XX)
1035 if (bank->method == METHOD_GPIO_1610)
1036 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1037#endif
b718aa81 1038#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1039 if (bank->method == METHOD_GPIO_7XX)
1040 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1041#endif
a8eb7ca0 1042#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1043 if (bank->method == METHOD_GPIO_24XX)
1044 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1045#endif
1046#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1047 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1048 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1049#endif
b1cc4c55
EK		 1050
1051 if (WARN_ON(!isr_reg))
1052 goto exit;
1053
92105bb7 1054 while(1) {
6e60e79a 1055 u32 isr_saved, level_mask = 0;
ea6dedd7 1056 u32 enabled;
6e60e79a 1057
ea6dedd7
ID		 1058 enabled = _get_gpio_irqbank_mask(bank);
1059 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1060
1061 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1062 isr &= 0x0000ffff;
1063
5492fb1a 1064 if (cpu_class_is_omap2()) {
b144ff6f 1065 level_mask = bank->level_mask & enabled;
ea6dedd7 1066 }
6e60e79a
TL		 1067
1068 /* clear edge sensitive interrupts before handler(s) are
1069 called so that we don't miss any interrupt occurred while
1070 executing them */
1071 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1072 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1073 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1074
1075 /* if there is only edge sensitive GPIO pin interrupts
1076 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1077 if (!level_mask && !unmasked) {
1078 unmasked = 1;
ee144182 1079 chained_irq_exit(chip, desc);
ea6dedd7 1080 }
92105bb7 1081
ea6dedd7
ID		 1082 isr |= retrigger;
1083 retrigger = 0;
92105bb7
TL		 1084 if (!isr)
1085 break;
1086
1087 gpio_irq = bank->virtual_irq_start;
1088 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1089 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1090
92105bb7
TL		 1091 if (!(isr & 1))
1092 continue;
29454dde 1093
4318f36b
CM		 1094#ifdef CONFIG_ARCH_OMAP1
1095 /*
1096 * Some chips can't respond to both rising and falling
1097 * at the same time. If this irq was requested with
1098 * both flags, we need to flip the ICR data for the IRQ
1099 * to respond to the IRQ for the opposite direction.
1100 * This will be indicated in the bank toggle_mask.
1101 */
1102 if (bank->toggle_mask & (1 << gpio_index))
1103 _toggle_gpio_edge_triggering(bank, gpio_index);
1104#endif
1105
d8aa0251 1106 generic_handle_irq(gpio_irq);
92105bb7 1107 }
1a8bfa1e 1108 }
ea6dedd7
ID		 1109 /* if bank has any level sensitive GPIO pin interrupt
1110 configured, we must unmask the bank interrupt only after
1111 handler(s) are executed in order to avoid spurious bank
1112 interrupt */
b1cc4c55 1113exit:
ea6dedd7 1114 if (!unmasked)
ee144182 1115 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 1116}
1117
e9191028 1118static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 1119{
e9191028
LB		 1120 unsigned int gpio = d->irq - IH_GPIO_BASE;
1121 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 1122 unsigned long flags;
4196dd6b 1123
85ec7b97 1124 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 1125 _reset_gpio(bank, gpio);
85ec7b97 1126 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 1127}
1128
e9191028 1129static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 1130{
e9191028
LB		 1131 unsigned int gpio = d->irq - IH_GPIO_BASE;
1132 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1133
1134 _clear_gpio_irqstatus(bank, gpio);
1135}
1136
e9191028 1137static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 1138{
e9191028
LB		 1139 unsigned int gpio = d->irq - IH_GPIO_BASE;
1140 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 1141 unsigned long flags;
5e1c5ff4 1142
85ec7b97 1143 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 1144 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1145 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
85ec7b97 1146 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1147}
1148
e9191028 1149static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 1150{
e9191028
LB		 1151 unsigned int gpio = d->irq - IH_GPIO_BASE;
1152 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
b144ff6f 1153 unsigned int irq_mask = 1 << get_gpio_index(gpio);
8c04a176 1154 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 1155 unsigned long flags;
55b6019a 1156
85ec7b97 1157 spin_lock_irqsave(&bank->lock, flags);
55b6019a
KH		 1158 if (trigger)
1159 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1160
1161 /* For level-triggered GPIOs, the clearing must be done after
1162 * the HW source is cleared, thus after the handler has run */
1163 if (bank->level_mask & irq_mask) {
1164 _set_gpio_irqenable(bank, gpio, 0);
1165 _clear_gpio_irqstatus(bank, gpio);
1166 }
5e1c5ff4 1167
4de8c75b 1168 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 1169 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1170}
1171
e5c56ed3
DB		 1172static struct irq_chip gpio_irq_chip = {
1173 .name = "GPIO",
e9191028
LB		 1174 .irq_shutdown = gpio_irq_shutdown,
1175 .irq_ack = gpio_ack_irq,
1176 .irq_mask = gpio_mask_irq,
1177 .irq_unmask = gpio_unmask_irq,
1178 .irq_set_type = gpio_irq_type,
1179 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 1180};
1181
1182/*---------------------------------------------------------------------*/
1183
1184#ifdef CONFIG_ARCH_OMAP1
1185
1186/* MPUIO uses the always-on 32k clock */
1187
e9191028 1188static void mpuio_ack_irq(struct irq_data *d)
5e1c5ff4
TL		 1189{
1190 /* The ISR is reset automatically, so do nothing here. */
1191}
1192
e9191028 1193static void mpuio_mask_irq(struct irq_data *d)
5e1c5ff4 1194{
e9191028
LB		 1195 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1196 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1197
1198 _set_gpio_irqenable(bank, gpio, 0);
1199}
1200
e9191028 1201static void mpuio_unmask_irq(struct irq_data *d)
5e1c5ff4 1202{
e9191028
LB		 1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1205
1206 _set_gpio_irqenable(bank, gpio, 1);
1207}
1208
e5c56ed3
DB		 1209static struct irq_chip mpuio_irq_chip = {
1210 .name = "MPUIO",
e9191028
LB		 1211 .irq_ack = mpuio_ack_irq,
1212 .irq_mask = mpuio_mask_irq,
1213 .irq_unmask = mpuio_unmask_irq,
1214 .irq_set_type = gpio_irq_type,
11a78b79
DB		 1215#ifdef CONFIG_ARCH_OMAP16XX
1216 /* REVISIT: assuming only 16xx supports MPUIO wake events */
e9191028 1217 .irq_set_wake = gpio_wake_enable,
11a78b79 1218#endif
5e1c5ff4
TL		 1219};
1220
e5c56ed3
DB		 1221
1222#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1223
11a78b79
DB		 1224
1225#ifdef CONFIG_ARCH_OMAP16XX
1226
1227#include <linux/platform_device.h>
1228
79ee031f 1229static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1230{
79ee031f 1231 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1232 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1233 void __iomem *mask_reg = bank->base +
1234 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1235 unsigned long flags;
11a78b79 1236
a6472533 1237 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1238 bank->saved_wakeup = __raw_readl(mask_reg);
1239 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1240 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1241
1242 return 0;
1243}
1244
79ee031f 1245static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1246{
79ee031f 1247 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1248 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1249 void __iomem *mask_reg = bank->base +
1250 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1251 unsigned long flags;
11a78b79 1252
a6472533 1253 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1254 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1255 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1256
1257 return 0;
1258}
1259
47145210 1260static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1261 .suspend_noirq = omap_mpuio_suspend_noirq,
1262 .resume_noirq = omap_mpuio_resume_noirq,
1263};
1264
3c437ffd 1265/* use platform_driver for this. */
11a78b79 1266static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1267 .driver = {
1268 .name = "mpuio",
79ee031f 1269 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1270 },
1271};
1272
1273static struct platform_device omap_mpuio_device = {
1274 .name = "mpuio",
1275 .id = -1,
1276 .dev = {
1277 .driver = &omap_mpuio_driver.driver,
1278 }
1279 /* could list the /proc/iomem resources */
1280};
1281
1282static inline void mpuio_init(void)
1283{
77640aab
VC		 1284 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1285 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1286
11a78b79
DB		 1287 if (platform_driver_register(&omap_mpuio_driver) == 0)
1288 (void) platform_device_register(&omap_mpuio_device);
1289}
1290
1291#else
1292static inline void mpuio_init(void) {}
1293#endif /* 16xx */
1294
e5c56ed3
DB		 1295#else
1296
1297extern struct irq_chip mpuio_irq_chip;
1298
1299#define bank_is_mpuio(bank) 0
11a78b79 1300static inline void mpuio_init(void) {}
e5c56ed3
DB		 1301
1302#endif
1303
1304/*---------------------------------------------------------------------*/
5e1c5ff4 1305
52e31344
DB		 1306/* REVISIT these are stupid implementations! replace by ones that
1307 * don't switch on METHOD_* and which mostly avoid spinlocks
1308 */
1309
1310static int gpio_input(struct gpio_chip *chip, unsigned offset)
1311{
1312 struct gpio_bank *bank;
1313 unsigned long flags;
1314
1315 bank = container_of(chip, struct gpio_bank, chip);
1316 spin_lock_irqsave(&bank->lock, flags);
1317 _set_gpio_direction(bank, offset, 1);
1318 spin_unlock_irqrestore(&bank->lock, flags);
1319 return 0;
1320}
1321
b37c45b8
RQ		 1322static int gpio_is_input(struct gpio_bank *bank, int mask)
1323{
1324 void __iomem *reg = bank->base;
1325
1326 switch (bank->method) {
1327 case METHOD_MPUIO:
5de62b86 1328 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
b37c45b8
RQ		 1329 break;
1330 case METHOD_GPIO_1510:
1331 reg += OMAP1510_GPIO_DIR_CONTROL;
1332 break;
1333 case METHOD_GPIO_1610:
1334 reg += OMAP1610_GPIO_DIRECTION;
1335 break;
7c006926
AB		 1336 case METHOD_GPIO_7XX:
1337 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1338 break;
1339 case METHOD_GPIO_24XX:
1340 reg += OMAP24XX_GPIO_OE;
1341 break;
9f096868
C		 1342 case METHOD_GPIO_44XX:
1343 reg += OMAP4_GPIO_OE;
1344 break;
1345 default:
1346 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1347 return -EINVAL;
b37c45b8
RQ		 1348 }
1349 return __raw_readl(reg) & mask;
1350}
1351
52e31344
DB		 1352static int gpio_get(struct gpio_chip *chip, unsigned offset)
1353{
b37c45b8
RQ		 1354 struct gpio_bank *bank;
1355 void __iomem *reg;
1356 int gpio;
1357 u32 mask;
1358
1359 gpio = chip->base + offset;
1360 bank = get_gpio_bank(gpio);
1361 reg = bank->base;
1362 mask = 1 << get_gpio_index(gpio);
1363
1364 if (gpio_is_input(bank, mask))
1365 return _get_gpio_datain(bank, gpio);
1366 else
1367 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1368}
1369
1370static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1371{
1372 struct gpio_bank *bank;
1373 unsigned long flags;
1374
1375 bank = container_of(chip, struct gpio_bank, chip);
1376 spin_lock_irqsave(&bank->lock, flags);
1377 _set_gpio_dataout(bank, offset, value);
1378 _set_gpio_direction(bank, offset, 0);
1379 spin_unlock_irqrestore(&bank->lock, flags);
1380 return 0;
1381}
1382
168ef3d9
FB		 1383static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1384 unsigned debounce)
1385{
1386 struct gpio_bank *bank;
1387 unsigned long flags;
1388
1389 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1390
1391 if (!bank->dbck) {
1392 bank->dbck = clk_get(bank->dev, "dbclk");
1393 if (IS_ERR(bank->dbck))
1394 dev_err(bank->dev, "Could not get gpio dbck\n");
1395 }
1396
168ef3d9
FB		 1397 spin_lock_irqsave(&bank->lock, flags);
1398 _set_gpio_debounce(bank, offset, debounce);
1399 spin_unlock_irqrestore(&bank->lock, flags);
1400
1401 return 0;
1402}
1403
52e31344
DB		 1404static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1405{
1406 struct gpio_bank *bank;
1407 unsigned long flags;
1408
1409 bank = container_of(chip, struct gpio_bank, chip);
1410 spin_lock_irqsave(&bank->lock, flags);
1411 _set_gpio_dataout(bank, offset, value);
1412 spin_unlock_irqrestore(&bank->lock, flags);
1413}
1414
a007b709
DB		 1415static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1416{
1417 struct gpio_bank *bank;
1418
1419 bank = container_of(chip, struct gpio_bank, chip);
1420 return bank->virtual_irq_start + offset;
1421}
1422
52e31344
DB		 1423/*---------------------------------------------------------------------*/
1424
9a748053 1425static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1426{
1427 u32 rev;
1428
9a748053
TL		 1429 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1430 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1431 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1432 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1433 else if (cpu_is_omap44xx())
9a748053 1434 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1435 else
1436 return;
1437
1438 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1439 (rev >> 4) & 0x0f, rev & 0x0f);
1440}
1441
8ba55c5c
DB		 1442/* This lock class tells lockdep that GPIO irqs are in a different
1443 * category than their parents, so it won't report false recursion.
1444 */
1445static struct lock_class_key gpio_lock_class;
1446
77640aab
VC		 1447static inline int init_gpio_info(struct platform_device *pdev)
1448{
1449 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1450 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1451 GFP_KERNEL);
1452 if (!gpio_bank) {
1453 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1454 return -ENOMEM;
1455 }
1456 return 0;
1457}
1458
1459/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1460static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1461{
1462 if (cpu_class_is_omap2()) {
1463 if (cpu_is_omap44xx()) {
1464 __raw_writel(0xffffffff, bank->base +
1465 OMAP4_GPIO_IRQSTATUSCLR0);
1466 __raw_writel(0x00000000, bank->base +
1467 OMAP4_GPIO_DEBOUNCENABLE);
1468 /* Initialize interface clk ungated, module enabled */
1469 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1470 } else if (cpu_is_omap34xx()) {
1471 __raw_writel(0x00000000, bank->base +
1472 OMAP24XX_GPIO_IRQENABLE1);
1473 __raw_writel(0xffffffff, bank->base +
1474 OMAP24XX_GPIO_IRQSTATUS1);
1475 __raw_writel(0x00000000, bank->base +
1476 OMAP24XX_GPIO_DEBOUNCE_EN);
1477
1478 /* Initialize interface clk ungated, module enabled */
1479 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1480 } else if (cpu_is_omap24xx()) {
1481 static const u32 non_wakeup_gpios[] = {
1482 0xe203ffc0, 0x08700040
1483 };
1484 if (id < ARRAY_SIZE(non_wakeup_gpios))
1485 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1486 }
1487 } else if (cpu_class_is_omap1()) {
1488 if (bank_is_mpuio(bank))
5de62b86
TL		 1489 __raw_writew(0xffff, bank->base +
1490 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1491 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1492 __raw_writew(0xffff, bank->base
1493 + OMAP1510_GPIO_INT_MASK);
1494 __raw_writew(0x0000, bank->base
1495 + OMAP1510_GPIO_INT_STATUS);
1496 }
1497 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1498 __raw_writew(0x0000, bank->base
1499 + OMAP1610_GPIO_IRQENABLE1);
1500 __raw_writew(0xffff, bank->base
1501 + OMAP1610_GPIO_IRQSTATUS1);
1502 __raw_writew(0x0014, bank->base
1503 + OMAP1610_GPIO_SYSCONFIG);
1504
1505 /*
1506 * Enable system clock for GPIO module.
1507 * The CAM_CLK_CTRL *is* really the right place.
1508 */
1509 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1510 ULPD_CAM_CLK_CTRL);
1511 }
1512 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1513 __raw_writel(0xffffffff, bank->base
1514 + OMAP7XX_GPIO_INT_MASK);
1515 __raw_writel(0x00000000, bank->base
1516 + OMAP7XX_GPIO_INT_STATUS);
1517 }
1518 }
1519}
1520
d52b31de 1521static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1522{
77640aab 1523 int j;
2fae7fbe
VC		 1524 static int gpio;
1525
2fae7fbe
VC		 1526 bank->mod_usage = 0;
1527 /*
1528 * REVISIT eventually switch from OMAP-specific gpio structs
1529 * over to the generic ones
1530 */
1531 bank->chip.request = omap_gpio_request;
1532 bank->chip.free = omap_gpio_free;
1533 bank->chip.direction_input = gpio_input;
1534 bank->chip.get = gpio_get;
1535 bank->chip.direction_output = gpio_output;
1536 bank->chip.set_debounce = gpio_debounce;
1537 bank->chip.set = gpio_set;
1538 bank->chip.to_irq = gpio_2irq;
1539 if (bank_is_mpuio(bank)) {
1540 bank->chip.label = "mpuio";
1541#ifdef CONFIG_ARCH_OMAP16XX
1542 bank->chip.dev = &omap_mpuio_device.dev;
1543#endif
1544 bank->chip.base = OMAP_MPUIO(0);
1545 } else {
1546 bank->chip.label = "gpio";
1547 bank->chip.base = gpio;
1548 gpio += bank_width;
1549 }
1550 bank->chip.ngpio = bank_width;
1551
1552 gpiochip_add(&bank->chip);
1553
1554 for (j = bank->virtual_irq_start;
1555 j < bank->virtual_irq_start + bank_width; j++) {
1475b85d 1556 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1557 irq_set_chip_data(j, bank);
2fae7fbe 1558 if (bank_is_mpuio(bank))
6845664a 1559 irq_set_chip(j, &mpuio_irq_chip);
2fae7fbe 1560 else
6845664a
TG		 1561 irq_set_chip(j, &gpio_irq_chip);
1562 irq_set_handler(j, handle_simple_irq);
2fae7fbe
VC		 1563 set_irq_flags(j, IRQF_VALID);
1564 }
6845664a
TG		 1565 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1566 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1567}
1568
77640aab 1569static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1570{
77640aab
VC		 1571 static int gpio_init_done;
1572 struct omap_gpio_platform_data *pdata;
1573 struct resource *res;
1574 int id;
5e1c5ff4
TL		 1575 struct gpio_bank *bank;
1576
77640aab
VC		 1577 if (!pdev->dev.platform_data)
1578 return -EINVAL;
5e1c5ff4 1579
77640aab 1580 pdata = pdev->dev.platform_data;
56a25641 1581
77640aab
VC		 1582 if (!gpio_init_done) {
1583 int ret;
5492fb1a 1584
77640aab
VC		 1585 ret = init_gpio_info(pdev);
1586 if (ret)
1587 return ret;
5492fb1a 1588 }
5492fb1a 1589
77640aab
VC		 1590 id = pdev->id;
1591 bank = &gpio_bank[id];
92105bb7 1592
77640aab
VC		 1593 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1594 if (unlikely(!res)) {
1595 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1596 return -ENODEV;
44169075 1597 }
5e1c5ff4 1598
77640aab
VC		 1599 bank->irq = res->start;
1600 bank->virtual_irq_start = pdata->virtual_irq_start;
1601 bank->method = pdata->bank_type;
1602 bank->dev = &pdev->dev;
1603 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1604 bank->stride = pdata->bank_stride;
77640aab 1605 bank_width = pdata->bank_width;
9f7065da 1606
77640aab 1607 spin_lock_init(&bank->lock);
9f7065da 1608
77640aab
VC		 1609 /* Static mapping, never released */
1610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1611 if (unlikely(!res)) {
1612 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1613 return -ENODEV;
1614 }
89db9482 1615
77640aab
VC		 1616 bank->base = ioremap(res->start, resource_size(res));
1617 if (!bank->base) {
1618 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1619 return -ENOMEM;
5e1c5ff4
TL		 1620 }
1621
77640aab
VC		 1622 pm_runtime_enable(bank->dev);
1623 pm_runtime_get_sync(bank->dev);
1624
1625 omap_gpio_mod_init(bank, id);
1626 omap_gpio_chip_init(bank);
9a748053 1627 omap_gpio_show_rev(bank);
9f7065da 1628
77640aab
VC		 1629 if (!gpio_init_done)
1630 gpio_init_done = 1;
1631
5e1c5ff4
TL		 1632 return 0;
1633}
1634
140455fa 1635#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1636static int omap_gpio_suspend(void)
92105bb7
TL		 1637{
1638 int i;
1639
5492fb1a 1640 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1641 return 0;
1642
1643 for (i = 0; i < gpio_bank_count; i++) {
1644 struct gpio_bank *bank = &gpio_bank[i];
1645 void __iomem *wake_status;
1646 void __iomem *wake_clear;
1647 void __iomem *wake_set;
a6472533 1648 unsigned long flags;
92105bb7
TL		 1649
1650 switch (bank->method) {
e5c56ed3 1651#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1652 case METHOD_GPIO_1610:
1653 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1654 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1655 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1656 break;
e5c56ed3 1657#endif
a8eb7ca0 1658#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1659 case METHOD_GPIO_24XX:
723fdb78 1660 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1661 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1662 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1663 break;
78a1a6d3
SR		 1664#endif
1665#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1666 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1667 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1668 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1669 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1670 break;
e5c56ed3 1671#endif
92105bb7
TL		 1672 default:
1673 continue;
1674 }
1675
a6472533 1676 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1677 bank->saved_wakeup = __raw_readl(wake_status);
1678 __raw_writel(0xffffffff, wake_clear);
1679 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1680 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1681 }
1682
1683 return 0;
1684}
1685
3c437ffd 1686static void omap_gpio_resume(void)
92105bb7
TL		 1687{
1688 int i;
1689
723fdb78 1690 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1691 return;
92105bb7
TL		 1692
1693 for (i = 0; i < gpio_bank_count; i++) {
1694 struct gpio_bank *bank = &gpio_bank[i];
1695 void __iomem *wake_clear;
1696 void __iomem *wake_set;
a6472533 1697 unsigned long flags;
92105bb7
TL		 1698
1699 switch (bank->method) {
e5c56ed3 1700#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1701 case METHOD_GPIO_1610:
1702 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1703 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1704 break;
e5c56ed3 1705#endif
a8eb7ca0 1706#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1707 case METHOD_GPIO_24XX:
0d9356cb
TL		 1708 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1709 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1710 break;
78a1a6d3
SR		 1711#endif
1712#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1713 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1714 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1715 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1716 break;
e5c56ed3 1717#endif
92105bb7
TL		 1718 default:
1719 continue;
1720 }
1721
a6472533 1722 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1723 __raw_writel(0xffffffff, wake_clear);
1724 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1725 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1726 }
92105bb7
TL		 1727}
1728
3c437ffd 1729static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1730 .suspend = omap_gpio_suspend,
1731 .resume = omap_gpio_resume,
1732};
1733
3ac4fa99
JY		 1734#endif
1735
140455fa 1736#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1737
1738static int workaround_enabled;
1739
72e06d08 1740void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1741{
1742 int i, c = 0;
a118b5f3 1743 int min = 0;
3ac4fa99 1744
a118b5f3
TK		 1745 if (cpu_is_omap34xx())
1746 min = 1;
43ffcd9a 1747
a118b5f3 1748 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1749 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1750 u32 l1 = 0, l2 = 0;
0aed0435 1751 int j;
3ac4fa99 1752
0aed0435 1753 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1754 clk_disable(bank->dbck);
1755
72e06d08 1756 if (!off_mode)
43ffcd9a
KH		 1757 continue;
1758
1759 /* If going to OFF, remove triggering for all
1760 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1761 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1762 if (!(bank->enabled_non_wakeup_gpios))
1763 continue;
3f1686a9
TL		 1764
1765 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1766 bank->saved_datain = __raw_readl(bank->base +
1767 OMAP24XX_GPIO_DATAIN);
1768 l1 = __raw_readl(bank->base +
1769 OMAP24XX_GPIO_FALLINGDETECT);
1770 l2 = __raw_readl(bank->base +
1771 OMAP24XX_GPIO_RISINGDETECT);
1772 }
1773
1774 if (cpu_is_omap44xx()) {
1775 bank->saved_datain = __raw_readl(bank->base +
1776 OMAP4_GPIO_DATAIN);
1777 l1 = __raw_readl(bank->base +
1778 OMAP4_GPIO_FALLINGDETECT);
1779 l2 = __raw_readl(bank->base +
1780 OMAP4_GPIO_RISINGDETECT);
1781 }
1782
3ac4fa99
JY		 1783 bank->saved_fallingdetect = l1;
1784 bank->saved_risingdetect = l2;
1785 l1 &= ~bank->enabled_non_wakeup_gpios;
1786 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1787
1788 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1789 __raw_writel(l1, bank->base +
1790 OMAP24XX_GPIO_FALLINGDETECT);
1791 __raw_writel(l2, bank->base +
1792 OMAP24XX_GPIO_RISINGDETECT);
1793 }
1794
1795 if (cpu_is_omap44xx()) {
1796 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1797 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1798 }
1799
3ac4fa99
JY		 1800 c++;
1801 }
1802 if (!c) {
1803 workaround_enabled = 0;
1804 return;
1805 }
1806 workaround_enabled = 1;
1807}
1808
43ffcd9a 1809void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1810{
1811 int i;
a118b5f3 1812 int min = 0;
3ac4fa99 1813
a118b5f3
TK		 1814 if (cpu_is_omap34xx())
1815 min = 1;
1816 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1817 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1818 u32 l = 0, gen, gen0, gen1;
0aed0435 1819 int j;
3ac4fa99 1820
0aed0435 1821 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1822 clk_enable(bank->dbck);
1823
43ffcd9a
KH		 1824 if (!workaround_enabled)
1825 continue;
1826
3ac4fa99
JY		 1827 if (!(bank->enabled_non_wakeup_gpios))
1828 continue;
3f1686a9
TL		 1829
1830 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1831 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1832 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1833 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1834 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1835 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1836 }
1837
1838 if (cpu_is_omap44xx()) {
1839 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1840 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1841 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1842 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1843 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1844 }
1845
3ac4fa99
JY		 1846 /* Check if any of the non-wakeup interrupt GPIOs have changed
1847 * state. If so, generate an IRQ by software. This is
1848 * horribly racy, but it's the best we can do to work around
1849 * this silicon bug. */
3ac4fa99 1850 l ^= bank->saved_datain;
a118b5f3 1851 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1852
1853 /*
1854 * No need to generate IRQs for the rising edge for gpio IRQs
1855 * configured with falling edge only; and vice versa.
1856 */
1857 gen0 = l & bank->saved_fallingdetect;
1858 gen0 &= bank->saved_datain;
1859
1860 gen1 = l & bank->saved_risingdetect;
1861 gen1 &= ~(bank->saved_datain);
1862
1863 /* FIXME: Consider GPIO IRQs with level detections properly! */
1864 gen = l & (~(bank->saved_fallingdetect) &
1865 ~(bank->saved_risingdetect));
1866 /* Consider all GPIO IRQs needed to be updated */
1867 gen |= gen0 | gen1;
1868
1869 if (gen) {
3ac4fa99 1870 u32 old0, old1;
3f1686a9 1871
f00d6497 1872 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1873 old0 = __raw_readl(bank->base +
1874 OMAP24XX_GPIO_LEVELDETECT0);
1875 old1 = __raw_readl(bank->base +
1876 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1877 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1878 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1879 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1880 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1881 __raw_writel(old0, bank->base +
3f1686a9 1882 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1883 __raw_writel(old1, bank->base +
3f1686a9
TL		 1884 OMAP24XX_GPIO_LEVELDETECT1);
1885 }
1886
1887 if (cpu_is_omap44xx()) {
1888 old0 = __raw_readl(bank->base +
78a1a6d3 1889 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1890 old1 = __raw_readl(bank->base +
78a1a6d3 1891 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1892 __raw_writel(old0 | l, bank->base +
78a1a6d3 1893 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1894 __raw_writel(old1 | l, bank->base +
78a1a6d3 1895 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1896 __raw_writel(old0, bank->base +
78a1a6d3 1897 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1898 __raw_writel(old1, bank->base +
78a1a6d3 1899 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1900 }
3ac4fa99
JY		 1901 }
1902 }
1903
1904}
1905
92105bb7
TL		 1906#endif
1907
a8eb7ca0 1908#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1909/* save the registers of bank 2-6 */
1910void omap_gpio_save_context(void)
1911{
1912 int i;
1913
1914 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1915 for (i = 1; i < gpio_bank_count; i++) {
1916 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1917 gpio_context[i].irqenable1 =
1918 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1919 gpio_context[i].irqenable2 =
1920 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1921 gpio_context[i].wake_en =
1922 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1923 gpio_context[i].ctrl =
1924 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1925 gpio_context[i].oe =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1927 gpio_context[i].leveldetect0 =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1929 gpio_context[i].leveldetect1 =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1931 gpio_context[i].risingdetect =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1933 gpio_context[i].fallingdetect =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1935 gpio_context[i].dataout =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1937 }
1938}
1939
1940/* restore the required registers of bank 2-6 */
1941void omap_gpio_restore_context(void)
1942{
1943 int i;
1944
1945 for (i = 1; i < gpio_bank_count; i++) {
1946 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1947 __raw_writel(gpio_context[i].irqenable1,
1948 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1949 __raw_writel(gpio_context[i].irqenable2,
1950 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1951 __raw_writel(gpio_context[i].wake_en,
1952 bank->base + OMAP24XX_GPIO_WAKE_EN);
1953 __raw_writel(gpio_context[i].ctrl,
1954 bank->base + OMAP24XX_GPIO_CTRL);
1955 __raw_writel(gpio_context[i].oe,
1956 bank->base + OMAP24XX_GPIO_OE);
1957 __raw_writel(gpio_context[i].leveldetect0,
1958 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1959 __raw_writel(gpio_context[i].leveldetect1,
1960 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1961 __raw_writel(gpio_context[i].risingdetect,
1962 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1963 __raw_writel(gpio_context[i].fallingdetect,
1964 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1965 __raw_writel(gpio_context[i].dataout,
1966 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1967 }
1968}
1969#endif
1970
77640aab
VC		 1971static struct platform_driver omap_gpio_driver = {
1972 .probe = omap_gpio_probe,
1973 .driver = {
1974 .name = "omap_gpio",
1975 },
1976};
1977
5e1c5ff4 1978/*
77640aab
VC		 1979 * gpio driver register needs to be done before
1980 * machine_init functions access gpio APIs.
1981 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1982 */
77640aab 1983static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1984{
77640aab 1985 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1986}
77640aab 1987postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1988
92105bb7
TL		 1989static int __init omap_gpio_sysinit(void)
1990{
11a78b79
DB		 1991 mpuio_init();
1992
140455fa 1993#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1994 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1995 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 1996#endif
1997
3c437ffd 1998 return 0;
92105bb7
TL		 1999}
2000
92105bb7 2001arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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