Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 | 31 | struct gpio_bank { |
9f7065da | 32 | unsigned long pbase; |
92105bb7 | 33 | void __iomem *base; |
5e1c5ff4 TL |
34 | u16 irq; |
35 | u16 virtual_irq_start; | |
92105bb7 | 36 | int method; |
140455fa | 37 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
38 | u32 suspend_wakeup; |
39 | u32 saved_wakeup; | |
3ac4fa99 | 40 | #endif |
3ac4fa99 JY |
41 | u32 non_wakeup_gpios; |
42 | u32 enabled_non_wakeup_gpios; | |
43 | ||
44 | u32 saved_datain; | |
45 | u32 saved_fallingdetect; | |
46 | u32 saved_risingdetect; | |
b144ff6f | 47 | u32 level_mask; |
4318f36b | 48 | u32 toggle_mask; |
5e1c5ff4 | 49 | spinlock_t lock; |
52e31344 | 50 | struct gpio_chip chip; |
89db9482 | 51 | struct clk *dbck; |
058af1ea | 52 | u32 mod_usage; |
8865b9b6 | 53 | u32 dbck_enable_mask; |
77640aab VC |
54 | struct device *dev; |
55 | bool dbck_flag; | |
5de62b86 | 56 | int stride; |
d5f46247 | 57 | u32 width; |
5e1c5ff4 TL |
58 | }; |
59 | ||
a8eb7ca0 | 60 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 | 61 | struct omap3_gpio_regs { |
40c670f0 RN |
62 | u32 irqenable1; |
63 | u32 irqenable2; | |
64 | u32 wake_en; | |
65 | u32 ctrl; | |
66 | u32 oe; | |
67 | u32 leveldetect0; | |
68 | u32 leveldetect1; | |
69 | u32 risingdetect; | |
70 | u32 fallingdetect; | |
71 | u32 dataout; | |
5492fb1a SMK |
72 | }; |
73 | ||
40c670f0 | 74 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
75 | #endif |
76 | ||
77640aab VC |
77 | /* |
78 | * TODO: Cleanup gpio_bank usage as it is having information | |
79 | * related to all instances of the device | |
80 | */ | |
81 | static struct gpio_bank *gpio_bank; | |
44169075 | 82 | |
c95d10bc VC |
83 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
84 | int gpio_bank_count; | |
5e1c5ff4 TL |
85 | |
86 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
87 | { | |
6e60e79a | 88 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
89 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
90 | return &gpio_bank[0]; | |
91 | return &gpio_bank[1]; | |
92 | } | |
5e1c5ff4 TL |
93 | if (cpu_is_omap16xx()) { |
94 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
95 | return &gpio_bank[0]; | |
96 | return &gpio_bank[1 + (gpio >> 4)]; | |
97 | } | |
56739a69 | 98 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
99 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
100 | return &gpio_bank[0]; | |
101 | return &gpio_bank[1 + (gpio >> 5)]; | |
102 | } | |
92105bb7 TL |
103 | if (cpu_is_omap24xx()) |
104 | return &gpio_bank[gpio >> 5]; | |
44169075 | 105 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 106 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
107 | BUG(); |
108 | return NULL; | |
5e1c5ff4 TL |
109 | } |
110 | ||
111 | static inline int get_gpio_index(int gpio) | |
112 | { | |
56739a69 | 113 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 114 | return gpio & 0x1f; |
92105bb7 TL |
115 | if (cpu_is_omap24xx()) |
116 | return gpio & 0x1f; | |
44169075 | 117 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 118 | return gpio & 0x1f; |
92105bb7 | 119 | return gpio & 0x0f; |
5e1c5ff4 TL |
120 | } |
121 | ||
122 | static inline int gpio_valid(int gpio) | |
123 | { | |
124 | if (gpio < 0) | |
125 | return -1; | |
d11ac979 | 126 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 127 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
128 | return -1; |
129 | return 0; | |
130 | } | |
6e60e79a | 131 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 132 | return 0; |
5e1c5ff4 TL |
133 | if ((cpu_is_omap16xx()) && gpio < 64) |
134 | return 0; | |
56739a69 | 135 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 136 | return 0; |
25d6f630 TL |
137 | if (cpu_is_omap2420() && gpio < 128) |
138 | return 0; | |
139 | if (cpu_is_omap2430() && gpio < 160) | |
92105bb7 | 140 | return 0; |
44169075 | 141 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 142 | return 0; |
5e1c5ff4 TL |
143 | return -1; |
144 | } | |
145 | ||
146 | static int check_gpio(int gpio) | |
147 | { | |
d32b20fc | 148 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
149 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
150 | dump_stack(); | |
151 | return -1; | |
152 | } | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
157 | { | |
92105bb7 | 158 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
159 | u32 l; |
160 | ||
161 | switch (bank->method) { | |
e5c56ed3 | 162 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 163 | case METHOD_MPUIO: |
5de62b86 | 164 | reg += OMAP_MPUIO_IO_CNTL / bank->stride; |
5e1c5ff4 | 165 | break; |
e5c56ed3 DB |
166 | #endif |
167 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
168 | case METHOD_GPIO_1510: |
169 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
170 | break; | |
e5c56ed3 DB |
171 | #endif |
172 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
173 | case METHOD_GPIO_1610: |
174 | reg += OMAP1610_GPIO_DIRECTION; | |
175 | break; | |
e5c56ed3 | 176 | #endif |
b718aa81 | 177 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
178 | case METHOD_GPIO_7XX: |
179 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
180 | break; |
181 | #endif | |
a8eb7ca0 | 182 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
183 | case METHOD_GPIO_24XX: |
184 | reg += OMAP24XX_GPIO_OE; | |
185 | break; | |
78a1a6d3 SR |
186 | #endif |
187 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 188 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
189 | reg += OMAP4_GPIO_OE; |
190 | break; | |
e5c56ed3 DB |
191 | #endif |
192 | default: | |
193 | WARN_ON(1); | |
194 | return; | |
5e1c5ff4 TL |
195 | } |
196 | l = __raw_readl(reg); | |
197 | if (is_input) | |
198 | l |= 1 << gpio; | |
199 | else | |
200 | l &= ~(1 << gpio); | |
201 | __raw_writel(l, reg); | |
202 | } | |
203 | ||
5e1c5ff4 TL |
204 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
205 | { | |
92105bb7 | 206 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
207 | u32 l = 0; |
208 | ||
209 | switch (bank->method) { | |
e5c56ed3 | 210 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 211 | case METHOD_MPUIO: |
5de62b86 | 212 | reg += OMAP_MPUIO_OUTPUT / bank->stride; |
5e1c5ff4 TL |
213 | l = __raw_readl(reg); |
214 | if (enable) | |
215 | l |= 1 << gpio; | |
216 | else | |
217 | l &= ~(1 << gpio); | |
218 | break; | |
e5c56ed3 DB |
219 | #endif |
220 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
221 | case METHOD_GPIO_1510: |
222 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
223 | l = __raw_readl(reg); | |
224 | if (enable) | |
225 | l |= 1 << gpio; | |
226 | else | |
227 | l &= ~(1 << gpio); | |
228 | break; | |
e5c56ed3 DB |
229 | #endif |
230 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
231 | case METHOD_GPIO_1610: |
232 | if (enable) | |
233 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
234 | else | |
235 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
236 | l = 1 << gpio; | |
237 | break; | |
e5c56ed3 | 238 | #endif |
b718aa81 | 239 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
240 | case METHOD_GPIO_7XX: |
241 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
242 | l = __raw_readl(reg); |
243 | if (enable) | |
244 | l |= 1 << gpio; | |
245 | else | |
246 | l &= ~(1 << gpio); | |
247 | break; | |
248 | #endif | |
a8eb7ca0 | 249 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
250 | case METHOD_GPIO_24XX: |
251 | if (enable) | |
252 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
253 | else | |
254 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
255 | l = 1 << gpio; | |
256 | break; | |
78a1a6d3 SR |
257 | #endif |
258 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 259 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
260 | if (enable) |
261 | reg += OMAP4_GPIO_SETDATAOUT; | |
262 | else | |
263 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
264 | l = 1 << gpio; | |
265 | break; | |
e5c56ed3 | 266 | #endif |
5e1c5ff4 | 267 | default: |
e5c56ed3 | 268 | WARN_ON(1); |
5e1c5ff4 TL |
269 | return; |
270 | } | |
271 | __raw_writel(l, reg); | |
272 | } | |
273 | ||
b37c45b8 | 274 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 275 | { |
92105bb7 | 276 | void __iomem *reg; |
5e1c5ff4 TL |
277 | |
278 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 279 | return -EINVAL; |
5e1c5ff4 TL |
280 | reg = bank->base; |
281 | switch (bank->method) { | |
e5c56ed3 | 282 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 283 | case METHOD_MPUIO: |
5de62b86 | 284 | reg += OMAP_MPUIO_INPUT_LATCH / bank->stride; |
5e1c5ff4 | 285 | break; |
e5c56ed3 DB |
286 | #endif |
287 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
288 | case METHOD_GPIO_1510: |
289 | reg += OMAP1510_GPIO_DATA_INPUT; | |
290 | break; | |
e5c56ed3 DB |
291 | #endif |
292 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
293 | case METHOD_GPIO_1610: |
294 | reg += OMAP1610_GPIO_DATAIN; | |
295 | break; | |
e5c56ed3 | 296 | #endif |
b718aa81 | 297 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
298 | case METHOD_GPIO_7XX: |
299 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
300 | break; |
301 | #endif | |
a8eb7ca0 | 302 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
303 | case METHOD_GPIO_24XX: |
304 | reg += OMAP24XX_GPIO_DATAIN; | |
305 | break; | |
78a1a6d3 SR |
306 | #endif |
307 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 308 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
309 | reg += OMAP4_GPIO_DATAIN; |
310 | break; | |
e5c56ed3 | 311 | #endif |
5e1c5ff4 | 312 | default: |
e5c56ed3 | 313 | return -EINVAL; |
5e1c5ff4 | 314 | } |
92105bb7 TL |
315 | return (__raw_readl(reg) |
316 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
317 | } |
318 | ||
b37c45b8 RQ |
319 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
320 | { | |
321 | void __iomem *reg; | |
322 | ||
323 | if (check_gpio(gpio) < 0) | |
324 | return -EINVAL; | |
325 | reg = bank->base; | |
326 | ||
327 | switch (bank->method) { | |
328 | #ifdef CONFIG_ARCH_OMAP1 | |
329 | case METHOD_MPUIO: | |
5de62b86 | 330 | reg += OMAP_MPUIO_OUTPUT / bank->stride; |
b37c45b8 RQ |
331 | break; |
332 | #endif | |
333 | #ifdef CONFIG_ARCH_OMAP15XX | |
334 | case METHOD_GPIO_1510: | |
335 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
336 | break; | |
337 | #endif | |
338 | #ifdef CONFIG_ARCH_OMAP16XX | |
339 | case METHOD_GPIO_1610: | |
340 | reg += OMAP1610_GPIO_DATAOUT; | |
341 | break; | |
342 | #endif | |
b718aa81 | 343 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
344 | case METHOD_GPIO_7XX: |
345 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
346 | break; |
347 | #endif | |
9f096868 | 348 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
b37c45b8 RQ |
349 | case METHOD_GPIO_24XX: |
350 | reg += OMAP24XX_GPIO_DATAOUT; | |
351 | break; | |
9f096868 C |
352 | #endif |
353 | #ifdef CONFIG_ARCH_OMAP4 | |
354 | case METHOD_GPIO_44XX: | |
355 | reg += OMAP4_GPIO_DATAOUT; | |
356 | break; | |
b37c45b8 RQ |
357 | #endif |
358 | default: | |
359 | return -EINVAL; | |
360 | } | |
361 | ||
362 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
363 | } | |
364 | ||
92105bb7 TL |
365 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
366 | do { \ | |
367 | int l = __raw_readl(base + reg); \ | |
368 | if (set) l |= bit_mask; \ | |
369 | else l &= ~bit_mask; \ | |
370 | __raw_writel(l, base + reg); \ | |
371 | } while(0) | |
372 | ||
168ef3d9 FB |
373 | /** |
374 | * _set_gpio_debounce - low level gpio debounce time | |
375 | * @bank: the gpio bank we're acting upon | |
376 | * @gpio: the gpio number on this @gpio | |
377 | * @debounce: debounce time to use | |
378 | * | |
379 | * OMAP's debounce time is in 31us steps so we need | |
380 | * to convert and round up to the closest unit. | |
381 | */ | |
382 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
383 | unsigned debounce) | |
384 | { | |
385 | void __iomem *reg = bank->base; | |
386 | u32 val; | |
387 | u32 l; | |
388 | ||
77640aab VC |
389 | if (!bank->dbck_flag) |
390 | return; | |
391 | ||
168ef3d9 FB |
392 | if (debounce < 32) |
393 | debounce = 0x01; | |
394 | else if (debounce > 7936) | |
395 | debounce = 0xff; | |
396 | else | |
397 | debounce = (debounce / 0x1f) - 1; | |
398 | ||
399 | l = 1 << get_gpio_index(gpio); | |
400 | ||
77640aab | 401 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
402 | reg += OMAP4_GPIO_DEBOUNCINGTIME; |
403 | else | |
404 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
405 | ||
406 | __raw_writel(debounce, reg); | |
407 | ||
408 | reg = bank->base; | |
77640aab | 409 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
410 | reg += OMAP4_GPIO_DEBOUNCENABLE; |
411 | else | |
412 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
413 | ||
414 | val = __raw_readl(reg); | |
415 | ||
416 | if (debounce) { | |
417 | val |= l; | |
77640aab | 418 | clk_enable(bank->dbck); |
168ef3d9 FB |
419 | } else { |
420 | val &= ~l; | |
77640aab | 421 | clk_disable(bank->dbck); |
168ef3d9 | 422 | } |
f7ec0b0b | 423 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
424 | |
425 | __raw_writel(val, reg); | |
426 | } | |
427 | ||
140455fa | 428 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
429 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
430 | int trigger) | |
5e1c5ff4 | 431 | { |
3ac4fa99 | 432 | void __iomem *base = bank->base; |
92105bb7 TL |
433 | u32 gpio_bit = 1 << gpio; |
434 | ||
78a1a6d3 SR |
435 | if (cpu_is_omap44xx()) { |
436 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
437 | trigger & IRQ_TYPE_LEVEL_LOW); | |
438 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
439 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
440 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
441 | trigger & IRQ_TYPE_EDGE_RISING); | |
442 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
443 | trigger & IRQ_TYPE_EDGE_FALLING); | |
444 | } else { | |
445 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
446 | trigger & IRQ_TYPE_LEVEL_LOW); | |
447 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
448 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
449 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
450 | trigger & IRQ_TYPE_EDGE_RISING); | |
451 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
452 | trigger & IRQ_TYPE_EDGE_FALLING); | |
453 | } | |
3ac4fa99 | 454 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 | 455 | if (cpu_is_omap44xx()) { |
0622b25b CC |
456 | MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit, |
457 | trigger != 0); | |
78a1a6d3 | 458 | } else { |
699117a6 CW |
459 | /* |
460 | * GPIO wakeup request can only be generated on edge | |
461 | * transitions | |
462 | */ | |
463 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 464 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 465 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
466 | else |
467 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 468 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 469 | } |
a118b5f3 TK |
470 | } |
471 | /* This part needs to be executed always for OMAP34xx */ | |
472 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
473 | /* |
474 | * Log the edge gpio and manually trigger the IRQ | |
475 | * after resume if the input level changes | |
476 | * to avoid irq lost during PER RET/OFF mode | |
477 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
478 | */ | |
479 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
480 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
481 | else | |
482 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
483 | } | |
5eb3bb9c | 484 | |
78a1a6d3 SR |
485 | if (cpu_is_omap44xx()) { |
486 | bank->level_mask = | |
487 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
488 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
489 | } else { | |
490 | bank->level_mask = | |
491 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
492 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
493 | } | |
92105bb7 | 494 | } |
3ac4fa99 | 495 | #endif |
92105bb7 | 496 | |
9198bcd3 | 497 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
498 | /* |
499 | * This only applies to chips that can't do both rising and falling edge | |
500 | * detection at once. For all other chips, this function is a noop. | |
501 | */ | |
502 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
503 | { | |
504 | void __iomem *reg = bank->base; | |
505 | u32 l = 0; | |
506 | ||
507 | switch (bank->method) { | |
4318f36b | 508 | case METHOD_MPUIO: |
5de62b86 | 509 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
4318f36b | 510 | break; |
4318f36b CM |
511 | #ifdef CONFIG_ARCH_OMAP15XX |
512 | case METHOD_GPIO_1510: | |
513 | reg += OMAP1510_GPIO_INT_CONTROL; | |
514 | break; | |
515 | #endif | |
516 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
517 | case METHOD_GPIO_7XX: | |
518 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
519 | break; | |
520 | #endif | |
521 | default: | |
522 | return; | |
523 | } | |
524 | ||
525 | l = __raw_readl(reg); | |
526 | if ((l >> gpio) & 1) | |
527 | l &= ~(1 << gpio); | |
528 | else | |
529 | l |= 1 << gpio; | |
530 | ||
531 | __raw_writel(l, reg); | |
532 | } | |
9198bcd3 | 533 | #endif |
4318f36b | 534 | |
92105bb7 TL |
535 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
536 | { | |
537 | void __iomem *reg = bank->base; | |
538 | u32 l = 0; | |
5e1c5ff4 TL |
539 | |
540 | switch (bank->method) { | |
e5c56ed3 | 541 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 542 | case METHOD_MPUIO: |
5de62b86 | 543 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
5e1c5ff4 | 544 | l = __raw_readl(reg); |
29501577 | 545 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 546 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 547 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 548 | l |= 1 << gpio; |
6cab4860 | 549 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 550 | l &= ~(1 << gpio); |
92105bb7 TL |
551 | else |
552 | goto bad; | |
5e1c5ff4 | 553 | break; |
e5c56ed3 DB |
554 | #endif |
555 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
556 | case METHOD_GPIO_1510: |
557 | reg += OMAP1510_GPIO_INT_CONTROL; | |
558 | l = __raw_readl(reg); | |
29501577 | 559 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 560 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 561 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 562 | l |= 1 << gpio; |
6cab4860 | 563 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 564 | l &= ~(1 << gpio); |
92105bb7 TL |
565 | else |
566 | goto bad; | |
5e1c5ff4 | 567 | break; |
e5c56ed3 | 568 | #endif |
3ac4fa99 | 569 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 570 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
571 | if (gpio & 0x08) |
572 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
573 | else | |
574 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
575 | gpio &= 0x07; | |
576 | l = __raw_readl(reg); | |
577 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 578 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 579 | l |= 2 << (gpio << 1); |
6cab4860 | 580 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 581 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
582 | if (trigger) |
583 | /* Enable wake-up during idle for dynamic tick */ | |
584 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
585 | else | |
586 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 587 | break; |
3ac4fa99 | 588 | #endif |
b718aa81 | 589 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
590 | case METHOD_GPIO_7XX: |
591 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 592 | l = __raw_readl(reg); |
29501577 | 593 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 594 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
595 | if (trigger & IRQ_TYPE_EDGE_RISING) |
596 | l |= 1 << gpio; | |
597 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
598 | l &= ~(1 << gpio); | |
599 | else | |
600 | goto bad; | |
601 | break; | |
602 | #endif | |
140455fa | 603 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 604 | case METHOD_GPIO_24XX: |
3f1686a9 | 605 | case METHOD_GPIO_44XX: |
3ac4fa99 | 606 | set_24xx_gpio_triggering(bank, gpio, trigger); |
f7c5cc45 | 607 | return 0; |
3ac4fa99 | 608 | #endif |
5e1c5ff4 | 609 | default: |
92105bb7 | 610 | goto bad; |
5e1c5ff4 | 611 | } |
92105bb7 TL |
612 | __raw_writel(l, reg); |
613 | return 0; | |
614 | bad: | |
615 | return -EINVAL; | |
5e1c5ff4 TL |
616 | } |
617 | ||
e9191028 | 618 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
619 | { |
620 | struct gpio_bank *bank; | |
92105bb7 TL |
621 | unsigned gpio; |
622 | int retval; | |
a6472533 | 623 | unsigned long flags; |
92105bb7 | 624 | |
e9191028 LB |
625 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
626 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 627 | else |
e9191028 | 628 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 TL |
629 | |
630 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
631 | return -EINVAL; |
632 | ||
e5c56ed3 | 633 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 634 | return -EINVAL; |
e5c56ed3 DB |
635 | |
636 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 637 | if (!cpu_class_is_omap2() |
e5c56ed3 | 638 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
639 | return -EINVAL; |
640 | ||
e9191028 | 641 | bank = irq_data_get_irq_chip_data(d); |
a6472533 | 642 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 643 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
a6472533 | 644 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
645 | |
646 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 647 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 648 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 649 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 650 | |
92105bb7 | 651 | return retval; |
5e1c5ff4 TL |
652 | } |
653 | ||
654 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
655 | { | |
92105bb7 | 656 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
657 | |
658 | switch (bank->method) { | |
e5c56ed3 | 659 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
660 | case METHOD_GPIO_1510: |
661 | reg += OMAP1510_GPIO_INT_STATUS; | |
662 | break; | |
e5c56ed3 DB |
663 | #endif |
664 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
665 | case METHOD_GPIO_1610: |
666 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
667 | break; | |
e5c56ed3 | 668 | #endif |
b718aa81 | 669 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
670 | case METHOD_GPIO_7XX: |
671 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
672 | break; |
673 | #endif | |
a8eb7ca0 | 674 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
675 | case METHOD_GPIO_24XX: |
676 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
677 | break; | |
78a1a6d3 SR |
678 | #endif |
679 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 680 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
681 | reg += OMAP4_GPIO_IRQSTATUS0; |
682 | break; | |
e5c56ed3 | 683 | #endif |
5e1c5ff4 | 684 | default: |
e5c56ed3 | 685 | WARN_ON(1); |
5e1c5ff4 TL |
686 | return; |
687 | } | |
688 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
689 | |
690 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
691 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
692 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
693 | else if (cpu_is_omap44xx()) | |
694 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
695 | ||
df3c8517 | 696 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) |
bedfd154 RQ |
697 | __raw_writel(gpio_mask, reg); |
698 | ||
699 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
700 | __raw_readl(reg); | |
5e1c5ff4 TL |
701 | } |
702 | ||
703 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
704 | { | |
705 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
706 | } | |
707 | ||
ea6dedd7 ID |
708 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
709 | { | |
710 | void __iomem *reg = bank->base; | |
99c47707 ID |
711 | int inv = 0; |
712 | u32 l; | |
c390aad0 | 713 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 ID |
714 | |
715 | switch (bank->method) { | |
e5c56ed3 | 716 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 | 717 | case METHOD_MPUIO: |
5de62b86 | 718 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
99c47707 | 719 | inv = 1; |
ea6dedd7 | 720 | break; |
e5c56ed3 DB |
721 | #endif |
722 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
723 | case METHOD_GPIO_1510: |
724 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 | 725 | inv = 1; |
ea6dedd7 | 726 | break; |
e5c56ed3 DB |
727 | #endif |
728 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
729 | case METHOD_GPIO_1610: |
730 | reg += OMAP1610_GPIO_IRQENABLE1; | |
731 | break; | |
e5c56ed3 | 732 | #endif |
b718aa81 | 733 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
734 | case METHOD_GPIO_7XX: |
735 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
736 | inv = 1; |
737 | break; | |
738 | #endif | |
a8eb7ca0 | 739 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
740 | case METHOD_GPIO_24XX: |
741 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
742 | break; | |
78a1a6d3 SR |
743 | #endif |
744 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 745 | case METHOD_GPIO_44XX: |
78a1a6d3 | 746 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
78a1a6d3 | 747 | break; |
e5c56ed3 | 748 | #endif |
ea6dedd7 | 749 | default: |
e5c56ed3 | 750 | WARN_ON(1); |
ea6dedd7 ID |
751 | return 0; |
752 | } | |
753 | ||
99c47707 ID |
754 | l = __raw_readl(reg); |
755 | if (inv) | |
756 | l = ~l; | |
757 | l &= mask; | |
758 | return l; | |
ea6dedd7 ID |
759 | } |
760 | ||
5e1c5ff4 TL |
761 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
762 | { | |
92105bb7 | 763 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
764 | u32 l; |
765 | ||
766 | switch (bank->method) { | |
e5c56ed3 | 767 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 768 | case METHOD_MPUIO: |
5de62b86 | 769 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
5e1c5ff4 TL |
770 | l = __raw_readl(reg); |
771 | if (enable) | |
772 | l &= ~(gpio_mask); | |
773 | else | |
774 | l |= gpio_mask; | |
775 | break; | |
e5c56ed3 DB |
776 | #endif |
777 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
778 | case METHOD_GPIO_1510: |
779 | reg += OMAP1510_GPIO_INT_MASK; | |
780 | l = __raw_readl(reg); | |
781 | if (enable) | |
782 | l &= ~(gpio_mask); | |
783 | else | |
784 | l |= gpio_mask; | |
785 | break; | |
e5c56ed3 DB |
786 | #endif |
787 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
788 | case METHOD_GPIO_1610: |
789 | if (enable) | |
790 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
791 | else | |
792 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
793 | l = gpio_mask; | |
794 | break; | |
e5c56ed3 | 795 | #endif |
b718aa81 | 796 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
797 | case METHOD_GPIO_7XX: |
798 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
799 | l = __raw_readl(reg); |
800 | if (enable) | |
801 | l &= ~(gpio_mask); | |
802 | else | |
803 | l |= gpio_mask; | |
804 | break; | |
805 | #endif | |
a8eb7ca0 | 806 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
807 | case METHOD_GPIO_24XX: |
808 | if (enable) | |
809 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
810 | else | |
811 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
812 | l = gpio_mask; | |
813 | break; | |
78a1a6d3 SR |
814 | #endif |
815 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 816 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
817 | if (enable) |
818 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
819 | else | |
820 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
821 | l = gpio_mask; | |
822 | break; | |
e5c56ed3 | 823 | #endif |
5e1c5ff4 | 824 | default: |
e5c56ed3 | 825 | WARN_ON(1); |
5e1c5ff4 TL |
826 | return; |
827 | } | |
828 | __raw_writel(l, reg); | |
829 | } | |
830 | ||
831 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
832 | { | |
833 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
834 | } | |
835 | ||
92105bb7 TL |
836 | /* |
837 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
838 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
839 | * to the target, system will wake up always on GPIO events. While | |
840 | * system is running all registered GPIO interrupts need to have wake-up | |
841 | * enabled. When system is suspended, only selected GPIO interrupts need | |
842 | * to have wake-up enabled. | |
843 | */ | |
844 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
845 | { | |
4cc6420c | 846 | unsigned long uninitialized_var(flags); |
a6472533 | 847 | |
92105bb7 | 848 | switch (bank->method) { |
3ac4fa99 | 849 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 850 | case METHOD_MPUIO: |
92105bb7 | 851 | case METHOD_GPIO_1610: |
a6472533 | 852 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 853 | if (enable) |
92105bb7 | 854 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 855 | else |
92105bb7 | 856 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 857 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 858 | return 0; |
3ac4fa99 | 859 | #endif |
140455fa | 860 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 861 | case METHOD_GPIO_24XX: |
3f1686a9 | 862 | case METHOD_GPIO_44XX: |
11a78b79 DB |
863 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
864 | printk(KERN_ERR "Unable to modify wakeup on " | |
865 | "non-wakeup GPIO%d\n", | |
d5f46247 | 866 | (bank - gpio_bank) * bank->width + gpio); |
11a78b79 DB |
867 | return -EINVAL; |
868 | } | |
a6472533 | 869 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 870 | if (enable) |
3ac4fa99 | 871 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 872 | else |
3ac4fa99 | 873 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 874 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
875 | return 0; |
876 | #endif | |
92105bb7 TL |
877 | default: |
878 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
879 | bank->method); | |
880 | return -EINVAL; | |
881 | } | |
882 | } | |
883 | ||
4196dd6b TL |
884 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
885 | { | |
886 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
887 | _set_gpio_irqenable(bank, gpio, 0); | |
888 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 889 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
890 | } |
891 | ||
92105bb7 | 892 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 893 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 894 | { |
e9191028 | 895 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
896 | struct gpio_bank *bank; |
897 | int retval; | |
898 | ||
899 | if (check_gpio(gpio) < 0) | |
900 | return -ENODEV; | |
e9191028 | 901 | bank = irq_data_get_irq_chip_data(d); |
92105bb7 | 902 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
903 | |
904 | return retval; | |
905 | } | |
906 | ||
3ff164e1 | 907 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 908 | { |
3ff164e1 | 909 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 910 | unsigned long flags; |
52e31344 | 911 | |
a6472533 | 912 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 913 | |
4196dd6b TL |
914 | /* Set trigger to none. You need to enable the desired trigger with |
915 | * request_irq() or set_irq_type(). | |
916 | */ | |
3ff164e1 | 917 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 918 | |
1a8bfa1e | 919 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 920 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 921 | void __iomem *reg; |
5e1c5ff4 | 922 | |
92105bb7 | 923 | /* Claim the pin for MPU */ |
5e1c5ff4 | 924 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 925 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
926 | } |
927 | #endif | |
058af1ea C |
928 | if (!cpu_class_is_omap1()) { |
929 | if (!bank->mod_usage) { | |
9f096868 | 930 | void __iomem *reg = bank->base; |
058af1ea | 931 | u32 ctrl; |
9f096868 C |
932 | |
933 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
934 | reg += OMAP24XX_GPIO_CTRL; | |
935 | else if (cpu_is_omap44xx()) | |
936 | reg += OMAP4_GPIO_CTRL; | |
937 | ctrl = __raw_readl(reg); | |
058af1ea | 938 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
939 | ctrl &= 0xFFFFFFFE; |
940 | __raw_writel(ctrl, reg); | |
058af1ea C |
941 | } |
942 | bank->mod_usage |= 1 << offset; | |
943 | } | |
a6472533 | 944 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
945 | |
946 | return 0; | |
947 | } | |
948 | ||
3ff164e1 | 949 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 950 | { |
3ff164e1 | 951 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 952 | unsigned long flags; |
5e1c5ff4 | 953 | |
a6472533 | 954 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
955 | #ifdef CONFIG_ARCH_OMAP16XX |
956 | if (bank->method == METHOD_GPIO_1610) { | |
957 | /* Disable wake-up during idle for dynamic tick */ | |
958 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 959 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
960 | } |
961 | #endif | |
9f096868 C |
962 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
963 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
964 | /* Disable wake-up during idle for dynamic tick */ |
965 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 966 | __raw_writel(1 << offset, reg); |
92105bb7 | 967 | } |
9f096868 C |
968 | #endif |
969 | #ifdef CONFIG_ARCH_OMAP4 | |
970 | if (bank->method == METHOD_GPIO_44XX) { | |
971 | /* Disable wake-up during idle for dynamic tick */ | |
972 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
973 | __raw_writel(1 << offset, reg); | |
974 | } | |
92105bb7 | 975 | #endif |
058af1ea C |
976 | if (!cpu_class_is_omap1()) { |
977 | bank->mod_usage &= ~(1 << offset); | |
978 | if (!bank->mod_usage) { | |
9f096868 | 979 | void __iomem *reg = bank->base; |
058af1ea | 980 | u32 ctrl; |
9f096868 C |
981 | |
982 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
983 | reg += OMAP24XX_GPIO_CTRL; | |
984 | else if (cpu_is_omap44xx()) | |
985 | reg += OMAP4_GPIO_CTRL; | |
986 | ctrl = __raw_readl(reg); | |
058af1ea C |
987 | /* Module is disabled, clocks are gated */ |
988 | ctrl |= 1; | |
9f096868 | 989 | __raw_writel(ctrl, reg); |
058af1ea C |
990 | } |
991 | } | |
3ff164e1 | 992 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 993 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
994 | } |
995 | ||
996 | /* | |
997 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
998 | * avoid missing GPIO interrupts for other lines in the bank. | |
999 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1000 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1001 | * If we wait to unmask individual GPIO lines in the bank after the | |
1002 | * line's interrupt handler has been run, we may miss some nested | |
1003 | * interrupts. | |
1004 | */ | |
10dd5ce2 | 1005 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1006 | { |
92105bb7 | 1007 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 1008 | u32 isr; |
4318f36b | 1009 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 1010 | struct gpio_bank *bank; |
ea6dedd7 ID |
1011 | u32 retrigger = 0; |
1012 | int unmasked = 0; | |
ee144182 | 1013 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 1014 | |
ee144182 | 1015 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 1016 | |
6845664a | 1017 | bank = irq_get_handler_data(irq); |
e5c56ed3 | 1018 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 1019 | if (bank->method == METHOD_MPUIO) |
5de62b86 TL |
1020 | isr_reg = bank->base + |
1021 | OMAP_MPUIO_GPIO_INT / bank->stride; | |
e5c56ed3 | 1022 | #endif |
1a8bfa1e | 1023 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1024 | if (bank->method == METHOD_GPIO_1510) |
1025 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1026 | #endif | |
1027 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1028 | if (bank->method == METHOD_GPIO_1610) | |
1029 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1030 | #endif | |
b718aa81 | 1031 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1032 | if (bank->method == METHOD_GPIO_7XX) |
1033 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1034 | #endif |
a8eb7ca0 | 1035 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1036 | if (bank->method == METHOD_GPIO_24XX) |
1037 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1038 | #endif |
1039 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1040 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 1041 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 1042 | #endif |
b1cc4c55 EK |
1043 | |
1044 | if (WARN_ON(!isr_reg)) | |
1045 | goto exit; | |
1046 | ||
92105bb7 | 1047 | while(1) { |
6e60e79a | 1048 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1049 | u32 enabled; |
6e60e79a | 1050 | |
ea6dedd7 ID |
1051 | enabled = _get_gpio_irqbank_mask(bank); |
1052 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1053 | |
1054 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1055 | isr &= 0x0000ffff; | |
1056 | ||
5492fb1a | 1057 | if (cpu_class_is_omap2()) { |
b144ff6f | 1058 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1059 | } |
6e60e79a TL |
1060 | |
1061 | /* clear edge sensitive interrupts before handler(s) are | |
1062 | called so that we don't miss any interrupt occurred while | |
1063 | executing them */ | |
1064 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1065 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1066 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1067 | ||
1068 | /* if there is only edge sensitive GPIO pin interrupts | |
1069 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1070 | if (!level_mask && !unmasked) { |
1071 | unmasked = 1; | |
ee144182 | 1072 | chained_irq_exit(chip, desc); |
ea6dedd7 | 1073 | } |
92105bb7 | 1074 | |
ea6dedd7 ID |
1075 | isr |= retrigger; |
1076 | retrigger = 0; | |
92105bb7 TL |
1077 | if (!isr) |
1078 | break; | |
1079 | ||
1080 | gpio_irq = bank->virtual_irq_start; | |
1081 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
4318f36b CM |
1082 | gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); |
1083 | ||
92105bb7 TL |
1084 | if (!(isr & 1)) |
1085 | continue; | |
29454dde | 1086 | |
4318f36b CM |
1087 | #ifdef CONFIG_ARCH_OMAP1 |
1088 | /* | |
1089 | * Some chips can't respond to both rising and falling | |
1090 | * at the same time. If this irq was requested with | |
1091 | * both flags, we need to flip the ICR data for the IRQ | |
1092 | * to respond to the IRQ for the opposite direction. | |
1093 | * This will be indicated in the bank toggle_mask. | |
1094 | */ | |
1095 | if (bank->toggle_mask & (1 << gpio_index)) | |
1096 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
1097 | #endif | |
1098 | ||
d8aa0251 | 1099 | generic_handle_irq(gpio_irq); |
92105bb7 | 1100 | } |
1a8bfa1e | 1101 | } |
ea6dedd7 ID |
1102 | /* if bank has any level sensitive GPIO pin interrupt |
1103 | configured, we must unmask the bank interrupt only after | |
1104 | handler(s) are executed in order to avoid spurious bank | |
1105 | interrupt */ | |
b1cc4c55 | 1106 | exit: |
ea6dedd7 | 1107 | if (!unmasked) |
ee144182 | 1108 | chained_irq_exit(chip, desc); |
5e1c5ff4 TL |
1109 | } |
1110 | ||
e9191028 | 1111 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 1112 | { |
e9191028 LB |
1113 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1114 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 1115 | unsigned long flags; |
4196dd6b | 1116 | |
85ec7b97 | 1117 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 1118 | _reset_gpio(bank, gpio); |
85ec7b97 | 1119 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
1120 | } |
1121 | ||
e9191028 | 1122 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 1123 | { |
e9191028 LB |
1124 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1125 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1126 | |
1127 | _clear_gpio_irqstatus(bank, gpio); | |
1128 | } | |
1129 | ||
e9191028 | 1130 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 1131 | { |
e9191028 LB |
1132 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1133 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 1134 | unsigned long flags; |
5e1c5ff4 | 1135 | |
85ec7b97 | 1136 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 1137 | _set_gpio_irqenable(bank, gpio, 0); |
55b6019a | 1138 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
85ec7b97 | 1139 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1140 | } |
1141 | ||
e9191028 | 1142 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 1143 | { |
e9191028 LB |
1144 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1145 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
b144ff6f | 1146 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
8c04a176 | 1147 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 1148 | unsigned long flags; |
55b6019a | 1149 | |
85ec7b97 | 1150 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a KH |
1151 | if (trigger) |
1152 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1153 | |
1154 | /* For level-triggered GPIOs, the clearing must be done after | |
1155 | * the HW source is cleared, thus after the handler has run */ | |
1156 | if (bank->level_mask & irq_mask) { | |
1157 | _set_gpio_irqenable(bank, gpio, 0); | |
1158 | _clear_gpio_irqstatus(bank, gpio); | |
1159 | } | |
5e1c5ff4 | 1160 | |
4de8c75b | 1161 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 1162 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1163 | } |
1164 | ||
e5c56ed3 DB |
1165 | static struct irq_chip gpio_irq_chip = { |
1166 | .name = "GPIO", | |
e9191028 LB |
1167 | .irq_shutdown = gpio_irq_shutdown, |
1168 | .irq_ack = gpio_ack_irq, | |
1169 | .irq_mask = gpio_mask_irq, | |
1170 | .irq_unmask = gpio_unmask_irq, | |
1171 | .irq_set_type = gpio_irq_type, | |
1172 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
1173 | }; |
1174 | ||
1175 | /*---------------------------------------------------------------------*/ | |
1176 | ||
1177 | #ifdef CONFIG_ARCH_OMAP1 | |
1178 | ||
1179 | /* MPUIO uses the always-on 32k clock */ | |
1180 | ||
e9191028 | 1181 | static void mpuio_ack_irq(struct irq_data *d) |
5e1c5ff4 TL |
1182 | { |
1183 | /* The ISR is reset automatically, so do nothing here. */ | |
1184 | } | |
1185 | ||
e9191028 | 1186 | static void mpuio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 1187 | { |
e9191028 LB |
1188 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
1189 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1190 | |
1191 | _set_gpio_irqenable(bank, gpio, 0); | |
1192 | } | |
1193 | ||
e9191028 | 1194 | static void mpuio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 1195 | { |
e9191028 LB |
1196 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
1197 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1198 | |
1199 | _set_gpio_irqenable(bank, gpio, 1); | |
1200 | } | |
1201 | ||
e5c56ed3 DB |
1202 | static struct irq_chip mpuio_irq_chip = { |
1203 | .name = "MPUIO", | |
e9191028 LB |
1204 | .irq_ack = mpuio_ack_irq, |
1205 | .irq_mask = mpuio_mask_irq, | |
1206 | .irq_unmask = mpuio_unmask_irq, | |
1207 | .irq_set_type = gpio_irq_type, | |
11a78b79 DB |
1208 | #ifdef CONFIG_ARCH_OMAP16XX |
1209 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
e9191028 | 1210 | .irq_set_wake = gpio_wake_enable, |
11a78b79 | 1211 | #endif |
5e1c5ff4 TL |
1212 | }; |
1213 | ||
e5c56ed3 DB |
1214 | |
1215 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1216 | ||
11a78b79 DB |
1217 | |
1218 | #ifdef CONFIG_ARCH_OMAP16XX | |
1219 | ||
1220 | #include <linux/platform_device.h> | |
1221 | ||
79ee031f | 1222 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1223 | { |
79ee031f | 1224 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1225 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1226 | void __iomem *mask_reg = bank->base + |
1227 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1228 | unsigned long flags; |
11a78b79 | 1229 | |
a6472533 | 1230 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1231 | bank->saved_wakeup = __raw_readl(mask_reg); |
1232 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1233 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1234 | |
1235 | return 0; | |
1236 | } | |
1237 | ||
79ee031f | 1238 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1239 | { |
79ee031f | 1240 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1241 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1242 | void __iomem *mask_reg = bank->base + |
1243 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1244 | unsigned long flags; |
11a78b79 | 1245 | |
a6472533 | 1246 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1247 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1248 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1249 | |
1250 | return 0; | |
1251 | } | |
1252 | ||
47145210 | 1253 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1254 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1255 | .resume_noirq = omap_mpuio_resume_noirq, | |
1256 | }; | |
1257 | ||
3c437ffd | 1258 | /* use platform_driver for this. */ |
11a78b79 | 1259 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
1260 | .driver = { |
1261 | .name = "mpuio", | |
79ee031f | 1262 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1263 | }, |
1264 | }; | |
1265 | ||
1266 | static struct platform_device omap_mpuio_device = { | |
1267 | .name = "mpuio", | |
1268 | .id = -1, | |
1269 | .dev = { | |
1270 | .driver = &omap_mpuio_driver.driver, | |
1271 | } | |
1272 | /* could list the /proc/iomem resources */ | |
1273 | }; | |
1274 | ||
1275 | static inline void mpuio_init(void) | |
1276 | { | |
77640aab VC |
1277 | struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); |
1278 | platform_set_drvdata(&omap_mpuio_device, bank); | |
fcf126d8 | 1279 | |
11a78b79 DB |
1280 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1281 | (void) platform_device_register(&omap_mpuio_device); | |
1282 | } | |
1283 | ||
1284 | #else | |
1285 | static inline void mpuio_init(void) {} | |
1286 | #endif /* 16xx */ | |
1287 | ||
e5c56ed3 DB |
1288 | #else |
1289 | ||
1290 | extern struct irq_chip mpuio_irq_chip; | |
1291 | ||
1292 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1293 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1294 | |
1295 | #endif | |
1296 | ||
1297 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1298 | |
52e31344 DB |
1299 | /* REVISIT these are stupid implementations! replace by ones that |
1300 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1301 | */ | |
1302 | ||
1303 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1304 | { | |
1305 | struct gpio_bank *bank; | |
1306 | unsigned long flags; | |
1307 | ||
1308 | bank = container_of(chip, struct gpio_bank, chip); | |
1309 | spin_lock_irqsave(&bank->lock, flags); | |
1310 | _set_gpio_direction(bank, offset, 1); | |
1311 | spin_unlock_irqrestore(&bank->lock, flags); | |
1312 | return 0; | |
1313 | } | |
1314 | ||
b37c45b8 RQ |
1315 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1316 | { | |
1317 | void __iomem *reg = bank->base; | |
1318 | ||
1319 | switch (bank->method) { | |
1320 | case METHOD_MPUIO: | |
5de62b86 | 1321 | reg += OMAP_MPUIO_IO_CNTL / bank->stride; |
b37c45b8 RQ |
1322 | break; |
1323 | case METHOD_GPIO_1510: | |
1324 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1325 | break; | |
1326 | case METHOD_GPIO_1610: | |
1327 | reg += OMAP1610_GPIO_DIRECTION; | |
1328 | break; | |
7c006926 AB |
1329 | case METHOD_GPIO_7XX: |
1330 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1331 | break; |
1332 | case METHOD_GPIO_24XX: | |
1333 | reg += OMAP24XX_GPIO_OE; | |
1334 | break; | |
9f096868 C |
1335 | case METHOD_GPIO_44XX: |
1336 | reg += OMAP4_GPIO_OE; | |
1337 | break; | |
1338 | default: | |
1339 | WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); | |
1340 | return -EINVAL; | |
b37c45b8 RQ |
1341 | } |
1342 | return __raw_readl(reg) & mask; | |
1343 | } | |
1344 | ||
52e31344 DB |
1345 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1346 | { | |
b37c45b8 RQ |
1347 | struct gpio_bank *bank; |
1348 | void __iomem *reg; | |
1349 | int gpio; | |
1350 | u32 mask; | |
1351 | ||
1352 | gpio = chip->base + offset; | |
1353 | bank = get_gpio_bank(gpio); | |
1354 | reg = bank->base; | |
1355 | mask = 1 << get_gpio_index(gpio); | |
1356 | ||
1357 | if (gpio_is_input(bank, mask)) | |
1358 | return _get_gpio_datain(bank, gpio); | |
1359 | else | |
1360 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1361 | } |
1362 | ||
1363 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1364 | { | |
1365 | struct gpio_bank *bank; | |
1366 | unsigned long flags; | |
1367 | ||
1368 | bank = container_of(chip, struct gpio_bank, chip); | |
1369 | spin_lock_irqsave(&bank->lock, flags); | |
1370 | _set_gpio_dataout(bank, offset, value); | |
1371 | _set_gpio_direction(bank, offset, 0); | |
1372 | spin_unlock_irqrestore(&bank->lock, flags); | |
1373 | return 0; | |
1374 | } | |
1375 | ||
168ef3d9 FB |
1376 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1377 | unsigned debounce) | |
1378 | { | |
1379 | struct gpio_bank *bank; | |
1380 | unsigned long flags; | |
1381 | ||
1382 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
1383 | |
1384 | if (!bank->dbck) { | |
1385 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1386 | if (IS_ERR(bank->dbck)) | |
1387 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
1388 | } | |
1389 | ||
168ef3d9 FB |
1390 | spin_lock_irqsave(&bank->lock, flags); |
1391 | _set_gpio_debounce(bank, offset, debounce); | |
1392 | spin_unlock_irqrestore(&bank->lock, flags); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
52e31344 DB |
1397 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1398 | { | |
1399 | struct gpio_bank *bank; | |
1400 | unsigned long flags; | |
1401 | ||
1402 | bank = container_of(chip, struct gpio_bank, chip); | |
1403 | spin_lock_irqsave(&bank->lock, flags); | |
1404 | _set_gpio_dataout(bank, offset, value); | |
1405 | spin_unlock_irqrestore(&bank->lock, flags); | |
1406 | } | |
1407 | ||
a007b709 DB |
1408 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1409 | { | |
1410 | struct gpio_bank *bank; | |
1411 | ||
1412 | bank = container_of(chip, struct gpio_bank, chip); | |
1413 | return bank->virtual_irq_start + offset; | |
1414 | } | |
1415 | ||
52e31344 DB |
1416 | /*---------------------------------------------------------------------*/ |
1417 | ||
9a748053 | 1418 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da TL |
1419 | { |
1420 | u32 rev; | |
1421 | ||
9a748053 TL |
1422 | if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) |
1423 | rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION); | |
9f7065da | 1424 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
9a748053 | 1425 | rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION); |
9f7065da | 1426 | else if (cpu_is_omap44xx()) |
9a748053 | 1427 | rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION); |
9f7065da TL |
1428 | else |
1429 | return; | |
1430 | ||
1431 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1432 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1433 | } | |
1434 | ||
8ba55c5c DB |
1435 | /* This lock class tells lockdep that GPIO irqs are in a different |
1436 | * category than their parents, so it won't report false recursion. | |
1437 | */ | |
1438 | static struct lock_class_key gpio_lock_class; | |
1439 | ||
77640aab VC |
1440 | static inline int init_gpio_info(struct platform_device *pdev) |
1441 | { | |
1442 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ | |
1443 | gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), | |
1444 | GFP_KERNEL); | |
1445 | if (!gpio_bank) { | |
1446 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1447 | return -ENOMEM; | |
1448 | } | |
1449 | return 0; | |
1450 | } | |
1451 | ||
1452 | /* TODO: Cleanup cpu_is_* checks */ | |
2fae7fbe VC |
1453 | static void omap_gpio_mod_init(struct gpio_bank *bank, int id) |
1454 | { | |
1455 | if (cpu_class_is_omap2()) { | |
1456 | if (cpu_is_omap44xx()) { | |
1457 | __raw_writel(0xffffffff, bank->base + | |
1458 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1459 | __raw_writel(0x00000000, bank->base + | |
1460 | OMAP4_GPIO_DEBOUNCENABLE); | |
1461 | /* Initialize interface clk ungated, module enabled */ | |
1462 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1463 | } else if (cpu_is_omap34xx()) { | |
1464 | __raw_writel(0x00000000, bank->base + | |
1465 | OMAP24XX_GPIO_IRQENABLE1); | |
1466 | __raw_writel(0xffffffff, bank->base + | |
1467 | OMAP24XX_GPIO_IRQSTATUS1); | |
1468 | __raw_writel(0x00000000, bank->base + | |
1469 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1470 | ||
1471 | /* Initialize interface clk ungated, module enabled */ | |
1472 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
1473 | } else if (cpu_is_omap24xx()) { | |
1474 | static const u32 non_wakeup_gpios[] = { | |
1475 | 0xe203ffc0, 0x08700040 | |
1476 | }; | |
1477 | if (id < ARRAY_SIZE(non_wakeup_gpios)) | |
1478 | bank->non_wakeup_gpios = non_wakeup_gpios[id]; | |
1479 | } | |
1480 | } else if (cpu_class_is_omap1()) { | |
1481 | if (bank_is_mpuio(bank)) | |
5de62b86 TL |
1482 | __raw_writew(0xffff, bank->base + |
1483 | OMAP_MPUIO_GPIO_MASKIT / bank->stride); | |
2fae7fbe VC |
1484 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
1485 | __raw_writew(0xffff, bank->base | |
1486 | + OMAP1510_GPIO_INT_MASK); | |
1487 | __raw_writew(0x0000, bank->base | |
1488 | + OMAP1510_GPIO_INT_STATUS); | |
1489 | } | |
1490 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | |
1491 | __raw_writew(0x0000, bank->base | |
1492 | + OMAP1610_GPIO_IRQENABLE1); | |
1493 | __raw_writew(0xffff, bank->base | |
1494 | + OMAP1610_GPIO_IRQSTATUS1); | |
1495 | __raw_writew(0x0014, bank->base | |
1496 | + OMAP1610_GPIO_SYSCONFIG); | |
1497 | ||
1498 | /* | |
1499 | * Enable system clock for GPIO module. | |
1500 | * The CAM_CLK_CTRL *is* really the right place. | |
1501 | */ | |
1502 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | |
1503 | ULPD_CAM_CLK_CTRL); | |
1504 | } | |
1505 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | |
1506 | __raw_writel(0xffffffff, bank->base | |
1507 | + OMAP7XX_GPIO_INT_MASK); | |
1508 | __raw_writel(0x00000000, bank->base | |
1509 | + OMAP7XX_GPIO_INT_STATUS); | |
1510 | } | |
1511 | } | |
1512 | } | |
1513 | ||
d52b31de | 1514 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1515 | { |
77640aab | 1516 | int j; |
2fae7fbe VC |
1517 | static int gpio; |
1518 | ||
2fae7fbe VC |
1519 | bank->mod_usage = 0; |
1520 | /* | |
1521 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1522 | * over to the generic ones | |
1523 | */ | |
1524 | bank->chip.request = omap_gpio_request; | |
1525 | bank->chip.free = omap_gpio_free; | |
1526 | bank->chip.direction_input = gpio_input; | |
1527 | bank->chip.get = gpio_get; | |
1528 | bank->chip.direction_output = gpio_output; | |
1529 | bank->chip.set_debounce = gpio_debounce; | |
1530 | bank->chip.set = gpio_set; | |
1531 | bank->chip.to_irq = gpio_2irq; | |
1532 | if (bank_is_mpuio(bank)) { | |
1533 | bank->chip.label = "mpuio"; | |
1534 | #ifdef CONFIG_ARCH_OMAP16XX | |
1535 | bank->chip.dev = &omap_mpuio_device.dev; | |
1536 | #endif | |
1537 | bank->chip.base = OMAP_MPUIO(0); | |
1538 | } else { | |
1539 | bank->chip.label = "gpio"; | |
1540 | bank->chip.base = gpio; | |
d5f46247 | 1541 | gpio += bank->width; |
2fae7fbe | 1542 | } |
d5f46247 | 1543 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1544 | |
1545 | gpiochip_add(&bank->chip); | |
1546 | ||
1547 | for (j = bank->virtual_irq_start; | |
d5f46247 | 1548 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 1549 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1550 | irq_set_chip_data(j, bank); |
2fae7fbe | 1551 | if (bank_is_mpuio(bank)) |
6845664a | 1552 | irq_set_chip(j, &mpuio_irq_chip); |
2fae7fbe | 1553 | else |
6845664a TG |
1554 | irq_set_chip(j, &gpio_irq_chip); |
1555 | irq_set_handler(j, handle_simple_irq); | |
2fae7fbe VC |
1556 | set_irq_flags(j, IRQF_VALID); |
1557 | } | |
6845664a TG |
1558 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1559 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1560 | } |
1561 | ||
77640aab | 1562 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1563 | { |
77640aab VC |
1564 | static int gpio_init_done; |
1565 | struct omap_gpio_platform_data *pdata; | |
1566 | struct resource *res; | |
1567 | int id; | |
5e1c5ff4 TL |
1568 | struct gpio_bank *bank; |
1569 | ||
77640aab VC |
1570 | if (!pdev->dev.platform_data) |
1571 | return -EINVAL; | |
5e1c5ff4 | 1572 | |
77640aab | 1573 | pdata = pdev->dev.platform_data; |
56a25641 | 1574 | |
77640aab VC |
1575 | if (!gpio_init_done) { |
1576 | int ret; | |
5492fb1a | 1577 | |
77640aab VC |
1578 | ret = init_gpio_info(pdev); |
1579 | if (ret) | |
1580 | return ret; | |
5492fb1a | 1581 | } |
5492fb1a | 1582 | |
77640aab VC |
1583 | id = pdev->id; |
1584 | bank = &gpio_bank[id]; | |
92105bb7 | 1585 | |
77640aab VC |
1586 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1587 | if (unlikely(!res)) { | |
1588 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); | |
1589 | return -ENODEV; | |
44169075 | 1590 | } |
5e1c5ff4 | 1591 | |
77640aab VC |
1592 | bank->irq = res->start; |
1593 | bank->virtual_irq_start = pdata->virtual_irq_start; | |
1594 | bank->method = pdata->bank_type; | |
1595 | bank->dev = &pdev->dev; | |
1596 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1597 | bank->stride = pdata->bank_stride; |
d5f46247 | 1598 | bank->width = pdata->bank_width; |
9f7065da | 1599 | |
77640aab | 1600 | spin_lock_init(&bank->lock); |
9f7065da | 1601 | |
77640aab VC |
1602 | /* Static mapping, never released */ |
1603 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1604 | if (unlikely(!res)) { | |
1605 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); | |
1606 | return -ENODEV; | |
1607 | } | |
89db9482 | 1608 | |
77640aab VC |
1609 | bank->base = ioremap(res->start, resource_size(res)); |
1610 | if (!bank->base) { | |
1611 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); | |
1612 | return -ENOMEM; | |
5e1c5ff4 TL |
1613 | } |
1614 | ||
77640aab VC |
1615 | pm_runtime_enable(bank->dev); |
1616 | pm_runtime_get_sync(bank->dev); | |
1617 | ||
1618 | omap_gpio_mod_init(bank, id); | |
1619 | omap_gpio_chip_init(bank); | |
9a748053 | 1620 | omap_gpio_show_rev(bank); |
9f7065da | 1621 | |
77640aab VC |
1622 | if (!gpio_init_done) |
1623 | gpio_init_done = 1; | |
1624 | ||
5e1c5ff4 TL |
1625 | return 0; |
1626 | } | |
1627 | ||
140455fa | 1628 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd | 1629 | static int omap_gpio_suspend(void) |
92105bb7 TL |
1630 | { |
1631 | int i; | |
1632 | ||
5492fb1a | 1633 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1634 | return 0; |
1635 | ||
1636 | for (i = 0; i < gpio_bank_count; i++) { | |
1637 | struct gpio_bank *bank = &gpio_bank[i]; | |
1638 | void __iomem *wake_status; | |
1639 | void __iomem *wake_clear; | |
1640 | void __iomem *wake_set; | |
a6472533 | 1641 | unsigned long flags; |
92105bb7 TL |
1642 | |
1643 | switch (bank->method) { | |
e5c56ed3 | 1644 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1645 | case METHOD_GPIO_1610: |
1646 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1647 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1648 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1649 | break; | |
e5c56ed3 | 1650 | #endif |
a8eb7ca0 | 1651 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1652 | case METHOD_GPIO_24XX: |
723fdb78 | 1653 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1654 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1655 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1656 | break; | |
78a1a6d3 SR |
1657 | #endif |
1658 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1659 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1660 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1661 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1662 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1663 | break; | |
e5c56ed3 | 1664 | #endif |
92105bb7 TL |
1665 | default: |
1666 | continue; | |
1667 | } | |
1668 | ||
a6472533 | 1669 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1670 | bank->saved_wakeup = __raw_readl(wake_status); |
1671 | __raw_writel(0xffffffff, wake_clear); | |
1672 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1673 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1674 | } |
1675 | ||
1676 | return 0; | |
1677 | } | |
1678 | ||
3c437ffd | 1679 | static void omap_gpio_resume(void) |
92105bb7 TL |
1680 | { |
1681 | int i; | |
1682 | ||
723fdb78 | 1683 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
3c437ffd | 1684 | return; |
92105bb7 TL |
1685 | |
1686 | for (i = 0; i < gpio_bank_count; i++) { | |
1687 | struct gpio_bank *bank = &gpio_bank[i]; | |
1688 | void __iomem *wake_clear; | |
1689 | void __iomem *wake_set; | |
a6472533 | 1690 | unsigned long flags; |
92105bb7 TL |
1691 | |
1692 | switch (bank->method) { | |
e5c56ed3 | 1693 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1694 | case METHOD_GPIO_1610: |
1695 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1696 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1697 | break; | |
e5c56ed3 | 1698 | #endif |
a8eb7ca0 | 1699 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1700 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1701 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1702 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1703 | break; |
78a1a6d3 SR |
1704 | #endif |
1705 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1706 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1707 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1708 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1709 | break; | |
e5c56ed3 | 1710 | #endif |
92105bb7 TL |
1711 | default: |
1712 | continue; | |
1713 | } | |
1714 | ||
a6472533 | 1715 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1716 | __raw_writel(0xffffffff, wake_clear); |
1717 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1718 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1719 | } |
92105bb7 TL |
1720 | } |
1721 | ||
3c437ffd | 1722 | static struct syscore_ops omap_gpio_syscore_ops = { |
92105bb7 TL |
1723 | .suspend = omap_gpio_suspend, |
1724 | .resume = omap_gpio_resume, | |
1725 | }; | |
1726 | ||
3ac4fa99 JY |
1727 | #endif |
1728 | ||
140455fa | 1729 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
1730 | |
1731 | static int workaround_enabled; | |
1732 | ||
72e06d08 | 1733 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 JY |
1734 | { |
1735 | int i, c = 0; | |
a118b5f3 | 1736 | int min = 0; |
3ac4fa99 | 1737 | |
a118b5f3 TK |
1738 | if (cpu_is_omap34xx()) |
1739 | min = 1; | |
43ffcd9a | 1740 | |
a118b5f3 | 1741 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 | 1742 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1743 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1744 | int j; |
3ac4fa99 | 1745 | |
0aed0435 | 1746 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1747 | clk_disable(bank->dbck); |
1748 | ||
72e06d08 | 1749 | if (!off_mode) |
43ffcd9a KH |
1750 | continue; |
1751 | ||
1752 | /* If going to OFF, remove triggering for all | |
1753 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1754 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
1755 | if (!(bank->enabled_non_wakeup_gpios)) |
1756 | continue; | |
3f1686a9 TL |
1757 | |
1758 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1759 | bank->saved_datain = __raw_readl(bank->base + | |
1760 | OMAP24XX_GPIO_DATAIN); | |
1761 | l1 = __raw_readl(bank->base + | |
1762 | OMAP24XX_GPIO_FALLINGDETECT); | |
1763 | l2 = __raw_readl(bank->base + | |
1764 | OMAP24XX_GPIO_RISINGDETECT); | |
1765 | } | |
1766 | ||
1767 | if (cpu_is_omap44xx()) { | |
1768 | bank->saved_datain = __raw_readl(bank->base + | |
1769 | OMAP4_GPIO_DATAIN); | |
1770 | l1 = __raw_readl(bank->base + | |
1771 | OMAP4_GPIO_FALLINGDETECT); | |
1772 | l2 = __raw_readl(bank->base + | |
1773 | OMAP4_GPIO_RISINGDETECT); | |
1774 | } | |
1775 | ||
3ac4fa99 JY |
1776 | bank->saved_fallingdetect = l1; |
1777 | bank->saved_risingdetect = l2; | |
1778 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1779 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
1780 | |
1781 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1782 | __raw_writel(l1, bank->base + | |
1783 | OMAP24XX_GPIO_FALLINGDETECT); | |
1784 | __raw_writel(l2, bank->base + | |
1785 | OMAP24XX_GPIO_RISINGDETECT); | |
1786 | } | |
1787 | ||
1788 | if (cpu_is_omap44xx()) { | |
1789 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1790 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
1791 | } | |
1792 | ||
3ac4fa99 JY |
1793 | c++; |
1794 | } | |
1795 | if (!c) { | |
1796 | workaround_enabled = 0; | |
1797 | return; | |
1798 | } | |
1799 | workaround_enabled = 1; | |
1800 | } | |
1801 | ||
43ffcd9a | 1802 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
1803 | { |
1804 | int i; | |
a118b5f3 | 1805 | int min = 0; |
3ac4fa99 | 1806 | |
a118b5f3 TK |
1807 | if (cpu_is_omap34xx()) |
1808 | min = 1; | |
1809 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 1810 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1811 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1812 | int j; |
3ac4fa99 | 1813 | |
0aed0435 | 1814 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1815 | clk_enable(bank->dbck); |
1816 | ||
43ffcd9a KH |
1817 | if (!workaround_enabled) |
1818 | continue; | |
1819 | ||
3ac4fa99 JY |
1820 | if (!(bank->enabled_non_wakeup_gpios)) |
1821 | continue; | |
3f1686a9 TL |
1822 | |
1823 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1824 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 1825 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 1826 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 1827 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
1828 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1829 | } | |
1830 | ||
1831 | if (cpu_is_omap44xx()) { | |
1832 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 1833 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 1834 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 1835 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
1836 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
1837 | } | |
1838 | ||
3ac4fa99 JY |
1839 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1840 | * state. If so, generate an IRQ by software. This is | |
1841 | * horribly racy, but it's the best we can do to work around | |
1842 | * this silicon bug. */ | |
3ac4fa99 | 1843 | l ^= bank->saved_datain; |
a118b5f3 | 1844 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1845 | |
1846 | /* | |
1847 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1848 | * configured with falling edge only; and vice versa. | |
1849 | */ | |
1850 | gen0 = l & bank->saved_fallingdetect; | |
1851 | gen0 &= bank->saved_datain; | |
1852 | ||
1853 | gen1 = l & bank->saved_risingdetect; | |
1854 | gen1 &= ~(bank->saved_datain); | |
1855 | ||
1856 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1857 | gen = l & (~(bank->saved_fallingdetect) & | |
1858 | ~(bank->saved_risingdetect)); | |
1859 | /* Consider all GPIO IRQs needed to be updated */ | |
1860 | gen |= gen0 | gen1; | |
1861 | ||
1862 | if (gen) { | |
3ac4fa99 | 1863 | u32 old0, old1; |
3f1686a9 | 1864 | |
f00d6497 | 1865 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
1866 | old0 = __raw_readl(bank->base + |
1867 | OMAP24XX_GPIO_LEVELDETECT0); | |
1868 | old1 = __raw_readl(bank->base + | |
1869 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 1870 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 1871 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1872 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 1873 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 1874 | __raw_writel(old0, bank->base + |
3f1686a9 | 1875 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1876 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
1877 | OMAP24XX_GPIO_LEVELDETECT1); |
1878 | } | |
1879 | ||
1880 | if (cpu_is_omap44xx()) { | |
1881 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 1882 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1883 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 1884 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1885 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 1886 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1887 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 1888 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1889 | __raw_writel(old0, bank->base + |
78a1a6d3 | 1890 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1891 | __raw_writel(old1, bank->base + |
78a1a6d3 | 1892 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1893 | } |
3ac4fa99 JY |
1894 | } |
1895 | } | |
1896 | ||
1897 | } | |
1898 | ||
92105bb7 TL |
1899 | #endif |
1900 | ||
a8eb7ca0 | 1901 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
1902 | /* save the registers of bank 2-6 */ |
1903 | void omap_gpio_save_context(void) | |
1904 | { | |
1905 | int i; | |
1906 | ||
1907 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
1908 | for (i = 1; i < gpio_bank_count; i++) { | |
1909 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1910 | gpio_context[i].irqenable1 = |
1911 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1912 | gpio_context[i].irqenable2 = | |
1913 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1914 | gpio_context[i].wake_en = | |
1915 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1916 | gpio_context[i].ctrl = | |
1917 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1918 | gpio_context[i].oe = | |
1919 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
1920 | gpio_context[i].leveldetect0 = | |
1921 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1922 | gpio_context[i].leveldetect1 = | |
1923 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1924 | gpio_context[i].risingdetect = | |
1925 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1926 | gpio_context[i].fallingdetect = | |
1927 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1928 | gpio_context[i].dataout = | |
1929 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1930 | } |
1931 | } | |
1932 | ||
1933 | /* restore the required registers of bank 2-6 */ | |
1934 | void omap_gpio_restore_context(void) | |
1935 | { | |
1936 | int i; | |
1937 | ||
1938 | for (i = 1; i < gpio_bank_count; i++) { | |
1939 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1940 | __raw_writel(gpio_context[i].irqenable1, |
1941 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1942 | __raw_writel(gpio_context[i].irqenable2, | |
1943 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1944 | __raw_writel(gpio_context[i].wake_en, | |
1945 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1946 | __raw_writel(gpio_context[i].ctrl, | |
1947 | bank->base + OMAP24XX_GPIO_CTRL); | |
1948 | __raw_writel(gpio_context[i].oe, | |
1949 | bank->base + OMAP24XX_GPIO_OE); | |
1950 | __raw_writel(gpio_context[i].leveldetect0, | |
1951 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1952 | __raw_writel(gpio_context[i].leveldetect1, | |
1953 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1954 | __raw_writel(gpio_context[i].risingdetect, | |
1955 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1956 | __raw_writel(gpio_context[i].fallingdetect, | |
1957 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1958 | __raw_writel(gpio_context[i].dataout, | |
1959 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1960 | } |
1961 | } | |
1962 | #endif | |
1963 | ||
77640aab VC |
1964 | static struct platform_driver omap_gpio_driver = { |
1965 | .probe = omap_gpio_probe, | |
1966 | .driver = { | |
1967 | .name = "omap_gpio", | |
1968 | }, | |
1969 | }; | |
1970 | ||
5e1c5ff4 | 1971 | /* |
77640aab VC |
1972 | * gpio driver register needs to be done before |
1973 | * machine_init functions access gpio APIs. | |
1974 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1975 | */ |
77640aab | 1976 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1977 | { |
77640aab | 1978 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1979 | } |
77640aab | 1980 | postcore_initcall(omap_gpio_drv_reg); |
5e1c5ff4 | 1981 | |
92105bb7 TL |
1982 | static int __init omap_gpio_sysinit(void) |
1983 | { | |
11a78b79 DB |
1984 | mpuio_init(); |
1985 | ||
140455fa | 1986 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd RW |
1987 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) |
1988 | register_syscore_ops(&omap_gpio_syscore_ops); | |
92105bb7 TL |
1989 | #endif |
1990 | ||
3c437ffd | 1991 | return 0; |
92105bb7 TL |
1992 | } |
1993 | ||
92105bb7 | 1994 | arch_initcall(omap_gpio_sysinit); |