Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb | 27 | #include <mach/irqs.h> |
1bc857f7 | 28 | #include <asm/gpio.h> |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
03e128ca C |
31 | static LIST_HEAD(omap_gpio_list); |
32 | ||
6d62e216 C |
33 | struct gpio_regs { |
34 | u32 irqenable1; | |
35 | u32 irqenable2; | |
36 | u32 wake_en; | |
37 | u32 ctrl; | |
38 | u32 oe; | |
39 | u32 leveldetect0; | |
40 | u32 leveldetect1; | |
41 | u32 risingdetect; | |
42 | u32 fallingdetect; | |
43 | u32 dataout; | |
44 | }; | |
45 | ||
5e1c5ff4 | 46 | struct gpio_bank { |
03e128ca | 47 | struct list_head node; |
9f7065da | 48 | unsigned long pbase; |
92105bb7 | 49 | void __iomem *base; |
5e1c5ff4 TL |
50 | u16 irq; |
51 | u16 virtual_irq_start; | |
92105bb7 TL |
52 | u32 suspend_wakeup; |
53 | u32 saved_wakeup; | |
3ac4fa99 JY |
54 | u32 non_wakeup_gpios; |
55 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 56 | struct gpio_regs context; |
3ac4fa99 JY |
57 | u32 saved_datain; |
58 | u32 saved_fallingdetect; | |
59 | u32 saved_risingdetect; | |
b144ff6f | 60 | u32 level_mask; |
4318f36b | 61 | u32 toggle_mask; |
5e1c5ff4 | 62 | spinlock_t lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
77640aab | 67 | struct device *dev; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
5de62b86 | 71 | int stride; |
d5f46247 | 72 | u32 width; |
60a3437d | 73 | int context_loss_count; |
03e128ca | 74 | u16 id; |
fa87931a KH |
75 | |
76 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 77 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
78 | |
79 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
80 | }; |
81 | ||
129fd223 KH |
82 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
83 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 84 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 TL |
85 | |
86 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
87 | { | |
92105bb7 | 88 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
89 | u32 l; |
90 | ||
fa87931a | 91 | reg += bank->regs->direction; |
5e1c5ff4 TL |
92 | l = __raw_readl(reg); |
93 | if (is_input) | |
94 | l |= 1 << gpio; | |
95 | else | |
96 | l &= ~(1 << gpio); | |
97 | __raw_writel(l, reg); | |
98 | } | |
99 | ||
fa87931a KH |
100 | |
101 | /* set data out value using dedicate set/clear register */ | |
102 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 103 | { |
92105bb7 | 104 | void __iomem *reg = bank->base; |
fa87931a | 105 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 106 | |
fa87931a KH |
107 | if (enable) |
108 | reg += bank->regs->set_dataout; | |
109 | else | |
110 | reg += bank->regs->clr_dataout; | |
5e1c5ff4 | 111 | |
5e1c5ff4 TL |
112 | __raw_writel(l, reg); |
113 | } | |
114 | ||
fa87931a KH |
115 | /* set data out value using mask register */ |
116 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 117 | { |
fa87931a KH |
118 | void __iomem *reg = bank->base + bank->regs->dataout; |
119 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
120 | u32 l; | |
5e1c5ff4 | 121 | |
fa87931a KH |
122 | l = __raw_readl(reg); |
123 | if (enable) | |
124 | l |= gpio_bit; | |
125 | else | |
126 | l &= ~gpio_bit; | |
5e1c5ff4 | 127 | __raw_writel(l, reg); |
5e1c5ff4 TL |
128 | } |
129 | ||
b37c45b8 | 130 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
b37c45b8 | 131 | { |
fa87931a | 132 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 133 | |
fa87931a | 134 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
5e1c5ff4 | 135 | } |
b37c45b8 | 136 | |
b37c45b8 RQ |
137 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
138 | { | |
fa87931a | 139 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 140 | |
129fd223 | 141 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
142 | } |
143 | ||
ece9528e KH |
144 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
145 | { | |
146 | int l = __raw_readl(base + reg); | |
147 | ||
148 | if (set) | |
149 | l |= mask; | |
150 | else | |
151 | l &= ~mask; | |
152 | ||
153 | __raw_writel(l, base + reg); | |
154 | } | |
92105bb7 | 155 | |
168ef3d9 FB |
156 | /** |
157 | * _set_gpio_debounce - low level gpio debounce time | |
158 | * @bank: the gpio bank we're acting upon | |
159 | * @gpio: the gpio number on this @gpio | |
160 | * @debounce: debounce time to use | |
161 | * | |
162 | * OMAP's debounce time is in 31us steps so we need | |
163 | * to convert and round up to the closest unit. | |
164 | */ | |
165 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
166 | unsigned debounce) | |
167 | { | |
9942da0e | 168 | void __iomem *reg; |
168ef3d9 FB |
169 | u32 val; |
170 | u32 l; | |
171 | ||
77640aab VC |
172 | if (!bank->dbck_flag) |
173 | return; | |
174 | ||
168ef3d9 FB |
175 | if (debounce < 32) |
176 | debounce = 0x01; | |
177 | else if (debounce > 7936) | |
178 | debounce = 0xff; | |
179 | else | |
180 | debounce = (debounce / 0x1f) - 1; | |
181 | ||
129fd223 | 182 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 183 | |
9942da0e | 184 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
185 | __raw_writel(debounce, reg); |
186 | ||
9942da0e | 187 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
188 | val = __raw_readl(reg); |
189 | ||
190 | if (debounce) { | |
191 | val |= l; | |
77640aab | 192 | clk_enable(bank->dbck); |
168ef3d9 FB |
193 | } else { |
194 | val &= ~l; | |
77640aab | 195 | clk_disable(bank->dbck); |
168ef3d9 | 196 | } |
f7ec0b0b | 197 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
198 | |
199 | __raw_writel(val, reg); | |
200 | } | |
201 | ||
5e571f38 | 202 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
5eb3bb9c | 203 | int trigger) |
5e1c5ff4 | 204 | { |
3ac4fa99 | 205 | void __iomem *base = bank->base; |
92105bb7 TL |
206 | u32 gpio_bit = 1 << gpio; |
207 | ||
5e571f38 TKD |
208 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
209 | trigger & IRQ_TYPE_LEVEL_LOW); | |
210 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
211 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
212 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
213 | trigger & IRQ_TYPE_EDGE_RISING); | |
214 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
215 | trigger & IRQ_TYPE_EDGE_FALLING); | |
216 | ||
217 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) | |
218 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); | |
219 | ||
55b220ca | 220 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
221 | if (!bank->regs->irqctrl) { |
222 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
223 | if (bank->non_wakeup_gpios) { | |
224 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
225 | goto exit; | |
226 | } | |
227 | ||
699117a6 CW |
228 | /* |
229 | * Log the edge gpio and manually trigger the IRQ | |
230 | * after resume if the input level changes | |
231 | * to avoid irq lost during PER RET/OFF mode | |
232 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
233 | */ | |
234 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
235 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
236 | else | |
237 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
238 | } | |
5eb3bb9c | 239 | |
5e571f38 | 240 | exit: |
9ea14d8c TKD |
241 | bank->level_mask = |
242 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
243 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
244 | } |
245 | ||
9198bcd3 | 246 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
247 | /* |
248 | * This only applies to chips that can't do both rising and falling edge | |
249 | * detection at once. For all other chips, this function is a noop. | |
250 | */ | |
251 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
252 | { | |
253 | void __iomem *reg = bank->base; | |
254 | u32 l = 0; | |
255 | ||
5e571f38 | 256 | if (!bank->regs->irqctrl) |
4318f36b | 257 | return; |
5e571f38 TKD |
258 | |
259 | reg += bank->regs->irqctrl; | |
4318f36b CM |
260 | |
261 | l = __raw_readl(reg); | |
262 | if ((l >> gpio) & 1) | |
263 | l &= ~(1 << gpio); | |
264 | else | |
265 | l |= 1 << gpio; | |
266 | ||
267 | __raw_writel(l, reg); | |
268 | } | |
5e571f38 TKD |
269 | #else |
270 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 271 | #endif |
4318f36b | 272 | |
92105bb7 TL |
273 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
274 | { | |
275 | void __iomem *reg = bank->base; | |
5e571f38 | 276 | void __iomem *base = bank->base; |
92105bb7 | 277 | u32 l = 0; |
5e1c5ff4 | 278 | |
5e571f38 TKD |
279 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
280 | set_gpio_trigger(bank, gpio, trigger); | |
281 | } else if (bank->regs->irqctrl) { | |
282 | reg += bank->regs->irqctrl; | |
283 | ||
5e1c5ff4 | 284 | l = __raw_readl(reg); |
29501577 | 285 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 286 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 287 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 288 | l |= 1 << gpio; |
6cab4860 | 289 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 290 | l &= ~(1 << gpio); |
92105bb7 | 291 | else |
5e571f38 TKD |
292 | return -EINVAL; |
293 | ||
294 | __raw_writel(l, reg); | |
295 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 296 | if (gpio & 0x08) |
5e571f38 | 297 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 298 | else |
5e571f38 TKD |
299 | reg += bank->regs->edgectrl1; |
300 | ||
5e1c5ff4 TL |
301 | gpio &= 0x07; |
302 | l = __raw_readl(reg); | |
303 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 304 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 305 | l |= 2 << (gpio << 1); |
6cab4860 | 306 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 307 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
308 | |
309 | /* Enable wake-up during idle for dynamic tick */ | |
310 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
311 | __raw_writel(l, reg); | |
5e1c5ff4 | 312 | } |
92105bb7 | 313 | return 0; |
5e1c5ff4 TL |
314 | } |
315 | ||
e9191028 | 316 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
317 | { |
318 | struct gpio_bank *bank; | |
92105bb7 TL |
319 | unsigned gpio; |
320 | int retval; | |
a6472533 | 321 | unsigned long flags; |
92105bb7 | 322 | |
e9191028 LB |
323 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
324 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 325 | else |
e9191028 | 326 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 | 327 | |
e5c56ed3 | 328 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 329 | return -EINVAL; |
e5c56ed3 | 330 | |
9ea14d8c TKD |
331 | bank = irq_data_get_irq_chip_data(d); |
332 | ||
333 | if (!bank->regs->leveldetect0 && | |
334 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
335 | return -EINVAL; |
336 | ||
a6472533 | 337 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 338 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 339 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
340 | |
341 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 342 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 343 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 344 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 345 | |
92105bb7 | 346 | return retval; |
5e1c5ff4 TL |
347 | } |
348 | ||
349 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
350 | { | |
92105bb7 | 351 | void __iomem *reg = bank->base; |
5e1c5ff4 | 352 | |
eef4bec7 | 353 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 354 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
355 | |
356 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
357 | if (bank->regs->irqstatus2) { |
358 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 359 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 360 | } |
bedfd154 RQ |
361 | |
362 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
363 | __raw_readl(reg); | |
5e1c5ff4 TL |
364 | } |
365 | ||
366 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
367 | { | |
129fd223 | 368 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
369 | } |
370 | ||
ea6dedd7 ID |
371 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
372 | { | |
373 | void __iomem *reg = bank->base; | |
99c47707 | 374 | u32 l; |
c390aad0 | 375 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 376 | |
28f3b5a0 | 377 | reg += bank->regs->irqenable; |
99c47707 | 378 | l = __raw_readl(reg); |
28f3b5a0 | 379 | if (bank->regs->irqenable_inv) |
99c47707 ID |
380 | l = ~l; |
381 | l &= mask; | |
382 | return l; | |
ea6dedd7 ID |
383 | } |
384 | ||
28f3b5a0 | 385 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 386 | { |
92105bb7 | 387 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
388 | u32 l; |
389 | ||
28f3b5a0 KH |
390 | if (bank->regs->set_irqenable) { |
391 | reg += bank->regs->set_irqenable; | |
392 | l = gpio_mask; | |
393 | } else { | |
394 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 395 | l = __raw_readl(reg); |
28f3b5a0 KH |
396 | if (bank->regs->irqenable_inv) |
397 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
398 | else |
399 | l |= gpio_mask; | |
28f3b5a0 KH |
400 | } |
401 | ||
402 | __raw_writel(l, reg); | |
403 | } | |
404 | ||
405 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
406 | { | |
407 | void __iomem *reg = bank->base; | |
408 | u32 l; | |
409 | ||
410 | if (bank->regs->clr_irqenable) { | |
411 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 412 | l = gpio_mask; |
28f3b5a0 KH |
413 | } else { |
414 | reg += bank->regs->irqenable; | |
56739a69 | 415 | l = __raw_readl(reg); |
28f3b5a0 | 416 | if (bank->regs->irqenable_inv) |
56739a69 | 417 | l |= gpio_mask; |
92105bb7 | 418 | else |
28f3b5a0 | 419 | l &= ~gpio_mask; |
5e1c5ff4 | 420 | } |
28f3b5a0 | 421 | |
5e1c5ff4 TL |
422 | __raw_writel(l, reg); |
423 | } | |
424 | ||
425 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
426 | { | |
28f3b5a0 | 427 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
428 | } |
429 | ||
92105bb7 TL |
430 | /* |
431 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
432 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
433 | * to the target, system will wake up always on GPIO events. While | |
434 | * system is running all registered GPIO interrupts need to have wake-up | |
435 | * enabled. When system is suspended, only selected GPIO interrupts need | |
436 | * to have wake-up enabled. | |
437 | */ | |
438 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
439 | { | |
f64ad1a0 KH |
440 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
441 | unsigned long flags; | |
a6472533 | 442 | |
f64ad1a0 KH |
443 | if (bank->non_wakeup_gpios & gpio_bit) { |
444 | dev_err(bank->dev, | |
445 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); | |
92105bb7 TL |
446 | return -EINVAL; |
447 | } | |
f64ad1a0 KH |
448 | |
449 | spin_lock_irqsave(&bank->lock, flags); | |
450 | if (enable) | |
451 | bank->suspend_wakeup |= gpio_bit; | |
452 | else | |
453 | bank->suspend_wakeup &= ~gpio_bit; | |
454 | ||
455 | spin_unlock_irqrestore(&bank->lock, flags); | |
456 | ||
457 | return 0; | |
92105bb7 TL |
458 | } |
459 | ||
4196dd6b TL |
460 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
461 | { | |
129fd223 | 462 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
463 | _set_gpio_irqenable(bank, gpio, 0); |
464 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 465 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
466 | } |
467 | ||
92105bb7 | 468 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 469 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 470 | { |
e9191028 | 471 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
472 | struct gpio_bank *bank; |
473 | int retval; | |
474 | ||
e9191028 | 475 | bank = irq_data_get_irq_chip_data(d); |
f64ad1a0 | 476 | retval = _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
477 | |
478 | return retval; | |
479 | } | |
480 | ||
3ff164e1 | 481 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 482 | { |
3ff164e1 | 483 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 484 | unsigned long flags; |
52e31344 | 485 | |
a6472533 | 486 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 487 | |
4196dd6b TL |
488 | /* Set trigger to none. You need to enable the desired trigger with |
489 | * request_irq() or set_irq_type(). | |
490 | */ | |
3ff164e1 | 491 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 492 | |
fad96ea8 C |
493 | if (bank->regs->pinctrl) { |
494 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 495 | |
92105bb7 | 496 | /* Claim the pin for MPU */ |
3ff164e1 | 497 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 498 | } |
fad96ea8 | 499 | |
c8eef65a C |
500 | if (bank->regs->ctrl && !bank->mod_usage) { |
501 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
502 | u32 ctrl; | |
503 | ||
504 | ctrl = __raw_readl(reg); | |
505 | /* Module is enabled, clocks are not gated */ | |
506 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
507 | __raw_writel(ctrl, reg); | |
058af1ea | 508 | } |
c8eef65a C |
509 | |
510 | bank->mod_usage |= 1 << offset; | |
511 | ||
a6472533 | 512 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
513 | |
514 | return 0; | |
515 | } | |
516 | ||
3ff164e1 | 517 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 518 | { |
3ff164e1 | 519 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 520 | void __iomem *base = bank->base; |
a6472533 | 521 | unsigned long flags; |
5e1c5ff4 | 522 | |
a6472533 | 523 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b TKD |
524 | |
525 | if (bank->regs->wkup_en) | |
9f096868 | 526 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b TKD |
527 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
528 | ||
c8eef65a C |
529 | bank->mod_usage &= ~(1 << offset); |
530 | ||
531 | if (bank->regs->ctrl && !bank->mod_usage) { | |
532 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
533 | u32 ctrl; | |
534 | ||
535 | ctrl = __raw_readl(reg); | |
536 | /* Module is disabled, clocks are gated */ | |
537 | ctrl |= GPIO_MOD_CTRL_BIT; | |
538 | __raw_writel(ctrl, reg); | |
058af1ea | 539 | } |
c8eef65a | 540 | |
3ff164e1 | 541 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 542 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
543 | } |
544 | ||
545 | /* | |
546 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
547 | * avoid missing GPIO interrupts for other lines in the bank. | |
548 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
549 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
550 | * If we wait to unmask individual GPIO lines in the bank after the | |
551 | * line's interrupt handler has been run, we may miss some nested | |
552 | * interrupts. | |
553 | */ | |
10dd5ce2 | 554 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 555 | { |
92105bb7 | 556 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 557 | u32 isr; |
4318f36b | 558 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 559 | struct gpio_bank *bank; |
ea6dedd7 ID |
560 | u32 retrigger = 0; |
561 | int unmasked = 0; | |
ee144182 | 562 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 563 | |
ee144182 | 564 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 565 | |
6845664a | 566 | bank = irq_get_handler_data(irq); |
eef4bec7 | 567 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
568 | |
569 | if (WARN_ON(!isr_reg)) | |
570 | goto exit; | |
571 | ||
92105bb7 | 572 | while(1) { |
6e60e79a | 573 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 574 | u32 enabled; |
6e60e79a | 575 | |
ea6dedd7 ID |
576 | enabled = _get_gpio_irqbank_mask(bank); |
577 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 578 | |
9ea14d8c | 579 | if (bank->level_mask) |
b144ff6f | 580 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
581 | |
582 | /* clear edge sensitive interrupts before handler(s) are | |
583 | called so that we don't miss any interrupt occurred while | |
584 | executing them */ | |
28f3b5a0 | 585 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 586 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 587 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
588 | |
589 | /* if there is only edge sensitive GPIO pin interrupts | |
590 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
591 | if (!level_mask && !unmasked) { |
592 | unmasked = 1; | |
ee144182 | 593 | chained_irq_exit(chip, desc); |
ea6dedd7 | 594 | } |
92105bb7 | 595 | |
ea6dedd7 ID |
596 | isr |= retrigger; |
597 | retrigger = 0; | |
92105bb7 TL |
598 | if (!isr) |
599 | break; | |
600 | ||
601 | gpio_irq = bank->virtual_irq_start; | |
602 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 603 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 604 | |
92105bb7 TL |
605 | if (!(isr & 1)) |
606 | continue; | |
29454dde | 607 | |
4318f36b CM |
608 | /* |
609 | * Some chips can't respond to both rising and falling | |
610 | * at the same time. If this irq was requested with | |
611 | * both flags, we need to flip the ICR data for the IRQ | |
612 | * to respond to the IRQ for the opposite direction. | |
613 | * This will be indicated in the bank toggle_mask. | |
614 | */ | |
615 | if (bank->toggle_mask & (1 << gpio_index)) | |
616 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 617 | |
d8aa0251 | 618 | generic_handle_irq(gpio_irq); |
92105bb7 | 619 | } |
1a8bfa1e | 620 | } |
ea6dedd7 ID |
621 | /* if bank has any level sensitive GPIO pin interrupt |
622 | configured, we must unmask the bank interrupt only after | |
623 | handler(s) are executed in order to avoid spurious bank | |
624 | interrupt */ | |
b1cc4c55 | 625 | exit: |
ea6dedd7 | 626 | if (!unmasked) |
ee144182 | 627 | chained_irq_exit(chip, desc); |
5e1c5ff4 TL |
628 | } |
629 | ||
e9191028 | 630 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 631 | { |
e9191028 LB |
632 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
633 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 634 | unsigned long flags; |
4196dd6b | 635 | |
85ec7b97 | 636 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 637 | _reset_gpio(bank, gpio); |
85ec7b97 | 638 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
639 | } |
640 | ||
e9191028 | 641 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 642 | { |
e9191028 LB |
643 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
644 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
645 | |
646 | _clear_gpio_irqstatus(bank, gpio); | |
647 | } | |
648 | ||
e9191028 | 649 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 650 | { |
e9191028 LB |
651 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
652 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 653 | unsigned long flags; |
5e1c5ff4 | 654 | |
85ec7b97 | 655 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 656 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 657 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 658 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
659 | } |
660 | ||
e9191028 | 661 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 662 | { |
e9191028 LB |
663 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
664 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 665 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 666 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 667 | unsigned long flags; |
55b6019a | 668 | |
85ec7b97 | 669 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 670 | if (trigger) |
129fd223 | 671 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
672 | |
673 | /* For level-triggered GPIOs, the clearing must be done after | |
674 | * the HW source is cleared, thus after the handler has run */ | |
675 | if (bank->level_mask & irq_mask) { | |
676 | _set_gpio_irqenable(bank, gpio, 0); | |
677 | _clear_gpio_irqstatus(bank, gpio); | |
678 | } | |
5e1c5ff4 | 679 | |
4de8c75b | 680 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 681 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
682 | } |
683 | ||
e5c56ed3 DB |
684 | static struct irq_chip gpio_irq_chip = { |
685 | .name = "GPIO", | |
e9191028 LB |
686 | .irq_shutdown = gpio_irq_shutdown, |
687 | .irq_ack = gpio_ack_irq, | |
688 | .irq_mask = gpio_mask_irq, | |
689 | .irq_unmask = gpio_unmask_irq, | |
690 | .irq_set_type = gpio_irq_type, | |
691 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
692 | }; |
693 | ||
694 | /*---------------------------------------------------------------------*/ | |
695 | ||
79ee031f | 696 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 697 | { |
79ee031f | 698 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 699 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
700 | void __iomem *mask_reg = bank->base + |
701 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 702 | unsigned long flags; |
11a78b79 | 703 | |
a6472533 | 704 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
705 | bank->saved_wakeup = __raw_readl(mask_reg); |
706 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 707 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
708 | |
709 | return 0; | |
710 | } | |
711 | ||
79ee031f | 712 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 713 | { |
79ee031f | 714 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 715 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
716 | void __iomem *mask_reg = bank->base + |
717 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 718 | unsigned long flags; |
11a78b79 | 719 | |
a6472533 | 720 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 721 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 722 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
723 | |
724 | return 0; | |
725 | } | |
726 | ||
47145210 | 727 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
728 | .suspend_noirq = omap_mpuio_suspend_noirq, |
729 | .resume_noirq = omap_mpuio_resume_noirq, | |
730 | }; | |
731 | ||
3c437ffd | 732 | /* use platform_driver for this. */ |
11a78b79 | 733 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
734 | .driver = { |
735 | .name = "mpuio", | |
79ee031f | 736 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
737 | }, |
738 | }; | |
739 | ||
740 | static struct platform_device omap_mpuio_device = { | |
741 | .name = "mpuio", | |
742 | .id = -1, | |
743 | .dev = { | |
744 | .driver = &omap_mpuio_driver.driver, | |
745 | } | |
746 | /* could list the /proc/iomem resources */ | |
747 | }; | |
748 | ||
03e128ca | 749 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 750 | { |
77640aab | 751 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 752 | |
11a78b79 DB |
753 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
754 | (void) platform_device_register(&omap_mpuio_device); | |
755 | } | |
756 | ||
e5c56ed3 | 757 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 758 | |
52e31344 DB |
759 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
760 | { | |
761 | struct gpio_bank *bank; | |
762 | unsigned long flags; | |
763 | ||
764 | bank = container_of(chip, struct gpio_bank, chip); | |
765 | spin_lock_irqsave(&bank->lock, flags); | |
766 | _set_gpio_direction(bank, offset, 1); | |
767 | spin_unlock_irqrestore(&bank->lock, flags); | |
768 | return 0; | |
769 | } | |
770 | ||
b37c45b8 RQ |
771 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
772 | { | |
fa87931a | 773 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 774 | |
b37c45b8 RQ |
775 | return __raw_readl(reg) & mask; |
776 | } | |
777 | ||
52e31344 DB |
778 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
779 | { | |
b37c45b8 RQ |
780 | struct gpio_bank *bank; |
781 | void __iomem *reg; | |
782 | int gpio; | |
783 | u32 mask; | |
784 | ||
785 | gpio = chip->base + offset; | |
a8be8daf | 786 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 787 | reg = bank->base; |
129fd223 | 788 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
789 | |
790 | if (gpio_is_input(bank, mask)) | |
791 | return _get_gpio_datain(bank, gpio); | |
792 | else | |
793 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
794 | } |
795 | ||
796 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
797 | { | |
798 | struct gpio_bank *bank; | |
799 | unsigned long flags; | |
800 | ||
801 | bank = container_of(chip, struct gpio_bank, chip); | |
802 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 803 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
804 | _set_gpio_direction(bank, offset, 0); |
805 | spin_unlock_irqrestore(&bank->lock, flags); | |
806 | return 0; | |
807 | } | |
808 | ||
168ef3d9 FB |
809 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
810 | unsigned debounce) | |
811 | { | |
812 | struct gpio_bank *bank; | |
813 | unsigned long flags; | |
814 | ||
815 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
816 | |
817 | if (!bank->dbck) { | |
818 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
819 | if (IS_ERR(bank->dbck)) | |
820 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
821 | } | |
822 | ||
168ef3d9 FB |
823 | spin_lock_irqsave(&bank->lock, flags); |
824 | _set_gpio_debounce(bank, offset, debounce); | |
825 | spin_unlock_irqrestore(&bank->lock, flags); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
52e31344 DB |
830 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
831 | { | |
832 | struct gpio_bank *bank; | |
833 | unsigned long flags; | |
834 | ||
835 | bank = container_of(chip, struct gpio_bank, chip); | |
836 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 837 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
838 | spin_unlock_irqrestore(&bank->lock, flags); |
839 | } | |
840 | ||
a007b709 DB |
841 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
842 | { | |
843 | struct gpio_bank *bank; | |
844 | ||
845 | bank = container_of(chip, struct gpio_bank, chip); | |
846 | return bank->virtual_irq_start + offset; | |
847 | } | |
848 | ||
52e31344 DB |
849 | /*---------------------------------------------------------------------*/ |
850 | ||
9a748053 | 851 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 852 | { |
e5ff4440 | 853 | static bool called; |
9f7065da TL |
854 | u32 rev; |
855 | ||
e5ff4440 | 856 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
857 | return; |
858 | ||
e5ff4440 KH |
859 | rev = __raw_readw(bank->base + bank->regs->revision); |
860 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 861 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
862 | |
863 | called = true; | |
9f7065da TL |
864 | } |
865 | ||
8ba55c5c DB |
866 | /* This lock class tells lockdep that GPIO irqs are in a different |
867 | * category than their parents, so it won't report false recursion. | |
868 | */ | |
869 | static struct lock_class_key gpio_lock_class; | |
870 | ||
03e128ca | 871 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 872 | { |
ab985f0f TKD |
873 | void __iomem *base = bank->base; |
874 | u32 l = 0xffffffff; | |
2fae7fbe | 875 | |
ab985f0f TKD |
876 | if (bank->width == 16) |
877 | l = 0xffff; | |
878 | ||
d0d665a8 | 879 | if (bank->is_mpuio) { |
ab985f0f TKD |
880 | __raw_writel(l, bank->base + bank->regs->irqenable); |
881 | return; | |
2fae7fbe | 882 | } |
ab985f0f TKD |
883 | |
884 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
885 | _gpio_rmw(base, bank->regs->irqstatus, l, | |
886 | bank->regs->irqenable_inv == false); | |
887 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0); | |
888 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0); | |
889 | if (bank->regs->debounce_en) | |
890 | _gpio_rmw(base, bank->regs->debounce_en, 0, 1); | |
891 | ||
892 | /* Initialize interface clk ungated, module enabled */ | |
893 | if (bank->regs->ctrl) | |
894 | _gpio_rmw(base, bank->regs->ctrl, 0, 1); | |
2fae7fbe VC |
895 | } |
896 | ||
f8b46b58 KH |
897 | static __init void |
898 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |
899 | unsigned int num) | |
900 | { | |
901 | struct irq_chip_generic *gc; | |
902 | struct irq_chip_type *ct; | |
903 | ||
904 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
905 | handle_simple_irq); | |
83233749 TP |
906 | if (!gc) { |
907 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
908 | return; | |
909 | } | |
910 | ||
f8b46b58 KH |
911 | ct = gc->chip_types; |
912 | ||
913 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
914 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
915 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
916 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
917 | |
918 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
919 | ct->chip.irq_set_wake = gpio_wake_enable, |
920 | ||
921 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
922 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
923 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
924 | } | |
925 | ||
d52b31de | 926 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 927 | { |
77640aab | 928 | int j; |
2fae7fbe VC |
929 | static int gpio; |
930 | ||
2fae7fbe VC |
931 | /* |
932 | * REVISIT eventually switch from OMAP-specific gpio structs | |
933 | * over to the generic ones | |
934 | */ | |
935 | bank->chip.request = omap_gpio_request; | |
936 | bank->chip.free = omap_gpio_free; | |
937 | bank->chip.direction_input = gpio_input; | |
938 | bank->chip.get = gpio_get; | |
939 | bank->chip.direction_output = gpio_output; | |
940 | bank->chip.set_debounce = gpio_debounce; | |
941 | bank->chip.set = gpio_set; | |
942 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 943 | if (bank->is_mpuio) { |
2fae7fbe | 944 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
945 | if (bank->regs->wkup_en) |
946 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
947 | bank->chip.base = OMAP_MPUIO(0); |
948 | } else { | |
949 | bank->chip.label = "gpio"; | |
950 | bank->chip.base = gpio; | |
d5f46247 | 951 | gpio += bank->width; |
2fae7fbe | 952 | } |
d5f46247 | 953 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
954 | |
955 | gpiochip_add(&bank->chip); | |
956 | ||
957 | for (j = bank->virtual_irq_start; | |
d5f46247 | 958 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 959 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 960 | irq_set_chip_data(j, bank); |
d0d665a8 | 961 | if (bank->is_mpuio) { |
f8b46b58 KH |
962 | omap_mpuio_alloc_gc(bank, j, bank->width); |
963 | } else { | |
6845664a | 964 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
965 | irq_set_handler(j, handle_simple_irq); |
966 | set_irq_flags(j, IRQF_VALID); | |
967 | } | |
2fae7fbe | 968 | } |
6845664a TG |
969 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
970 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
971 | } |
972 | ||
77640aab | 973 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 974 | { |
77640aab VC |
975 | struct omap_gpio_platform_data *pdata; |
976 | struct resource *res; | |
5e1c5ff4 | 977 | struct gpio_bank *bank; |
03e128ca | 978 | int ret = 0; |
5e1c5ff4 | 979 | |
03e128ca C |
980 | if (!pdev->dev.platform_data) { |
981 | ret = -EINVAL; | |
982 | goto err_exit; | |
5492fb1a | 983 | } |
5492fb1a | 984 | |
03e128ca C |
985 | bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); |
986 | if (!bank) { | |
987 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
988 | ret = -ENOMEM; | |
989 | goto err_exit; | |
990 | } | |
92105bb7 | 991 | |
77640aab VC |
992 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
993 | if (unlikely(!res)) { | |
03e128ca C |
994 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", |
995 | pdev->id); | |
996 | ret = -ENODEV; | |
997 | goto err_free; | |
44169075 | 998 | } |
5e1c5ff4 | 999 | |
77640aab | 1000 | bank->irq = res->start; |
03e128ca C |
1001 | bank->id = pdev->id; |
1002 | ||
1003 | pdata = pdev->dev.platform_data; | |
77640aab | 1004 | bank->virtual_irq_start = pdata->virtual_irq_start; |
77640aab VC |
1005 | bank->dev = &pdev->dev; |
1006 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1007 | bank->stride = pdata->bank_stride; |
d5f46247 | 1008 | bank->width = pdata->bank_width; |
d0d665a8 | 1009 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1010 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1011 | bank->loses_context = pdata->loses_context; |
60a3437d | 1012 | bank->get_context_loss_count = pdata->get_context_loss_count; |
fa87931a KH |
1013 | bank->regs = pdata->regs; |
1014 | ||
1015 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1016 | bank->set_dataout = _set_gpio_dataout_reg; | |
1017 | else | |
1018 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1019 | |
77640aab | 1020 | spin_lock_init(&bank->lock); |
9f7065da | 1021 | |
77640aab VC |
1022 | /* Static mapping, never released */ |
1023 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1024 | if (unlikely(!res)) { | |
03e128ca C |
1025 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", |
1026 | pdev->id); | |
1027 | ret = -ENODEV; | |
1028 | goto err_free; | |
77640aab | 1029 | } |
89db9482 | 1030 | |
77640aab VC |
1031 | bank->base = ioremap(res->start, resource_size(res)); |
1032 | if (!bank->base) { | |
03e128ca C |
1033 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", |
1034 | pdev->id); | |
1035 | ret = -ENOMEM; | |
1036 | goto err_free; | |
5e1c5ff4 TL |
1037 | } |
1038 | ||
77640aab VC |
1039 | pm_runtime_enable(bank->dev); |
1040 | pm_runtime_get_sync(bank->dev); | |
1041 | ||
d0d665a8 | 1042 | if (bank->is_mpuio) |
ab985f0f TKD |
1043 | mpuio_init(bank); |
1044 | ||
03e128ca | 1045 | omap_gpio_mod_init(bank); |
77640aab | 1046 | omap_gpio_chip_init(bank); |
9a748053 | 1047 | omap_gpio_show_rev(bank); |
9f7065da | 1048 | |
03e128ca | 1049 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1050 | |
03e128ca C |
1051 | return ret; |
1052 | ||
1053 | err_free: | |
1054 | kfree(bank); | |
1055 | err_exit: | |
1056 | return ret; | |
5e1c5ff4 TL |
1057 | } |
1058 | ||
3c437ffd | 1059 | static int omap_gpio_suspend(void) |
92105bb7 | 1060 | { |
03e128ca | 1061 | struct gpio_bank *bank; |
92105bb7 | 1062 | |
03e128ca | 1063 | list_for_each_entry(bank, &omap_gpio_list, node) { |
6ed87c5b | 1064 | void __iomem *base = bank->base; |
92105bb7 | 1065 | void __iomem *wake_status; |
a6472533 | 1066 | unsigned long flags; |
92105bb7 | 1067 | |
6ed87c5b TKD |
1068 | if (!bank->regs->wkup_en) |
1069 | return 0; | |
1070 | ||
1071 | wake_status = bank->base + bank->regs->wkup_en; | |
92105bb7 | 1072 | |
a6472533 | 1073 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1074 | bank->saved_wakeup = __raw_readl(wake_status); |
6ed87c5b TKD |
1075 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); |
1076 | _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1); | |
a6472533 | 1077 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1078 | } |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
3c437ffd | 1083 | static void omap_gpio_resume(void) |
92105bb7 | 1084 | { |
03e128ca | 1085 | struct gpio_bank *bank; |
92105bb7 | 1086 | |
03e128ca | 1087 | list_for_each_entry(bank, &omap_gpio_list, node) { |
6ed87c5b | 1088 | void __iomem *base = bank->base; |
a6472533 | 1089 | unsigned long flags; |
92105bb7 | 1090 | |
6ed87c5b TKD |
1091 | if (!bank->regs->wkup_en) |
1092 | return; | |
92105bb7 | 1093 | |
a6472533 | 1094 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b TKD |
1095 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); |
1096 | _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1); | |
a6472533 | 1097 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1098 | } |
92105bb7 TL |
1099 | } |
1100 | ||
3c437ffd | 1101 | static struct syscore_ops omap_gpio_syscore_ops = { |
92105bb7 TL |
1102 | .suspend = omap_gpio_suspend, |
1103 | .resume = omap_gpio_resume, | |
1104 | }; | |
1105 | ||
140455fa | 1106 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 1107 | |
60a3437d TKD |
1108 | static void omap_gpio_save_context(struct gpio_bank *bank); |
1109 | static void omap_gpio_restore_context(struct gpio_bank *bank); | |
3ac4fa99 | 1110 | |
72e06d08 | 1111 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 | 1112 | { |
03e128ca | 1113 | struct gpio_bank *bank; |
43ffcd9a | 1114 | |
03e128ca | 1115 | list_for_each_entry(bank, &omap_gpio_list, node) { |
ca828760 | 1116 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1117 | int j; |
3ac4fa99 | 1118 | |
0cde8d03 | 1119 | if (!bank->loses_context) |
03e128ca C |
1120 | continue; |
1121 | ||
0aed0435 | 1122 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1123 | clk_disable(bank->dbck); |
1124 | ||
72e06d08 | 1125 | if (!off_mode) |
43ffcd9a KH |
1126 | continue; |
1127 | ||
1128 | /* If going to OFF, remove triggering for all | |
1129 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1130 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 | 1131 | if (!(bank->enabled_non_wakeup_gpios)) |
60a3437d | 1132 | goto save_gpio_context; |
3f1686a9 | 1133 | |
9ea14d8c TKD |
1134 | bank->saved_datain = __raw_readl(bank->base + |
1135 | bank->regs->datain); | |
1136 | l1 = __raw_readl(bank->base + bank->regs->fallingdetect); | |
1137 | l2 = __raw_readl(bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1138 | |
3ac4fa99 JY |
1139 | bank->saved_fallingdetect = l1; |
1140 | bank->saved_risingdetect = l2; | |
1141 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1142 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1143 | |
9ea14d8c TKD |
1144 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1145 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1146 | |
60a3437d TKD |
1147 | save_gpio_context: |
1148 | if (bank->get_context_loss_count) | |
1149 | bank->context_loss_count = | |
1150 | bank->get_context_loss_count(bank->dev); | |
1151 | ||
1152 | omap_gpio_save_context(bank); | |
3ac4fa99 | 1153 | } |
3ac4fa99 JY |
1154 | } |
1155 | ||
43ffcd9a | 1156 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 | 1157 | { |
03e128ca | 1158 | struct gpio_bank *bank; |
3ac4fa99 | 1159 | |
03e128ca | 1160 | list_for_each_entry(bank, &omap_gpio_list, node) { |
60a3437d | 1161 | int context_lost_cnt_after; |
ca828760 | 1162 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1163 | int j; |
3ac4fa99 | 1164 | |
0cde8d03 | 1165 | if (!bank->loses_context) |
03e128ca C |
1166 | continue; |
1167 | ||
0aed0435 | 1168 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1169 | clk_enable(bank->dbck); |
1170 | ||
60a3437d TKD |
1171 | if (bank->get_context_loss_count) { |
1172 | context_lost_cnt_after = | |
1173 | bank->get_context_loss_count(bank->dev); | |
1174 | if (context_lost_cnt_after != bank->context_loss_count | |
1175 | || !context_lost_cnt_after) | |
1176 | omap_gpio_restore_context(bank); | |
1177 | } | |
43ffcd9a | 1178 | |
3ac4fa99 JY |
1179 | if (!(bank->enabled_non_wakeup_gpios)) |
1180 | continue; | |
3f1686a9 | 1181 | |
9ea14d8c TKD |
1182 | __raw_writel(bank->saved_fallingdetect, |
1183 | bank->base + bank->regs->fallingdetect); | |
1184 | __raw_writel(bank->saved_risingdetect, | |
1185 | bank->base + bank->regs->risingdetect); | |
1186 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1187 | |
3ac4fa99 JY |
1188 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1189 | * state. If so, generate an IRQ by software. This is | |
1190 | * horribly racy, but it's the best we can do to work around | |
1191 | * this silicon bug. */ | |
3ac4fa99 | 1192 | l ^= bank->saved_datain; |
a118b5f3 | 1193 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1194 | |
1195 | /* | |
1196 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1197 | * configured with falling edge only; and vice versa. | |
1198 | */ | |
1199 | gen0 = l & bank->saved_fallingdetect; | |
1200 | gen0 &= bank->saved_datain; | |
1201 | ||
1202 | gen1 = l & bank->saved_risingdetect; | |
1203 | gen1 &= ~(bank->saved_datain); | |
1204 | ||
1205 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1206 | gen = l & (~(bank->saved_fallingdetect) & | |
1207 | ~(bank->saved_risingdetect)); | |
1208 | /* Consider all GPIO IRQs needed to be updated */ | |
1209 | gen |= gen0 | gen1; | |
1210 | ||
1211 | if (gen) { | |
3ac4fa99 | 1212 | u32 old0, old1; |
3f1686a9 | 1213 | |
9ea14d8c TKD |
1214 | old0 = __raw_readl(bank->base + |
1215 | bank->regs->leveldetect0); | |
1216 | old1 = __raw_readl(bank->base + | |
1217 | bank->regs->leveldetect1); | |
1218 | ||
f00d6497 | 1219 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
9ea14d8c TKD |
1220 | old0 |= gen; |
1221 | old1 |= gen; | |
3f1686a9 TL |
1222 | } |
1223 | ||
1224 | if (cpu_is_omap44xx()) { | |
9ea14d8c TKD |
1225 | old0 |= l; |
1226 | old1 |= l; | |
3f1686a9 | 1227 | } |
9ea14d8c TKD |
1228 | __raw_writel(old0, bank->base + |
1229 | bank->regs->leveldetect0); | |
1230 | __raw_writel(old1, bank->base + | |
1231 | bank->regs->leveldetect1); | |
3ac4fa99 JY |
1232 | } |
1233 | } | |
3ac4fa99 JY |
1234 | } |
1235 | ||
60a3437d | 1236 | static void omap_gpio_save_context(struct gpio_bank *bank) |
40c670f0 | 1237 | { |
60a3437d | 1238 | bank->context.irqenable1 = |
ae10f233 | 1239 | __raw_readl(bank->base + bank->regs->irqenable); |
60a3437d | 1240 | bank->context.irqenable2 = |
ae10f233 | 1241 | __raw_readl(bank->base + bank->regs->irqenable2); |
60a3437d | 1242 | bank->context.wake_en = |
ae10f233 TKD |
1243 | __raw_readl(bank->base + bank->regs->wkup_en); |
1244 | bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl); | |
1245 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
60a3437d | 1246 | bank->context.leveldetect0 = |
ae10f233 | 1247 | __raw_readl(bank->base + bank->regs->leveldetect0); |
60a3437d | 1248 | bank->context.leveldetect1 = |
ae10f233 | 1249 | __raw_readl(bank->base + bank->regs->leveldetect1); |
60a3437d | 1250 | bank->context.risingdetect = |
ae10f233 | 1251 | __raw_readl(bank->base + bank->regs->risingdetect); |
60a3437d | 1252 | bank->context.fallingdetect = |
ae10f233 TKD |
1253 | __raw_readl(bank->base + bank->regs->fallingdetect); |
1254 | bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout); | |
40c670f0 RN |
1255 | } |
1256 | ||
60a3437d | 1257 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1258 | { |
60a3437d | 1259 | __raw_writel(bank->context.irqenable1, |
ae10f233 | 1260 | bank->base + bank->regs->irqenable); |
60a3437d | 1261 | __raw_writel(bank->context.irqenable2, |
ae10f233 | 1262 | bank->base + bank->regs->irqenable2); |
60a3437d | 1263 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1264 | bank->base + bank->regs->wkup_en); |
1265 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1266 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); | |
60a3437d | 1267 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1268 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1269 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1270 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1271 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1272 | bank->base + bank->regs->risingdetect); |
60a3437d | 1273 | __raw_writel(bank->context.fallingdetect, |
ae10f233 TKD |
1274 | bank->base + bank->regs->fallingdetect); |
1275 | __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout); | |
40c670f0 RN |
1276 | } |
1277 | #endif | |
1278 | ||
77640aab VC |
1279 | static struct platform_driver omap_gpio_driver = { |
1280 | .probe = omap_gpio_probe, | |
1281 | .driver = { | |
1282 | .name = "omap_gpio", | |
1283 | }, | |
1284 | }; | |
1285 | ||
5e1c5ff4 | 1286 | /* |
77640aab VC |
1287 | * gpio driver register needs to be done before |
1288 | * machine_init functions access gpio APIs. | |
1289 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1290 | */ |
77640aab | 1291 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1292 | { |
77640aab | 1293 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1294 | } |
77640aab | 1295 | postcore_initcall(omap_gpio_drv_reg); |
5e1c5ff4 | 1296 | |
92105bb7 TL |
1297 | static int __init omap_gpio_sysinit(void) |
1298 | { | |
11a78b79 | 1299 | |
140455fa | 1300 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd RW |
1301 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) |
1302 | register_syscore_ops(&omap_gpio_syscore_ops); | |
92105bb7 TL |
1303 | #endif |
1304 | ||
3c437ffd | 1305 | return 0; |
92105bb7 TL |
1306 | } |
1307 | ||
92105bb7 | 1308 | arch_initcall(omap_gpio_sysinit); |