Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/irqdomain.h> | |
de88cbb7 | 28 | #include <linux/irqchip/chained_irq.h> |
4b25408f TL |
29 | #include <linux/gpio.h> |
30 | #include <linux/platform_data/gpio-omap.h> | |
5e1c5ff4 | 31 | |
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
5e1c5ff4 | 54 | u16 irq; |
384ebe1c | 55 | struct irq_domain *domain; |
3ac4fa99 JY |
56 | u32 non_wakeup_gpios; |
57 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 58 | struct gpio_regs context; |
3ac4fa99 | 59 | u32 saved_datain; |
b144ff6f | 60 | u32 level_mask; |
4318f36b | 61 | u32 toggle_mask; |
5e1c5ff4 | 62 | spinlock_t lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
fa365e4d | 66 | u32 irq_usage; |
8865b9b6 | 67 | u32 dbck_enable_mask; |
72f83af9 | 68 | bool dbck_enabled; |
77640aab | 69 | struct device *dev; |
d0d665a8 | 70 | bool is_mpuio; |
77640aab | 71 | bool dbck_flag; |
0cde8d03 | 72 | bool loses_context; |
352a2d5b | 73 | bool context_valid; |
5de62b86 | 74 | int stride; |
d5f46247 | 75 | u32 width; |
60a3437d | 76 | int context_loss_count; |
2dc983c5 TKD |
77 | int power_mode; |
78 | bool workaround_enabled; | |
fa87931a KH |
79 | |
80 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 81 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
82 | |
83 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
84 | }; |
85 | ||
129fd223 KH |
86 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
87 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 88 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 89 | |
fa365e4d JMC |
90 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
91 | #define LINE_USED(line, offset) (line & (1 << offset)) | |
92 | ||
25db711d BC |
93 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
94 | { | |
ede4d7a5 JH |
95 | return bank->chip.base + gpio_irq; |
96 | } | |
97 | ||
98 | static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
99 | { | |
100 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); | |
101 | ||
102 | return irq_find_mapping(bank->domain, offset); | |
25db711d BC |
103 | } |
104 | ||
5e1c5ff4 TL |
105 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
106 | { | |
92105bb7 | 107 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
108 | u32 l; |
109 | ||
fa87931a | 110 | reg += bank->regs->direction; |
5e1c5ff4 TL |
111 | l = __raw_readl(reg); |
112 | if (is_input) | |
113 | l |= 1 << gpio; | |
114 | else | |
115 | l &= ~(1 << gpio); | |
116 | __raw_writel(l, reg); | |
41d87cbd | 117 | bank->context.oe = l; |
5e1c5ff4 TL |
118 | } |
119 | ||
fa87931a KH |
120 | |
121 | /* set data out value using dedicate set/clear register */ | |
122 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 123 | { |
92105bb7 | 124 | void __iomem *reg = bank->base; |
fa87931a | 125 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 126 | |
2c836f7e | 127 | if (enable) { |
fa87931a | 128 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
129 | bank->context.dataout |= l; |
130 | } else { | |
fa87931a | 131 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
132 | bank->context.dataout &= ~l; |
133 | } | |
5e1c5ff4 | 134 | |
5e1c5ff4 TL |
135 | __raw_writel(l, reg); |
136 | } | |
137 | ||
fa87931a KH |
138 | /* set data out value using mask register */ |
139 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 140 | { |
fa87931a KH |
141 | void __iomem *reg = bank->base + bank->regs->dataout; |
142 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
143 | u32 l; | |
5e1c5ff4 | 144 | |
fa87931a KH |
145 | l = __raw_readl(reg); |
146 | if (enable) | |
147 | l |= gpio_bit; | |
148 | else | |
149 | l &= ~gpio_bit; | |
5e1c5ff4 | 150 | __raw_writel(l, reg); |
41d87cbd | 151 | bank->context.dataout = l; |
5e1c5ff4 TL |
152 | } |
153 | ||
7fcca715 | 154 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 155 | { |
fa87931a | 156 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 157 | |
7fcca715 | 158 | return (__raw_readl(reg) & (1 << offset)) != 0; |
5e1c5ff4 | 159 | } |
b37c45b8 | 160 | |
7fcca715 | 161 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 162 | { |
fa87931a | 163 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 164 | |
7fcca715 | 165 | return (__raw_readl(reg) & (1 << offset)) != 0; |
b37c45b8 RQ |
166 | } |
167 | ||
ece9528e KH |
168 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
169 | { | |
170 | int l = __raw_readl(base + reg); | |
171 | ||
862ff640 | 172 | if (set) |
ece9528e KH |
173 | l |= mask; |
174 | else | |
175 | l &= ~mask; | |
176 | ||
177 | __raw_writel(l, base + reg); | |
178 | } | |
92105bb7 | 179 | |
72f83af9 TKD |
180 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
181 | { | |
182 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
183 | clk_enable(bank->dbck); | |
184 | bank->dbck_enabled = true; | |
9e303f22 GI |
185 | |
186 | __raw_writel(bank->dbck_enable_mask, | |
187 | bank->base + bank->regs->debounce_en); | |
72f83af9 TKD |
188 | } |
189 | } | |
190 | ||
191 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
192 | { | |
193 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
194 | /* |
195 | * Disable debounce before cutting it's clock. If debounce is | |
196 | * enabled but the clock is not, GPIO module seems to be unable | |
197 | * to detect events and generate interrupts at least on OMAP3. | |
198 | */ | |
199 | __raw_writel(0, bank->base + bank->regs->debounce_en); | |
200 | ||
72f83af9 TKD |
201 | clk_disable(bank->dbck); |
202 | bank->dbck_enabled = false; | |
203 | } | |
204 | } | |
205 | ||
168ef3d9 FB |
206 | /** |
207 | * _set_gpio_debounce - low level gpio debounce time | |
208 | * @bank: the gpio bank we're acting upon | |
209 | * @gpio: the gpio number on this @gpio | |
210 | * @debounce: debounce time to use | |
211 | * | |
212 | * OMAP's debounce time is in 31us steps so we need | |
213 | * to convert and round up to the closest unit. | |
214 | */ | |
215 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
216 | unsigned debounce) | |
217 | { | |
9942da0e | 218 | void __iomem *reg; |
168ef3d9 FB |
219 | u32 val; |
220 | u32 l; | |
221 | ||
77640aab VC |
222 | if (!bank->dbck_flag) |
223 | return; | |
224 | ||
168ef3d9 FB |
225 | if (debounce < 32) |
226 | debounce = 0x01; | |
227 | else if (debounce > 7936) | |
228 | debounce = 0xff; | |
229 | else | |
230 | debounce = (debounce / 0x1f) - 1; | |
231 | ||
129fd223 | 232 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 233 | |
6fd9c421 | 234 | clk_enable(bank->dbck); |
9942da0e | 235 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
236 | __raw_writel(debounce, reg); |
237 | ||
9942da0e | 238 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
239 | val = __raw_readl(reg); |
240 | ||
6fd9c421 | 241 | if (debounce) |
168ef3d9 | 242 | val |= l; |
6fd9c421 | 243 | else |
168ef3d9 | 244 | val &= ~l; |
f7ec0b0b | 245 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
246 | |
247 | __raw_writel(val, reg); | |
6fd9c421 TKD |
248 | clk_disable(bank->dbck); |
249 | /* | |
250 | * Enable debounce clock per module. | |
251 | * This call is mandatory because in omap_gpio_request() when | |
252 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
253 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
254 | * used within _gpio_dbck_enable() is still not initialized at | |
255 | * that point. Therefore we have to enable dbck here. | |
256 | */ | |
257 | _gpio_dbck_enable(bank); | |
ae547354 NM |
258 | if (bank->dbck_enable_mask) { |
259 | bank->context.debounce = debounce; | |
260 | bank->context.debounce_en = val; | |
261 | } | |
168ef3d9 FB |
262 | } |
263 | ||
c9c55d92 JH |
264 | /** |
265 | * _clear_gpio_debounce - clear debounce settings for a gpio | |
266 | * @bank: the gpio bank we're acting upon | |
267 | * @gpio: the gpio number on this @gpio | |
268 | * | |
269 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
270 | * this is the only gpio in this bank using debounce, then clear the debounce | |
271 | * time too. The debounce clock will also be disabled when calling this function | |
272 | * if this is the only gpio in the bank using debounce. | |
273 | */ | |
274 | static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | |
275 | { | |
276 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
277 | ||
278 | if (!bank->dbck_flag) | |
279 | return; | |
280 | ||
281 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
282 | return; | |
283 | ||
284 | bank->dbck_enable_mask &= ~gpio_bit; | |
285 | bank->context.debounce_en &= ~gpio_bit; | |
286 | __raw_writel(bank->context.debounce_en, | |
287 | bank->base + bank->regs->debounce_en); | |
288 | ||
289 | if (!bank->dbck_enable_mask) { | |
290 | bank->context.debounce = 0; | |
291 | __raw_writel(bank->context.debounce, bank->base + | |
292 | bank->regs->debounce); | |
293 | clk_disable(bank->dbck); | |
294 | bank->dbck_enabled = false; | |
295 | } | |
296 | } | |
297 | ||
5e571f38 | 298 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 299 | unsigned trigger) |
5e1c5ff4 | 300 | { |
3ac4fa99 | 301 | void __iomem *base = bank->base; |
92105bb7 TL |
302 | u32 gpio_bit = 1 << gpio; |
303 | ||
5e571f38 TKD |
304 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
305 | trigger & IRQ_TYPE_LEVEL_LOW); | |
306 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
307 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
308 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
309 | trigger & IRQ_TYPE_EDGE_RISING); | |
310 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
311 | trigger & IRQ_TYPE_EDGE_FALLING); | |
312 | ||
41d87cbd TKD |
313 | bank->context.leveldetect0 = |
314 | __raw_readl(bank->base + bank->regs->leveldetect0); | |
315 | bank->context.leveldetect1 = | |
316 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
317 | bank->context.risingdetect = | |
318 | __raw_readl(bank->base + bank->regs->risingdetect); | |
319 | bank->context.fallingdetect = | |
320 | __raw_readl(bank->base + bank->regs->fallingdetect); | |
321 | ||
322 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 323 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd TKD |
324 | bank->context.wake_en = |
325 | __raw_readl(bank->base + bank->regs->wkup_en); | |
326 | } | |
5e571f38 | 327 | |
55b220ca | 328 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
329 | if (!bank->regs->irqctrl) { |
330 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
331 | if (bank->non_wakeup_gpios) { | |
332 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
333 | goto exit; | |
334 | } | |
335 | ||
699117a6 CW |
336 | /* |
337 | * Log the edge gpio and manually trigger the IRQ | |
338 | * after resume if the input level changes | |
339 | * to avoid irq lost during PER RET/OFF mode | |
340 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
341 | */ | |
342 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
343 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
344 | else | |
345 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
346 | } | |
5eb3bb9c | 347 | |
5e571f38 | 348 | exit: |
9ea14d8c TKD |
349 | bank->level_mask = |
350 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
351 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
352 | } |
353 | ||
9198bcd3 | 354 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
355 | /* |
356 | * This only applies to chips that can't do both rising and falling edge | |
357 | * detection at once. For all other chips, this function is a noop. | |
358 | */ | |
359 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
360 | { | |
361 | void __iomem *reg = bank->base; | |
362 | u32 l = 0; | |
363 | ||
5e571f38 | 364 | if (!bank->regs->irqctrl) |
4318f36b | 365 | return; |
5e571f38 TKD |
366 | |
367 | reg += bank->regs->irqctrl; | |
4318f36b CM |
368 | |
369 | l = __raw_readl(reg); | |
370 | if ((l >> gpio) & 1) | |
371 | l &= ~(1 << gpio); | |
372 | else | |
373 | l |= 1 << gpio; | |
374 | ||
375 | __raw_writel(l, reg); | |
376 | } | |
5e571f38 TKD |
377 | #else |
378 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 379 | #endif |
4318f36b | 380 | |
00ece7e4 TKD |
381 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, |
382 | unsigned trigger) | |
92105bb7 TL |
383 | { |
384 | void __iomem *reg = bank->base; | |
5e571f38 | 385 | void __iomem *base = bank->base; |
92105bb7 | 386 | u32 l = 0; |
5e1c5ff4 | 387 | |
5e571f38 TKD |
388 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
389 | set_gpio_trigger(bank, gpio, trigger); | |
390 | } else if (bank->regs->irqctrl) { | |
391 | reg += bank->regs->irqctrl; | |
392 | ||
5e1c5ff4 | 393 | l = __raw_readl(reg); |
29501577 | 394 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 395 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 396 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 397 | l |= 1 << gpio; |
6cab4860 | 398 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 399 | l &= ~(1 << gpio); |
92105bb7 | 400 | else |
5e571f38 TKD |
401 | return -EINVAL; |
402 | ||
403 | __raw_writel(l, reg); | |
404 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 405 | if (gpio & 0x08) |
5e571f38 | 406 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 407 | else |
5e571f38 TKD |
408 | reg += bank->regs->edgectrl1; |
409 | ||
5e1c5ff4 TL |
410 | gpio &= 0x07; |
411 | l = __raw_readl(reg); | |
412 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 413 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 414 | l |= 2 << (gpio << 1); |
6cab4860 | 415 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 416 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
417 | |
418 | /* Enable wake-up during idle for dynamic tick */ | |
419 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd TKD |
420 | bank->context.wake_en = |
421 | __raw_readl(bank->base + bank->regs->wkup_en); | |
5e571f38 | 422 | __raw_writel(l, reg); |
5e1c5ff4 | 423 | } |
92105bb7 | 424 | return 0; |
5e1c5ff4 TL |
425 | } |
426 | ||
fa365e4d JMC |
427 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
428 | { | |
429 | void __iomem *reg = bank->base + bank->regs->direction; | |
430 | ||
431 | return __raw_readl(reg) & mask; | |
432 | } | |
433 | ||
e9191028 | 434 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 435 | { |
25db711d | 436 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
4b25408f | 437 | unsigned gpio = 0; |
92105bb7 | 438 | int retval; |
a6472533 | 439 | unsigned long flags; |
92105bb7 | 440 | |
fa365e4d | 441 | if (WARN_ON(!BANK_USED(bank))) |
8d4c277e JH |
442 | return -EINVAL; |
443 | ||
4b25408f TL |
444 | #ifdef CONFIG_ARCH_OMAP1 |
445 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 446 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
447 | #endif |
448 | ||
449 | if (!gpio) | |
ede4d7a5 | 450 | gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 | 451 | |
e5c56ed3 | 452 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 453 | return -EINVAL; |
e5c56ed3 | 454 | |
9ea14d8c TKD |
455 | if (!bank->regs->leveldetect0 && |
456 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
457 | return -EINVAL; |
458 | ||
a6472533 | 459 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 460 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
fa365e4d | 461 | bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio); |
a6472533 | 462 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
463 | |
464 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 465 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 466 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 467 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 468 | |
92105bb7 | 469 | return retval; |
5e1c5ff4 TL |
470 | } |
471 | ||
472 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
473 | { | |
92105bb7 | 474 | void __iomem *reg = bank->base; |
5e1c5ff4 | 475 | |
eef4bec7 | 476 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 477 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
478 | |
479 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
480 | if (bank->regs->irqstatus2) { |
481 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 482 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 483 | } |
bedfd154 RQ |
484 | |
485 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
486 | __raw_readl(reg); | |
5e1c5ff4 TL |
487 | } |
488 | ||
489 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
490 | { | |
129fd223 | 491 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
492 | } |
493 | ||
ea6dedd7 ID |
494 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
495 | { | |
496 | void __iomem *reg = bank->base; | |
99c47707 | 497 | u32 l; |
c390aad0 | 498 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 499 | |
28f3b5a0 | 500 | reg += bank->regs->irqenable; |
99c47707 | 501 | l = __raw_readl(reg); |
28f3b5a0 | 502 | if (bank->regs->irqenable_inv) |
99c47707 ID |
503 | l = ~l; |
504 | l &= mask; | |
505 | return l; | |
ea6dedd7 ID |
506 | } |
507 | ||
28f3b5a0 | 508 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 509 | { |
92105bb7 | 510 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
511 | u32 l; |
512 | ||
28f3b5a0 KH |
513 | if (bank->regs->set_irqenable) { |
514 | reg += bank->regs->set_irqenable; | |
515 | l = gpio_mask; | |
2a900eb7 | 516 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
517 | } else { |
518 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 519 | l = __raw_readl(reg); |
28f3b5a0 KH |
520 | if (bank->regs->irqenable_inv) |
521 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
522 | else |
523 | l |= gpio_mask; | |
2a900eb7 | 524 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
525 | } |
526 | ||
527 | __raw_writel(l, reg); | |
528 | } | |
529 | ||
530 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
531 | { | |
532 | void __iomem *reg = bank->base; | |
533 | u32 l; | |
534 | ||
535 | if (bank->regs->clr_irqenable) { | |
536 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 537 | l = gpio_mask; |
2a900eb7 | 538 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
539 | } else { |
540 | reg += bank->regs->irqenable; | |
56739a69 | 541 | l = __raw_readl(reg); |
28f3b5a0 | 542 | if (bank->regs->irqenable_inv) |
56739a69 | 543 | l |= gpio_mask; |
92105bb7 | 544 | else |
28f3b5a0 | 545 | l &= ~gpio_mask; |
2a900eb7 | 546 | bank->context.irqenable1 = l; |
5e1c5ff4 | 547 | } |
28f3b5a0 | 548 | |
5e1c5ff4 TL |
549 | __raw_writel(l, reg); |
550 | } | |
551 | ||
552 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
553 | { | |
8276536c TKD |
554 | if (enable) |
555 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
556 | else | |
557 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
5e1c5ff4 TL |
558 | } |
559 | ||
92105bb7 TL |
560 | /* |
561 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
562 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
563 | * to the target, system will wake up always on GPIO events. While | |
564 | * system is running all registered GPIO interrupts need to have wake-up | |
565 | * enabled. When system is suspended, only selected GPIO interrupts need | |
566 | * to have wake-up enabled. | |
567 | */ | |
568 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
569 | { | |
f64ad1a0 KH |
570 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
571 | unsigned long flags; | |
a6472533 | 572 | |
f64ad1a0 | 573 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 574 | dev_err(bank->dev, |
f64ad1a0 | 575 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
576 | return -EINVAL; |
577 | } | |
f64ad1a0 KH |
578 | |
579 | spin_lock_irqsave(&bank->lock, flags); | |
580 | if (enable) | |
0aa27273 | 581 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 582 | else |
0aa27273 | 583 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 584 | |
0aa27273 | 585 | __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
586 | spin_unlock_irqrestore(&bank->lock, flags); |
587 | ||
588 | return 0; | |
92105bb7 TL |
589 | } |
590 | ||
4196dd6b TL |
591 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
592 | { | |
129fd223 | 593 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
594 | _set_gpio_irqenable(bank, gpio, 0); |
595 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 596 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
c9c55d92 | 597 | _clear_gpio_debounce(bank, gpio); |
4196dd6b TL |
598 | } |
599 | ||
92105bb7 | 600 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 601 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 602 | { |
25db711d | 603 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 604 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
92105bb7 | 605 | |
25db711d | 606 | return _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
607 | } |
608 | ||
3ff164e1 | 609 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 610 | { |
3ff164e1 | 611 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 612 | unsigned long flags; |
52e31344 | 613 | |
55b93c32 TKD |
614 | /* |
615 | * If this is the first gpio_request for the bank, | |
616 | * enable the bank module. | |
617 | */ | |
fa365e4d | 618 | if (!BANK_USED(bank)) |
55b93c32 | 619 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 620 | |
55b93c32 | 621 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
622 | /* Set trigger to none. You need to enable the desired trigger with |
623 | * request_irq() or set_irq_type(). | |
624 | */ | |
3ff164e1 | 625 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 626 | |
fad96ea8 C |
627 | if (bank->regs->pinctrl) { |
628 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 629 | |
92105bb7 | 630 | /* Claim the pin for MPU */ |
3ff164e1 | 631 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 632 | } |
fad96ea8 | 633 | |
fa365e4d | 634 | if (bank->regs->ctrl && !BANK_USED(bank)) { |
c8eef65a C |
635 | void __iomem *reg = bank->base + bank->regs->ctrl; |
636 | u32 ctrl; | |
637 | ||
638 | ctrl = __raw_readl(reg); | |
639 | /* Module is enabled, clocks are not gated */ | |
640 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
641 | __raw_writel(ctrl, reg); | |
41d87cbd | 642 | bank->context.ctrl = ctrl; |
058af1ea | 643 | } |
c8eef65a C |
644 | |
645 | bank->mod_usage |= 1 << offset; | |
646 | ||
a6472533 | 647 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
648 | |
649 | return 0; | |
650 | } | |
651 | ||
3ff164e1 | 652 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 653 | { |
3ff164e1 | 654 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 655 | void __iomem *base = bank->base; |
a6472533 | 656 | unsigned long flags; |
5e1c5ff4 | 657 | |
a6472533 | 658 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b | 659 | |
41d87cbd | 660 | if (bank->regs->wkup_en) { |
9f096868 | 661 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b | 662 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
41d87cbd TKD |
663 | bank->context.wake_en = |
664 | __raw_readl(bank->base + bank->regs->wkup_en); | |
665 | } | |
6ed87c5b | 666 | |
c8eef65a C |
667 | bank->mod_usage &= ~(1 << offset); |
668 | ||
fa365e4d | 669 | if (bank->regs->ctrl && !BANK_USED(bank)) { |
c8eef65a C |
670 | void __iomem *reg = bank->base + bank->regs->ctrl; |
671 | u32 ctrl; | |
672 | ||
673 | ctrl = __raw_readl(reg); | |
674 | /* Module is disabled, clocks are gated */ | |
675 | ctrl |= GPIO_MOD_CTRL_BIT; | |
676 | __raw_writel(ctrl, reg); | |
41d87cbd | 677 | bank->context.ctrl = ctrl; |
058af1ea | 678 | } |
c8eef65a | 679 | |
3ff164e1 | 680 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 681 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
682 | |
683 | /* | |
684 | * If this is the last gpio to be freed in the bank, | |
685 | * disable the bank module. | |
686 | */ | |
fa365e4d | 687 | if (!BANK_USED(bank)) |
55b93c32 | 688 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
689 | } |
690 | ||
691 | /* | |
692 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
693 | * avoid missing GPIO interrupts for other lines in the bank. | |
694 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
695 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
696 | * If we wait to unmask individual GPIO lines in the bank after the | |
697 | * line's interrupt handler has been run, we may miss some nested | |
698 | * interrupts. | |
699 | */ | |
10dd5ce2 | 700 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 701 | { |
92105bb7 | 702 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 703 | u32 isr; |
3513cdec | 704 | unsigned int bit; |
5e1c5ff4 | 705 | struct gpio_bank *bank; |
ea6dedd7 | 706 | int unmasked = 0; |
ee144182 | 707 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 708 | |
ee144182 | 709 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 710 | |
6845664a | 711 | bank = irq_get_handler_data(irq); |
eef4bec7 | 712 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 713 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
714 | |
715 | if (WARN_ON(!isr_reg)) | |
716 | goto exit; | |
717 | ||
e83507b7 | 718 | while (1) { |
6e60e79a | 719 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 720 | u32 enabled; |
6e60e79a | 721 | |
ea6dedd7 ID |
722 | enabled = _get_gpio_irqbank_mask(bank); |
723 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 724 | |
9ea14d8c | 725 | if (bank->level_mask) |
b144ff6f | 726 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
727 | |
728 | /* clear edge sensitive interrupts before handler(s) are | |
729 | called so that we don't miss any interrupt occurred while | |
730 | executing them */ | |
28f3b5a0 | 731 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 732 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 733 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
734 | |
735 | /* if there is only edge sensitive GPIO pin interrupts | |
736 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
737 | if (!level_mask && !unmasked) { |
738 | unmasked = 1; | |
ee144182 | 739 | chained_irq_exit(chip, desc); |
ea6dedd7 | 740 | } |
92105bb7 TL |
741 | |
742 | if (!isr) | |
743 | break; | |
744 | ||
3513cdec JH |
745 | while (isr) { |
746 | bit = __ffs(isr); | |
747 | isr &= ~(1 << bit); | |
25db711d | 748 | |
4318f36b CM |
749 | /* |
750 | * Some chips can't respond to both rising and falling | |
751 | * at the same time. If this irq was requested with | |
752 | * both flags, we need to flip the ICR data for the IRQ | |
753 | * to respond to the IRQ for the opposite direction. | |
754 | * This will be indicated in the bank toggle_mask. | |
755 | */ | |
3513cdec JH |
756 | if (bank->toggle_mask & (1 << bit)) |
757 | _toggle_gpio_edge_triggering(bank, bit); | |
4318f36b | 758 | |
3513cdec | 759 | generic_handle_irq(irq_find_mapping(bank->domain, bit)); |
92105bb7 | 760 | } |
1a8bfa1e | 761 | } |
ea6dedd7 ID |
762 | /* if bank has any level sensitive GPIO pin interrupt |
763 | configured, we must unmask the bank interrupt only after | |
764 | handler(s) are executed in order to avoid spurious bank | |
765 | interrupt */ | |
b1cc4c55 | 766 | exit: |
ea6dedd7 | 767 | if (!unmasked) |
ee144182 | 768 | chained_irq_exit(chip, desc); |
55b93c32 | 769 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
770 | } |
771 | ||
e9191028 | 772 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 773 | { |
e9191028 | 774 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 775 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 776 | unsigned long flags; |
fa365e4d | 777 | unsigned offset = GPIO_INDEX(bank, gpio); |
4196dd6b | 778 | |
85ec7b97 | 779 | spin_lock_irqsave(&bank->lock, flags); |
fa365e4d | 780 | bank->irq_usage &= ~(1 << offset); |
4196dd6b | 781 | _reset_gpio(bank, gpio); |
85ec7b97 | 782 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
783 | } |
784 | ||
e9191028 | 785 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 786 | { |
e9191028 | 787 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 788 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 TL |
789 | |
790 | _clear_gpio_irqstatus(bank, gpio); | |
791 | } | |
792 | ||
e9191028 | 793 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 794 | { |
e9191028 | 795 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 796 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 797 | unsigned long flags; |
5e1c5ff4 | 798 | |
85ec7b97 | 799 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 800 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 801 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 802 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
803 | } |
804 | ||
e9191028 | 805 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 806 | { |
e9191028 | 807 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 808 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
129fd223 | 809 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 810 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 811 | unsigned long flags; |
55b6019a | 812 | |
85ec7b97 | 813 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 814 | if (trigger) |
129fd223 | 815 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
816 | |
817 | /* For level-triggered GPIOs, the clearing must be done after | |
818 | * the HW source is cleared, thus after the handler has run */ | |
819 | if (bank->level_mask & irq_mask) { | |
820 | _set_gpio_irqenable(bank, gpio, 0); | |
821 | _clear_gpio_irqstatus(bank, gpio); | |
822 | } | |
5e1c5ff4 | 823 | |
4de8c75b | 824 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 825 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
826 | } |
827 | ||
e5c56ed3 DB |
828 | static struct irq_chip gpio_irq_chip = { |
829 | .name = "GPIO", | |
e9191028 LB |
830 | .irq_shutdown = gpio_irq_shutdown, |
831 | .irq_ack = gpio_ack_irq, | |
832 | .irq_mask = gpio_mask_irq, | |
833 | .irq_unmask = gpio_unmask_irq, | |
834 | .irq_set_type = gpio_irq_type, | |
835 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
836 | }; |
837 | ||
838 | /*---------------------------------------------------------------------*/ | |
839 | ||
79ee031f | 840 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 841 | { |
79ee031f | 842 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 843 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
844 | void __iomem *mask_reg = bank->base + |
845 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 846 | unsigned long flags; |
11a78b79 | 847 | |
a6472533 | 848 | spin_lock_irqsave(&bank->lock, flags); |
0aa27273 | 849 | __raw_writel(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 850 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
79ee031f | 855 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 856 | { |
79ee031f | 857 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 858 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
859 | void __iomem *mask_reg = bank->base + |
860 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 861 | unsigned long flags; |
11a78b79 | 862 | |
a6472533 | 863 | spin_lock_irqsave(&bank->lock, flags); |
499fa287 | 864 | __raw_writel(bank->context.wake_en, mask_reg); |
a6472533 | 865 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
866 | |
867 | return 0; | |
868 | } | |
869 | ||
47145210 | 870 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
871 | .suspend_noirq = omap_mpuio_suspend_noirq, |
872 | .resume_noirq = omap_mpuio_resume_noirq, | |
873 | }; | |
874 | ||
3c437ffd | 875 | /* use platform_driver for this. */ |
11a78b79 | 876 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
877 | .driver = { |
878 | .name = "mpuio", | |
79ee031f | 879 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
880 | }, |
881 | }; | |
882 | ||
883 | static struct platform_device omap_mpuio_device = { | |
884 | .name = "mpuio", | |
885 | .id = -1, | |
886 | .dev = { | |
887 | .driver = &omap_mpuio_driver.driver, | |
888 | } | |
889 | /* could list the /proc/iomem resources */ | |
890 | }; | |
891 | ||
03e128ca | 892 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 893 | { |
77640aab | 894 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 895 | |
11a78b79 DB |
896 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
897 | (void) platform_device_register(&omap_mpuio_device); | |
898 | } | |
899 | ||
e5c56ed3 | 900 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 901 | |
52e31344 DB |
902 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
903 | { | |
904 | struct gpio_bank *bank; | |
905 | unsigned long flags; | |
906 | ||
907 | bank = container_of(chip, struct gpio_bank, chip); | |
908 | spin_lock_irqsave(&bank->lock, flags); | |
909 | _set_gpio_direction(bank, offset, 1); | |
910 | spin_unlock_irqrestore(&bank->lock, flags); | |
911 | return 0; | |
912 | } | |
913 | ||
914 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | |
915 | { | |
b37c45b8 | 916 | struct gpio_bank *bank; |
b37c45b8 RQ |
917 | u32 mask; |
918 | ||
a8be8daf | 919 | bank = container_of(chip, struct gpio_bank, chip); |
7fcca715 | 920 | mask = (1 << offset); |
b37c45b8 RQ |
921 | |
922 | if (gpio_is_input(bank, mask)) | |
7fcca715 | 923 | return _get_gpio_datain(bank, offset); |
b37c45b8 | 924 | else |
7fcca715 | 925 | return _get_gpio_dataout(bank, offset); |
52e31344 DB |
926 | } |
927 | ||
928 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
929 | { | |
930 | struct gpio_bank *bank; | |
931 | unsigned long flags; | |
932 | ||
933 | bank = container_of(chip, struct gpio_bank, chip); | |
934 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 935 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
936 | _set_gpio_direction(bank, offset, 0); |
937 | spin_unlock_irqrestore(&bank->lock, flags); | |
938 | return 0; | |
939 | } | |
940 | ||
168ef3d9 FB |
941 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
942 | unsigned debounce) | |
943 | { | |
944 | struct gpio_bank *bank; | |
945 | unsigned long flags; | |
946 | ||
947 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 948 | |
168ef3d9 FB |
949 | spin_lock_irqsave(&bank->lock, flags); |
950 | _set_gpio_debounce(bank, offset, debounce); | |
951 | spin_unlock_irqrestore(&bank->lock, flags); | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
52e31344 DB |
956 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
957 | { | |
958 | struct gpio_bank *bank; | |
959 | unsigned long flags; | |
960 | ||
961 | bank = container_of(chip, struct gpio_bank, chip); | |
962 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 963 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
964 | spin_unlock_irqrestore(&bank->lock, flags); |
965 | } | |
966 | ||
967 | /*---------------------------------------------------------------------*/ | |
968 | ||
9a748053 | 969 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 970 | { |
e5ff4440 | 971 | static bool called; |
9f7065da TL |
972 | u32 rev; |
973 | ||
e5ff4440 | 974 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
975 | return; |
976 | ||
e5ff4440 KH |
977 | rev = __raw_readw(bank->base + bank->regs->revision); |
978 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 979 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
980 | |
981 | called = true; | |
9f7065da TL |
982 | } |
983 | ||
8ba55c5c DB |
984 | /* This lock class tells lockdep that GPIO irqs are in a different |
985 | * category than their parents, so it won't report false recursion. | |
986 | */ | |
987 | static struct lock_class_key gpio_lock_class; | |
988 | ||
03e128ca | 989 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 990 | { |
ab985f0f TKD |
991 | void __iomem *base = bank->base; |
992 | u32 l = 0xffffffff; | |
2fae7fbe | 993 | |
ab985f0f TKD |
994 | if (bank->width == 16) |
995 | l = 0xffff; | |
996 | ||
d0d665a8 | 997 | if (bank->is_mpuio) { |
ab985f0f TKD |
998 | __raw_writel(l, bank->base + bank->regs->irqenable); |
999 | return; | |
2fae7fbe | 1000 | } |
ab985f0f TKD |
1001 | |
1002 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
6edd94db | 1003 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); |
ab985f0f | 1004 | if (bank->regs->debounce_en) |
6edd94db | 1005 | __raw_writel(0, base + bank->regs->debounce_en); |
ab985f0f | 1006 | |
2dc983c5 TKD |
1007 | /* Save OE default value (0xffffffff) in the context */ |
1008 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
1009 | /* Initialize interface clk ungated, module enabled */ |
1010 | if (bank->regs->ctrl) | |
6edd94db | 1011 | __raw_writel(0, base + bank->regs->ctrl); |
34672013 TKD |
1012 | |
1013 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1014 | if (IS_ERR(bank->dbck)) | |
1015 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1016 | } |
1017 | ||
3836309d | 1018 | static void |
f8b46b58 KH |
1019 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1020 | unsigned int num) | |
1021 | { | |
1022 | struct irq_chip_generic *gc; | |
1023 | struct irq_chip_type *ct; | |
1024 | ||
1025 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1026 | handle_simple_irq); | |
83233749 TP |
1027 | if (!gc) { |
1028 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1029 | return; | |
1030 | } | |
1031 | ||
f8b46b58 KH |
1032 | ct = gc->chip_types; |
1033 | ||
1034 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1035 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1036 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
1037 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
1038 | |
1039 | if (bank->regs->wkup_en) | |
388f4308 | 1040 | ct->chip.irq_set_wake = gpio_wake_enable; |
f8b46b58 KH |
1041 | |
1042 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1043 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1044 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1045 | } | |
1046 | ||
3836309d | 1047 | static void omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1048 | { |
77640aab | 1049 | int j; |
2fae7fbe VC |
1050 | static int gpio; |
1051 | ||
2fae7fbe VC |
1052 | /* |
1053 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1054 | * over to the generic ones | |
1055 | */ | |
1056 | bank->chip.request = omap_gpio_request; | |
1057 | bank->chip.free = omap_gpio_free; | |
1058 | bank->chip.direction_input = gpio_input; | |
1059 | bank->chip.get = gpio_get; | |
1060 | bank->chip.direction_output = gpio_output; | |
1061 | bank->chip.set_debounce = gpio_debounce; | |
1062 | bank->chip.set = gpio_set; | |
ede4d7a5 | 1063 | bank->chip.to_irq = omap_gpio_to_irq; |
d0d665a8 | 1064 | if (bank->is_mpuio) { |
2fae7fbe | 1065 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1066 | if (bank->regs->wkup_en) |
1067 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1068 | bank->chip.base = OMAP_MPUIO(0); |
1069 | } else { | |
1070 | bank->chip.label = "gpio"; | |
1071 | bank->chip.base = gpio; | |
d5f46247 | 1072 | gpio += bank->width; |
2fae7fbe | 1073 | } |
d5f46247 | 1074 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1075 | |
1076 | gpiochip_add(&bank->chip); | |
1077 | ||
ede4d7a5 JH |
1078 | for (j = 0; j < bank->width; j++) { |
1079 | int irq = irq_create_mapping(bank->domain, j); | |
1080 | irq_set_lockdep_class(irq, &gpio_lock_class); | |
1081 | irq_set_chip_data(irq, bank); | |
d0d665a8 | 1082 | if (bank->is_mpuio) { |
ede4d7a5 | 1083 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
f8b46b58 | 1084 | } else { |
ede4d7a5 JH |
1085 | irq_set_chip_and_handler(irq, &gpio_irq_chip, |
1086 | handle_simple_irq); | |
1087 | set_irq_flags(irq, IRQF_VALID); | |
f8b46b58 | 1088 | } |
2fae7fbe | 1089 | } |
6845664a TG |
1090 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1091 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1092 | } |
1093 | ||
384ebe1c BC |
1094 | static const struct of_device_id omap_gpio_match[]; |
1095 | ||
3836309d | 1096 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1097 | { |
862ff640 | 1098 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1099 | struct device_node *node = dev->of_node; |
1100 | const struct of_device_id *match; | |
f6817a2c | 1101 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1102 | struct resource *res; |
5e1c5ff4 | 1103 | struct gpio_bank *bank; |
397eada9 JMC |
1104 | #ifdef CONFIG_ARCH_OMAP1 |
1105 | int irq_base; | |
1106 | #endif | |
5e1c5ff4 | 1107 | |
384ebe1c BC |
1108 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1109 | ||
e56aee18 | 1110 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1111 | if (!pdata) |
96751fcb | 1112 | return -EINVAL; |
5492fb1a | 1113 | |
086d585f | 1114 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1115 | if (!bank) { |
862ff640 | 1116 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1117 | return -ENOMEM; |
03e128ca | 1118 | } |
92105bb7 | 1119 | |
77640aab VC |
1120 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1121 | if (unlikely(!res)) { | |
862ff640 | 1122 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1123 | return -ENODEV; |
44169075 | 1124 | } |
5e1c5ff4 | 1125 | |
77640aab | 1126 | bank->irq = res->start; |
862ff640 | 1127 | bank->dev = dev; |
77640aab | 1128 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1129 | bank->stride = pdata->bank_stride; |
d5f46247 | 1130 | bank->width = pdata->bank_width; |
d0d665a8 | 1131 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1132 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1133 | bank->regs = pdata->regs; |
384ebe1c BC |
1134 | #ifdef CONFIG_OF_GPIO |
1135 | bank->chip.of_node = of_node_get(node); | |
1136 | #endif | |
a2797bea JH |
1137 | if (node) { |
1138 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1139 | bank->loses_context = true; | |
1140 | } else { | |
1141 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1142 | |
1143 | if (bank->loses_context) | |
1144 | bank->get_context_loss_count = | |
1145 | pdata->get_context_loss_count; | |
384ebe1c BC |
1146 | } |
1147 | ||
397eada9 JMC |
1148 | #ifdef CONFIG_ARCH_OMAP1 |
1149 | /* | |
1150 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1151 | * irq_alloc_descs() and irq_domain_add_legacy() and just use a | |
1152 | * linear IRQ domain mapping for all OMAP platforms. | |
1153 | */ | |
1154 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1155 | if (irq_base < 0) { | |
1156 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
1157 | return -ENODEV; | |
1158 | } | |
384ebe1c | 1159 | |
397eada9 JMC |
1160 | bank->domain = irq_domain_add_legacy(node, bank->width, irq_base, |
1161 | 0, &irq_domain_simple_ops, NULL); | |
1162 | #else | |
ede4d7a5 JH |
1163 | bank->domain = irq_domain_add_linear(node, bank->width, |
1164 | &irq_domain_simple_ops, NULL); | |
397eada9 JMC |
1165 | #endif |
1166 | if (!bank->domain) { | |
1167 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
384ebe1c | 1168 | return -ENODEV; |
397eada9 | 1169 | } |
fa87931a KH |
1170 | |
1171 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1172 | bank->set_dataout = _set_gpio_dataout_reg; | |
1173 | else | |
1174 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1175 | |
77640aab | 1176 | spin_lock_init(&bank->lock); |
9f7065da | 1177 | |
77640aab VC |
1178 | /* Static mapping, never released */ |
1179 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1180 | if (unlikely(!res)) { | |
862ff640 | 1181 | dev_err(dev, "Invalid mem resource\n"); |
879fe324 | 1182 | irq_domain_remove(bank->domain); |
96751fcb BC |
1183 | return -ENODEV; |
1184 | } | |
1185 | ||
1186 | if (!devm_request_mem_region(dev, res->start, resource_size(res), | |
1187 | pdev->name)) { | |
1188 | dev_err(dev, "Region already claimed\n"); | |
879fe324 | 1189 | irq_domain_remove(bank->domain); |
96751fcb | 1190 | return -EBUSY; |
77640aab | 1191 | } |
89db9482 | 1192 | |
96751fcb | 1193 | bank->base = devm_ioremap(dev, res->start, resource_size(res)); |
77640aab | 1194 | if (!bank->base) { |
862ff640 | 1195 | dev_err(dev, "Could not ioremap\n"); |
879fe324 | 1196 | irq_domain_remove(bank->domain); |
96751fcb | 1197 | return -ENOMEM; |
5e1c5ff4 TL |
1198 | } |
1199 | ||
065cd795 TKD |
1200 | platform_set_drvdata(pdev, bank); |
1201 | ||
77640aab | 1202 | pm_runtime_enable(bank->dev); |
55b93c32 | 1203 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1204 | pm_runtime_get_sync(bank->dev); |
1205 | ||
d0d665a8 | 1206 | if (bank->is_mpuio) |
ab985f0f TKD |
1207 | mpuio_init(bank); |
1208 | ||
03e128ca | 1209 | omap_gpio_mod_init(bank); |
77640aab | 1210 | omap_gpio_chip_init(bank); |
9a748053 | 1211 | omap_gpio_show_rev(bank); |
9f7065da | 1212 | |
55b93c32 TKD |
1213 | pm_runtime_put(bank->dev); |
1214 | ||
03e128ca | 1215 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1216 | |
879fe324 | 1217 | return 0; |
5e1c5ff4 TL |
1218 | } |
1219 | ||
55b93c32 TKD |
1220 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1221 | ||
2dc983c5 | 1222 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1223 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1224 | |
2dc983c5 | 1225 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1226 | { |
2dc983c5 TKD |
1227 | struct platform_device *pdev = to_platform_device(dev); |
1228 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1229 | u32 l1 = 0, l2 = 0; | |
1230 | unsigned long flags; | |
68942edb | 1231 | u32 wake_low, wake_hi; |
8865b9b6 | 1232 | |
2dc983c5 | 1233 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1234 | |
1235 | /* | |
1236 | * Only edges can generate a wakeup event to the PRCM. | |
1237 | * | |
1238 | * Therefore, ensure any wake-up capable GPIOs have | |
1239 | * edge-detection enabled before going idle to ensure a wakeup | |
1240 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1241 | * NDA TRM 25.5.3.1) | |
1242 | * | |
1243 | * The normal values will be restored upon ->runtime_resume() | |
1244 | * by writing back the values saved in bank->context. | |
1245 | */ | |
1246 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1247 | if (wake_low) | |
1248 | __raw_writel(wake_low | bank->context.fallingdetect, | |
1249 | bank->base + bank->regs->fallingdetect); | |
1250 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1251 | if (wake_hi) | |
1252 | __raw_writel(wake_hi | bank->context.risingdetect, | |
1253 | bank->base + bank->regs->risingdetect); | |
1254 | ||
b3c64bc3 KH |
1255 | if (!bank->enabled_non_wakeup_gpios) |
1256 | goto update_gpio_context_count; | |
1257 | ||
2dc983c5 TKD |
1258 | if (bank->power_mode != OFF_MODE) { |
1259 | bank->power_mode = 0; | |
41d87cbd | 1260 | goto update_gpio_context_count; |
2dc983c5 TKD |
1261 | } |
1262 | /* | |
1263 | * If going to OFF, remove triggering for all | |
1264 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1265 | * generated. See OMAP2420 Errata item 1.101. | |
1266 | */ | |
2dc983c5 TKD |
1267 | bank->saved_datain = __raw_readl(bank->base + |
1268 | bank->regs->datain); | |
c6f31c9e TKD |
1269 | l1 = bank->context.fallingdetect; |
1270 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1271 | |
2dc983c5 TKD |
1272 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1273 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1274 | |
2dc983c5 TKD |
1275 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1276 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1277 | |
2dc983c5 | 1278 | bank->workaround_enabled = true; |
3f1686a9 | 1279 | |
41d87cbd | 1280 | update_gpio_context_count: |
2dc983c5 TKD |
1281 | if (bank->get_context_loss_count) |
1282 | bank->context_loss_count = | |
60a3437d TKD |
1283 | bank->get_context_loss_count(bank->dev); |
1284 | ||
72f83af9 | 1285 | _gpio_dbck_disable(bank); |
2dc983c5 | 1286 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1287 | |
2dc983c5 | 1288 | return 0; |
3ac4fa99 JY |
1289 | } |
1290 | ||
352a2d5b JH |
1291 | static void omap_gpio_init_context(struct gpio_bank *p); |
1292 | ||
2dc983c5 | 1293 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1294 | { |
2dc983c5 TKD |
1295 | struct platform_device *pdev = to_platform_device(dev); |
1296 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1297 | u32 l = 0, gen, gen0, gen1; |
1298 | unsigned long flags; | |
a2797bea | 1299 | int c; |
8865b9b6 | 1300 | |
2dc983c5 | 1301 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1302 | |
1303 | /* | |
1304 | * On the first resume during the probe, the context has not | |
1305 | * been initialised and so initialise it now. Also initialise | |
1306 | * the context loss count. | |
1307 | */ | |
1308 | if (bank->loses_context && !bank->context_valid) { | |
1309 | omap_gpio_init_context(bank); | |
1310 | ||
1311 | if (bank->get_context_loss_count) | |
1312 | bank->context_loss_count = | |
1313 | bank->get_context_loss_count(bank->dev); | |
1314 | } | |
1315 | ||
72f83af9 | 1316 | _gpio_dbck_enable(bank); |
68942edb KH |
1317 | |
1318 | /* | |
1319 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1320 | * GPIOs were set to edge trigger also in order to be able to | |
1321 | * generate a PRCM wakeup. Here we restore the | |
1322 | * pre-runtime_suspend() values for edge triggering. | |
1323 | */ | |
1324 | __raw_writel(bank->context.fallingdetect, | |
1325 | bank->base + bank->regs->fallingdetect); | |
1326 | __raw_writel(bank->context.risingdetect, | |
1327 | bank->base + bank->regs->risingdetect); | |
1328 | ||
a2797bea JH |
1329 | if (bank->loses_context) { |
1330 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1331 | omap_gpio_restore_context(bank); |
1332 | } else { | |
a2797bea JH |
1333 | c = bank->get_context_loss_count(bank->dev); |
1334 | if (c != bank->context_loss_count) { | |
1335 | omap_gpio_restore_context(bank); | |
1336 | } else { | |
1337 | spin_unlock_irqrestore(&bank->lock, flags); | |
1338 | return 0; | |
1339 | } | |
60a3437d | 1340 | } |
2dc983c5 | 1341 | } |
43ffcd9a | 1342 | |
1b128703 TKD |
1343 | if (!bank->workaround_enabled) { |
1344 | spin_unlock_irqrestore(&bank->lock, flags); | |
1345 | return 0; | |
1346 | } | |
1347 | ||
2dc983c5 | 1348 | l = __raw_readl(bank->base + bank->regs->datain); |
3f1686a9 | 1349 | |
2dc983c5 TKD |
1350 | /* |
1351 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1352 | * state. If so, generate an IRQ by software. This is | |
1353 | * horribly racy, but it's the best we can do to work around | |
1354 | * this silicon bug. | |
1355 | */ | |
1356 | l ^= bank->saved_datain; | |
1357 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1358 | |
2dc983c5 TKD |
1359 | /* |
1360 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1361 | * configured with falling edge only; and vice versa. | |
1362 | */ | |
c6f31c9e | 1363 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1364 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1365 | |
c6f31c9e | 1366 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1367 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1368 | |
2dc983c5 | 1369 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1370 | gen = l & (~(bank->context.fallingdetect) & |
1371 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1372 | /* Consider all GPIO IRQs needed to be updated */ |
1373 | gen |= gen0 | gen1; | |
82dbb9d3 | 1374 | |
2dc983c5 TKD |
1375 | if (gen) { |
1376 | u32 old0, old1; | |
82dbb9d3 | 1377 | |
2dc983c5 TKD |
1378 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1379 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1380 | |
4e962e89 | 1381 | if (!bank->regs->irqstatus_raw0) { |
2dc983c5 | 1382 | __raw_writel(old0 | gen, bank->base + |
9ea14d8c | 1383 | bank->regs->leveldetect0); |
2dc983c5 | 1384 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1385 | bank->regs->leveldetect1); |
2dc983c5 | 1386 | } |
9ea14d8c | 1387 | |
4e962e89 | 1388 | if (bank->regs->irqstatus_raw0) { |
2dc983c5 | 1389 | __raw_writel(old0 | l, bank->base + |
9ea14d8c | 1390 | bank->regs->leveldetect0); |
2dc983c5 | 1391 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1392 | bank->regs->leveldetect1); |
3ac4fa99 | 1393 | } |
2dc983c5 TKD |
1394 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1395 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1396 | } | |
1397 | ||
1398 | bank->workaround_enabled = false; | |
1399 | spin_unlock_irqrestore(&bank->lock, flags); | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | #endif /* CONFIG_PM_RUNTIME */ | |
1404 | ||
1405 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1406 | { | |
1407 | struct gpio_bank *bank; | |
1408 | ||
1409 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1410 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1411 | continue; |
1412 | ||
1413 | bank->power_mode = pwr_mode; | |
1414 | ||
2dc983c5 TKD |
1415 | pm_runtime_put_sync_suspend(bank->dev); |
1416 | } | |
1417 | } | |
1418 | ||
1419 | void omap2_gpio_resume_after_idle(void) | |
1420 | { | |
1421 | struct gpio_bank *bank; | |
1422 | ||
1423 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1424 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1425 | continue; |
1426 | ||
2dc983c5 | 1427 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1428 | } |
3ac4fa99 JY |
1429 | } |
1430 | ||
2dc983c5 | 1431 | #if defined(CONFIG_PM_RUNTIME) |
352a2d5b JH |
1432 | static void omap_gpio_init_context(struct gpio_bank *p) |
1433 | { | |
1434 | struct omap_gpio_reg_offs *regs = p->regs; | |
1435 | void __iomem *base = p->base; | |
1436 | ||
1437 | p->context.ctrl = __raw_readl(base + regs->ctrl); | |
1438 | p->context.oe = __raw_readl(base + regs->direction); | |
1439 | p->context.wake_en = __raw_readl(base + regs->wkup_en); | |
1440 | p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0); | |
1441 | p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1); | |
1442 | p->context.risingdetect = __raw_readl(base + regs->risingdetect); | |
1443 | p->context.fallingdetect = __raw_readl(base + regs->fallingdetect); | |
1444 | p->context.irqenable1 = __raw_readl(base + regs->irqenable); | |
1445 | p->context.irqenable2 = __raw_readl(base + regs->irqenable2); | |
1446 | ||
1447 | if (regs->set_dataout && p->regs->clr_dataout) | |
1448 | p->context.dataout = __raw_readl(base + regs->set_dataout); | |
1449 | else | |
1450 | p->context.dataout = __raw_readl(base + regs->dataout); | |
1451 | ||
1452 | p->context_valid = true; | |
1453 | } | |
1454 | ||
60a3437d | 1455 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1456 | { |
60a3437d | 1457 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1458 | bank->base + bank->regs->wkup_en); |
1459 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
60a3437d | 1460 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1461 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1462 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1463 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1464 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1465 | bank->base + bank->regs->risingdetect); |
60a3437d | 1466 | __raw_writel(bank->context.fallingdetect, |
ae10f233 | 1467 | bank->base + bank->regs->fallingdetect); |
f86bcc30 NM |
1468 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1469 | __raw_writel(bank->context.dataout, | |
1470 | bank->base + bank->regs->set_dataout); | |
1471 | else | |
1472 | __raw_writel(bank->context.dataout, | |
1473 | bank->base + bank->regs->dataout); | |
6d13eaaf NM |
1474 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); |
1475 | ||
ae547354 NM |
1476 | if (bank->dbck_enable_mask) { |
1477 | __raw_writel(bank->context.debounce, bank->base + | |
1478 | bank->regs->debounce); | |
1479 | __raw_writel(bank->context.debounce_en, | |
1480 | bank->base + bank->regs->debounce_en); | |
1481 | } | |
ba805be5 NM |
1482 | |
1483 | __raw_writel(bank->context.irqenable1, | |
1484 | bank->base + bank->regs->irqenable); | |
1485 | __raw_writel(bank->context.irqenable2, | |
1486 | bank->base + bank->regs->irqenable2); | |
40c670f0 | 1487 | } |
2dc983c5 | 1488 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 | 1489 | #else |
2dc983c5 TKD |
1490 | #define omap_gpio_runtime_suspend NULL |
1491 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1492 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1493 | #endif |
1494 | ||
55b93c32 | 1495 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1496 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1497 | NULL) | |
55b93c32 TKD |
1498 | }; |
1499 | ||
384ebe1c BC |
1500 | #if defined(CONFIG_OF) |
1501 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1502 | .revision = OMAP24XX_GPIO_REVISION, | |
1503 | .direction = OMAP24XX_GPIO_OE, | |
1504 | .datain = OMAP24XX_GPIO_DATAIN, | |
1505 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1506 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1507 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1508 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1509 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1510 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1511 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1512 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1513 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1514 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1515 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1516 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1517 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1518 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1519 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1520 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1521 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1522 | }; | |
1523 | ||
1524 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1525 | .revision = OMAP4_GPIO_REVISION, | |
1526 | .direction = OMAP4_GPIO_OE, | |
1527 | .datain = OMAP4_GPIO_DATAIN, | |
1528 | .dataout = OMAP4_GPIO_DATAOUT, | |
1529 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1530 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1531 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1532 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1533 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1534 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1535 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1536 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1537 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1538 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1539 | .ctrl = OMAP4_GPIO_CTRL, | |
1540 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1541 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1542 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1543 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1544 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1545 | }; | |
1546 | ||
e9a65bb6 | 1547 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1548 | .regs = &omap2_gpio_regs, |
1549 | .bank_width = 32, | |
1550 | .dbck_flag = false, | |
1551 | }; | |
1552 | ||
e9a65bb6 | 1553 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1554 | .regs = &omap2_gpio_regs, |
1555 | .bank_width = 32, | |
1556 | .dbck_flag = true, | |
1557 | }; | |
1558 | ||
e9a65bb6 | 1559 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1560 | .regs = &omap4_gpio_regs, |
1561 | .bank_width = 32, | |
1562 | .dbck_flag = true, | |
1563 | }; | |
1564 | ||
1565 | static const struct of_device_id omap_gpio_match[] = { | |
1566 | { | |
1567 | .compatible = "ti,omap4-gpio", | |
1568 | .data = &omap4_pdata, | |
1569 | }, | |
1570 | { | |
1571 | .compatible = "ti,omap3-gpio", | |
1572 | .data = &omap3_pdata, | |
1573 | }, | |
1574 | { | |
1575 | .compatible = "ti,omap2-gpio", | |
1576 | .data = &omap2_pdata, | |
1577 | }, | |
1578 | { }, | |
1579 | }; | |
1580 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1581 | #endif | |
1582 | ||
77640aab VC |
1583 | static struct platform_driver omap_gpio_driver = { |
1584 | .probe = omap_gpio_probe, | |
1585 | .driver = { | |
1586 | .name = "omap_gpio", | |
55b93c32 | 1587 | .pm = &gpio_pm_ops, |
384ebe1c | 1588 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1589 | }, |
1590 | }; | |
1591 | ||
5e1c5ff4 | 1592 | /* |
77640aab VC |
1593 | * gpio driver register needs to be done before |
1594 | * machine_init functions access gpio APIs. | |
1595 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1596 | */ |
77640aab | 1597 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1598 | { |
77640aab | 1599 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1600 | } |
77640aab | 1601 | postcore_initcall(omap_gpio_drv_reg); |