Commit | Line | Data |
---|---|---|
9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1965d303 NC |
21 | #ifdef CONFIG_OF_GPIO |
22 | #include <linux/of_platform.h> | |
1965d303 | 23 | #endif |
f32517bf | 24 | #include <linux/acpi.h> |
9e60fdcf | 25 | |
33226ffd HZ |
26 | #define PCA953X_INPUT 0 |
27 | #define PCA953X_OUTPUT 1 | |
28 | #define PCA953X_INVERT 2 | |
29 | #define PCA953X_DIRECTION 3 | |
30 | ||
ae79c190 AS |
31 | #define REG_ADDR_AI 0x80 |
32 | ||
33226ffd HZ |
33 | #define PCA957X_IN 0 |
34 | #define PCA957X_INVRT 1 | |
35 | #define PCA957X_BKEN 2 | |
36 | #define PCA957X_PUPD 3 | |
37 | #define PCA957X_CFG 4 | |
38 | #define PCA957X_OUT 5 | |
39 | #define PCA957X_MSK 6 | |
40 | #define PCA957X_INTS 7 | |
41 | ||
42 | #define PCA_GPIO_MASK 0x00FF | |
43 | #define PCA_INT 0x0100 | |
44 | #define PCA953X_TYPE 0x1000 | |
45 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
46 | #define PCA_TYPE_MASK 0xF000 |
47 | ||
48 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 49 | |
3760f736 | 50 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 51 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
52 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
53 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
54 | { "pca9536", 4 | PCA953X_TYPE, }, | |
55 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
56 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
57 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
58 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
59 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
60 | { "pca9556", 8 | PCA953X_TYPE, }, | |
61 | { "pca9557", 8 | PCA953X_TYPE, }, | |
62 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
63 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 64 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd HZ |
65 | |
66 | { "max7310", 8 | PCA953X_TYPE, }, | |
67 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
68 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
69 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
70 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
71 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
72 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 73 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 74 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 75 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 76 | { } |
f5e8ff48 | 77 | }; |
3760f736 | 78 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 79 | |
f32517bf AS |
80 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
81 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT, }, | |
82 | { } | |
83 | }; | |
84 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
85 | ||
f5f0b7aa GC |
86 | #define MAX_BANK 5 |
87 | #define BANK_SZ 8 | |
88 | ||
89 | #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ) | |
90 | ||
f3dc3630 | 91 | struct pca953x_chip { |
9e60fdcf | 92 | unsigned gpio_start; |
f5f0b7aa GC |
93 | u8 reg_output[MAX_BANK]; |
94 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 95 | struct mutex i2c_lock; |
9e60fdcf | 96 | |
89ea8bbe MZ |
97 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
98 | struct mutex irq_lock; | |
f5f0b7aa GC |
99 | u8 irq_mask[MAX_BANK]; |
100 | u8 irq_stat[MAX_BANK]; | |
101 | u8 irq_trig_raise[MAX_BANK]; | |
102 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
103 | #endif |
104 | ||
9e60fdcf | 105 | struct i2c_client *client; |
106 | struct gpio_chip gpio_chip; | |
62154991 | 107 | const char *const *names; |
33226ffd | 108 | int chip_type; |
c6664149 | 109 | unsigned long driver_data; |
9e60fdcf | 110 | }; |
111 | ||
7bcbce55 LW |
112 | static inline struct pca953x_chip *to_pca(struct gpio_chip *gc) |
113 | { | |
114 | return container_of(gc, struct pca953x_chip, gpio_chip); | |
115 | } | |
116 | ||
f5f0b7aa GC |
117 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
118 | int off) | |
119 | { | |
120 | int ret; | |
121 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
122 | int offset = off / BANK_SZ; | |
123 | ||
124 | ret = i2c_smbus_read_byte_data(chip->client, | |
125 | (reg << bank_shift) + offset); | |
126 | *val = ret; | |
127 | ||
128 | if (ret < 0) { | |
129 | dev_err(&chip->client->dev, "failed reading register\n"); | |
130 | return ret; | |
131 | } | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
137 | int off) | |
138 | { | |
139 | int ret = 0; | |
140 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
141 | int offset = off / BANK_SZ; | |
142 | ||
143 | ret = i2c_smbus_write_byte_data(chip->client, | |
144 | (reg << bank_shift) + offset, val); | |
145 | ||
146 | if (ret < 0) { | |
147 | dev_err(&chip->client->dev, "failed writing register\n"); | |
148 | return ret; | |
149 | } | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
9e60fdcf | 155 | { |
33226ffd | 156 | int ret = 0; |
f5e8ff48 GL |
157 | |
158 | if (chip->gpio_chip.ngpio <= 8) | |
f5f0b7aa GC |
159 | ret = i2c_smbus_write_byte_data(chip->client, reg, *val); |
160 | else if (chip->gpio_chip.ngpio >= 24) { | |
161 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
96b70641 | 162 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
f5f0b7aa GC |
163 | (reg << bank_shift) | REG_ADDR_AI, |
164 | NBANK(chip), val); | |
50e44430 | 165 | } else { |
33226ffd HZ |
166 | switch (chip->chip_type) { |
167 | case PCA953X_TYPE: | |
168 | ret = i2c_smbus_write_word_data(chip->client, | |
f5f0b7aa | 169 | reg << 1, (u16) *val); |
33226ffd HZ |
170 | break; |
171 | case PCA957X_TYPE: | |
172 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
f5f0b7aa | 173 | val[0]); |
33226ffd HZ |
174 | if (ret < 0) |
175 | break; | |
176 | ret = i2c_smbus_write_byte_data(chip->client, | |
177 | (reg << 1) + 1, | |
f5f0b7aa | 178 | val[1]); |
33226ffd HZ |
179 | break; |
180 | } | |
181 | } | |
f5e8ff48 GL |
182 | |
183 | if (ret < 0) { | |
184 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 185 | return ret; |
f5e8ff48 GL |
186 | } |
187 | ||
188 | return 0; | |
9e60fdcf | 189 | } |
190 | ||
f5f0b7aa | 191 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 192 | { |
193 | int ret; | |
194 | ||
96b70641 | 195 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 196 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 197 | *val = ret; |
f5f0b7aa GC |
198 | } else if (chip->gpio_chip.ngpio >= 24) { |
199 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
200 | ||
96b70641 | 201 | ret = i2c_smbus_read_i2c_block_data(chip->client, |
f5f0b7aa GC |
202 | (reg << bank_shift) | REG_ADDR_AI, |
203 | NBANK(chip), val); | |
96b70641 | 204 | } else { |
f5e8ff48 | 205 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
f5f0b7aa GC |
206 | val[0] = (u16)ret & 0xFF; |
207 | val[1] = (u16)ret >> 8; | |
96b70641 | 208 | } |
9e60fdcf | 209 | if (ret < 0) { |
210 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 211 | return ret; |
9e60fdcf | 212 | } |
213 | ||
9e60fdcf | 214 | return 0; |
215 | } | |
216 | ||
f3dc3630 | 217 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 218 | { |
7bcbce55 | 219 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 220 | u8 reg_val; |
33226ffd | 221 | int ret, offset = 0; |
9e60fdcf | 222 | |
6e20fb18 | 223 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 224 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd HZ |
225 | |
226 | switch (chip->chip_type) { | |
227 | case PCA953X_TYPE: | |
228 | offset = PCA953X_DIRECTION; | |
229 | break; | |
230 | case PCA957X_TYPE: | |
231 | offset = PCA957X_CFG; | |
232 | break; | |
233 | } | |
f5f0b7aa | 234 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 235 | if (ret) |
6e20fb18 | 236 | goto exit; |
9e60fdcf | 237 | |
f5f0b7aa | 238 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
239 | ret = 0; |
240 | exit: | |
241 | mutex_unlock(&chip->i2c_lock); | |
242 | return ret; | |
9e60fdcf | 243 | } |
244 | ||
f3dc3630 | 245 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 246 | unsigned off, int val) |
247 | { | |
7bcbce55 | 248 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 249 | u8 reg_val; |
33226ffd | 250 | int ret, offset = 0; |
9e60fdcf | 251 | |
6e20fb18 | 252 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 253 | /* set output level */ |
254 | if (val) | |
f5f0b7aa GC |
255 | reg_val = chip->reg_output[off / BANK_SZ] |
256 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 257 | else |
f5f0b7aa GC |
258 | reg_val = chip->reg_output[off / BANK_SZ] |
259 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 260 | |
33226ffd HZ |
261 | switch (chip->chip_type) { |
262 | case PCA953X_TYPE: | |
263 | offset = PCA953X_OUTPUT; | |
264 | break; | |
265 | case PCA957X_TYPE: | |
266 | offset = PCA957X_OUT; | |
267 | break; | |
268 | } | |
f5f0b7aa | 269 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 270 | if (ret) |
6e20fb18 | 271 | goto exit; |
9e60fdcf | 272 | |
f5f0b7aa | 273 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 274 | |
275 | /* then direction */ | |
f5f0b7aa | 276 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
33226ffd HZ |
277 | switch (chip->chip_type) { |
278 | case PCA953X_TYPE: | |
279 | offset = PCA953X_DIRECTION; | |
280 | break; | |
281 | case PCA957X_TYPE: | |
282 | offset = PCA957X_CFG; | |
283 | break; | |
284 | } | |
f5f0b7aa | 285 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 286 | if (ret) |
6e20fb18 | 287 | goto exit; |
9e60fdcf | 288 | |
f5f0b7aa | 289 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
290 | ret = 0; |
291 | exit: | |
292 | mutex_unlock(&chip->i2c_lock); | |
293 | return ret; | |
9e60fdcf | 294 | } |
295 | ||
f3dc3630 | 296 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 297 | { |
7bcbce55 | 298 | struct pca953x_chip *chip = to_pca(gc); |
ae79c190 | 299 | u32 reg_val; |
33226ffd | 300 | int ret, offset = 0; |
9e60fdcf | 301 | |
6e20fb18 | 302 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
303 | switch (chip->chip_type) { |
304 | case PCA953X_TYPE: | |
305 | offset = PCA953X_INPUT; | |
306 | break; | |
307 | case PCA957X_TYPE: | |
308 | offset = PCA957X_IN; | |
309 | break; | |
310 | } | |
f5f0b7aa | 311 | ret = pca953x_read_single(chip, offset, ®_val, off); |
6e20fb18 | 312 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 313 | if (ret < 0) { |
314 | /* NOTE: diagnostic already emitted; that's all we should | |
315 | * do unless gpio_*_value_cansleep() calls become different | |
316 | * from their nonsleeping siblings (and report faults). | |
317 | */ | |
318 | return 0; | |
319 | } | |
320 | ||
40a625da | 321 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 322 | } |
323 | ||
f3dc3630 | 324 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 325 | { |
7bcbce55 | 326 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 327 | u8 reg_val; |
33226ffd | 328 | int ret, offset = 0; |
9e60fdcf | 329 | |
6e20fb18 | 330 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 331 | if (val) |
f5f0b7aa GC |
332 | reg_val = chip->reg_output[off / BANK_SZ] |
333 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 334 | else |
f5f0b7aa GC |
335 | reg_val = chip->reg_output[off / BANK_SZ] |
336 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 337 | |
33226ffd HZ |
338 | switch (chip->chip_type) { |
339 | case PCA953X_TYPE: | |
340 | offset = PCA953X_OUTPUT; | |
341 | break; | |
342 | case PCA957X_TYPE: | |
343 | offset = PCA957X_OUT; | |
344 | break; | |
345 | } | |
f5f0b7aa | 346 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 347 | if (ret) |
6e20fb18 | 348 | goto exit; |
9e60fdcf | 349 | |
f5f0b7aa | 350 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
351 | exit: |
352 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 353 | } |
354 | ||
f5e8ff48 | 355 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 356 | { |
357 | struct gpio_chip *gc; | |
358 | ||
359 | gc = &chip->gpio_chip; | |
360 | ||
f3dc3630 GL |
361 | gc->direction_input = pca953x_gpio_direction_input; |
362 | gc->direction_output = pca953x_gpio_direction_output; | |
363 | gc->get = pca953x_gpio_get_value; | |
364 | gc->set = pca953x_gpio_set_value; | |
9fb1f39e | 365 | gc->can_sleep = true; |
9e60fdcf | 366 | |
367 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
368 | gc->ngpio = gpios; |
369 | gc->label = chip->client->name; | |
58383c78 | 370 | gc->parent = &chip->client->dev; |
d72cbed0 | 371 | gc->owner = THIS_MODULE; |
77906a54 | 372 | gc->names = chip->names; |
9e60fdcf | 373 | } |
374 | ||
89ea8bbe | 375 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 376 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 377 | { |
7bcbce55 LW |
378 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
379 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe | 380 | |
f5f0b7aa | 381 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
382 | } |
383 | ||
6f5cfc0e | 384 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 385 | { |
7bcbce55 LW |
386 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
387 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe | 388 | |
f5f0b7aa | 389 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
390 | } |
391 | ||
6f5cfc0e | 392 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 393 | { |
7bcbce55 LW |
394 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
395 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe MZ |
396 | |
397 | mutex_lock(&chip->irq_lock); | |
398 | } | |
399 | ||
6f5cfc0e | 400 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 401 | { |
7bcbce55 LW |
402 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
403 | struct pca953x_chip *chip = to_pca(gc); | |
f5f0b7aa GC |
404 | u8 new_irqs; |
405 | int level, i; | |
a2cb9aeb MZ |
406 | |
407 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
408 | for (i = 0; i < NBANK(chip); i++) { |
409 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
410 | new_irqs &= ~chip->reg_direction[i]; | |
411 | ||
412 | while (new_irqs) { | |
413 | level = __ffs(new_irqs); | |
414 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
415 | level + (BANK_SZ * i)); | |
416 | new_irqs &= ~(1 << level); | |
417 | } | |
a2cb9aeb | 418 | } |
89ea8bbe MZ |
419 | |
420 | mutex_unlock(&chip->irq_lock); | |
421 | } | |
422 | ||
6f5cfc0e | 423 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 424 | { |
7bcbce55 LW |
425 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
426 | struct pca953x_chip *chip = to_pca(gc); | |
f5f0b7aa GC |
427 | int bank_nb = d->hwirq / BANK_SZ; |
428 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
429 | |
430 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
431 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 432 | d->irq, type); |
89ea8bbe MZ |
433 | return -EINVAL; |
434 | } | |
435 | ||
436 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 437 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 438 | else |
f5f0b7aa | 439 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
440 | |
441 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 442 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 443 | else |
f5f0b7aa | 444 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 445 | |
a2cb9aeb | 446 | return 0; |
89ea8bbe MZ |
447 | } |
448 | ||
449 | static struct irq_chip pca953x_irq_chip = { | |
450 | .name = "pca953x", | |
6f5cfc0e LB |
451 | .irq_mask = pca953x_irq_mask, |
452 | .irq_unmask = pca953x_irq_unmask, | |
453 | .irq_bus_lock = pca953x_irq_bus_lock, | |
454 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
455 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
456 | }; |
457 | ||
b6ac1280 | 458 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 459 | { |
f5f0b7aa GC |
460 | u8 cur_stat[MAX_BANK]; |
461 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
462 | bool pending_seen = false; |
463 | bool trigger_seen = false; | |
464 | u8 trigger[MAX_BANK]; | |
f5f0b7aa | 465 | int ret, i, offset = 0; |
33226ffd HZ |
466 | |
467 | switch (chip->chip_type) { | |
468 | case PCA953X_TYPE: | |
469 | offset = PCA953X_INPUT; | |
470 | break; | |
471 | case PCA957X_TYPE: | |
472 | offset = PCA957X_IN; | |
473 | break; | |
474 | } | |
f5f0b7aa | 475 | ret = pca953x_read_regs(chip, offset, cur_stat); |
89ea8bbe | 476 | if (ret) |
b6ac1280 | 477 | return false; |
89ea8bbe MZ |
478 | |
479 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
480 | for (i = 0; i < NBANK(chip); i++) |
481 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 482 | |
f5f0b7aa | 483 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 484 | |
f5f0b7aa GC |
485 | for (i = 0; i < NBANK(chip); i++) { |
486 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
487 | if (trigger[i]) |
488 | trigger_seen = true; | |
f5f0b7aa GC |
489 | } |
490 | ||
b6ac1280 JS |
491 | if (!trigger_seen) |
492 | return false; | |
89ea8bbe | 493 | |
f5f0b7aa | 494 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 495 | |
f5f0b7aa GC |
496 | for (i = 0; i < NBANK(chip); i++) { |
497 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
498 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
499 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
500 | if (pending[i]) |
501 | pending_seen = true; | |
f5f0b7aa | 502 | } |
89ea8bbe | 503 | |
b6ac1280 | 504 | return pending_seen; |
89ea8bbe MZ |
505 | } |
506 | ||
507 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
508 | { | |
509 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
510 | u8 pending[MAX_BANK]; |
511 | u8 level; | |
3275d072 | 512 | unsigned nhandled = 0; |
f5f0b7aa | 513 | int i; |
89ea8bbe | 514 | |
f5f0b7aa | 515 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 516 | return IRQ_NONE; |
89ea8bbe | 517 | |
f5f0b7aa GC |
518 | for (i = 0; i < NBANK(chip); i++) { |
519 | while (pending[i]) { | |
520 | level = __ffs(pending[i]); | |
7bcbce55 | 521 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
522 | level + (BANK_SZ * i))); |
523 | pending[i] &= ~(1 << level); | |
3275d072 | 524 | nhandled++; |
f5f0b7aa GC |
525 | } |
526 | } | |
89ea8bbe | 527 | |
3275d072 | 528 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
529 | } |
530 | ||
531 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 532 | int irq_base) |
89ea8bbe MZ |
533 | { |
534 | struct i2c_client *client = chip->client; | |
f5f0b7aa | 535 | int ret, i, offset = 0; |
89ea8bbe | 536 | |
4bb93349 | 537 | if (client->irq && irq_base != -1 |
c6664149 | 538 | && (chip->driver_data & PCA_INT)) { |
89ea8bbe | 539 | |
33226ffd HZ |
540 | switch (chip->chip_type) { |
541 | case PCA953X_TYPE: | |
542 | offset = PCA953X_INPUT; | |
543 | break; | |
544 | case PCA957X_TYPE: | |
545 | offset = PCA957X_IN; | |
546 | break; | |
547 | } | |
f5f0b7aa | 548 | ret = pca953x_read_regs(chip, offset, chip->irq_stat); |
89ea8bbe | 549 | if (ret) |
b42748c9 | 550 | return ret; |
89ea8bbe MZ |
551 | |
552 | /* | |
553 | * There is no way to know which GPIO line generated the | |
554 | * interrupt. We have to rely on the previous read for | |
555 | * this purpose. | |
556 | */ | |
f5f0b7aa GC |
557 | for (i = 0; i < NBANK(chip); i++) |
558 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
559 | mutex_init(&chip->irq_lock); |
560 | ||
b42748c9 LW |
561 | ret = devm_request_threaded_irq(&client->dev, |
562 | client->irq, | |
89ea8bbe MZ |
563 | NULL, |
564 | pca953x_irq_handler, | |
91329132 TS |
565 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
566 | IRQF_SHARED, | |
89ea8bbe MZ |
567 | dev_name(&client->dev), chip); |
568 | if (ret) { | |
569 | dev_err(&client->dev, "failed to request irq %d\n", | |
570 | client->irq); | |
0e8f2fda | 571 | return ret; |
89ea8bbe MZ |
572 | } |
573 | ||
7bcbce55 LW |
574 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
575 | &pca953x_irq_chip, | |
576 | irq_base, | |
577 | handle_simple_irq, | |
578 | IRQ_TYPE_NONE); | |
579 | if (ret) { | |
580 | dev_err(&client->dev, | |
581 | "could not connect irqchip to gpiochip\n"); | |
582 | return ret; | |
583 | } | |
fdd50409 GS |
584 | |
585 | gpiochip_set_chained_irqchip(&chip->gpio_chip, | |
586 | &pca953x_irq_chip, | |
587 | client->irq, NULL); | |
89ea8bbe MZ |
588 | } |
589 | ||
590 | return 0; | |
89ea8bbe MZ |
591 | } |
592 | ||
89ea8bbe MZ |
593 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
594 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 595 | int irq_base) |
89ea8bbe MZ |
596 | { |
597 | struct i2c_client *client = chip->client; | |
89ea8bbe | 598 | |
c6664149 | 599 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
600 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
601 | ||
602 | return 0; | |
603 | } | |
89ea8bbe MZ |
604 | #endif |
605 | ||
3836309d | 606 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
607 | { |
608 | int ret; | |
f5f0b7aa | 609 | u8 val[MAX_BANK]; |
33226ffd | 610 | |
f5f0b7aa | 611 | ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output); |
33226ffd HZ |
612 | if (ret) |
613 | goto out; | |
614 | ||
f5f0b7aa GC |
615 | ret = pca953x_read_regs(chip, PCA953X_DIRECTION, |
616 | chip->reg_direction); | |
33226ffd HZ |
617 | if (ret) |
618 | goto out; | |
619 | ||
620 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
621 | if (invert) |
622 | memset(val, 0xFF, NBANK(chip)); | |
623 | else | |
624 | memset(val, 0, NBANK(chip)); | |
625 | ||
626 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
627 | out: |
628 | return ret; | |
629 | } | |
630 | ||
3836309d | 631 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
632 | { |
633 | int ret; | |
f5f0b7aa | 634 | u8 val[MAX_BANK]; |
33226ffd | 635 | |
f5f0b7aa | 636 | ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output); |
33226ffd HZ |
637 | if (ret) |
638 | goto out; | |
f5f0b7aa | 639 | ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction); |
33226ffd HZ |
640 | if (ret) |
641 | goto out; | |
642 | ||
643 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
644 | if (invert) |
645 | memset(val, 0xFF, NBANK(chip)); | |
646 | else | |
647 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
648 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
649 | if (ret) | |
650 | goto out; | |
33226ffd | 651 | |
20a8a968 | 652 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 653 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
654 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
655 | if (ret) | |
656 | goto out; | |
33226ffd HZ |
657 | |
658 | return 0; | |
659 | out: | |
660 | return ret; | |
661 | } | |
662 | ||
3836309d | 663 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 664 | const struct i2c_device_id *id) |
9e60fdcf | 665 | { |
f3dc3630 GL |
666 | struct pca953x_platform_data *pdata; |
667 | struct pca953x_chip *chip; | |
6a7b36aa | 668 | int irq_base = 0; |
7ea2aa20 | 669 | int ret; |
6a7b36aa | 670 | u32 invert = 0; |
9e60fdcf | 671 | |
b42748c9 LW |
672 | chip = devm_kzalloc(&client->dev, |
673 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
674 | if (chip == NULL) |
675 | return -ENOMEM; | |
676 | ||
e56aee18 | 677 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
678 | if (pdata) { |
679 | irq_base = pdata->irq_base; | |
680 | chip->gpio_start = pdata->gpio_base; | |
681 | invert = pdata->invert; | |
682 | chip->names = pdata->names; | |
683 | } else { | |
4bb93349 MP |
684 | chip->gpio_start = -1; |
685 | irq_base = 0; | |
1965d303 | 686 | } |
9e60fdcf | 687 | |
688 | chip->client = client; | |
689 | ||
f32517bf AS |
690 | if (id) { |
691 | chip->driver_data = id->driver_data; | |
692 | } else { | |
693 | const struct acpi_device_id *id; | |
694 | ||
695 | id = acpi_match_device(pca953x_acpi_ids, &client->dev); | |
696 | if (!id) | |
697 | return -ENODEV; | |
698 | ||
699 | chip->driver_data = id->driver_data; | |
700 | } | |
701 | ||
c6664149 | 702 | chip->chip_type = PCA_CHIP_TYPE(chip->driver_data); |
77906a54 | 703 | |
6e20fb18 RS |
704 | mutex_init(&chip->i2c_lock); |
705 | ||
9e60fdcf | 706 | /* initialize cached registers from their original values. |
707 | * we can't share this chip with another i2c master. | |
708 | */ | |
c6664149 | 709 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 710 | |
33226ffd | 711 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 712 | ret = device_pca953x_init(chip, invert); |
33226ffd | 713 | else |
7ea2aa20 WS |
714 | ret = device_pca957x_init(chip, invert); |
715 | if (ret) | |
b42748c9 | 716 | return ret; |
9e60fdcf | 717 | |
7bcbce55 | 718 | ret = gpiochip_add(&chip->gpio_chip); |
89ea8bbe | 719 | if (ret) |
b42748c9 | 720 | return ret; |
f5e8ff48 | 721 | |
c6664149 | 722 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 723 | if (ret) |
b42748c9 | 724 | return ret; |
9e60fdcf | 725 | |
c6dcf592 | 726 | if (pdata && pdata->setup) { |
9e60fdcf | 727 | ret = pdata->setup(client, chip->gpio_chip.base, |
728 | chip->gpio_chip.ngpio, pdata->context); | |
729 | if (ret < 0) | |
730 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
731 | } | |
732 | ||
733 | i2c_set_clientdata(client, chip); | |
734 | return 0; | |
9e60fdcf | 735 | } |
736 | ||
f3dc3630 | 737 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 738 | { |
e56aee18 | 739 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 740 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
9e60fdcf | 741 | int ret = 0; |
742 | ||
c6dcf592 | 743 | if (pdata && pdata->teardown) { |
9e60fdcf | 744 | ret = pdata->teardown(client, chip->gpio_chip.base, |
745 | chip->gpio_chip.ngpio, pdata->context); | |
746 | if (ret < 0) { | |
747 | dev_err(&client->dev, "%s failed, %d\n", | |
748 | "teardown", ret); | |
749 | return ret; | |
750 | } | |
751 | } | |
752 | ||
9f5132ae | 753 | gpiochip_remove(&chip->gpio_chip); |
9e60fdcf | 754 | |
9e60fdcf | 755 | return 0; |
756 | } | |
757 | ||
ed32620e | 758 | static const struct of_device_id pca953x_dt_ids[] = { |
89f5df01 | 759 | { .compatible = "nxp,pca9505", }, |
ed32620e MR |
760 | { .compatible = "nxp,pca9534", }, |
761 | { .compatible = "nxp,pca9535", }, | |
762 | { .compatible = "nxp,pca9536", }, | |
763 | { .compatible = "nxp,pca9537", }, | |
764 | { .compatible = "nxp,pca9538", }, | |
765 | { .compatible = "nxp,pca9539", }, | |
766 | { .compatible = "nxp,pca9554", }, | |
767 | { .compatible = "nxp,pca9555", }, | |
768 | { .compatible = "nxp,pca9556", }, | |
769 | { .compatible = "nxp,pca9557", }, | |
770 | { .compatible = "nxp,pca9574", }, | |
771 | { .compatible = "nxp,pca9575", }, | |
eb32b5aa | 772 | { .compatible = "nxp,pca9698", }, |
ed32620e MR |
773 | |
774 | { .compatible = "maxim,max7310", }, | |
775 | { .compatible = "maxim,max7312", }, | |
776 | { .compatible = "maxim,max7313", }, | |
777 | { .compatible = "maxim,max7315", }, | |
778 | ||
779 | { .compatible = "ti,pca6107", }, | |
780 | { .compatible = "ti,tca6408", }, | |
781 | { .compatible = "ti,tca6416", }, | |
782 | { .compatible = "ti,tca6424", }, | |
e73760a6 | 783 | |
9f49f6dd BD |
784 | { .compatible = "onsemi,pca9654" }, |
785 | ||
e73760a6 | 786 | { .compatible = "exar,xra1202", }, |
ed32620e MR |
787 | { } |
788 | }; | |
789 | ||
790 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
791 | ||
f3dc3630 | 792 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 793 | .driver = { |
f3dc3630 | 794 | .name = "pca953x", |
ed32620e | 795 | .of_match_table = pca953x_dt_ids, |
f32517bf | 796 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 797 | }, |
f3dc3630 GL |
798 | .probe = pca953x_probe, |
799 | .remove = pca953x_remove, | |
3760f736 | 800 | .id_table = pca953x_id, |
9e60fdcf | 801 | }; |
802 | ||
f3dc3630 | 803 | static int __init pca953x_init(void) |
9e60fdcf | 804 | { |
f3dc3630 | 805 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 806 | } |
2f8d1197 DB |
807 | /* register after i2c postcore initcall and before |
808 | * subsys initcalls that may rely on these GPIOs | |
809 | */ | |
810 | subsys_initcall(pca953x_init); | |
9e60fdcf | 811 | |
f3dc3630 | 812 | static void __exit pca953x_exit(void) |
9e60fdcf | 813 | { |
f3dc3630 | 814 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 815 | } |
f3dc3630 | 816 | module_exit(pca953x_exit); |
9e60fdcf | 817 | |
818 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 819 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 820 | MODULE_LICENSE("GPL"); |