Commit | Line | Data |
---|---|---|
04c17aa8 | 1 | /* |
f4574beb | 2 | * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
04c17aa8 TM |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
bb207ef1 | 17 | #include <linux/module.h> |
04c17aa8 TM |
18 | #include <linux/kernel.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/gpio.h> | |
38eb18a6 TM |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | ||
24 | #define PCH_EDGE_FALLING 0 | |
25 | #define PCH_EDGE_RISING BIT(0) | |
26 | #define PCH_LEVEL_L BIT(1) | |
27 | #define PCH_LEVEL_H (BIT(0) | BIT(1)) | |
28 | #define PCH_EDGE_BOTH BIT(2) | |
29 | #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) | |
30 | ||
31 | #define PCH_IRQ_BASE 24 | |
04c17aa8 | 32 | |
04c17aa8 TM |
33 | struct pch_regs { |
34 | u32 ien; | |
35 | u32 istatus; | |
36 | u32 idisp; | |
37 | u32 iclr; | |
38 | u32 imask; | |
39 | u32 imaskclr; | |
40 | u32 po; | |
41 | u32 pi; | |
42 | u32 pm; | |
43 | u32 im0; | |
44 | u32 im1; | |
e98bed7f TM |
45 | u32 reserved[3]; |
46 | u32 gpio_use_sel; | |
04c17aa8 TM |
47 | u32 reset; |
48 | }; | |
49 | ||
d4260e6d TM |
50 | enum pch_type_t { |
51 | INTEL_EG20T_PCH, | |
f4574beb TM |
52 | OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */ |
53 | OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */ | |
d4260e6d TM |
54 | }; |
55 | ||
56 | /* Specifies number of GPIO PINS */ | |
57 | static int gpio_pins[] = { | |
58 | [INTEL_EG20T_PCH] = 12, | |
59 | [OKISEMI_ML7223m_IOH] = 8, | |
60 | [OKISEMI_ML7223n_IOH] = 8, | |
61 | }; | |
62 | ||
04c17aa8 TM |
63 | /** |
64 | * struct pch_gpio_reg_data - The register store data. | |
38eb18a6 TM |
65 | * @ien_reg: To store contents of IEN register. |
66 | * @imask_reg: To store contents of IMASK register. | |
04c17aa8 TM |
67 | * @po_reg: To store contents of PO register. |
68 | * @pm_reg: To store contents of PM register. | |
e98bed7f TM |
69 | * @im0_reg: To store contents of IM0 register. |
70 | * @im1_reg: To store contents of IM1 register. | |
71 | * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. | |
72 | * (Only ML7223 Bus-n) | |
04c17aa8 TM |
73 | */ |
74 | struct pch_gpio_reg_data { | |
38eb18a6 TM |
75 | u32 ien_reg; |
76 | u32 imask_reg; | |
04c17aa8 TM |
77 | u32 po_reg; |
78 | u32 pm_reg; | |
e98bed7f TM |
79 | u32 im0_reg; |
80 | u32 im1_reg; | |
81 | u32 gpio_use_sel_reg; | |
04c17aa8 TM |
82 | }; |
83 | ||
84 | /** | |
85 | * struct pch_gpio - GPIO private data structure. | |
86 | * @base: PCI base address of Memory mapped I/O register. | |
87 | * @reg: Memory mapped PCH GPIO register list. | |
88 | * @dev: Pointer to device structure. | |
89 | * @gpio: Data for GPIO infrastructure. | |
90 | * @pch_gpio_reg: Memory mapped Register data is saved here | |
91 | * when suspend. | |
38eb18a6 TM |
92 | * @lock: Used for register access protection |
93 | * @irq_base: Save base of IRQ number for interrupt | |
d4260e6d | 94 | * @ioh: IOH ID |
7cb6580c | 95 | * @spinlock: Used for register access protection |
04c17aa8 TM |
96 | */ |
97 | struct pch_gpio { | |
98 | void __iomem *base; | |
99 | struct pch_regs __iomem *reg; | |
100 | struct device *dev; | |
101 | struct gpio_chip gpio; | |
102 | struct pch_gpio_reg_data pch_gpio_reg; | |
38eb18a6 | 103 | int irq_base; |
d4260e6d | 104 | enum pch_type_t ioh; |
d568a681 | 105 | spinlock_t spinlock; |
04c17aa8 TM |
106 | }; |
107 | ||
108 | static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) | |
109 | { | |
110 | u32 reg_val; | |
111 | struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); | |
7cb6580c | 112 | unsigned long flags; |
04c17aa8 | 113 | |
7cb6580c | 114 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 TM |
115 | reg_val = ioread32(&chip->reg->po); |
116 | if (val) | |
117 | reg_val |= (1 << nr); | |
118 | else | |
119 | reg_val &= ~(1 << nr); | |
120 | ||
121 | iowrite32(reg_val, &chip->reg->po); | |
7cb6580c | 122 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
123 | } |
124 | ||
125 | static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr) | |
126 | { | |
127 | struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); | |
128 | ||
129 | return ioread32(&chip->reg->pi) & (1 << nr); | |
130 | } | |
131 | ||
132 | static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, | |
133 | int val) | |
134 | { | |
135 | struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); | |
136 | u32 pm; | |
137 | u32 reg_val; | |
7cb6580c | 138 | unsigned long flags; |
04c17aa8 | 139 | |
7cb6580c | 140 | spin_lock_irqsave(&chip->spinlock, flags); |
d4260e6d | 141 | pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); |
04c17aa8 TM |
142 | pm |= (1 << nr); |
143 | iowrite32(pm, &chip->reg->pm); | |
144 | ||
145 | reg_val = ioread32(&chip->reg->po); | |
146 | if (val) | |
147 | reg_val |= (1 << nr); | |
148 | else | |
149 | reg_val &= ~(1 << nr); | |
88aab934 | 150 | iowrite32(reg_val, &chip->reg->po); |
7cb6580c | 151 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
152 | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) | |
157 | { | |
158 | struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); | |
159 | u32 pm; | |
7cb6580c | 160 | unsigned long flags; |
04c17aa8 | 161 | |
7cb6580c | 162 | spin_lock_irqsave(&chip->spinlock, flags); |
d4260e6d | 163 | pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); |
04c17aa8 TM |
164 | pm &= ~(1 << nr); |
165 | iowrite32(pm, &chip->reg->pm); | |
7cb6580c | 166 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
167 | |
168 | return 0; | |
169 | } | |
170 | ||
171 | /* | |
172 | * Save register configuration and disable interrupts. | |
173 | */ | |
174 | static void pch_gpio_save_reg_conf(struct pch_gpio *chip) | |
175 | { | |
38eb18a6 TM |
176 | chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); |
177 | chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); | |
04c17aa8 TM |
178 | chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); |
179 | chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); | |
e98bed7f TM |
180 | chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); |
181 | if (chip->ioh == INTEL_EG20T_PCH) | |
182 | chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); | |
183 | if (chip->ioh == OKISEMI_ML7223n_IOH) | |
184 | chip->pch_gpio_reg.gpio_use_sel_reg =\ | |
185 | ioread32(&chip->reg->gpio_use_sel); | |
04c17aa8 TM |
186 | } |
187 | ||
188 | /* | |
189 | * This function restores the register configuration of the GPIO device. | |
190 | */ | |
191 | static void pch_gpio_restore_reg_conf(struct pch_gpio *chip) | |
192 | { | |
38eb18a6 TM |
193 | iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); |
194 | iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); | |
04c17aa8 TM |
195 | /* to store contents of PO register */ |
196 | iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); | |
197 | /* to store contents of PM register */ | |
198 | iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); | |
e98bed7f TM |
199 | iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); |
200 | if (chip->ioh == INTEL_EG20T_PCH) | |
201 | iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); | |
202 | if (chip->ioh == OKISEMI_ML7223n_IOH) | |
203 | iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, | |
204 | &chip->reg->gpio_use_sel); | |
04c17aa8 TM |
205 | } |
206 | ||
38eb18a6 TM |
207 | static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) |
208 | { | |
209 | struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); | |
210 | return chip->irq_base + offset; | |
211 | } | |
212 | ||
04c17aa8 TM |
213 | static void pch_gpio_setup(struct pch_gpio *chip) |
214 | { | |
215 | struct gpio_chip *gpio = &chip->gpio; | |
216 | ||
217 | gpio->label = dev_name(chip->dev); | |
5c868fc6 | 218 | gpio->dev = chip->dev; |
04c17aa8 TM |
219 | gpio->owner = THIS_MODULE; |
220 | gpio->direction_input = pch_gpio_direction_input; | |
221 | gpio->get = pch_gpio_get; | |
222 | gpio->direction_output = pch_gpio_direction_output; | |
223 | gpio->set = pch_gpio_set; | |
224 | gpio->dbg_show = NULL; | |
225 | gpio->base = -1; | |
d4260e6d | 226 | gpio->ngpio = gpio_pins[chip->ioh]; |
04c17aa8 | 227 | gpio->can_sleep = 0; |
38eb18a6 TM |
228 | gpio->to_irq = pch_gpio_to_irq; |
229 | } | |
230 | ||
231 | static int pch_irq_type(struct irq_data *d, unsigned int type) | |
232 | { | |
38eb18a6 TM |
233 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
234 | struct pch_gpio *chip = gc->private; | |
df9541a6 TG |
235 | u32 im, im_pos, val; |
236 | u32 __iomem *im_reg; | |
237 | unsigned long flags; | |
238 | int ch, irq = d->irq; | |
38eb18a6 TM |
239 | |
240 | ch = irq - chip->irq_base; | |
241 | if (irq <= chip->irq_base + 7) { | |
242 | im_reg = &chip->reg->im0; | |
243 | im_pos = ch; | |
244 | } else { | |
245 | im_reg = &chip->reg->im1; | |
246 | im_pos = ch - 8; | |
247 | } | |
248 | dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n", | |
249 | __func__, irq, type, ch, im_pos); | |
250 | ||
251 | spin_lock_irqsave(&chip->spinlock, flags); | |
252 | ||
253 | switch (type) { | |
254 | case IRQ_TYPE_EDGE_RISING: | |
255 | val = PCH_EDGE_RISING; | |
256 | break; | |
257 | case IRQ_TYPE_EDGE_FALLING: | |
258 | val = PCH_EDGE_FALLING; | |
259 | break; | |
260 | case IRQ_TYPE_EDGE_BOTH: | |
261 | val = PCH_EDGE_BOTH; | |
262 | break; | |
263 | case IRQ_TYPE_LEVEL_HIGH: | |
264 | val = PCH_LEVEL_H; | |
265 | break; | |
266 | case IRQ_TYPE_LEVEL_LOW: | |
267 | val = PCH_LEVEL_L; | |
268 | break; | |
38eb18a6 | 269 | default: |
df9541a6 | 270 | goto unlock; |
38eb18a6 TM |
271 | } |
272 | ||
273 | /* Set interrupt mode */ | |
274 | im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4)); | |
275 | iowrite32(im | (val << (im_pos * 4)), im_reg); | |
276 | ||
df9541a6 TG |
277 | /* And the handler */ |
278 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
279 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
280 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
281 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
38eb18a6 | 282 | |
df9541a6 | 283 | unlock: |
38eb18a6 | 284 | spin_unlock_irqrestore(&chip->spinlock, flags); |
38eb18a6 TM |
285 | return 0; |
286 | } | |
287 | ||
288 | static void pch_irq_unmask(struct irq_data *d) | |
289 | { | |
290 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
291 | struct pch_gpio *chip = gc->private; | |
292 | ||
293 | iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr); | |
294 | } | |
295 | ||
296 | static void pch_irq_mask(struct irq_data *d) | |
297 | { | |
298 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
299 | struct pch_gpio *chip = gc->private; | |
300 | ||
301 | iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask); | |
302 | } | |
303 | ||
df9541a6 TG |
304 | static void pch_irq_ack(struct irq_data *d) |
305 | { | |
306 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
307 | struct pch_gpio *chip = gc->private; | |
308 | ||
309 | iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr); | |
310 | } | |
311 | ||
38eb18a6 TM |
312 | static irqreturn_t pch_gpio_handler(int irq, void *dev_id) |
313 | { | |
314 | struct pch_gpio *chip = dev_id; | |
315 | u32 reg_val = ioread32(&chip->reg->istatus); | |
df9541a6 | 316 | int i, ret = IRQ_NONE; |
38eb18a6 TM |
317 | |
318 | for (i = 0; i < gpio_pins[chip->ioh]; i++) { | |
319 | if (reg_val & BIT(i)) { | |
320 | dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n", | |
321 | __func__, i, irq, reg_val); | |
38eb18a6 TM |
322 | generic_handle_irq(chip->irq_base + i); |
323 | ret = IRQ_HANDLED; | |
324 | } | |
325 | } | |
326 | return ret; | |
327 | } | |
328 | ||
3836309d | 329 | static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip, |
38eb18a6 TM |
330 | unsigned int irq_start, unsigned int num) |
331 | { | |
332 | struct irq_chip_generic *gc; | |
333 | struct irq_chip_type *ct; | |
334 | ||
335 | gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base, | |
336 | handle_simple_irq); | |
337 | gc->private = chip; | |
338 | ct = gc->chip_types; | |
339 | ||
df9541a6 | 340 | ct->chip.irq_ack = pch_irq_ack; |
38eb18a6 TM |
341 | ct->chip.irq_mask = pch_irq_mask; |
342 | ct->chip.irq_unmask = pch_irq_unmask; | |
343 | ct->chip.irq_set_type = pch_irq_type; | |
344 | ||
345 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
346 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
04c17aa8 TM |
347 | } |
348 | ||
3836309d | 349 | static int pch_gpio_probe(struct pci_dev *pdev, |
04c17aa8 TM |
350 | const struct pci_device_id *id) |
351 | { | |
352 | s32 ret; | |
353 | struct pch_gpio *chip; | |
38eb18a6 | 354 | int irq_base; |
df9541a6 | 355 | u32 msk; |
04c17aa8 TM |
356 | |
357 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | |
358 | if (chip == NULL) | |
359 | return -ENOMEM; | |
360 | ||
361 | chip->dev = &pdev->dev; | |
362 | ret = pci_enable_device(pdev); | |
363 | if (ret) { | |
364 | dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__); | |
365 | goto err_pci_enable; | |
366 | } | |
367 | ||
368 | ret = pci_request_regions(pdev, KBUILD_MODNAME); | |
369 | if (ret) { | |
370 | dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret); | |
371 | goto err_request_regions; | |
372 | } | |
373 | ||
374 | chip->base = pci_iomap(pdev, 1, 0); | |
c4addcb5 | 375 | if (!chip->base) { |
04c17aa8 TM |
376 | dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); |
377 | ret = -ENOMEM; | |
378 | goto err_iomap; | |
379 | } | |
380 | ||
d4260e6d TM |
381 | if (pdev->device == 0x8803) |
382 | chip->ioh = INTEL_EG20T_PCH; | |
383 | else if (pdev->device == 0x8014) | |
384 | chip->ioh = OKISEMI_ML7223m_IOH; | |
385 | else if (pdev->device == 0x8043) | |
386 | chip->ioh = OKISEMI_ML7223n_IOH; | |
387 | ||
04c17aa8 TM |
388 | chip->reg = chip->base; |
389 | pci_set_drvdata(pdev, chip); | |
d166370a | 390 | spin_lock_init(&chip->spinlock); |
04c17aa8 TM |
391 | pch_gpio_setup(chip); |
392 | ret = gpiochip_add(&chip->gpio); | |
393 | if (ret) { | |
394 | dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n"); | |
395 | goto err_gpiochip_add; | |
396 | } | |
397 | ||
2824bc9c | 398 | irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE); |
38eb18a6 TM |
399 | if (irq_base < 0) { |
400 | dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n"); | |
401 | chip->irq_base = -1; | |
402 | goto end; | |
403 | } | |
404 | chip->irq_base = irq_base; | |
405 | ||
df9541a6 TG |
406 | /* Mask all interrupts, but enable them */ |
407 | msk = (1 << gpio_pins[chip->ioh]) - 1; | |
408 | iowrite32(msk, &chip->reg->imask); | |
409 | iowrite32(msk, &chip->reg->ien); | |
410 | ||
38eb18a6 | 411 | ret = request_irq(pdev->irq, pch_gpio_handler, |
df9541a6 | 412 | IRQF_SHARED, KBUILD_MODNAME, chip); |
38eb18a6 TM |
413 | if (ret != 0) { |
414 | dev_err(&pdev->dev, | |
415 | "%s request_irq failed\n", __func__); | |
416 | goto err_request_irq; | |
417 | } | |
418 | ||
419 | pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); | |
420 | ||
38eb18a6 | 421 | end: |
04c17aa8 TM |
422 | return 0; |
423 | ||
38eb18a6 TM |
424 | err_request_irq: |
425 | irq_free_descs(irq_base, gpio_pins[chip->ioh]); | |
426 | ||
cfb10898 | 427 | if (gpiochip_remove(&chip->gpio)) |
38eb18a6 TM |
428 | dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__); |
429 | ||
04c17aa8 TM |
430 | err_gpiochip_add: |
431 | pci_iounmap(pdev, chip->base); | |
432 | ||
433 | err_iomap: | |
434 | pci_release_regions(pdev); | |
435 | ||
436 | err_request_regions: | |
437 | pci_disable_device(pdev); | |
438 | ||
439 | err_pci_enable: | |
440 | kfree(chip); | |
441 | dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret); | |
442 | return ret; | |
443 | } | |
444 | ||
206210ce | 445 | static void pch_gpio_remove(struct pci_dev *pdev) |
04c17aa8 TM |
446 | { |
447 | int err; | |
448 | struct pch_gpio *chip = pci_get_drvdata(pdev); | |
449 | ||
38eb18a6 TM |
450 | if (chip->irq_base != -1) { |
451 | free_irq(pdev->irq, chip); | |
452 | ||
453 | irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]); | |
454 | } | |
455 | ||
04c17aa8 TM |
456 | err = gpiochip_remove(&chip->gpio); |
457 | if (err) | |
458 | dev_err(&pdev->dev, "Failed gpiochip_remove\n"); | |
459 | ||
460 | pci_iounmap(pdev, chip->base); | |
461 | pci_release_regions(pdev); | |
462 | pci_disable_device(pdev); | |
463 | kfree(chip); | |
464 | } | |
465 | ||
466 | #ifdef CONFIG_PM | |
467 | static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state) | |
468 | { | |
469 | s32 ret; | |
470 | struct pch_gpio *chip = pci_get_drvdata(pdev); | |
d568a681 | 471 | unsigned long flags; |
04c17aa8 | 472 | |
d568a681 | 473 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 | 474 | pch_gpio_save_reg_conf(chip); |
d568a681 | 475 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
476 | |
477 | ret = pci_save_state(pdev); | |
478 | if (ret) { | |
479 | dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); | |
480 | return ret; | |
481 | } | |
482 | pci_disable_device(pdev); | |
483 | pci_set_power_state(pdev, PCI_D0); | |
484 | ret = pci_enable_wake(pdev, PCI_D0, 1); | |
485 | if (ret) | |
486 | dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | static int pch_gpio_resume(struct pci_dev *pdev) | |
492 | { | |
493 | s32 ret; | |
494 | struct pch_gpio *chip = pci_get_drvdata(pdev); | |
d568a681 | 495 | unsigned long flags; |
04c17aa8 TM |
496 | |
497 | ret = pci_enable_wake(pdev, PCI_D0, 0); | |
498 | ||
499 | pci_set_power_state(pdev, PCI_D0); | |
500 | ret = pci_enable_device(pdev); | |
501 | if (ret) { | |
502 | dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); | |
503 | return ret; | |
504 | } | |
505 | pci_restore_state(pdev); | |
506 | ||
d568a681 | 507 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 TM |
508 | iowrite32(0x01, &chip->reg->reset); |
509 | iowrite32(0x00, &chip->reg->reset); | |
510 | pch_gpio_restore_reg_conf(chip); | |
d568a681 | 511 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
512 | |
513 | return 0; | |
514 | } | |
515 | #else | |
516 | #define pch_gpio_suspend NULL | |
517 | #define pch_gpio_resume NULL | |
518 | #endif | |
519 | ||
bc786cce | 520 | #define PCI_VENDOR_ID_ROHM 0x10DB |
04c17aa8 TM |
521 | static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = { |
522 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) }, | |
bc786cce | 523 | { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) }, |
c3520a1a | 524 | { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) }, |
868fea05 | 525 | { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) }, |
04c17aa8 TM |
526 | { 0, } |
527 | }; | |
19234cdd | 528 | MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id); |
04c17aa8 TM |
529 | |
530 | static struct pci_driver pch_gpio_driver = { | |
531 | .name = "pch_gpio", | |
532 | .id_table = pch_gpio_pcidev_id, | |
533 | .probe = pch_gpio_probe, | |
8283c4ff | 534 | .remove = pch_gpio_remove, |
04c17aa8 TM |
535 | .suspend = pch_gpio_suspend, |
536 | .resume = pch_gpio_resume | |
537 | }; | |
538 | ||
93baa65f | 539 | module_pci_driver(pch_gpio_driver); |
04c17aa8 TM |
540 | |
541 | MODULE_DESCRIPTION("PCH GPIO PCI Driver"); | |
542 | MODULE_LICENSE("GPL"); |