Merge tag 'spi-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
[deliverable/linux.git] / drivers / gpio / gpio-sch.c
CommitLineData
be9b06b2 1/*
c103de24 2 * GPIO interface for Intel Poulsbo SCH
be9b06b2
DT
3 *
4 * Copyright (c) 2010 CompuLab Ltd
5 * Author: Denis Turischev <denis@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License 2 as published
9 * by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/io.h>
25#include <linux/errno.h>
26#include <linux/acpi.h>
27#include <linux/platform_device.h>
f04ddfcd 28#include <linux/pci_ids.h>
be9b06b2
DT
29
30#include <linux/gpio.h>
31
c479ff09
MW
32#define GEN 0x00
33#define GIO 0x04
34#define GLV 0x08
35
36struct sch_gpio {
37 struct gpio_chip chip;
38 spinlock_t lock;
39 unsigned short iobase;
40 unsigned short core_base;
41 unsigned short resume_base;
42};
be9b06b2 43
920dfd82 44#define to_sch_gpio(gc) container_of(gc, struct sch_gpio, chip)
be9b06b2 45
c479ff09
MW
46static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
47 unsigned reg)
be9b06b2 48{
c479ff09 49 unsigned base = 0;
be9b06b2 50
c479ff09
MW
51 if (gpio >= sch->resume_base) {
52 gpio -= sch->resume_base;
53 base += 0x20;
54 }
be9b06b2 55
c479ff09 56 return base + reg + gpio / 8;
be9b06b2
DT
57}
58
c479ff09 59static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
be9b06b2 60{
c479ff09
MW
61 if (gpio >= sch->resume_base)
62 gpio -= sch->resume_base;
63 return gpio % 8;
be9b06b2
DT
64}
65
920dfd82 66static int sch_gpio_reg_get(struct gpio_chip *gc, unsigned gpio, unsigned reg)
be9b06b2 67{
920dfd82 68 struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2 69 unsigned short offset, bit;
920dfd82 70 u8 reg_val;
be9b06b2 71
920dfd82 72 offset = sch_gpio_offset(sch, gpio, reg);
c479ff09 73 bit = sch_gpio_bit(sch, gpio);
be9b06b2 74
920dfd82 75 reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
1e0d9823 76
920dfd82 77 return reg_val;
be9b06b2
DT
78}
79
920dfd82
CRSF
80static void sch_gpio_reg_set(struct gpio_chip *gc, unsigned gpio, unsigned reg,
81 int val)
be9b06b2 82{
c479ff09 83 struct sch_gpio *sch = to_sch_gpio(gc);
3cbf1822 84 unsigned short offset, bit;
920dfd82 85 u8 reg_val;
be9b06b2 86
920dfd82
CRSF
87 offset = sch_gpio_offset(sch, gpio, reg);
88 bit = sch_gpio_bit(sch, gpio);
be9b06b2 89
920dfd82 90 reg_val = inb(sch->iobase + offset);
3cbf1822 91
920dfd82
CRSF
92 if (val)
93 outb(reg_val | BIT(bit), sch->iobase + offset);
94 else
95 outb((reg_val & ~BIT(bit)), sch->iobase + offset);
96}
be9b06b2 97
920dfd82
CRSF
98static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
99{
100 struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2 101
920dfd82
CRSF
102 spin_lock(&sch->lock);
103 sch_gpio_reg_set(gc, gpio_num, GIO, 1);
c479ff09 104 spin_unlock(&sch->lock);
be9b06b2
DT
105 return 0;
106}
107
c479ff09 108static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
be9b06b2 109{
920dfd82 110 return sch_gpio_reg_get(gc, gpio_num, GLV);
be9b06b2
DT
111}
112
c479ff09 113static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
be9b06b2 114{
c479ff09 115 struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2 116
c479ff09 117 spin_lock(&sch->lock);
920dfd82 118 sch_gpio_reg_set(gc, gpio_num, GLV, val);
c479ff09 119 spin_unlock(&sch->lock);
be9b06b2
DT
120}
121
c479ff09
MW
122static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
123 int val)
be9b06b2 124{
c479ff09 125 struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2 126
c479ff09 127 spin_lock(&sch->lock);
920dfd82 128 sch_gpio_reg_set(gc, gpio_num, GIO, 0);
c479ff09 129 spin_unlock(&sch->lock);
1e0d9823
DK
130
131 /*
c479ff09
MW
132 * according to the datasheet, writing to the level register has no
133 * effect when GPIO is programmed as input.
134 * Actually the the level register is read-only when configured as input.
135 * Thus presetting the output level before switching to output is _NOT_ possible.
136 * Hence we set the level after configuring the GPIO as output.
137 * But we cannot prevent a short low pulse if direction is set to high
138 * and an external pull-up is connected.
139 */
140 sch_gpio_set(gc, gpio_num, val);
be9b06b2
DT
141 return 0;
142}
143
c479ff09
MW
144static struct gpio_chip sch_gpio_chip = {
145 .label = "sch_gpio",
be9b06b2 146 .owner = THIS_MODULE,
c479ff09
MW
147 .direction_input = sch_gpio_direction_in,
148 .get = sch_gpio_get,
149 .direction_output = sch_gpio_direction_out,
150 .set = sch_gpio_set,
be9b06b2
DT
151};
152
3836309d 153static int sch_gpio_probe(struct platform_device *pdev)
be9b06b2 154{
c479ff09 155 struct sch_gpio *sch;
be9b06b2 156 struct resource *res;
f04ddfcd 157
c479ff09
MW
158 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
159 if (!sch)
160 return -ENOMEM;
be9b06b2
DT
161
162 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
163 if (!res)
164 return -EBUSY;
165
c479ff09
MW
166 if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
167 pdev->name))
be9b06b2
DT
168 return -EBUSY;
169
c479ff09
MW
170 spin_lock_init(&sch->lock);
171 sch->iobase = res->start;
172 sch->chip = sch_gpio_chip;
173 sch->chip.label = dev_name(&pdev->dev);
174 sch->chip.dev = &pdev->dev;
be9b06b2 175
c479ff09 176 switch (pdev->id) {
be41cf58 177 case PCI_DEVICE_ID_INTEL_SCH_LPC:
c479ff09
MW
178 sch->core_base = 0;
179 sch->resume_base = 10;
180 sch->chip.ngpio = 14;
181
be41cf58
LN
182 /*
183 * GPIO[6:0] enabled by default
184 * GPIO7 is configured by the CMC as SLPIOVR
185 * Enable GPIO[9:8] core powered gpios explicitly
186 */
920dfd82
CRSF
187 sch_gpio_reg_set(&sch->chip, 8, GEN, 1);
188 sch_gpio_reg_set(&sch->chip, 9, GEN, 1);
be41cf58
LN
189 /*
190 * SUS_GPIO[2:0] enabled by default
191 * Enable SUS_GPIO3 resume powered gpio explicitly
192 */
920dfd82 193 sch_gpio_reg_set(&sch->chip, 13, GEN, 1);
be41cf58
LN
194 break;
195
196 case PCI_DEVICE_ID_INTEL_ITC_LPC:
c479ff09
MW
197 sch->core_base = 0;
198 sch->resume_base = 5;
199 sch->chip.ngpio = 14;
be41cf58
LN
200 break;
201
202 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
c479ff09
MW
203 sch->core_base = 0;
204 sch->resume_base = 21;
205 sch->chip.ngpio = 30;
be41cf58
LN
206 break;
207
92021490
CRSF
208 case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
209 sch->core_base = 0;
210 sch->resume_base = 2;
211 sch->chip.ngpio = 8;
212 break;
213
be41cf58 214 default:
c479ff09 215 return -ENODEV;
f04ddfcd 216 }
be9b06b2 217
c479ff09 218 platform_set_drvdata(pdev, sch);
be9b06b2 219
c479ff09 220 return gpiochip_add(&sch->chip);
be9b06b2
DT
221}
222
206210ce 223static int sch_gpio_remove(struct platform_device *pdev)
be9b06b2 224{
c479ff09 225 struct sch_gpio *sch = platform_get_drvdata(pdev);
be9b06b2 226
c479ff09 227 gpiochip_remove(&sch->chip);
be9b06b2
DT
228 return 0;
229}
230
231static struct platform_driver sch_gpio_driver = {
232 .driver = {
233 .name = "sch_gpio",
be9b06b2
DT
234 },
235 .probe = sch_gpio_probe,
8283c4ff 236 .remove = sch_gpio_remove,
be9b06b2
DT
237};
238
6f61415e 239module_platform_driver(sch_gpio_driver);
be9b06b2
DT
240
241MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
242MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
243MODULE_LICENSE("GPL");
244MODULE_ALIAS("platform:sch_gpio");
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