Commit | Line | Data |
---|---|---|
03f822f5 RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License, version 2 | |
5 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
6 | */ | |
7 | ||
03f822f5 RV |
8 | #include <linux/init.h> |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/gpio.h> | |
03f822f5 | 12 | #include <linux/interrupt.h> |
86605cfe | 13 | #include <linux/of.h> |
03f822f5 | 14 | #include <linux/mfd/stmpe.h> |
27ec8a9c | 15 | #include <linux/seq_file.h> |
03f822f5 RV |
16 | |
17 | /* | |
18 | * These registers are modified under the irq bus lock and cached to avoid | |
19 | * unnecessary writes in bus_sync_unlock. | |
20 | */ | |
21 | enum { REG_RE, REG_FE, REG_IE }; | |
22 | ||
23 | #define CACHE_NR_REGS 3 | |
9e9dc7d9 LW |
24 | /* No variant has more than 24 GPIOs */ |
25 | #define CACHE_NR_BANKS (24 / 8) | |
03f822f5 RV |
26 | |
27 | struct stmpe_gpio { | |
28 | struct gpio_chip chip; | |
29 | struct stmpe *stmpe; | |
30 | struct device *dev; | |
31 | struct mutex irq_lock; | |
1dfb4a0d | 32 | u32 norequest_mask; |
03f822f5 RV |
33 | /* Caches of interrupt control registers for bus_lock */ |
34 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
35 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
36 | }; | |
37 | ||
03f822f5 RV |
38 | static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) |
39 | { | |
b03c04a0 | 40 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
41 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
42 | u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); | |
43 | u8 mask = 1 << (offset % 8); | |
44 | int ret; | |
45 | ||
46 | ret = stmpe_reg_read(stmpe, reg); | |
47 | if (ret < 0) | |
48 | return ret; | |
49 | ||
7535b8be | 50 | return !!(ret & mask); |
03f822f5 RV |
51 | } |
52 | ||
53 | static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
54 | { | |
b03c04a0 | 55 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
56 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
57 | int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; | |
58 | u8 reg = stmpe->regs[which] - (offset / 8); | |
59 | u8 mask = 1 << (offset % 8); | |
60 | ||
cccdceb9 VK |
61 | /* |
62 | * Some variants have single register for gpio set/clear functionality. | |
63 | * For them we need to write 0 to clear and 1 to set. | |
64 | */ | |
65 | if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) | |
66 | stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); | |
67 | else | |
68 | stmpe_reg_write(stmpe, reg, mask); | |
03f822f5 RV |
69 | } |
70 | ||
71 | static int stmpe_gpio_direction_output(struct gpio_chip *chip, | |
72 | unsigned offset, int val) | |
73 | { | |
b03c04a0 | 74 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
75 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
76 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
77 | u8 mask = 1 << (offset % 8); | |
78 | ||
79 | stmpe_gpio_set(chip, offset, val); | |
80 | ||
81 | return stmpe_set_bits(stmpe, reg, mask, mask); | |
82 | } | |
83 | ||
84 | static int stmpe_gpio_direction_input(struct gpio_chip *chip, | |
85 | unsigned offset) | |
86 | { | |
b03c04a0 | 87 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
88 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
89 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
90 | u8 mask = 1 << (offset % 8); | |
91 | ||
92 | return stmpe_set_bits(stmpe, reg, mask, 0); | |
93 | } | |
94 | ||
03f822f5 RV |
95 | static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) |
96 | { | |
b03c04a0 | 97 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
98 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
99 | ||
b8e9cf0b WS |
100 | if (stmpe_gpio->norequest_mask & (1 << offset)) |
101 | return -EINVAL; | |
102 | ||
03f822f5 RV |
103 | return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); |
104 | } | |
105 | ||
106 | static struct gpio_chip template_chip = { | |
107 | .label = "stmpe", | |
108 | .owner = THIS_MODULE, | |
109 | .direction_input = stmpe_gpio_direction_input, | |
110 | .get = stmpe_gpio_get, | |
111 | .direction_output = stmpe_gpio_direction_output, | |
112 | .set = stmpe_gpio_set, | |
03f822f5 | 113 | .request = stmpe_gpio_request, |
9fb1f39e | 114 | .can_sleep = true, |
03f822f5 RV |
115 | }; |
116 | ||
2a866f39 | 117 | static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
03f822f5 | 118 | { |
fe44e70d | 119 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 120 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 121 | int offset = d->hwirq; |
03f822f5 RV |
122 | int regoffset = offset / 8; |
123 | int mask = 1 << (offset % 8); | |
124 | ||
1fe3bd9e | 125 | if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) |
03f822f5 RV |
126 | return -EINVAL; |
127 | ||
cccdceb9 VK |
128 | /* STMPE801 doesn't have RE and FE registers */ |
129 | if (stmpe_gpio->stmpe->partnum == STMPE801) | |
130 | return 0; | |
131 | ||
1fe3bd9e | 132 | if (type & IRQ_TYPE_EDGE_RISING) |
03f822f5 RV |
133 | stmpe_gpio->regs[REG_RE][regoffset] |= mask; |
134 | else | |
135 | stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; | |
136 | ||
1fe3bd9e | 137 | if (type & IRQ_TYPE_EDGE_FALLING) |
03f822f5 RV |
138 | stmpe_gpio->regs[REG_FE][regoffset] |= mask; |
139 | else | |
140 | stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
2a866f39 | 145 | static void stmpe_gpio_irq_lock(struct irq_data *d) |
03f822f5 | 146 | { |
fe44e70d | 147 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 148 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
03f822f5 RV |
149 | |
150 | mutex_lock(&stmpe_gpio->irq_lock); | |
151 | } | |
152 | ||
2a866f39 | 153 | static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) |
03f822f5 | 154 | { |
fe44e70d | 155 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 156 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
03f822f5 RV |
157 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
158 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
159 | static const u8 regmap[] = { | |
160 | [REG_RE] = STMPE_IDX_GPRER_LSB, | |
161 | [REG_FE] = STMPE_IDX_GPFER_LSB, | |
162 | [REG_IE] = STMPE_IDX_IEGPIOR_LSB, | |
163 | }; | |
164 | int i, j; | |
165 | ||
166 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
cccdceb9 VK |
167 | /* STMPE801 doesn't have RE and FE registers */ |
168 | if ((stmpe->partnum == STMPE801) && | |
169 | (i != REG_IE)) | |
170 | continue; | |
171 | ||
03f822f5 RV |
172 | for (j = 0; j < num_banks; j++) { |
173 | u8 old = stmpe_gpio->oldregs[i][j]; | |
174 | u8 new = stmpe_gpio->regs[i][j]; | |
175 | ||
176 | if (new == old) | |
177 | continue; | |
178 | ||
179 | stmpe_gpio->oldregs[i][j] = new; | |
180 | stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); | |
181 | } | |
182 | } | |
183 | ||
184 | mutex_unlock(&stmpe_gpio->irq_lock); | |
185 | } | |
186 | ||
2a866f39 | 187 | static void stmpe_gpio_irq_mask(struct irq_data *d) |
03f822f5 | 188 | { |
fe44e70d | 189 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 190 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 191 | int offset = d->hwirq; |
03f822f5 RV |
192 | int regoffset = offset / 8; |
193 | int mask = 1 << (offset % 8); | |
194 | ||
195 | stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; | |
196 | } | |
197 | ||
2a866f39 | 198 | static void stmpe_gpio_irq_unmask(struct irq_data *d) |
03f822f5 | 199 | { |
fe44e70d | 200 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 201 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 202 | int offset = d->hwirq; |
03f822f5 RV |
203 | int regoffset = offset / 8; |
204 | int mask = 1 << (offset % 8); | |
205 | ||
206 | stmpe_gpio->regs[REG_IE][regoffset] |= mask; | |
207 | } | |
208 | ||
27ec8a9c LW |
209 | static void stmpe_dbg_show_one(struct seq_file *s, |
210 | struct gpio_chip *gc, | |
211 | unsigned offset, unsigned gpio) | |
212 | { | |
b03c04a0 | 213 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
27ec8a9c LW |
214 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
215 | const char *label = gpiochip_is_requested(gc, offset); | |
216 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
217 | bool val = !!stmpe_gpio_get(gc, offset); | |
218 | u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
219 | u8 mask = 1 << (offset % 8); | |
220 | int ret; | |
221 | u8 dir; | |
222 | ||
223 | ret = stmpe_reg_read(stmpe, dir_reg); | |
224 | if (ret < 0) | |
225 | return; | |
226 | dir = !!(ret & mask); | |
227 | ||
228 | if (dir) { | |
229 | seq_printf(s, " gpio-%-3d (%-20.20s) out %s", | |
230 | gpio, label ?: "(none)", | |
231 | val ? "hi" : "lo"); | |
232 | } else { | |
233 | u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8); | |
234 | u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8); | |
235 | u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8); | |
236 | u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8); | |
237 | bool edge_det; | |
238 | bool rise; | |
239 | bool fall; | |
240 | bool irqen; | |
241 | ||
242 | ret = stmpe_reg_read(stmpe, edge_det_reg); | |
243 | if (ret < 0) | |
244 | return; | |
245 | edge_det = !!(ret & mask); | |
246 | ret = stmpe_reg_read(stmpe, rise_reg); | |
247 | if (ret < 0) | |
248 | return; | |
249 | rise = !!(ret & mask); | |
250 | ret = stmpe_reg_read(stmpe, fall_reg); | |
251 | if (ret < 0) | |
252 | return; | |
253 | fall = !!(ret & mask); | |
254 | ret = stmpe_reg_read(stmpe, irqen_reg); | |
255 | if (ret < 0) | |
256 | return; | |
257 | irqen = !!(ret & mask); | |
258 | ||
259 | seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s", | |
260 | gpio, label ?: "(none)", | |
261 | val ? "hi" : "lo", | |
262 | edge_det ? "edge-asserted" : "edge-inactive", | |
263 | irqen ? "IRQ-enabled" : "", | |
264 | rise ? " rising-edge-detection" : "", | |
265 | fall ? " falling-edge-detection" : ""); | |
266 | } | |
267 | } | |
268 | ||
269 | static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
270 | { | |
271 | unsigned i; | |
272 | unsigned gpio = gc->base; | |
273 | ||
274 | for (i = 0; i < gc->ngpio; i++, gpio++) { | |
275 | stmpe_dbg_show_one(s, gc, i, gpio); | |
276 | seq_printf(s, "\n"); | |
277 | } | |
278 | } | |
279 | ||
03f822f5 RV |
280 | static struct irq_chip stmpe_gpio_irq_chip = { |
281 | .name = "stmpe-gpio", | |
2a866f39 LB |
282 | .irq_bus_lock = stmpe_gpio_irq_lock, |
283 | .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, | |
284 | .irq_mask = stmpe_gpio_irq_mask, | |
285 | .irq_unmask = stmpe_gpio_irq_unmask, | |
286 | .irq_set_type = stmpe_gpio_irq_set_type, | |
03f822f5 RV |
287 | }; |
288 | ||
289 | static irqreturn_t stmpe_gpio_irq(int irq, void *dev) | |
290 | { | |
291 | struct stmpe_gpio *stmpe_gpio = dev; | |
292 | struct stmpe *stmpe = stmpe_gpio->stmpe; | |
293 | u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; | |
294 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
295 | u8 status[num_banks]; | |
296 | int ret; | |
297 | int i; | |
298 | ||
299 | ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); | |
300 | if (ret < 0) | |
301 | return IRQ_NONE; | |
302 | ||
303 | for (i = 0; i < num_banks; i++) { | |
304 | int bank = num_banks - i - 1; | |
305 | unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; | |
306 | unsigned int stat = status[i]; | |
307 | ||
308 | stat &= enabled; | |
309 | if (!stat) | |
310 | continue; | |
311 | ||
312 | while (stat) { | |
313 | int bit = __ffs(stat); | |
314 | int line = bank * 8 + bit; | |
fe44e70d | 315 | int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain, |
ed05e204 | 316 | line); |
03f822f5 | 317 | |
ed05e204 | 318 | handle_nested_irq(child_irq); |
03f822f5 RV |
319 | stat &= ~(1 << bit); |
320 | } | |
321 | ||
322 | stmpe_reg_write(stmpe, statmsbreg + i, status[i]); | |
cccdceb9 VK |
323 | |
324 | /* Edge detect register is not present on 801 */ | |
325 | if (stmpe->partnum != STMPE801) | |
326 | stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] | |
327 | + i, status[i]); | |
03f822f5 RV |
328 | } |
329 | ||
330 | return IRQ_HANDLED; | |
331 | } | |
332 | ||
3836309d | 333 | static int stmpe_gpio_probe(struct platform_device *pdev) |
03f822f5 RV |
334 | { |
335 | struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); | |
86605cfe | 336 | struct device_node *np = pdev->dev.of_node; |
03f822f5 RV |
337 | struct stmpe_gpio *stmpe_gpio; |
338 | int ret; | |
38040c85 | 339 | int irq = 0; |
03f822f5 | 340 | |
03f822f5 | 341 | irq = platform_get_irq(pdev, 0); |
03f822f5 RV |
342 | |
343 | stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); | |
344 | if (!stmpe_gpio) | |
345 | return -ENOMEM; | |
346 | ||
347 | mutex_init(&stmpe_gpio->irq_lock); | |
348 | ||
349 | stmpe_gpio->dev = &pdev->dev; | |
350 | stmpe_gpio->stmpe = stmpe; | |
03f822f5 RV |
351 | stmpe_gpio->chip = template_chip; |
352 | stmpe_gpio->chip.ngpio = stmpe->num_gpios; | |
58383c78 | 353 | stmpe_gpio->chip.parent = &pdev->dev; |
9afd9b70 | 354 | stmpe_gpio->chip.of_node = np; |
9e9dc7d9 | 355 | stmpe_gpio->chip.base = -1; |
03f822f5 | 356 | |
27ec8a9c LW |
357 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
358 | stmpe_gpio->chip.dbg_show = stmpe_dbg_show; | |
359 | ||
1dfb4a0d LW |
360 | of_property_read_u32(np, "st,norequest-mask", |
361 | &stmpe_gpio->norequest_mask); | |
86605cfe | 362 | |
9e9dc7d9 | 363 | if (irq < 0) |
38040c85 | 364 | dev_info(&pdev->dev, |
fe44e70d | 365 | "device configured in no-irq mode: " |
38040c85 | 366 | "irqs are not available\n"); |
03f822f5 RV |
367 | |
368 | ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); | |
369 | if (ret) | |
02bf0749 | 370 | goto out_free; |
03f822f5 | 371 | |
b03c04a0 | 372 | ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio); |
3f97d5fc LW |
373 | if (ret) { |
374 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
375 | goto out_disable; | |
376 | } | |
377 | ||
fe44e70d LW |
378 | if (irq > 0) { |
379 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
380 | stmpe_gpio_irq, IRQF_ONESHOT, | |
381 | "stmpe-gpio", stmpe_gpio); | |
38040c85 CB |
382 | if (ret) { |
383 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
fc13d5a5 | 384 | goto out_disable; |
38040c85 | 385 | } |
fe44e70d LW |
386 | ret = gpiochip_irqchip_add(&stmpe_gpio->chip, |
387 | &stmpe_gpio_irq_chip, | |
388 | 0, | |
389 | handle_simple_irq, | |
390 | IRQ_TYPE_NONE); | |
391 | if (ret) { | |
392 | dev_err(&pdev->dev, | |
393 | "could not connect irqchip to gpiochip\n"); | |
3f97d5fc | 394 | goto out_disable; |
fe44e70d | 395 | } |
03f822f5 | 396 | |
3f97d5fc LW |
397 | gpiochip_set_chained_irqchip(&stmpe_gpio->chip, |
398 | &stmpe_gpio_irq_chip, | |
399 | irq, | |
400 | NULL); | |
03f822f5 RV |
401 | } |
402 | ||
03f822f5 RV |
403 | platform_set_drvdata(pdev, stmpe_gpio); |
404 | ||
405 | return 0; | |
406 | ||
02bf0749 VK |
407 | out_disable: |
408 | stmpe_disable(stmpe, STMPE_BLOCK_GPIO); | |
3f97d5fc | 409 | gpiochip_remove(&stmpe_gpio->chip); |
03f822f5 RV |
410 | out_free: |
411 | kfree(stmpe_gpio); | |
412 | return ret; | |
413 | } | |
414 | ||
03f822f5 | 415 | static struct platform_driver stmpe_gpio_driver = { |
3b52bb96 PG |
416 | .driver = { |
417 | .suppress_bind_attrs = true, | |
418 | .name = "stmpe-gpio", | |
419 | .owner = THIS_MODULE, | |
420 | }, | |
03f822f5 | 421 | .probe = stmpe_gpio_probe, |
03f822f5 RV |
422 | }; |
423 | ||
424 | static int __init stmpe_gpio_init(void) | |
425 | { | |
426 | return platform_driver_register(&stmpe_gpio_driver); | |
427 | } | |
428 | subsys_initcall(stmpe_gpio_init); |