Commit | Line | Data |
---|---|---|
03f822f5 RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License, version 2 | |
5 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
6 | */ | |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/gpio.h> | |
03f822f5 | 13 | #include <linux/interrupt.h> |
86605cfe | 14 | #include <linux/of.h> |
03f822f5 | 15 | #include <linux/mfd/stmpe.h> |
27ec8a9c | 16 | #include <linux/seq_file.h> |
03f822f5 RV |
17 | |
18 | /* | |
19 | * These registers are modified under the irq bus lock and cached to avoid | |
20 | * unnecessary writes in bus_sync_unlock. | |
21 | */ | |
22 | enum { REG_RE, REG_FE, REG_IE }; | |
23 | ||
24 | #define CACHE_NR_REGS 3 | |
9e9dc7d9 LW |
25 | /* No variant has more than 24 GPIOs */ |
26 | #define CACHE_NR_BANKS (24 / 8) | |
03f822f5 RV |
27 | |
28 | struct stmpe_gpio { | |
29 | struct gpio_chip chip; | |
30 | struct stmpe *stmpe; | |
31 | struct device *dev; | |
32 | struct mutex irq_lock; | |
1dfb4a0d | 33 | u32 norequest_mask; |
03f822f5 RV |
34 | /* Caches of interrupt control registers for bus_lock */ |
35 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
36 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
37 | }; | |
38 | ||
03f822f5 RV |
39 | static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) |
40 | { | |
b03c04a0 | 41 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
42 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
43 | u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); | |
44 | u8 mask = 1 << (offset % 8); | |
45 | int ret; | |
46 | ||
47 | ret = stmpe_reg_read(stmpe, reg); | |
48 | if (ret < 0) | |
49 | return ret; | |
50 | ||
7535b8be | 51 | return !!(ret & mask); |
03f822f5 RV |
52 | } |
53 | ||
54 | static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
55 | { | |
b03c04a0 | 56 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
57 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
58 | int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; | |
59 | u8 reg = stmpe->regs[which] - (offset / 8); | |
60 | u8 mask = 1 << (offset % 8); | |
61 | ||
cccdceb9 VK |
62 | /* |
63 | * Some variants have single register for gpio set/clear functionality. | |
64 | * For them we need to write 0 to clear and 1 to set. | |
65 | */ | |
66 | if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) | |
67 | stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); | |
68 | else | |
69 | stmpe_reg_write(stmpe, reg, mask); | |
03f822f5 RV |
70 | } |
71 | ||
72 | static int stmpe_gpio_direction_output(struct gpio_chip *chip, | |
73 | unsigned offset, int val) | |
74 | { | |
b03c04a0 | 75 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
76 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
77 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
78 | u8 mask = 1 << (offset % 8); | |
79 | ||
80 | stmpe_gpio_set(chip, offset, val); | |
81 | ||
82 | return stmpe_set_bits(stmpe, reg, mask, mask); | |
83 | } | |
84 | ||
85 | static int stmpe_gpio_direction_input(struct gpio_chip *chip, | |
86 | unsigned offset) | |
87 | { | |
b03c04a0 | 88 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
89 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
90 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
91 | u8 mask = 1 << (offset % 8); | |
92 | ||
93 | return stmpe_set_bits(stmpe, reg, mask, 0); | |
94 | } | |
95 | ||
03f822f5 RV |
96 | static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) |
97 | { | |
b03c04a0 | 98 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
99 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
100 | ||
b8e9cf0b WS |
101 | if (stmpe_gpio->norequest_mask & (1 << offset)) |
102 | return -EINVAL; | |
103 | ||
03f822f5 RV |
104 | return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); |
105 | } | |
106 | ||
107 | static struct gpio_chip template_chip = { | |
108 | .label = "stmpe", | |
109 | .owner = THIS_MODULE, | |
110 | .direction_input = stmpe_gpio_direction_input, | |
111 | .get = stmpe_gpio_get, | |
112 | .direction_output = stmpe_gpio_direction_output, | |
113 | .set = stmpe_gpio_set, | |
03f822f5 | 114 | .request = stmpe_gpio_request, |
9fb1f39e | 115 | .can_sleep = true, |
03f822f5 RV |
116 | }; |
117 | ||
2a866f39 | 118 | static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
03f822f5 | 119 | { |
fe44e70d | 120 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 121 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 122 | int offset = d->hwirq; |
03f822f5 RV |
123 | int regoffset = offset / 8; |
124 | int mask = 1 << (offset % 8); | |
125 | ||
1fe3bd9e | 126 | if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) |
03f822f5 RV |
127 | return -EINVAL; |
128 | ||
cccdceb9 VK |
129 | /* STMPE801 doesn't have RE and FE registers */ |
130 | if (stmpe_gpio->stmpe->partnum == STMPE801) | |
131 | return 0; | |
132 | ||
1fe3bd9e | 133 | if (type & IRQ_TYPE_EDGE_RISING) |
03f822f5 RV |
134 | stmpe_gpio->regs[REG_RE][regoffset] |= mask; |
135 | else | |
136 | stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; | |
137 | ||
1fe3bd9e | 138 | if (type & IRQ_TYPE_EDGE_FALLING) |
03f822f5 RV |
139 | stmpe_gpio->regs[REG_FE][regoffset] |= mask; |
140 | else | |
141 | stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
2a866f39 | 146 | static void stmpe_gpio_irq_lock(struct irq_data *d) |
03f822f5 | 147 | { |
fe44e70d | 148 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 149 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
03f822f5 RV |
150 | |
151 | mutex_lock(&stmpe_gpio->irq_lock); | |
152 | } | |
153 | ||
2a866f39 | 154 | static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) |
03f822f5 | 155 | { |
fe44e70d | 156 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 157 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
03f822f5 RV |
158 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
159 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
160 | static const u8 regmap[] = { | |
161 | [REG_RE] = STMPE_IDX_GPRER_LSB, | |
162 | [REG_FE] = STMPE_IDX_GPFER_LSB, | |
163 | [REG_IE] = STMPE_IDX_IEGPIOR_LSB, | |
164 | }; | |
165 | int i, j; | |
166 | ||
167 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
cccdceb9 VK |
168 | /* STMPE801 doesn't have RE and FE registers */ |
169 | if ((stmpe->partnum == STMPE801) && | |
170 | (i != REG_IE)) | |
171 | continue; | |
172 | ||
03f822f5 RV |
173 | for (j = 0; j < num_banks; j++) { |
174 | u8 old = stmpe_gpio->oldregs[i][j]; | |
175 | u8 new = stmpe_gpio->regs[i][j]; | |
176 | ||
177 | if (new == old) | |
178 | continue; | |
179 | ||
180 | stmpe_gpio->oldregs[i][j] = new; | |
181 | stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); | |
182 | } | |
183 | } | |
184 | ||
185 | mutex_unlock(&stmpe_gpio->irq_lock); | |
186 | } | |
187 | ||
2a866f39 | 188 | static void stmpe_gpio_irq_mask(struct irq_data *d) |
03f822f5 | 189 | { |
fe44e70d | 190 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 191 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 192 | int offset = d->hwirq; |
03f822f5 RV |
193 | int regoffset = offset / 8; |
194 | int mask = 1 << (offset % 8); | |
195 | ||
196 | stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; | |
197 | } | |
198 | ||
2a866f39 | 199 | static void stmpe_gpio_irq_unmask(struct irq_data *d) |
03f822f5 | 200 | { |
fe44e70d | 201 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 202 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 203 | int offset = d->hwirq; |
03f822f5 RV |
204 | int regoffset = offset / 8; |
205 | int mask = 1 << (offset % 8); | |
206 | ||
207 | stmpe_gpio->regs[REG_IE][regoffset] |= mask; | |
208 | } | |
209 | ||
27ec8a9c LW |
210 | static void stmpe_dbg_show_one(struct seq_file *s, |
211 | struct gpio_chip *gc, | |
212 | unsigned offset, unsigned gpio) | |
213 | { | |
b03c04a0 | 214 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
27ec8a9c LW |
215 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
216 | const char *label = gpiochip_is_requested(gc, offset); | |
217 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
218 | bool val = !!stmpe_gpio_get(gc, offset); | |
219 | u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
220 | u8 mask = 1 << (offset % 8); | |
221 | int ret; | |
222 | u8 dir; | |
223 | ||
224 | ret = stmpe_reg_read(stmpe, dir_reg); | |
225 | if (ret < 0) | |
226 | return; | |
227 | dir = !!(ret & mask); | |
228 | ||
229 | if (dir) { | |
230 | seq_printf(s, " gpio-%-3d (%-20.20s) out %s", | |
231 | gpio, label ?: "(none)", | |
232 | val ? "hi" : "lo"); | |
233 | } else { | |
234 | u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8); | |
235 | u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8); | |
236 | u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8); | |
237 | u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8); | |
238 | bool edge_det; | |
239 | bool rise; | |
240 | bool fall; | |
241 | bool irqen; | |
242 | ||
243 | ret = stmpe_reg_read(stmpe, edge_det_reg); | |
244 | if (ret < 0) | |
245 | return; | |
246 | edge_det = !!(ret & mask); | |
247 | ret = stmpe_reg_read(stmpe, rise_reg); | |
248 | if (ret < 0) | |
249 | return; | |
250 | rise = !!(ret & mask); | |
251 | ret = stmpe_reg_read(stmpe, fall_reg); | |
252 | if (ret < 0) | |
253 | return; | |
254 | fall = !!(ret & mask); | |
255 | ret = stmpe_reg_read(stmpe, irqen_reg); | |
256 | if (ret < 0) | |
257 | return; | |
258 | irqen = !!(ret & mask); | |
259 | ||
260 | seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s", | |
261 | gpio, label ?: "(none)", | |
262 | val ? "hi" : "lo", | |
263 | edge_det ? "edge-asserted" : "edge-inactive", | |
264 | irqen ? "IRQ-enabled" : "", | |
265 | rise ? " rising-edge-detection" : "", | |
266 | fall ? " falling-edge-detection" : ""); | |
267 | } | |
268 | } | |
269 | ||
270 | static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
271 | { | |
272 | unsigned i; | |
273 | unsigned gpio = gc->base; | |
274 | ||
275 | for (i = 0; i < gc->ngpio; i++, gpio++) { | |
276 | stmpe_dbg_show_one(s, gc, i, gpio); | |
277 | seq_printf(s, "\n"); | |
278 | } | |
279 | } | |
280 | ||
03f822f5 RV |
281 | static struct irq_chip stmpe_gpio_irq_chip = { |
282 | .name = "stmpe-gpio", | |
2a866f39 LB |
283 | .irq_bus_lock = stmpe_gpio_irq_lock, |
284 | .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, | |
285 | .irq_mask = stmpe_gpio_irq_mask, | |
286 | .irq_unmask = stmpe_gpio_irq_unmask, | |
287 | .irq_set_type = stmpe_gpio_irq_set_type, | |
03f822f5 RV |
288 | }; |
289 | ||
290 | static irqreturn_t stmpe_gpio_irq(int irq, void *dev) | |
291 | { | |
292 | struct stmpe_gpio *stmpe_gpio = dev; | |
293 | struct stmpe *stmpe = stmpe_gpio->stmpe; | |
294 | u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; | |
295 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
296 | u8 status[num_banks]; | |
297 | int ret; | |
298 | int i; | |
299 | ||
300 | ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); | |
301 | if (ret < 0) | |
302 | return IRQ_NONE; | |
303 | ||
304 | for (i = 0; i < num_banks; i++) { | |
305 | int bank = num_banks - i - 1; | |
306 | unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; | |
307 | unsigned int stat = status[i]; | |
308 | ||
309 | stat &= enabled; | |
310 | if (!stat) | |
311 | continue; | |
312 | ||
313 | while (stat) { | |
314 | int bit = __ffs(stat); | |
315 | int line = bank * 8 + bit; | |
fe44e70d | 316 | int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain, |
ed05e204 | 317 | line); |
03f822f5 | 318 | |
ed05e204 | 319 | handle_nested_irq(child_irq); |
03f822f5 RV |
320 | stat &= ~(1 << bit); |
321 | } | |
322 | ||
323 | stmpe_reg_write(stmpe, statmsbreg + i, status[i]); | |
cccdceb9 VK |
324 | |
325 | /* Edge detect register is not present on 801 */ | |
326 | if (stmpe->partnum != STMPE801) | |
327 | stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] | |
328 | + i, status[i]); | |
03f822f5 RV |
329 | } |
330 | ||
331 | return IRQ_HANDLED; | |
332 | } | |
333 | ||
3836309d | 334 | static int stmpe_gpio_probe(struct platform_device *pdev) |
03f822f5 RV |
335 | { |
336 | struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); | |
86605cfe | 337 | struct device_node *np = pdev->dev.of_node; |
03f822f5 RV |
338 | struct stmpe_gpio *stmpe_gpio; |
339 | int ret; | |
38040c85 | 340 | int irq = 0; |
03f822f5 | 341 | |
03f822f5 | 342 | irq = platform_get_irq(pdev, 0); |
03f822f5 RV |
343 | |
344 | stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); | |
345 | if (!stmpe_gpio) | |
346 | return -ENOMEM; | |
347 | ||
348 | mutex_init(&stmpe_gpio->irq_lock); | |
349 | ||
350 | stmpe_gpio->dev = &pdev->dev; | |
351 | stmpe_gpio->stmpe = stmpe; | |
03f822f5 RV |
352 | stmpe_gpio->chip = template_chip; |
353 | stmpe_gpio->chip.ngpio = stmpe->num_gpios; | |
58383c78 | 354 | stmpe_gpio->chip.parent = &pdev->dev; |
9afd9b70 | 355 | stmpe_gpio->chip.of_node = np; |
9e9dc7d9 | 356 | stmpe_gpio->chip.base = -1; |
03f822f5 | 357 | |
27ec8a9c LW |
358 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
359 | stmpe_gpio->chip.dbg_show = stmpe_dbg_show; | |
360 | ||
1dfb4a0d LW |
361 | of_property_read_u32(np, "st,norequest-mask", |
362 | &stmpe_gpio->norequest_mask); | |
86605cfe | 363 | |
9e9dc7d9 | 364 | if (irq < 0) |
38040c85 | 365 | dev_info(&pdev->dev, |
fe44e70d | 366 | "device configured in no-irq mode: " |
38040c85 | 367 | "irqs are not available\n"); |
03f822f5 RV |
368 | |
369 | ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); | |
370 | if (ret) | |
02bf0749 | 371 | goto out_free; |
03f822f5 | 372 | |
b03c04a0 | 373 | ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio); |
3f97d5fc LW |
374 | if (ret) { |
375 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
376 | goto out_disable; | |
377 | } | |
378 | ||
fe44e70d LW |
379 | if (irq > 0) { |
380 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
381 | stmpe_gpio_irq, IRQF_ONESHOT, | |
382 | "stmpe-gpio", stmpe_gpio); | |
38040c85 CB |
383 | if (ret) { |
384 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
fc13d5a5 | 385 | goto out_disable; |
38040c85 | 386 | } |
fe44e70d LW |
387 | ret = gpiochip_irqchip_add(&stmpe_gpio->chip, |
388 | &stmpe_gpio_irq_chip, | |
389 | 0, | |
390 | handle_simple_irq, | |
391 | IRQ_TYPE_NONE); | |
392 | if (ret) { | |
393 | dev_err(&pdev->dev, | |
394 | "could not connect irqchip to gpiochip\n"); | |
3f97d5fc | 395 | goto out_disable; |
fe44e70d | 396 | } |
03f822f5 | 397 | |
3f97d5fc LW |
398 | gpiochip_set_chained_irqchip(&stmpe_gpio->chip, |
399 | &stmpe_gpio_irq_chip, | |
400 | irq, | |
401 | NULL); | |
03f822f5 RV |
402 | } |
403 | ||
03f822f5 RV |
404 | platform_set_drvdata(pdev, stmpe_gpio); |
405 | ||
406 | return 0; | |
407 | ||
02bf0749 VK |
408 | out_disable: |
409 | stmpe_disable(stmpe, STMPE_BLOCK_GPIO); | |
3f97d5fc | 410 | gpiochip_remove(&stmpe_gpio->chip); |
03f822f5 RV |
411 | out_free: |
412 | kfree(stmpe_gpio); | |
413 | return ret; | |
414 | } | |
415 | ||
206210ce | 416 | static int stmpe_gpio_remove(struct platform_device *pdev) |
03f822f5 RV |
417 | { |
418 | struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); | |
419 | struct stmpe *stmpe = stmpe_gpio->stmpe; | |
03f822f5 | 420 | |
9f5132ae | 421 | gpiochip_remove(&stmpe_gpio->chip); |
03f822f5 | 422 | stmpe_disable(stmpe, STMPE_BLOCK_GPIO); |
03f822f5 RV |
423 | kfree(stmpe_gpio); |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
428 | static struct platform_driver stmpe_gpio_driver = { | |
429 | .driver.name = "stmpe-gpio", | |
430 | .driver.owner = THIS_MODULE, | |
431 | .probe = stmpe_gpio_probe, | |
8283c4ff | 432 | .remove = stmpe_gpio_remove, |
03f822f5 RV |
433 | }; |
434 | ||
435 | static int __init stmpe_gpio_init(void) | |
436 | { | |
437 | return platform_driver_register(&stmpe_gpio_driver); | |
438 | } | |
439 | subsys_initcall(stmpe_gpio_init); | |
440 | ||
441 | static void __exit stmpe_gpio_exit(void) | |
442 | { | |
443 | platform_driver_unregister(&stmpe_gpio_driver); | |
444 | } | |
445 | module_exit(stmpe_gpio_exit); | |
446 | ||
447 | MODULE_LICENSE("GPL v2"); | |
448 | MODULE_DESCRIPTION("STMPExxxx GPIO driver"); | |
449 | MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); |