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d88b25be RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License, version 2 | |
5 | * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson | |
6 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/gpio.h> | |
3113e679 | 14 | #include <linux/of.h> |
d88b25be | 15 | #include <linux/interrupt.h> |
c6eda6c5 | 16 | #include <linux/mfd/tc3589x.h> |
d88b25be RV |
17 | |
18 | /* | |
19 | * These registers are modified under the irq bus lock and cached to avoid | |
20 | * unnecessary writes in bus_sync_unlock. | |
21 | */ | |
22 | enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; | |
23 | ||
24 | #define CACHE_NR_REGS 4 | |
25 | #define CACHE_NR_BANKS 3 | |
26 | ||
20406ebf | 27 | struct tc3589x_gpio { |
d88b25be | 28 | struct gpio_chip chip; |
20406ebf | 29 | struct tc3589x *tc3589x; |
d88b25be RV |
30 | struct device *dev; |
31 | struct mutex irq_lock; | |
d88b25be RV |
32 | /* Caches of interrupt control registers for bus_lock */ |
33 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
34 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
35 | }; | |
36 | ||
20406ebf | 37 | static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset) |
d88b25be | 38 | { |
b0d38473 | 39 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
40 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
41 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
d88b25be RV |
42 | u8 mask = 1 << (offset % 8); |
43 | int ret; | |
44 | ||
20406ebf | 45 | ret = tc3589x_reg_read(tc3589x, reg); |
d88b25be RV |
46 | if (ret < 0) |
47 | return ret; | |
48 | ||
27ca2267 | 49 | return !!(ret & mask); |
d88b25be RV |
50 | } |
51 | ||
20406ebf | 52 | static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
d88b25be | 53 | { |
b0d38473 | 54 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
55 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
56 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
d88b25be RV |
57 | unsigned pos = offset % 8; |
58 | u8 data[] = {!!val << pos, 1 << pos}; | |
59 | ||
20406ebf | 60 | tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data); |
d88b25be RV |
61 | } |
62 | ||
20406ebf | 63 | static int tc3589x_gpio_direction_output(struct gpio_chip *chip, |
d88b25be RV |
64 | unsigned offset, int val) |
65 | { | |
b0d38473 | 66 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
67 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
68 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
d88b25be RV |
69 | unsigned pos = offset % 8; |
70 | ||
20406ebf | 71 | tc3589x_gpio_set(chip, offset, val); |
d88b25be | 72 | |
20406ebf | 73 | return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos); |
d88b25be RV |
74 | } |
75 | ||
20406ebf | 76 | static int tc3589x_gpio_direction_input(struct gpio_chip *chip, |
d88b25be RV |
77 | unsigned offset) |
78 | { | |
b0d38473 | 79 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
80 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
81 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
d88b25be RV |
82 | unsigned pos = offset % 8; |
83 | ||
20406ebf | 84 | return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0); |
d88b25be RV |
85 | } |
86 | ||
d88b25be | 87 | static struct gpio_chip template_chip = { |
20406ebf | 88 | .label = "tc3589x", |
d88b25be | 89 | .owner = THIS_MODULE, |
20406ebf SI |
90 | .direction_input = tc3589x_gpio_direction_input, |
91 | .get = tc3589x_gpio_get, | |
92 | .direction_output = tc3589x_gpio_direction_output, | |
93 | .set = tc3589x_gpio_set, | |
9fb1f39e | 94 | .can_sleep = true, |
d88b25be RV |
95 | }; |
96 | ||
33fcc1b8 | 97 | static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
d88b25be | 98 | { |
cf42f1cf | 99 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 100 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 101 | int offset = d->hwirq; |
d88b25be RV |
102 | int regoffset = offset / 8; |
103 | int mask = 1 << (offset % 8); | |
104 | ||
105 | if (type == IRQ_TYPE_EDGE_BOTH) { | |
20406ebf | 106 | tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; |
d88b25be RV |
107 | return 0; |
108 | } | |
109 | ||
20406ebf | 110 | tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; |
d88b25be RV |
111 | |
112 | if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 113 | tc3589x_gpio->regs[REG_IS][regoffset] |= mask; |
d88b25be | 114 | else |
20406ebf | 115 | tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; |
d88b25be RV |
116 | |
117 | if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 118 | tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; |
d88b25be | 119 | else |
20406ebf | 120 | tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; |
d88b25be RV |
121 | |
122 | return 0; | |
123 | } | |
124 | ||
33fcc1b8 | 125 | static void tc3589x_gpio_irq_lock(struct irq_data *d) |
d88b25be | 126 | { |
cf42f1cf | 127 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 128 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
d88b25be | 129 | |
20406ebf | 130 | mutex_lock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
131 | } |
132 | ||
33fcc1b8 | 133 | static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d) |
d88b25be | 134 | { |
cf42f1cf | 135 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 136 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
20406ebf | 137 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
d88b25be | 138 | static const u8 regmap[] = { |
20406ebf SI |
139 | [REG_IBE] = TC3589x_GPIOIBE0, |
140 | [REG_IEV] = TC3589x_GPIOIEV0, | |
141 | [REG_IS] = TC3589x_GPIOIS0, | |
142 | [REG_IE] = TC3589x_GPIOIE0, | |
d88b25be RV |
143 | }; |
144 | int i, j; | |
145 | ||
146 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
147 | for (j = 0; j < CACHE_NR_BANKS; j++) { | |
20406ebf SI |
148 | u8 old = tc3589x_gpio->oldregs[i][j]; |
149 | u8 new = tc3589x_gpio->regs[i][j]; | |
d88b25be RV |
150 | |
151 | if (new == old) | |
152 | continue; | |
153 | ||
20406ebf SI |
154 | tc3589x_gpio->oldregs[i][j] = new; |
155 | tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new); | |
d88b25be RV |
156 | } |
157 | } | |
158 | ||
20406ebf | 159 | mutex_unlock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
160 | } |
161 | ||
33fcc1b8 | 162 | static void tc3589x_gpio_irq_mask(struct irq_data *d) |
d88b25be | 163 | { |
cf42f1cf | 164 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 165 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 166 | int offset = d->hwirq; |
d88b25be RV |
167 | int regoffset = offset / 8; |
168 | int mask = 1 << (offset % 8); | |
169 | ||
20406ebf | 170 | tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; |
d88b25be RV |
171 | } |
172 | ||
33fcc1b8 | 173 | static void tc3589x_gpio_irq_unmask(struct irq_data *d) |
d88b25be | 174 | { |
cf42f1cf | 175 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 176 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 177 | int offset = d->hwirq; |
d88b25be RV |
178 | int regoffset = offset / 8; |
179 | int mask = 1 << (offset % 8); | |
180 | ||
20406ebf | 181 | tc3589x_gpio->regs[REG_IE][regoffset] |= mask; |
d88b25be RV |
182 | } |
183 | ||
20406ebf SI |
184 | static struct irq_chip tc3589x_gpio_irq_chip = { |
185 | .name = "tc3589x-gpio", | |
33fcc1b8 LB |
186 | .irq_bus_lock = tc3589x_gpio_irq_lock, |
187 | .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock, | |
188 | .irq_mask = tc3589x_gpio_irq_mask, | |
189 | .irq_unmask = tc3589x_gpio_irq_unmask, | |
190 | .irq_set_type = tc3589x_gpio_irq_set_type, | |
d88b25be RV |
191 | }; |
192 | ||
20406ebf | 193 | static irqreturn_t tc3589x_gpio_irq(int irq, void *dev) |
d88b25be | 194 | { |
20406ebf SI |
195 | struct tc3589x_gpio *tc3589x_gpio = dev; |
196 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
d88b25be RV |
197 | u8 status[CACHE_NR_BANKS]; |
198 | int ret; | |
199 | int i; | |
200 | ||
20406ebf | 201 | ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0, |
d88b25be RV |
202 | ARRAY_SIZE(status), status); |
203 | if (ret < 0) | |
204 | return IRQ_NONE; | |
205 | ||
206 | for (i = 0; i < ARRAY_SIZE(status); i++) { | |
207 | unsigned int stat = status[i]; | |
208 | if (!stat) | |
209 | continue; | |
210 | ||
211 | while (stat) { | |
212 | int bit = __ffs(stat); | |
213 | int line = i * 8 + bit; | |
cf42f1cf LW |
214 | int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain, |
215 | line); | |
d88b25be | 216 | |
e300376d | 217 | handle_nested_irq(irq); |
d88b25be RV |
218 | stat &= ~(1 << bit); |
219 | } | |
220 | ||
20406ebf | 221 | tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]); |
d88b25be RV |
222 | } |
223 | ||
224 | return IRQ_HANDLED; | |
225 | } | |
226 | ||
3836309d | 227 | static int tc3589x_gpio_probe(struct platform_device *pdev) |
d88b25be | 228 | { |
20406ebf | 229 | struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent); |
3113e679 | 230 | struct device_node *np = pdev->dev.of_node; |
20406ebf | 231 | struct tc3589x_gpio *tc3589x_gpio; |
d88b25be RV |
232 | int ret; |
233 | int irq; | |
234 | ||
53e41f55 LW |
235 | if (!np) { |
236 | dev_err(&pdev->dev, "No Device Tree node found\n"); | |
3113e679 LJ |
237 | return -EINVAL; |
238 | } | |
d88b25be RV |
239 | |
240 | irq = platform_get_irq(pdev, 0); | |
241 | if (irq < 0) | |
242 | return irq; | |
243 | ||
033f2752 LW |
244 | tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio), |
245 | GFP_KERNEL); | |
20406ebf | 246 | if (!tc3589x_gpio) |
d88b25be RV |
247 | return -ENOMEM; |
248 | ||
20406ebf | 249 | mutex_init(&tc3589x_gpio->irq_lock); |
d88b25be | 250 | |
20406ebf SI |
251 | tc3589x_gpio->dev = &pdev->dev; |
252 | tc3589x_gpio->tc3589x = tc3589x; | |
d88b25be | 253 | |
20406ebf SI |
254 | tc3589x_gpio->chip = template_chip; |
255 | tc3589x_gpio->chip.ngpio = tc3589x->num_gpio; | |
58383c78 | 256 | tc3589x_gpio->chip.parent = &pdev->dev; |
90f2d0f7 | 257 | tc3589x_gpio->chip.base = -1; |
e90c636b | 258 | tc3589x_gpio->chip.of_node = np; |
d88b25be RV |
259 | |
260 | /* Bring the GPIO module out of reset */ | |
20406ebf SI |
261 | ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, |
262 | TC3589x_RSTCTRL_GPIRST, 0); | |
d88b25be | 263 | if (ret < 0) |
033f2752 | 264 | return ret; |
d88b25be | 265 | |
033f2752 LW |
266 | ret = devm_request_threaded_irq(&pdev->dev, |
267 | irq, NULL, tc3589x_gpio_irq, | |
268 | IRQF_ONESHOT, "tc3589x-gpio", | |
269 | tc3589x_gpio); | |
d88b25be RV |
270 | if (ret) { |
271 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
033f2752 | 272 | return ret; |
d88b25be RV |
273 | } |
274 | ||
b0d38473 | 275 | ret = gpiochip_add_data(&tc3589x_gpio->chip, tc3589x_gpio); |
d88b25be RV |
276 | if (ret) { |
277 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
033f2752 | 278 | return ret; |
d88b25be RV |
279 | } |
280 | ||
cf42f1cf LW |
281 | ret = gpiochip_irqchip_add(&tc3589x_gpio->chip, |
282 | &tc3589x_gpio_irq_chip, | |
283 | 0, | |
284 | handle_simple_irq, | |
285 | IRQ_TYPE_NONE); | |
286 | if (ret) { | |
287 | dev_err(&pdev->dev, | |
288 | "could not connect irqchip to gpiochip\n"); | |
289 | return ret; | |
290 | } | |
291 | ||
3f97d5fc LW |
292 | gpiochip_set_chained_irqchip(&tc3589x_gpio->chip, |
293 | &tc3589x_gpio_irq_chip, | |
294 | irq, | |
295 | NULL); | |
296 | ||
20406ebf | 297 | platform_set_drvdata(pdev, tc3589x_gpio); |
d88b25be RV |
298 | |
299 | return 0; | |
d88b25be RV |
300 | } |
301 | ||
206210ce | 302 | static int tc3589x_gpio_remove(struct platform_device *pdev) |
d88b25be | 303 | { |
20406ebf | 304 | struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev); |
f0a7a98d | 305 | |
9f5132ae | 306 | gpiochip_remove(&tc3589x_gpio->chip); |
d88b25be | 307 | |
d88b25be RV |
308 | return 0; |
309 | } | |
310 | ||
20406ebf SI |
311 | static struct platform_driver tc3589x_gpio_driver = { |
312 | .driver.name = "tc3589x-gpio", | |
d88b25be | 313 | .driver.owner = THIS_MODULE, |
20406ebf | 314 | .probe = tc3589x_gpio_probe, |
8283c4ff | 315 | .remove = tc3589x_gpio_remove, |
d88b25be RV |
316 | }; |
317 | ||
20406ebf | 318 | static int __init tc3589x_gpio_init(void) |
d88b25be | 319 | { |
20406ebf | 320 | return platform_driver_register(&tc3589x_gpio_driver); |
d88b25be | 321 | } |
20406ebf | 322 | subsys_initcall(tc3589x_gpio_init); |
d88b25be | 323 | |
20406ebf | 324 | static void __exit tc3589x_gpio_exit(void) |
d88b25be | 325 | { |
20406ebf | 326 | platform_driver_unregister(&tc3589x_gpio_driver); |
d88b25be | 327 | } |
20406ebf | 328 | module_exit(tc3589x_gpio_exit); |
d88b25be RV |
329 | |
330 | MODULE_LICENSE("GPL v2"); | |
20406ebf | 331 | MODULE_DESCRIPTION("TC3589x GPIO driver"); |
d88b25be | 332 | MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); |