[deliverable/linux.git] / drivers / gpio / gpio-tc3589x.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/bitops.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_IBE, REG_IEV, REG_IS, REG_IE };

#define CACHE_NR_REGS	4
#define CACHE_NR_BANKS	3

struct tc3589x_gpio {
	struct gpio_chip chip;
	struct tc3589x *tc3589x;
	struct device *dev;
	struct mutex irq_lock;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	u8 mask = BIT(offset % 8);
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	unsigned pos = offset % 8;
	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};

	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}

static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	tc3589x_gpio_set(chip, offset, val);

	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
}

static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
}

static int tc3589x_gpio_single_ended(struct gpio_chip *chip,
				     unsigned offset,
				     enum single_ended_mode mode)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	/*
	 * These registers are alterated at each second address
	 * ODM bit 0 = drive to GND or Hi-Z (open drain)
	 * ODM bit 1 = drive to VDD or Hi-Z (open source)
	 */
	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
	unsigned pos = offset % 8;
	int ret;

	switch(mode) {
	case LINE_MODE_OPEN_DRAIN:
		/* Set open drain mode */
		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
		if (ret)
			return ret;
		/* Enable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	case LINE_MODE_OPEN_SOURCE:
		/* Set open source mode */
		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
		if (ret)
			return ret;
		/* Enable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	case LINE_MODE_PUSH_PULL:
		/* Disable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
	default:
		break;
	}
	return -ENOTSUPP;
}

static struct gpio_chip template_chip = {
	.label			= "tc3589x",
	.owner			= THIS_MODULE,
	.direction_input	= tc3589x_gpio_direction_input,
	.get			= tc3589x_gpio_get,
	.direction_output	= tc3589x_gpio_direction_output,
	.set			= tc3589x_gpio_set,
	.set_single_ended	= tc3589x_gpio_single_ended,
	.can_sleep		= true,
};

static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type == IRQ_TYPE_EDGE_BOTH) {
		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
		return 0;
	}

	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;

	return 0;
}

static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);

	mutex_lock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	static const u8 regmap[] = {
		[REG_IBE]	= TC3589x_GPIOIBE0,
		[REG_IEV]	= TC3589x_GPIOIEV0,
		[REG_IS]	= TC3589x_GPIOIS0,
		[REG_IE]	= TC3589x_GPIOIE0,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < CACHE_NR_BANKS; j++) {
			u8 old = tc3589x_gpio->oldregs[i][j];
			u8 new = tc3589x_gpio->regs[i][j];

			if (new == old)
				continue;

			tc3589x_gpio->oldregs[i][j] = new;
			tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
		}
	}

	mutex_unlock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip tc3589x_gpio_irq_chip = {
	.name			= "tc3589x-gpio",
	.irq_bus_lock		= tc3589x_gpio_irq_lock,
	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
	.irq_mask		= tc3589x_gpio_irq_mask,
	.irq_unmask		= tc3589x_gpio_irq_unmask,
	.irq_set_type		= tc3589x_gpio_irq_set_type,
};

static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
	struct tc3589x_gpio *tc3589x_gpio = dev;
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 status[CACHE_NR_BANKS];
	int ret;
	int i;

	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
				 ARRAY_SIZE(status), status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < ARRAY_SIZE(status); i++) {
		unsigned int stat = status[i];
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = i * 8 + bit;
			int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
						   line);

			handle_nested_irq(irq);
			stat &= ~(1 << bit);
		}

		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
	}

	return IRQ_HANDLED;
}

static int tc3589x_gpio_probe(struct platform_device *pdev)
{
	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct tc3589x_gpio *tc3589x_gpio;
	int ret;
	int irq;

	if (!np) {
		dev_err(&pdev->dev, "No Device Tree node found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
				    GFP_KERNEL);
	if (!tc3589x_gpio)
		return -ENOMEM;

	mutex_init(&tc3589x_gpio->irq_lock);

	tc3589x_gpio->dev = &pdev->dev;
	tc3589x_gpio->tc3589x = tc3589x;

	tc3589x_gpio->chip = template_chip;
	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	tc3589x_gpio->chip.parent = &pdev->dev;
	tc3589x_gpio->chip.base = -1;
	tc3589x_gpio->chip.of_node = np;

	/* Bring the GPIO module out of reset */
	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
			       TC3589x_RSTCTRL_GPIRST, 0);
	if (ret < 0)
		return ret;

	ret = devm_request_threaded_irq(&pdev->dev,
					irq, NULL, tc3589x_gpio_irq,
					IRQF_ONESHOT, "tc3589x-gpio",
					tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		return ret;
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
				     tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		return ret;
	}

	ret =  gpiochip_irqchip_add(&tc3589x_gpio->chip,
				    &tc3589x_gpio_irq_chip,
				    0,
				    handle_simple_irq,
				    IRQ_TYPE_NONE);
	if (ret) {
		dev_err(&pdev->dev,
			"could not connect irqchip to gpiochip\n");
		return ret;
	}

	gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
				     &tc3589x_gpio_irq_chip,
				     irq,
				     NULL);

	platform_set_drvdata(pdev, tc3589x_gpio);

	return 0;
}

static struct platform_driver tc3589x_gpio_driver = {
	.driver.name	= "tc3589x-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= tc3589x_gpio_probe,
};

static int __init tc3589x_gpio_init(void)
{
	return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);
Commit	Line	Data
d88b25be RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
	6	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	7	*/
	8
d88b25be RV	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
cee1b40d	12	#include <linux/gpio/driver.h>
3113e679	13	#include <linux/of.h>
d88b25be	14	#include <linux/interrupt.h>
c6eda6c5	15	#include <linux/mfd/tc3589x.h>
cee1b40d	16	#include <linux/bitops.h>
d88b25be RV	17
	18	/*
	19	* These registers are modified under the irq bus lock and cached to avoid
	20	* unnecessary writes in bus_sync_unlock.
	21	*/
	22	enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
	23
	24	#define CACHE_NR_REGS 4
	25	#define CACHE_NR_BANKS 3
	26
20406ebf	27	struct tc3589x_gpio {
d88b25be	28	struct gpio_chip chip;
20406ebf	29	struct tc3589x *tc3589x;
d88b25be RV	30	struct device *dev;
d88b25be RV	31	struct mutex irq_lock;
d88b25be RV	32	/* Caches of interrupt control registers for bus_lock */
	33	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	34	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	35	};
	36
20406ebf	37	static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
d88b25be	38	{
b0d38473	39	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	40	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	41	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
cee1b40d	42	u8 mask = BIT(offset % 8);
d88b25be RV	43	int ret;
d88b25be RV	44
20406ebf	45	ret = tc3589x_reg_read(tc3589x, reg);
d88b25be RV	46	if (ret < 0)
	47	return ret;
	48
27ca2267	49	return !!(ret & mask);
d88b25be RV	50	}
d88b25be RV	51
20406ebf	52	static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
d88b25be	53	{
b0d38473	54	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	55	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	56	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be	57	unsigned pos = offset % 8;
cee1b40d	58	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
d88b25be	59
20406ebf	60	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
d88b25be RV	61	}
d88b25be RV	62
20406ebf	63	static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
d88b25be RV	64	unsigned offset, int val)
d88b25be RV	65	{
b0d38473	66	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	67	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	68	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	69	unsigned pos = offset % 8;
d88b25be RV	70
20406ebf	71	tc3589x_gpio_set(chip, offset, val);
d88b25be	72
cee1b40d	73	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
d88b25be RV	74	}
d88b25be RV	75
20406ebf	76	static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
d88b25be RV	77	unsigned offset)
d88b25be RV	78	{
b0d38473	79	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	80	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	81	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	82	unsigned pos = offset % 8;
d88b25be RV	83
cee1b40d	84	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
d88b25be RV	85	}
d88b25be RV	86
8b866b06 LW	87	static int tc3589x_gpio_single_ended(struct gpio_chip *chip,
	88	unsigned offset,
	89	enum single_ended_mode mode)
	90	{
	91	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	92	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	93	/*
	94	* These registers are alterated at each second address
	95	* ODM bit 0 = drive to GND or Hi-Z (open drain)
	96	* ODM bit 1 = drive to VDD or Hi-Z (open source)
	97	*/
	98	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
	99	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
	100	unsigned pos = offset % 8;
	101	int ret;
	102
	103	switch(mode) {
	104	case LINE_MODE_OPEN_DRAIN:
	105	/* Set open drain mode */
	106	ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
	107	if (ret)
	108	return ret;
	109	/* Enable open drain/source mode */
	110	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	111	case LINE_MODE_OPEN_SOURCE:
	112	/* Set open source mode */
	113	ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
	114	if (ret)
	115	return ret;
	116	/* Enable open drain/source mode */
	117	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	118	case LINE_MODE_PUSH_PULL:
	119	/* Disable open drain/source mode */
	120	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
	121	default:
	122	break;
	123	}
	124	return -ENOTSUPP;
	125	}
	126
d88b25be	127	static struct gpio_chip template_chip = {
20406ebf	128	.label = "tc3589x",
d88b25be	129	.owner = THIS_MODULE,
20406ebf SI	130	.direction_input = tc3589x_gpio_direction_input,
	131	.get = tc3589x_gpio_get,
	132	.direction_output = tc3589x_gpio_direction_output,
	133	.set = tc3589x_gpio_set,
8b866b06	134	.set_single_ended = tc3589x_gpio_single_ended,
9fb1f39e	135	.can_sleep = true,
d88b25be RV	136	};
d88b25be RV	137
33fcc1b8	138	static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
d88b25be	139	{
cf42f1cf	140	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	141	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	142	int offset = d->hwirq;
d88b25be	143	int regoffset = offset / 8;
cee1b40d	144	int mask = BIT(offset % 8);
d88b25be RV	145
d88b25be RV	146	if (type == IRQ_TYPE_EDGE_BOTH) {
20406ebf	147	tc3589x_gpio->regs[REG_IBE][regoffset] \|= mask;
d88b25be RV	148	return 0;
	149	}
	150
20406ebf	151	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
d88b25be RV	152
d88b25be RV	153	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	154	tc3589x_gpio->regs[REG_IS][regoffset] \|= mask;
d88b25be	155	else
20406ebf	156	tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
d88b25be RV	157
d88b25be RV	158	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	159	tc3589x_gpio->regs[REG_IEV][regoffset] \|= mask;
d88b25be	160	else
20406ebf	161	tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
d88b25be RV	162
	163	return 0;
	164	}
	165
33fcc1b8	166	static void tc3589x_gpio_irq_lock(struct irq_data *d)
d88b25be	167	{
cf42f1cf	168	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	169	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
d88b25be	170
20406ebf	171	mutex_lock(&tc3589x_gpio->irq_lock);
d88b25be RV	172	}
d88b25be RV	173
33fcc1b8	174	static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
d88b25be	175	{
cf42f1cf	176	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	177	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
20406ebf	178	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be	179	static const u8 regmap[] = {
20406ebf SI	180	[REG_IBE] = TC3589x_GPIOIBE0,
	181	[REG_IEV] = TC3589x_GPIOIEV0,
	182	[REG_IS] = TC3589x_GPIOIS0,
	183	[REG_IE] = TC3589x_GPIOIE0,
d88b25be RV	184	};
	185	int i, j;
	186
	187	for (i = 0; i < CACHE_NR_REGS; i++) {
	188	for (j = 0; j < CACHE_NR_BANKS; j++) {
20406ebf SI	189	u8 old = tc3589x_gpio->oldregs[i][j];
20406ebf SI	190	u8 new = tc3589x_gpio->regs[i][j];
d88b25be RV	191
	192	if (new == old)
	193	continue;
	194
20406ebf SI	195	tc3589x_gpio->oldregs[i][j] = new;
20406ebf SI	196	tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
d88b25be RV	197	}
	198	}
	199
20406ebf	200	mutex_unlock(&tc3589x_gpio->irq_lock);
d88b25be RV	201	}
d88b25be RV	202
33fcc1b8	203	static void tc3589x_gpio_irq_mask(struct irq_data *d)
d88b25be	204	{
cf42f1cf	205	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	206	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	207	int offset = d->hwirq;
d88b25be	208	int regoffset = offset / 8;
cee1b40d	209	int mask = BIT(offset % 8);
d88b25be	210
20406ebf	211	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
d88b25be RV	212	}
d88b25be RV	213
33fcc1b8	214	static void tc3589x_gpio_irq_unmask(struct irq_data *d)
d88b25be	215	{
cf42f1cf	216	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	217	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	218	int offset = d->hwirq;
d88b25be	219	int regoffset = offset / 8;
cee1b40d	220	int mask = BIT(offset % 8);
d88b25be	221
20406ebf	222	tc3589x_gpio->regs[REG_IE][regoffset] \|= mask;
d88b25be RV	223	}
d88b25be RV	224
20406ebf SI	225	static struct irq_chip tc3589x_gpio_irq_chip = {
20406ebf SI	226	.name = "tc3589x-gpio",
33fcc1b8 LB	227	.irq_bus_lock = tc3589x_gpio_irq_lock,
	228	.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
	229	.irq_mask = tc3589x_gpio_irq_mask,
	230	.irq_unmask = tc3589x_gpio_irq_unmask,
	231	.irq_set_type = tc3589x_gpio_irq_set_type,
d88b25be RV	232	};
d88b25be RV	233
20406ebf	234	static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
d88b25be	235	{
20406ebf SI	236	struct tc3589x_gpio *tc3589x_gpio = dev;
20406ebf SI	237	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be RV	238	u8 status[CACHE_NR_BANKS];
	239	int ret;
	240	int i;
	241
20406ebf	242	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
d88b25be RV	243	ARRAY_SIZE(status), status);
	244	if (ret < 0)
	245	return IRQ_NONE;
	246
	247	for (i = 0; i < ARRAY_SIZE(status); i++) {
	248	unsigned int stat = status[i];
	249	if (!stat)
	250	continue;
	251
	252	while (stat) {
	253	int bit = __ffs(stat);
	254	int line = i * 8 + bit;
cf42f1cf LW	255	int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
cf42f1cf LW	256	line);
d88b25be	257
e300376d	258	handle_nested_irq(irq);
d88b25be RV	259	stat &= ~(1 << bit);
	260	}
	261
20406ebf	262	tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
d88b25be RV	263	}
	264
	265	return IRQ_HANDLED;
	266	}
	267
3836309d	268	static int tc3589x_gpio_probe(struct platform_device *pdev)
d88b25be	269	{
20406ebf	270	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
3113e679	271	struct device_node *np = pdev->dev.of_node;
20406ebf	272	struct tc3589x_gpio *tc3589x_gpio;
d88b25be RV	273	int ret;
	274	int irq;
	275
53e41f55 LW	276	if (!np) {
53e41f55 LW	277	dev_err(&pdev->dev, "No Device Tree node found\n");
3113e679 LJ	278	return -EINVAL;
3113e679 LJ	279	}
d88b25be RV	280
	281	irq = platform_get_irq(pdev, 0);
	282	if (irq < 0)
	283	return irq;
	284
033f2752 LW	285	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
033f2752 LW	286	GFP_KERNEL);
20406ebf	287	if (!tc3589x_gpio)
d88b25be RV	288	return -ENOMEM;
d88b25be RV	289
20406ebf	290	mutex_init(&tc3589x_gpio->irq_lock);
d88b25be	291
20406ebf SI	292	tc3589x_gpio->dev = &pdev->dev;
20406ebf SI	293	tc3589x_gpio->tc3589x = tc3589x;
d88b25be	294
20406ebf SI	295	tc3589x_gpio->chip = template_chip;
20406ebf SI	296	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
58383c78	297	tc3589x_gpio->chip.parent = &pdev->dev;
90f2d0f7	298	tc3589x_gpio->chip.base = -1;
e90c636b	299	tc3589x_gpio->chip.of_node = np;
d88b25be RV	300
d88b25be RV	301	/* Bring the GPIO module out of reset */
20406ebf SI	302	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
20406ebf SI	303	TC3589x_RSTCTRL_GPIRST, 0);
d88b25be	304	if (ret < 0)
033f2752	305	return ret;
d88b25be	306
033f2752 LW	307	ret = devm_request_threaded_irq(&pdev->dev,
	308	irq, NULL, tc3589x_gpio_irq,
	309	IRQF_ONESHOT, "tc3589x-gpio",
	310	tc3589x_gpio);
d88b25be RV	311	if (ret) {
d88b25be RV	312	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
033f2752	313	return ret;
d88b25be RV	314	}
d88b25be RV	315
f3378b6a LD	316	ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
f3378b6a LD	317	tc3589x_gpio);
d88b25be RV	318	if (ret) {
d88b25be RV	319	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
033f2752	320	return ret;
d88b25be RV	321	}
d88b25be RV	322
cf42f1cf LW	323	ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
	324	&tc3589x_gpio_irq_chip,
	325	0,
	326	handle_simple_irq,
	327	IRQ_TYPE_NONE);
	328	if (ret) {
	329	dev_err(&pdev->dev,
	330	"could not connect irqchip to gpiochip\n");
	331	return ret;
	332	}
	333
3f97d5fc LW	334	gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
	335	&tc3589x_gpio_irq_chip,
	336	irq,
	337	NULL);
	338
20406ebf	339	platform_set_drvdata(pdev, tc3589x_gpio);
d88b25be RV	340
d88b25be RV	341	return 0;
d88b25be RV	342	}
d88b25be RV	343
20406ebf SI	344	static struct platform_driver tc3589x_gpio_driver = {
20406ebf SI	345	.driver.name = "tc3589x-gpio",
d88b25be	346	.driver.owner = THIS_MODULE,
20406ebf	347	.probe = tc3589x_gpio_probe,
d88b25be RV	348	};
d88b25be RV	349
20406ebf	350	static int __init tc3589x_gpio_init(void)
d88b25be	351	{
20406ebf	352	return platform_driver_register(&tc3589x_gpio_driver);
d88b25be	353	}
20406ebf	354	subsys_initcall(tc3589x_gpio_init);