[deliverable/linux.git] / drivers / gpio / gpio-tc3589x.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_IBE, REG_IEV, REG_IS, REG_IE };

#define CACHE_NR_REGS	4
#define CACHE_NR_BANKS	3

struct tc3589x_gpio {
	struct gpio_chip chip;
	struct tc3589x *tc3589x;
	struct device *dev;
	struct mutex irq_lock;
	struct irq_domain *domain;

	int irq_base;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct tc3589x_gpio, chip);
}

static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return ret & mask;
}

static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	unsigned pos = offset % 8;
	u8 data[] = {!!val << pos, 1 << pos};

	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}

static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	tc3589x_gpio_set(chip, offset, val);

	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
}

static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
}

/**
 * tc3589x_gpio_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
 *
 * @tc3589x_gpio: tc3589x_gpio_irq controller to operate on.
 * @irq: index of the interrupt requested in the chip IRQs
 *
 * Useful for drivers to request their own IRQs.
 */
static int tc3589x_gpio_irq_get_virq(struct tc3589x_gpio *tc3589x_gpio,
				     int irq)
{
	if (!tc3589x_gpio)
		return -EINVAL;

	return irq_create_mapping(tc3589x_gpio->domain, irq);
}

static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);

	return tc3589x_gpio_irq_get_virq(tc3589x_gpio, offset);
}

static struct gpio_chip template_chip = {
	.label			= "tc3589x",
	.owner			= THIS_MODULE,
	.direction_input	= tc3589x_gpio_direction_input,
	.get			= tc3589x_gpio_get,
	.direction_output	= tc3589x_gpio_direction_output,
	.set			= tc3589x_gpio_set,
	.to_irq			= tc3589x_gpio_to_irq,
	.can_sleep		= 1,
};

static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_EDGE_BOTH) {
		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
		return 0;
	}

	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;

	return 0;
}

static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);

	mutex_lock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	static const u8 regmap[] = {
		[REG_IBE]	= TC3589x_GPIOIBE0,
		[REG_IEV]	= TC3589x_GPIOIEV0,
		[REG_IS]	= TC3589x_GPIOIS0,
		[REG_IE]	= TC3589x_GPIOIE0,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < CACHE_NR_BANKS; j++) {
			u8 old = tc3589x_gpio->oldregs[i][j];
			u8 new = tc3589x_gpio->regs[i][j];

			if (new == old)
				continue;

			tc3589x_gpio->oldregs[i][j] = new;
			tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
		}
	}

	mutex_unlock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip tc3589x_gpio_irq_chip = {
	.name			= "tc3589x-gpio",
	.irq_bus_lock		= tc3589x_gpio_irq_lock,
	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
	.irq_mask		= tc3589x_gpio_irq_mask,
	.irq_unmask		= tc3589x_gpio_irq_unmask,
	.irq_set_type		= tc3589x_gpio_irq_set_type,
};

static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
	struct tc3589x_gpio *tc3589x_gpio = dev;
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 status[CACHE_NR_BANKS];
	int ret;
	int i;

	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
				 ARRAY_SIZE(status), status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < ARRAY_SIZE(status); i++) {
		unsigned int stat = status[i];
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = i * 8 + bit;
			int virq = tc3589x_gpio_irq_get_virq(tc3589x_gpio, line);

			handle_nested_irq(virq);
			stat &= ~(1 << bit);
		}

		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
	}

	return IRQ_HANDLED;
}

static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int virq,
				irq_hw_number_t hwirq)
{
	struct tc3589x *tc3589x_gpio = d->host_data;

	irq_set_chip_data(virq, tc3589x_gpio);
	irq_set_chip_and_handler(virq, &tc3589x_gpio_irq_chip,
				handle_simple_irq);
	irq_set_nested_thread(virq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(virq, IRQF_VALID);
#else
	irq_set_noprobe(virq);
#endif

	return 0;
}

static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
{
#ifdef CONFIG_ARM
	set_irq_flags(virq, 0);
#endif
	irq_set_chip_and_handler(virq, NULL, NULL);
	irq_set_chip_data(virq, NULL);
}

static struct irq_domain_ops tc3589x_irq_ops = {
        .map    = tc3589x_gpio_irq_map,
        .unmap  = tc3589x_gpio_irq_unmap,
        .xlate  = irq_domain_xlate_twocell,
};

static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio)
{
	int base = tc3589x_gpio->irq_base;

	if (base) {
		tc3589x_gpio->domain = irq_domain_add_legacy(
			NULL, tc3589x_gpio->chip.ngpio, base,
			0, &tc3589x_irq_ops, tc3589x_gpio);
	}
	else {
		tc3589x_gpio->domain = irq_domain_add_linear(
			NULL, tc3589x_gpio->chip.ngpio,
			&tc3589x_irq_ops, tc3589x_gpio);
	}

	if (!tc3589x_gpio->domain) {
		dev_err(tc3589x_gpio->dev, "Failed to create irqdomain\n");
		return -ENOSYS;
	}

	return 0;
}

static int __devinit tc3589x_gpio_probe(struct platform_device *pdev)
{
	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	struct tc3589x_gpio_platform_data *pdata;
	struct tc3589x_gpio *tc3589x_gpio;
	int ret;
	int irq;

	pdata = tc3589x->pdata->gpio;
	if (!pdata)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
	if (!tc3589x_gpio)
		return -ENOMEM;

	mutex_init(&tc3589x_gpio->irq_lock);

	tc3589x_gpio->dev = &pdev->dev;
	tc3589x_gpio->tc3589x = tc3589x;

	tc3589x_gpio->chip = template_chip;
	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	tc3589x_gpio->chip.dev = &pdev->dev;
	tc3589x_gpio->chip.base = pdata->gpio_base;

	tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0);

	tc3589x_gpio->irq_base = tc3589x->irq_base ?
		tc3589x->irq_base + TC3589x_INT_GPIO(0) : 0;

	/* Bring the GPIO module out of reset */
	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
			       TC3589x_RSTCTRL_GPIRST, 0);
	if (ret < 0)
		goto out_free;

	ret = tc3589x_gpio_irq_init(tc3589x_gpio);
	if (ret)
		goto out_free;

	ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
				   "tc3589x-gpio", tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		goto out_free;
	}

	ret = gpiochip_add(&tc3589x_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata->setup)
		pdata->setup(tc3589x, tc3589x_gpio->chip.base);

	platform_set_drvdata(pdev, tc3589x_gpio);

	return 0;

out_freeirq:
	free_irq(irq, tc3589x_gpio);
out_free:
	kfree(tc3589x_gpio);
	return ret;
}

static int __devexit tc3589x_gpio_remove(struct platform_device *pdev)
{
	struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata->remove)
		pdata->remove(tc3589x, tc3589x_gpio->chip.base);

	ret = gpiochip_remove(&tc3589x_gpio->chip);
	if (ret < 0) {
		dev_err(tc3589x_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	free_irq(irq, tc3589x_gpio);

	platform_set_drvdata(pdev, NULL);
	kfree(tc3589x_gpio);

	return 0;
}

static struct platform_driver tc3589x_gpio_driver = {
	.driver.name	= "tc3589x-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= tc3589x_gpio_probe,
	.remove		= __devexit_p(tc3589x_gpio_remove),
};

static int __init tc3589x_gpio_init(void)
{
	return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);

static void __exit tc3589x_gpio_exit(void)
{
	platform_driver_unregister(&tc3589x_gpio_driver);
}
module_exit(tc3589x_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TC3589x GPIO driver");
MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");
Commit	Line	Data
d88b25be RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
	6	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/slab.h>
	13	#include <linux/gpio.h>
	14	#include <linux/irq.h>
efe4c949	15	#include <linux/irqdomain.h>
d88b25be	16	#include <linux/interrupt.h>
c6eda6c5	17	#include <linux/mfd/tc3589x.h>
d88b25be RV	18
	19	/*
	20	* These registers are modified under the irq bus lock and cached to avoid
	21	* unnecessary writes in bus_sync_unlock.
	22	*/
	23	enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
	24
	25	#define CACHE_NR_REGS 4
	26	#define CACHE_NR_BANKS 3
	27
20406ebf	28	struct tc3589x_gpio {
d88b25be	29	struct gpio_chip chip;
20406ebf	30	struct tc3589x *tc3589x;
d88b25be RV	31	struct device *dev;
d88b25be RV	32	struct mutex irq_lock;
efe4c949	33	struct irq_domain *domain;
d88b25be RV	34
	35	int irq_base;
	36
	37	/* Caches of interrupt control registers for bus_lock */
	38	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	40	};
	41
20406ebf	42	static inline struct tc3589x_gpio to_tc3589x_gpio(struct gpio_chip chip)
d88b25be	43	{
20406ebf	44	return container_of(chip, struct tc3589x_gpio, chip);
d88b25be RV	45	}
d88b25be RV	46
20406ebf	47	static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
d88b25be	48	{
20406ebf SI	49	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	50	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	51	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be RV	52	u8 mask = 1 << (offset % 8);
	53	int ret;
	54
20406ebf	55	ret = tc3589x_reg_read(tc3589x, reg);
d88b25be RV	56	if (ret < 0)
	57	return ret;
	58
	59	return ret & mask;
	60	}
	61
20406ebf	62	static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
d88b25be	63	{
20406ebf SI	64	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	65	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	66	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be RV	67	unsigned pos = offset % 8;
	68	u8 data[] = {!!val << pos, 1 << pos};
	69
20406ebf	70	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
d88b25be RV	71	}
d88b25be RV	72
20406ebf	73	static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
d88b25be RV	74	unsigned offset, int val)
d88b25be RV	75	{
20406ebf SI	76	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	77	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	78	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	79	unsigned pos = offset % 8;
d88b25be RV	80
20406ebf	81	tc3589x_gpio_set(chip, offset, val);
d88b25be	82
20406ebf	83	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
d88b25be RV	84	}
d88b25be RV	85
20406ebf	86	static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
d88b25be RV	87	unsigned offset)
d88b25be RV	88	{
20406ebf SI	89	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	90	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	91	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	92	unsigned pos = offset % 8;
d88b25be RV	93
20406ebf	94	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
d88b25be RV	95	}
d88b25be RV	96
efe4c949 LJ	97	/**
	98	* tc3589x_gpio_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
	99	*
	100	* @tc3589x_gpio: tc3589x_gpio_irq controller to operate on.
	101	* @irq: index of the interrupt requested in the chip IRQs
	102	*
	103	* Useful for drivers to request their own IRQs.
	104	*/
	105	static int tc3589x_gpio_irq_get_virq(struct tc3589x_gpio *tc3589x_gpio,
	106	int irq)
	107	{
	108	if (!tc3589x_gpio)
	109	return -EINVAL;
	110
	111	return irq_create_mapping(tc3589x_gpio->domain, irq);
	112	}
	113
20406ebf	114	static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
d88b25be	115	{
20406ebf	116	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
d88b25be	117
efe4c949	118	return tc3589x_gpio_irq_get_virq(tc3589x_gpio, offset);
d88b25be RV	119	}
	120
	121	static struct gpio_chip template_chip = {
20406ebf	122	.label = "tc3589x",
d88b25be	123	.owner = THIS_MODULE,
20406ebf SI	124	.direction_input = tc3589x_gpio_direction_input,
	125	.get = tc3589x_gpio_get,
	126	.direction_output = tc3589x_gpio_direction_output,
	127	.set = tc3589x_gpio_set,
	128	.to_irq = tc3589x_gpio_to_irq,
d88b25be RV	129	.can_sleep = 1,
	130	};
	131
33fcc1b8	132	static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
d88b25be	133	{
33fcc1b8	134	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
efe4c949	135	int offset = d->hwirq;
d88b25be RV	136	int regoffset = offset / 8;
	137	int mask = 1 << (offset % 8);
	138
	139	if (type == IRQ_TYPE_EDGE_BOTH) {
20406ebf	140	tc3589x_gpio->regs[REG_IBE][regoffset] \|= mask;
d88b25be RV	141	return 0;
	142	}
	143
20406ebf	144	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
d88b25be RV	145
d88b25be RV	146	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	147	tc3589x_gpio->regs[REG_IS][regoffset] \|= mask;
d88b25be	148	else
20406ebf	149	tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
d88b25be RV	150
d88b25be RV	151	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	152	tc3589x_gpio->regs[REG_IEV][regoffset] \|= mask;
d88b25be	153	else
20406ebf	154	tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
d88b25be RV	155
	156	return 0;
	157	}
	158
33fcc1b8	159	static void tc3589x_gpio_irq_lock(struct irq_data *d)
d88b25be	160	{
33fcc1b8	161	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
d88b25be	162
20406ebf	163	mutex_lock(&tc3589x_gpio->irq_lock);
d88b25be RV	164	}
d88b25be RV	165
33fcc1b8	166	static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
d88b25be	167	{
33fcc1b8	168	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
20406ebf	169	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be	170	static const u8 regmap[] = {
20406ebf SI	171	[REG_IBE] = TC3589x_GPIOIBE0,
	172	[REG_IEV] = TC3589x_GPIOIEV0,
	173	[REG_IS] = TC3589x_GPIOIS0,
	174	[REG_IE] = TC3589x_GPIOIE0,
d88b25be RV	175	};
	176	int i, j;
	177
	178	for (i = 0; i < CACHE_NR_REGS; i++) {
	179	for (j = 0; j < CACHE_NR_BANKS; j++) {
20406ebf SI	180	u8 old = tc3589x_gpio->oldregs[i][j];
20406ebf SI	181	u8 new = tc3589x_gpio->regs[i][j];
d88b25be RV	182
	183	if (new == old)
	184	continue;
	185
20406ebf SI	186	tc3589x_gpio->oldregs[i][j] = new;
20406ebf SI	187	tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
d88b25be RV	188	}
	189	}
	190
20406ebf	191	mutex_unlock(&tc3589x_gpio->irq_lock);
d88b25be RV	192	}
d88b25be RV	193
33fcc1b8	194	static void tc3589x_gpio_irq_mask(struct irq_data *d)
d88b25be	195	{
33fcc1b8	196	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
efe4c949	197	int offset = d->hwirq;
d88b25be RV	198	int regoffset = offset / 8;
	199	int mask = 1 << (offset % 8);
	200
20406ebf	201	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
d88b25be RV	202	}
d88b25be RV	203
33fcc1b8	204	static void tc3589x_gpio_irq_unmask(struct irq_data *d)
d88b25be	205	{
33fcc1b8	206	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
efe4c949	207	int offset = d->hwirq;
d88b25be RV	208	int regoffset = offset / 8;
	209	int mask = 1 << (offset % 8);
	210
20406ebf	211	tc3589x_gpio->regs[REG_IE][regoffset] \|= mask;
d88b25be RV	212	}
d88b25be RV	213
20406ebf SI	214	static struct irq_chip tc3589x_gpio_irq_chip = {
20406ebf SI	215	.name = "tc3589x-gpio",
33fcc1b8 LB	216	.irq_bus_lock = tc3589x_gpio_irq_lock,
	217	.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
	218	.irq_mask = tc3589x_gpio_irq_mask,
	219	.irq_unmask = tc3589x_gpio_irq_unmask,
	220	.irq_set_type = tc3589x_gpio_irq_set_type,
d88b25be RV	221	};
d88b25be RV	222
20406ebf	223	static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
d88b25be	224	{
20406ebf SI	225	struct tc3589x_gpio *tc3589x_gpio = dev;
20406ebf SI	226	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be RV	227	u8 status[CACHE_NR_BANKS];
	228	int ret;
	229	int i;
	230
20406ebf	231	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
d88b25be RV	232	ARRAY_SIZE(status), status);
	233	if (ret < 0)
	234	return IRQ_NONE;
	235
	236	for (i = 0; i < ARRAY_SIZE(status); i++) {
	237	unsigned int stat = status[i];
	238	if (!stat)
	239	continue;
	240
	241	while (stat) {
	242	int bit = __ffs(stat);
	243	int line = i * 8 + bit;
efe4c949	244	int virq = tc3589x_gpio_irq_get_virq(tc3589x_gpio, line);
d88b25be	245
efe4c949	246	handle_nested_irq(virq);
d88b25be RV	247	stat &= ~(1 << bit);
	248	}
	249
20406ebf	250	tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
d88b25be RV	251	}
	252
	253	return IRQ_HANDLED;
	254	}
	255
efe4c949 LJ	256	static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int virq,
efe4c949 LJ	257	irq_hw_number_t hwirq)
d88b25be	258	{
efe4c949	259	struct tc3589x *tc3589x_gpio = d->host_data;
d88b25be	260
efe4c949 LJ	261	irq_set_chip_data(virq, tc3589x_gpio);
	262	irq_set_chip_and_handler(virq, &tc3589x_gpio_irq_chip,
	263	handle_simple_irq);
	264	irq_set_nested_thread(virq, 1);
d88b25be	265	#ifdef CONFIG_ARM
efe4c949	266	set_irq_flags(virq, IRQF_VALID);
d88b25be	267	#else
efe4c949	268	irq_set_noprobe(virq);
d88b25be	269	#endif
d88b25be RV	270
	271	return 0;
	272	}
	273
efe4c949	274	static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
d88b25be	275	{
d88b25be	276	#ifdef CONFIG_ARM
efe4c949	277	set_irq_flags(virq, 0);
d88b25be	278	#endif
efe4c949 LJ	279	irq_set_chip_and_handler(virq, NULL, NULL);
	280	irq_set_chip_data(virq, NULL);
	281	}
	282
	283	static struct irq_domain_ops tc3589x_irq_ops = {
	284	.map = tc3589x_gpio_irq_map,
	285	.unmap = tc3589x_gpio_irq_unmap,
	286	.xlate = irq_domain_xlate_twocell,
	287	};
	288
	289	static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio)
	290	{
	291	int base = tc3589x_gpio->irq_base;
	292
	293	if (base) {
	294	tc3589x_gpio->domain = irq_domain_add_legacy(
	295	NULL, tc3589x_gpio->chip.ngpio, base,
	296	0, &tc3589x_irq_ops, tc3589x_gpio);
d88b25be	297	}
efe4c949 LJ	298	else {
	299	tc3589x_gpio->domain = irq_domain_add_linear(
	300	NULL, tc3589x_gpio->chip.ngpio,
	301	&tc3589x_irq_ops, tc3589x_gpio);
	302	}
	303
	304	if (!tc3589x_gpio->domain) {
	305	dev_err(tc3589x_gpio->dev, "Failed to create irqdomain\n");
	306	return -ENOSYS;
	307	}
	308
	309	return 0;
d88b25be RV	310	}
d88b25be RV	311
20406ebf	312	static int __devinit tc3589x_gpio_probe(struct platform_device *pdev)
d88b25be	313	{
20406ebf SI	314	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	315	struct tc3589x_gpio_platform_data *pdata;
	316	struct tc3589x_gpio *tc3589x_gpio;
d88b25be RV	317	int ret;
	318	int irq;
	319
20406ebf	320	pdata = tc3589x->pdata->gpio;
d88b25be RV	321	if (!pdata)
	322	return -ENODEV;
	323
	324	irq = platform_get_irq(pdev, 0);
	325	if (irq < 0)
	326	return irq;
	327
20406ebf SI	328	tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
20406ebf SI	329	if (!tc3589x_gpio)
d88b25be RV	330	return -ENOMEM;
d88b25be RV	331
20406ebf	332	mutex_init(&tc3589x_gpio->irq_lock);
d88b25be	333
20406ebf SI	334	tc3589x_gpio->dev = &pdev->dev;
20406ebf SI	335	tc3589x_gpio->tc3589x = tc3589x;
d88b25be	336
20406ebf SI	337	tc3589x_gpio->chip = template_chip;
	338	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	339	tc3589x_gpio->chip.dev = &pdev->dev;
	340	tc3589x_gpio->chip.base = pdata->gpio_base;
d88b25be	341
20406ebf	342	tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0);
d88b25be	343
efe4c949 LJ	344	tc3589x_gpio->irq_base = tc3589x->irq_base ?
	345	tc3589x->irq_base + TC3589x_INT_GPIO(0) : 0;
	346
d88b25be	347	/* Bring the GPIO module out of reset */
20406ebf SI	348	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
20406ebf SI	349	TC3589x_RSTCTRL_GPIRST, 0);
d88b25be RV	350	if (ret < 0)
	351	goto out_free;
	352
20406ebf	353	ret = tc3589x_gpio_irq_init(tc3589x_gpio);
d88b25be RV	354	if (ret)
	355	goto out_free;
	356
20406ebf SI	357	ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
20406ebf SI	358	"tc3589x-gpio", tc3589x_gpio);
d88b25be RV	359	if (ret) {
d88b25be RV	360	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
efe4c949	361	goto out_free;
d88b25be RV	362	}
d88b25be RV	363
20406ebf	364	ret = gpiochip_add(&tc3589x_gpio->chip);
d88b25be RV	365	if (ret) {
	366	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	367	goto out_freeirq;
	368	}
	369
f0a7a98d	370	if (pdata->setup)
20406ebf	371	pdata->setup(tc3589x, tc3589x_gpio->chip.base);
f0a7a98d	372
20406ebf	373	platform_set_drvdata(pdev, tc3589x_gpio);
d88b25be RV	374
	375	return 0;
	376
	377	out_freeirq:
20406ebf	378	free_irq(irq, tc3589x_gpio);
d88b25be	379	out_free:
20406ebf	380	kfree(tc3589x_gpio);
d88b25be RV	381	return ret;
	382	}
	383
20406ebf	384	static int __devexit tc3589x_gpio_remove(struct platform_device *pdev)
d88b25be	385	{
20406ebf SI	386	struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
	387	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	388	struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
d88b25be RV	389	int irq = platform_get_irq(pdev, 0);
	390	int ret;
	391
f0a7a98d	392	if (pdata->remove)
20406ebf	393	pdata->remove(tc3589x, tc3589x_gpio->chip.base);
f0a7a98d	394
20406ebf	395	ret = gpiochip_remove(&tc3589x_gpio->chip);
d88b25be	396	if (ret < 0) {
20406ebf	397	dev_err(tc3589x_gpio->dev,
d88b25be RV	398	"unable to remove gpiochip: %d\n", ret);
	399	return ret;
	400	}
	401
20406ebf	402	free_irq(irq, tc3589x_gpio);
d88b25be RV	403
d88b25be RV	404	platform_set_drvdata(pdev, NULL);
20406ebf	405	kfree(tc3589x_gpio);
d88b25be RV	406
	407	return 0;
	408	}
	409
20406ebf SI	410	static struct platform_driver tc3589x_gpio_driver = {
20406ebf SI	411	.driver.name = "tc3589x-gpio",
d88b25be	412	.driver.owner = THIS_MODULE,
20406ebf SI	413	.probe = tc3589x_gpio_probe,
20406ebf SI	414	.remove = __devexit_p(tc3589x_gpio_remove),
d88b25be RV	415	};
d88b25be RV	416
20406ebf	417	static int __init tc3589x_gpio_init(void)
d88b25be	418	{
20406ebf	419	return platform_driver_register(&tc3589x_gpio_driver);
d88b25be	420	}
20406ebf	421	subsys_initcall(tc3589x_gpio_init);
d88b25be	422
20406ebf	423	static void __exit tc3589x_gpio_exit(void)
d88b25be	424	{
20406ebf	425	platform_driver_unregister(&tc3589x_gpio_driver);
d88b25be	426	}
20406ebf	427	module_exit(tc3589x_gpio_exit);
d88b25be RV	428
d88b25be RV	429	MODULE_LICENSE("GPL v2");
20406ebf	430	MODULE_DESCRIPTION("TC3589x GPIO driver");
d88b25be	431	MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");