Commit | Line | Data |
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3c92db9a EG |
1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
2e47b8b3 | 22 | #include <linux/interrupt.h> |
3c92db9a EG |
23 | #include <linux/io.h> |
24 | #include <linux/gpio.h> | |
5c1e2c9d | 25 | #include <linux/of_device.h> |
88d8951e SW |
26 | #include <linux/platform_device.h> |
27 | #include <linux/module.h> | |
6f74dc9b | 28 | #include <linux/irqdomain.h> |
3e215d0a | 29 | #include <linux/pinctrl/consumer.h> |
3c92db9a | 30 | |
98022940 WD |
31 | #include <asm/mach/irq.h> |
32 | ||
3c92db9a EG |
33 | #define GPIO_BANK(x) ((x) >> 5) |
34 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
35 | #define GPIO_BIT(x) ((x) & 0x7) | |
36 | ||
5c1e2c9d SW |
37 | #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ |
38 | GPIO_PORT(x) * 4) | |
3c92db9a EG |
39 | |
40 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) | |
41 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) | |
42 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) | |
43 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) | |
44 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) | |
45 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) | |
46 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) | |
47 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) | |
48 | ||
5c1e2c9d SW |
49 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) |
50 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) | |
51 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) | |
52 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) | |
53 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) | |
54 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) | |
3c92db9a EG |
55 | |
56 | #define GPIO_INT_LVL_MASK 0x010101 | |
57 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
58 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
59 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
60 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
61 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
62 | ||
63 | struct tegra_gpio_bank { | |
64 | int bank; | |
65 | int irq; | |
66 | spinlock_t lvl_lock[4]; | |
2e47b8b3 CC |
67 | #ifdef CONFIG_PM |
68 | u32 cnf[4]; | |
69 | u32 out[4]; | |
70 | u32 oe[4]; | |
71 | u32 int_enb[4]; | |
72 | u32 int_lvl[4]; | |
73 | #endif | |
3c92db9a EG |
74 | }; |
75 | ||
bdc93a77 | 76 | static struct irq_domain *irq_domain; |
88d8951e | 77 | static void __iomem *regs; |
3391811c | 78 | static u32 tegra_gpio_bank_count; |
5c1e2c9d SW |
79 | static u32 tegra_gpio_bank_stride; |
80 | static u32 tegra_gpio_upper_offset; | |
3391811c | 81 | static struct tegra_gpio_bank *tegra_gpio_banks; |
88d8951e SW |
82 | |
83 | static inline void tegra_gpio_writel(u32 val, u32 reg) | |
84 | { | |
85 | __raw_writel(val, regs + reg); | |
86 | } | |
87 | ||
88 | static inline u32 tegra_gpio_readl(u32 reg) | |
89 | { | |
90 | return __raw_readl(regs + reg); | |
91 | } | |
3c92db9a EG |
92 | |
93 | static int tegra_gpio_compose(int bank, int port, int bit) | |
94 | { | |
95 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
96 | } | |
97 | ||
98 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |
99 | { | |
100 | u32 val; | |
101 | ||
102 | val = 0x100 << GPIO_BIT(gpio); | |
103 | if (value) | |
104 | val |= 1 << GPIO_BIT(gpio); | |
88d8951e | 105 | tegra_gpio_writel(val, reg); |
3c92db9a EG |
106 | } |
107 | ||
3e215d0a | 108 | static void tegra_gpio_enable(int gpio) |
3c92db9a EG |
109 | { |
110 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | |
111 | } | |
691e06c0 | 112 | EXPORT_SYMBOL_GPL(tegra_gpio_enable); |
3c92db9a | 113 | |
3e215d0a | 114 | static void tegra_gpio_disable(int gpio) |
3c92db9a EG |
115 | { |
116 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | |
117 | } | |
691e06c0 | 118 | EXPORT_SYMBOL_GPL(tegra_gpio_disable); |
3c92db9a | 119 | |
3e215d0a SW |
120 | int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) |
121 | { | |
122 | return pinctrl_request_gpio(offset); | |
123 | } | |
124 | ||
125 | void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) | |
126 | { | |
127 | pinctrl_free_gpio(offset); | |
128 | tegra_gpio_disable(offset); | |
129 | } | |
130 | ||
3c92db9a EG |
131 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
132 | { | |
133 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | |
134 | } | |
135 | ||
136 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
137 | { | |
88d8951e | 138 | return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; |
3c92db9a EG |
139 | } |
140 | ||
141 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
142 | { | |
143 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | |
3e215d0a | 144 | tegra_gpio_enable(offset); |
3c92db9a EG |
145 | return 0; |
146 | } | |
147 | ||
148 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
149 | int value) | |
150 | { | |
151 | tegra_gpio_set(chip, offset, value); | |
152 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | |
3e215d0a | 153 | tegra_gpio_enable(offset); |
3c92db9a EG |
154 | return 0; |
155 | } | |
156 | ||
438a99c0 SW |
157 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
158 | { | |
bdc93a77 | 159 | return irq_find_mapping(irq_domain, offset); |
438a99c0 | 160 | } |
3c92db9a EG |
161 | |
162 | static struct gpio_chip tegra_gpio_chip = { | |
163 | .label = "tegra-gpio", | |
3e215d0a SW |
164 | .request = tegra_gpio_request, |
165 | .free = tegra_gpio_free, | |
3c92db9a EG |
166 | .direction_input = tegra_gpio_direction_input, |
167 | .get = tegra_gpio_get, | |
168 | .direction_output = tegra_gpio_direction_output, | |
169 | .set = tegra_gpio_set, | |
438a99c0 | 170 | .to_irq = tegra_gpio_to_irq, |
3c92db9a | 171 | .base = 0, |
3c92db9a EG |
172 | }; |
173 | ||
37337a8d | 174 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 175 | { |
6f74dc9b | 176 | int gpio = d->hwirq; |
3c92db9a | 177 | |
88d8951e | 178 | tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); |
3c92db9a EG |
179 | } |
180 | ||
37337a8d | 181 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 182 | { |
6f74dc9b | 183 | int gpio = d->hwirq; |
3c92db9a EG |
184 | |
185 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); | |
186 | } | |
187 | ||
37337a8d | 188 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 189 | { |
6f74dc9b | 190 | int gpio = d->hwirq; |
3c92db9a EG |
191 | |
192 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); | |
193 | } | |
194 | ||
37337a8d | 195 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 196 | { |
6f74dc9b | 197 | int gpio = d->hwirq; |
37337a8d | 198 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
3c92db9a EG |
199 | int port = GPIO_PORT(gpio); |
200 | int lvl_type; | |
201 | int val; | |
202 | unsigned long flags; | |
203 | ||
204 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
205 | case IRQ_TYPE_EDGE_RISING: | |
206 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
207 | break; | |
208 | ||
209 | case IRQ_TYPE_EDGE_FALLING: | |
210 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
211 | break; | |
212 | ||
213 | case IRQ_TYPE_EDGE_BOTH: | |
214 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
215 | break; | |
216 | ||
217 | case IRQ_TYPE_LEVEL_HIGH: | |
218 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
219 | break; | |
220 | ||
221 | case IRQ_TYPE_LEVEL_LOW: | |
222 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
223 | break; | |
224 | ||
225 | default: | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
229 | spin_lock_irqsave(&bank->lvl_lock[port], flags); | |
230 | ||
88d8951e | 231 | val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
3c92db9a EG |
232 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
233 | val |= lvl_type << GPIO_BIT(gpio); | |
88d8951e | 234 | tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); |
3c92db9a EG |
235 | |
236 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
237 | ||
d941136f SW |
238 | tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); |
239 | tegra_gpio_enable(gpio); | |
240 | ||
3c92db9a | 241 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
6845664a | 242 | __irq_set_handler_locked(d->irq, handle_level_irq); |
3c92db9a | 243 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 244 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
3c92db9a EG |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
249 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
250 | { | |
251 | struct tegra_gpio_bank *bank; | |
252 | int port; | |
253 | int pin; | |
254 | int unmasked = 0; | |
98022940 | 255 | struct irq_chip *chip = irq_desc_get_chip(desc); |
3c92db9a | 256 | |
98022940 | 257 | chained_irq_enter(chip, desc); |
3c92db9a | 258 | |
6845664a | 259 | bank = irq_get_handler_data(irq); |
3c92db9a EG |
260 | |
261 | for (port = 0; port < 4; port++) { | |
262 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | |
88d8951e SW |
263 | unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & |
264 | tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
265 | u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
3c92db9a EG |
266 | |
267 | for_each_set_bit(pin, &sta, 8) { | |
88d8951e | 268 | tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); |
3c92db9a EG |
269 | |
270 | /* if gpio is edge triggered, clear condition | |
271 | * before executing the hander so that we don't | |
272 | * miss edges | |
273 | */ | |
274 | if (lvl & (0x100 << pin)) { | |
275 | unmasked = 1; | |
98022940 | 276 | chained_irq_exit(chip, desc); |
3c92db9a EG |
277 | } |
278 | ||
279 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
280 | } | |
281 | } | |
282 | ||
283 | if (!unmasked) | |
98022940 | 284 | chained_irq_exit(chip, desc); |
3c92db9a EG |
285 | |
286 | } | |
287 | ||
2e47b8b3 CC |
288 | #ifdef CONFIG_PM |
289 | void tegra_gpio_resume(void) | |
290 | { | |
291 | unsigned long flags; | |
c8309ef6 CC |
292 | int b; |
293 | int p; | |
2e47b8b3 CC |
294 | |
295 | local_irq_save(flags); | |
296 | ||
3391811c | 297 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
2e47b8b3 CC |
298 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
299 | ||
300 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
301 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
302 | tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); |
303 | tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); | |
304 | tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); | |
305 | tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); | |
306 | tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); | |
2e47b8b3 CC |
307 | } |
308 | } | |
309 | ||
310 | local_irq_restore(flags); | |
2e47b8b3 CC |
311 | } |
312 | ||
313 | void tegra_gpio_suspend(void) | |
314 | { | |
315 | unsigned long flags; | |
c8309ef6 CC |
316 | int b; |
317 | int p; | |
2e47b8b3 | 318 | |
2e47b8b3 | 319 | local_irq_save(flags); |
3391811c | 320 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
2e47b8b3 CC |
321 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
322 | ||
323 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
324 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
325 | bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); |
326 | bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); | |
327 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); | |
328 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
329 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
2e47b8b3 CC |
330 | } |
331 | } | |
332 | local_irq_restore(flags); | |
333 | } | |
334 | ||
37337a8d | 335 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 336 | { |
37337a8d | 337 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
6845664a | 338 | return irq_set_irq_wake(bank->irq, enable); |
2e47b8b3 CC |
339 | } |
340 | #endif | |
3c92db9a EG |
341 | |
342 | static struct irq_chip tegra_gpio_irq_chip = { | |
343 | .name = "GPIO", | |
37337a8d LB |
344 | .irq_ack = tegra_gpio_irq_ack, |
345 | .irq_mask = tegra_gpio_irq_mask, | |
346 | .irq_unmask = tegra_gpio_irq_unmask, | |
347 | .irq_set_type = tegra_gpio_irq_set_type, | |
2e47b8b3 | 348 | #ifdef CONFIG_PM |
37337a8d | 349 | .irq_set_wake = tegra_gpio_wake_enable, |
2e47b8b3 | 350 | #endif |
3c92db9a EG |
351 | }; |
352 | ||
5c1e2c9d SW |
353 | struct tegra_gpio_soc_config { |
354 | u32 bank_stride; | |
355 | u32 upper_offset; | |
356 | }; | |
357 | ||
358 | static struct tegra_gpio_soc_config tegra20_gpio_config = { | |
359 | .bank_stride = 0x80, | |
360 | .upper_offset = 0x800, | |
361 | }; | |
362 | ||
363 | static struct tegra_gpio_soc_config tegra30_gpio_config = { | |
364 | .bank_stride = 0x100, | |
365 | .upper_offset = 0x80, | |
366 | }; | |
367 | ||
368 | static struct of_device_id tegra_gpio_of_match[] __devinitdata = { | |
369 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, | |
370 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, | |
371 | { }, | |
372 | }; | |
3c92db9a EG |
373 | |
374 | /* This lock class tells lockdep that GPIO irqs are in a different | |
375 | * category than their parents, so it won't report false recursion. | |
376 | */ | |
377 | static struct lock_class_key gpio_lock_class; | |
378 | ||
88d8951e | 379 | static int __devinit tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 380 | { |
5c1e2c9d SW |
381 | const struct of_device_id *match; |
382 | struct tegra_gpio_soc_config *config; | |
3391811c | 383 | int irq_base; |
88d8951e | 384 | struct resource *res; |
3c92db9a | 385 | struct tegra_gpio_bank *bank; |
47008001 | 386 | int gpio; |
3c92db9a EG |
387 | int i; |
388 | int j; | |
389 | ||
5c1e2c9d SW |
390 | match = of_match_device(tegra_gpio_of_match, &pdev->dev); |
391 | if (match) | |
392 | config = (struct tegra_gpio_soc_config *)match->data; | |
393 | else | |
394 | config = &tegra20_gpio_config; | |
395 | ||
396 | tegra_gpio_bank_stride = config->bank_stride; | |
397 | tegra_gpio_upper_offset = config->upper_offset; | |
398 | ||
3391811c SW |
399 | for (;;) { |
400 | res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); | |
401 | if (!res) | |
402 | break; | |
403 | tegra_gpio_bank_count++; | |
404 | } | |
405 | if (!tegra_gpio_bank_count) { | |
406 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
407 | return -ENODEV; | |
408 | } | |
409 | ||
410 | tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; | |
411 | ||
412 | tegra_gpio_banks = devm_kzalloc(&pdev->dev, | |
413 | tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), | |
414 | GFP_KERNEL); | |
415 | if (!tegra_gpio_banks) { | |
416 | dev_err(&pdev->dev, "Couldn't allocate bank structure\n"); | |
417 | return -ENODEV; | |
418 | } | |
419 | ||
420 | irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0); | |
421 | if (irq_base < 0) { | |
6f74dc9b SW |
422 | dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n"); |
423 | return -ENODEV; | |
424 | } | |
bdc93a77 SW |
425 | irq_domain = irq_domain_add_legacy(pdev->dev.of_node, |
426 | tegra_gpio_chip.ngpio, irq_base, 0, | |
427 | &irq_domain_simple_ops, NULL); | |
6f74dc9b | 428 | |
3391811c | 429 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
88d8951e SW |
430 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); |
431 | if (!res) { | |
432 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
433 | return -ENODEV; | |
434 | } | |
435 | ||
436 | bank = &tegra_gpio_banks[i]; | |
437 | bank->bank = i; | |
438 | bank->irq = res->start; | |
439 | } | |
440 | ||
441 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
442 | if (!res) { | |
443 | dev_err(&pdev->dev, "Missing MEM resource\n"); | |
444 | return -ENODEV; | |
445 | } | |
446 | ||
aedd4fdf | 447 | regs = devm_request_and_ioremap(&pdev->dev, res); |
88d8951e SW |
448 | if (!regs) { |
449 | dev_err(&pdev->dev, "Couldn't ioremap regs\n"); | |
450 | return -ENODEV; | |
451 | } | |
452 | ||
4a3398ee | 453 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
454 | for (j = 0; j < 4; j++) { |
455 | int gpio = tegra_gpio_compose(i, j, 0); | |
88d8951e | 456 | tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); |
3c92db9a EG |
457 | } |
458 | } | |
459 | ||
df221227 | 460 | #ifdef CONFIG_OF_GPIO |
88d8951e SW |
461 | tegra_gpio_chip.of_node = pdev->dev.of_node; |
462 | #endif | |
df221227 | 463 | |
3c92db9a EG |
464 | gpiochip_add(&tegra_gpio_chip); |
465 | ||
3391811c | 466 | for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { |
bdc93a77 | 467 | int irq = irq_find_mapping(irq_domain, gpio); |
47008001 | 468 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
3c92db9a | 469 | |
47008001 | 470 | bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; |
3c92db9a | 471 | |
47008001 SW |
472 | irq_set_lockdep_class(irq, &gpio_lock_class); |
473 | irq_set_chip_data(irq, bank); | |
474 | irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, | |
f38c02f3 | 475 | handle_simple_irq); |
47008001 | 476 | set_irq_flags(irq, IRQF_VALID); |
3c92db9a EG |
477 | } |
478 | ||
3391811c | 479 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
480 | bank = &tegra_gpio_banks[i]; |
481 | ||
6845664a TG |
482 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
483 | irq_set_handler_data(bank->irq, bank); | |
3c92db9a EG |
484 | |
485 | for (j = 0; j < 4; j++) | |
486 | spin_lock_init(&bank->lvl_lock[j]); | |
487 | } | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
88d8951e SW |
492 | static struct platform_driver tegra_gpio_driver = { |
493 | .driver = { | |
494 | .name = "tegra-gpio", | |
495 | .owner = THIS_MODULE, | |
496 | .of_match_table = tegra_gpio_of_match, | |
497 | }, | |
498 | .probe = tegra_gpio_probe, | |
499 | }; | |
500 | ||
501 | static int __init tegra_gpio_init(void) | |
502 | { | |
503 | return platform_driver_register(&tegra_gpio_driver); | |
504 | } | |
3c92db9a EG |
505 | postcore_initcall(tegra_gpio_init); |
506 | ||
507 | #ifdef CONFIG_DEBUG_FS | |
508 | ||
509 | #include <linux/debugfs.h> | |
510 | #include <linux/seq_file.h> | |
511 | ||
512 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
513 | { | |
514 | int i; | |
515 | int j; | |
516 | ||
4a3398ee | 517 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
518 | for (j = 0; j < 4; j++) { |
519 | int gpio = tegra_gpio_compose(i, j, 0); | |
2e47b8b3 CC |
520 | seq_printf(s, |
521 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
522 | i, j, | |
88d8951e SW |
523 | tegra_gpio_readl(GPIO_CNF(gpio)), |
524 | tegra_gpio_readl(GPIO_OE(gpio)), | |
525 | tegra_gpio_readl(GPIO_OUT(gpio)), | |
526 | tegra_gpio_readl(GPIO_IN(gpio)), | |
527 | tegra_gpio_readl(GPIO_INT_STA(gpio)), | |
528 | tegra_gpio_readl(GPIO_INT_ENB(gpio)), | |
529 | tegra_gpio_readl(GPIO_INT_LVL(gpio))); | |
3c92db9a EG |
530 | } |
531 | } | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
536 | { | |
537 | return single_open(file, dbg_gpio_show, &inode->i_private); | |
538 | } | |
539 | ||
540 | static const struct file_operations debug_fops = { | |
541 | .open = dbg_gpio_open, | |
542 | .read = seq_read, | |
543 | .llseek = seq_lseek, | |
544 | .release = single_release, | |
545 | }; | |
546 | ||
547 | static int __init tegra_gpio_debuginit(void) | |
548 | { | |
549 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
550 | NULL, NULL, &debug_fops); | |
551 | return 0; | |
552 | } | |
553 | late_initcall(tegra_gpio_debuginit); | |
554 | #endif |