[deliverable/linux.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
					GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM_SLEEP
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
	u32 wake_enb[4];
#endif
};

struct tegra_gpio_soc_config {
	u32 bank_stride;
	u32 upper_offset;
};

static struct device *dev;
static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static u32 tegra_gpio_bank_stride;
static u32 tegra_gpio_upper_offset;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

static void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

static void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(offset);
}

static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(offset);
	tegra_gpio_disable(offset);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	/* If gpio is in output mode then read from the out value */
	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
		return (tegra_gpio_readl(GPIO_OUT(offset)) >>
				GPIO_BIT(offset)) & 0x1;

	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.request		= tegra_gpio_request,
	.free			= tegra_gpio_free,
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;
	int ret;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio);
	if (ret) {
		dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio);
		return ret;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	tegra_gpio_enable(gpio);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		irq_set_handler_locked(d, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_shutdown(struct irq_data *d)
{
	int gpio = d->hwirq;

	gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio);
}

static void tegra_gpio_irq_handler(struct irq_desc *desc)
{
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);

	chained_irq_enter(chip, desc);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the handler so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_suspend(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));

			/* Enable gpio irq for wake up source */
			tegra_gpio_writel(bank->wake_enb[p],
					  GPIO_INT_ENB(gpio));
		}
	}
	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int gpio = d->hwirq;
	u32 port, bit, mask;

	port = GPIO_PORT(gpio);
	bit = GPIO_BIT(gpio);
	mask = BIT(bit);

	if (enable)
		bank->wake_enb[port] |= mask;
	else
		bank->wake_enb[port] &= ~mask;

	return irq_set_irq_wake(bank->irq, enable);
}
#endif

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static void tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
}

#else

static inline void tegra_gpio_debuginit(void)
{
}

#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
	.irq_shutdown	= tegra_gpio_irq_shutdown,
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake	= tegra_gpio_irq_set_wake,
#endif
};

static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int tegra_gpio_probe(struct platform_device *pdev)
{
	const struct tegra_gpio_soc_config *config;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int ret;
	int gpio;
	int i;
	int j;

	dev = &pdev->dev;

	config = of_device_get_match_data(&pdev->dev);
	if (!config) {
		dev_err(&pdev->dev, "Error: No device match found\n");
		return -ENODEV;
	}

	tegra_gpio_bank_stride = config->bank_stride;
	tegra_gpio_upper_offset = config->upper_offset;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks)
		return -ENODEV;

	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio,
					   &irq_domain_simple_ops, NULL);
	if (!irq_domain)
		return -ENODEV;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

	tegra_gpio_chip.of_node = pdev->dev.of_node;

	ret = devm_gpiochip_add_data(&pdev->dev, &tegra_gpio_chip, NULL);
	if (ret < 0) {
		irq_domain_remove(irq_domain);
		return ret;
	}

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_create_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler_and_data(bank->irq,
						 tegra_gpio_irq_handler, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	tegra_gpio_debuginit();

	return 0;
}

static const struct tegra_gpio_soc_config tegra20_gpio_config = {
	.bank_stride = 0x80,
	.upper_offset = 0x800,
};

static const struct tegra_gpio_soc_config tegra30_gpio_config = {
	.bank_stride = 0x100,
	.upper_offset = 0x80,
};

static const struct of_device_id tegra_gpio_of_match[] = {
	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	{ },
};

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.pm	= &tegra_gpio_pm_ops,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
641d0342	20	#include <linux/err.h>
3c92db9a EG	21	#include <linux/init.h>
3c92db9a EG	22	#include <linux/irq.h>
2e47b8b3	23	#include <linux/interrupt.h>
3c92db9a EG	24	#include <linux/io.h>
3c92db9a EG	25	#include <linux/gpio.h>
5c1e2c9d	26	#include <linux/of_device.h>
88d8951e SW	27	#include <linux/platform_device.h>
88d8951e SW	28	#include <linux/module.h>
6f74dc9b	29	#include <linux/irqdomain.h>
de88cbb7	30	#include <linux/irqchip/chained_irq.h>
3e215d0a	31	#include <linux/pinctrl/consumer.h>
8939ddc7	32	#include <linux/pm.h>
3c92db9a	33
3c92db9a EG	34	#define GPIO_BANK(x) ((x) >> 5)
	35	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	36	#define GPIO_BIT(x) ((x) & 0x7)
	37
5c1e2c9d SW	38	#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
5c1e2c9d SW	39	GPIO_PORT(x) * 4)
3c92db9a EG	40
	41	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	42	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	43	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	44	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	45	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	46	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	47	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	48	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	49
5c1e2c9d SW	50	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
	51	#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
	52	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
	53	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
	54	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
	55	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
3c92db9a EG	56
	57	#define GPIO_INT_LVL_MASK 0x010101
	58	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	59	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	60	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	61	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	62	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	63
	64	struct tegra_gpio_bank {
	65	int bank;
	66	int irq;
	67	spinlock_t lvl_lock[4];
8939ddc7	68	#ifdef CONFIG_PM_SLEEP
2e47b8b3 CC	69	u32 cnf[4];
	70	u32 out[4];
	71	u32 oe[4];
	72	u32 int_enb[4];
	73	u32 int_lvl[4];
203f31cb	74	u32 wake_enb[4];
2e47b8b3	75	#endif
3c92db9a EG	76	};
3c92db9a EG	77
171b92c8 LD	78	struct tegra_gpio_soc_config {
	79	u32 bank_stride;
	80	u32 upper_offset;
	81	};
	82
df231f28	83	static struct device *dev;
bdc93a77	84	static struct irq_domain *irq_domain;
88d8951e	85	static void __iomem *regs;
3391811c	86	static u32 tegra_gpio_bank_count;
5c1e2c9d SW	87	static u32 tegra_gpio_bank_stride;
5c1e2c9d SW	88	static u32 tegra_gpio_upper_offset;
3391811c	89	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	90
	91	static inline void tegra_gpio_writel(u32 val, u32 reg)
	92	{
	93	__raw_writel(val, regs + reg);
	94	}
	95
	96	static inline u32 tegra_gpio_readl(u32 reg)
	97	{
	98	return __raw_readl(regs + reg);
	99	}
3c92db9a EG	100
	101	static int tegra_gpio_compose(int bank, int port, int bit)
	102	{
	103	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	104	}
	105
	106	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	107	{
	108	u32 val;
	109
	110	val = 0x100 << GPIO_BIT(gpio);
	111	if (value)
	112	val \|= 1 << GPIO_BIT(gpio);
88d8951e	113	tegra_gpio_writel(val, reg);
3c92db9a EG	114	}
3c92db9a EG	115
3e215d0a	116	static void tegra_gpio_enable(int gpio)
3c92db9a EG	117	{
	118	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	119	}
	120
3e215d0a	121	static void tegra_gpio_disable(int gpio)
3c92db9a EG	122	{
	123	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	124	}
	125
924a0987	126	static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	127	{
	128	return pinctrl_request_gpio(offset);
	129	}
	130
924a0987	131	static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	132	{
	133	pinctrl_free_gpio(offset);
	134	tegra_gpio_disable(offset);
	135	}
	136
3c92db9a EG	137	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	138	{
	139	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	140	}
	141
	142	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	143	{
195812e4 LD	144	/* If gpio is in output mode then read from the out value */
	145	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
	146	return (tegra_gpio_readl(GPIO_OUT(offset)) >>
	147	GPIO_BIT(offset)) & 0x1;
	148
88d8951e	149	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	150	}
	151
	152	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	153	{
	154	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
3e215d0a	155	tegra_gpio_enable(offset);
3c92db9a EG	156	return 0;
	157	}
	158
	159	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	160	int value)
	161	{
	162	tegra_gpio_set(chip, offset, value);
	163	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
3e215d0a	164	tegra_gpio_enable(offset);
3c92db9a EG	165	return 0;
	166	}
	167
438a99c0 SW	168	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	169	{
bdc93a77	170	return irq_find_mapping(irq_domain, offset);
438a99c0	171	}
3c92db9a EG	172
	173	static struct gpio_chip tegra_gpio_chip = {
	174	.label = "tegra-gpio",
3e215d0a SW	175	.request = tegra_gpio_request,
3e215d0a SW	176	.free = tegra_gpio_free,
3c92db9a EG	177	.direction_input = tegra_gpio_direction_input,
	178	.get = tegra_gpio_get,
	179	.direction_output = tegra_gpio_direction_output,
	180	.set = tegra_gpio_set,
438a99c0	181	.to_irq = tegra_gpio_to_irq,
3c92db9a	182	.base = 0,
3c92db9a EG	183	};
3c92db9a EG	184
37337a8d	185	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	186	{
6f74dc9b	187	int gpio = d->hwirq;
3c92db9a	188
88d8951e	189	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	190	}
3c92db9a EG	191
37337a8d	192	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	193	{
6f74dc9b	194	int gpio = d->hwirq;
3c92db9a EG	195
	196	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	197	}
	198
37337a8d	199	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	200	{
6f74dc9b	201	int gpio = d->hwirq;
3c92db9a EG	202
	203	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	204	}
	205
37337a8d	206	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	207	{
6f74dc9b	208	int gpio = d->hwirq;
37337a8d	209	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	210	int port = GPIO_PORT(gpio);
	211	int lvl_type;
	212	int val;
	213	unsigned long flags;
df231f28	214	int ret;
3c92db9a EG	215
	216	switch (type & IRQ_TYPE_SENSE_MASK) {
	217	case IRQ_TYPE_EDGE_RISING:
	218	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	219	break;
	220
	221	case IRQ_TYPE_EDGE_FALLING:
	222	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	223	break;
	224
	225	case IRQ_TYPE_EDGE_BOTH:
	226	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	227	break;
	228
	229	case IRQ_TYPE_LEVEL_HIGH:
	230	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	231	break;
	232
	233	case IRQ_TYPE_LEVEL_LOW:
	234	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	235	break;
	236
	237	default:
	238	return -EINVAL;
	239	}
	240
e3a2e878	241	ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio);
df231f28 SW	242	if (ret) {
	243	dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio);
	244	return ret;
	245	}
	246
3c92db9a EG	247	spin_lock_irqsave(&bank->lvl_lock[port], flags);
3c92db9a EG	248
88d8951e	249	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	250	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	251	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	252	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	253
	254	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	255
d941136f SW	256	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	257	tegra_gpio_enable(gpio);
	258
3c92db9a	259	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
f170d71e	260	irq_set_handler_locked(d, handle_level_irq);
3c92db9a	261	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
f170d71e	262	irq_set_handler_locked(d, handle_edge_irq);
3c92db9a EG	263
	264	return 0;
	265	}
	266
df231f28 SW	267	static void tegra_gpio_irq_shutdown(struct irq_data *d)
	268	{
	269	int gpio = d->hwirq;
	270
e3a2e878	271	gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio);
df231f28 SW	272	}
df231f28 SW	273
bd0b9ac4	274	static void tegra_gpio_irq_handler(struct irq_desc *desc)
3c92db9a	275	{
3c92db9a EG	276	int port;
	277	int pin;
	278	int unmasked = 0;
98022940	279	struct irq_chip *chip = irq_desc_get_chip(desc);
476f8b4c	280	struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
3c92db9a	281
98022940	282	chained_irq_enter(chip, desc);
3c92db9a	283
3c92db9a EG	284	for (port = 0; port < 4; port++) {
3c92db9a EG	285	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	286	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	287	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	288	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	289
3c92db9a EG	290	for_each_set_bit(pin, &sta, 8) {
88d8951e	291	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	292
3c92db9a EG	293	/* if gpio is edge triggered, clear condition
20a8a968	294	* before executing the handler so that we don't
3c92db9a EG	295	* miss edges
	296	*/
	297	if (lvl & (0x100 << pin)) {
	298	unmasked = 1;
98022940	299	chained_irq_exit(chip, desc);
3c92db9a EG	300	}
	301
	302	generic_handle_irq(gpio_to_irq(gpio + pin));
	303	}
	304	}
	305
	306	if (!unmasked)
98022940	307	chained_irq_exit(chip, desc);
3c92db9a EG	308
	309	}
	310
8939ddc7 LD	311	#ifdef CONFIG_PM_SLEEP
8939ddc7 LD	312	static int tegra_gpio_resume(struct device *dev)
2e47b8b3 CC	313	{
2e47b8b3 CC	314	unsigned long flags;
c8309ef6 CC	315	int b;
c8309ef6 CC	316	int p;
2e47b8b3 CC	317
	318	local_irq_save(flags);
	319
3391811c	320	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	321	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	322
	323	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	324	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	325	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	326	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	327	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	328	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	329	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	330	}
	331	}
	332
	333	local_irq_restore(flags);
8939ddc7	334	return 0;
2e47b8b3 CC	335	}
2e47b8b3 CC	336
8939ddc7	337	static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 CC	338	{
2e47b8b3 CC	339	unsigned long flags;
c8309ef6 CC	340	int b;
c8309ef6 CC	341	int p;
2e47b8b3	342
2e47b8b3	343	local_irq_save(flags);
3391811c	344	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	345	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	346
	347	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	348	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	349	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	350	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	351	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	352	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	353	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
203f31cb JL	354
	355	/* Enable gpio irq for wake up source */
	356	tegra_gpio_writel(bank->wake_enb[p],
	357	GPIO_INT_ENB(gpio));
2e47b8b3 CC	358	}
	359	}
	360	local_irq_restore(flags);
8939ddc7	361	return 0;
2e47b8b3 CC	362	}
2e47b8b3 CC	363
203f31cb	364	static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
2e47b8b3	365	{
37337a8d	366	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
203f31cb JL	367	int gpio = d->hwirq;
	368	u32 port, bit, mask;
	369
	370	port = GPIO_PORT(gpio);
	371	bit = GPIO_BIT(gpio);
	372	mask = BIT(bit);
	373
	374	if (enable)
	375	bank->wake_enb[port] \|= mask;
	376	else
	377	bank->wake_enb[port] &= ~mask;
	378
6845664a	379	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	380	}
2e47b8b3 CC	381	#endif
3c92db9a	382
b59d5fb7 SP	383	#ifdef CONFIG_DEBUG_FS
	384
	385	#include <linux/debugfs.h>
	386	#include <linux/seq_file.h>
	387
	388	static int dbg_gpio_show(struct seq_file s, void unused)
	389	{
	390	int i;
	391	int j;
	392
	393	for (i = 0; i < tegra_gpio_bank_count; i++) {
	394	for (j = 0; j < 4; j++) {
	395	int gpio = tegra_gpio_compose(i, j, 0);
	396	seq_printf(s,
	397	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	398	i, j,
	399	tegra_gpio_readl(GPIO_CNF(gpio)),
	400	tegra_gpio_readl(GPIO_OE(gpio)),
	401	tegra_gpio_readl(GPIO_OUT(gpio)),
	402	tegra_gpio_readl(GPIO_IN(gpio)),
	403	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	404	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	405	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
	406	}
	407	}
	408	return 0;
	409	}
	410
	411	static int dbg_gpio_open(struct inode inode, struct file file)
	412	{
	413	return single_open(file, dbg_gpio_show, &inode->i_private);
	414	}
	415
	416	static const struct file_operations debug_fops = {
	417	.open = dbg_gpio_open,
	418	.read = seq_read,
	419	.llseek = seq_lseek,
	420	.release = single_release,
	421	};
	422
	423	static void tegra_gpio_debuginit(void)
	424	{
	425	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	426	NULL, NULL, &debug_fops);
	427	}
	428
	429	#else
	430
	431	static inline void tegra_gpio_debuginit(void)
	432	{
	433	}
	434
	435	#endif
	436
3c92db9a EG	437	static struct irq_chip tegra_gpio_irq_chip = {
3c92db9a EG	438	.name = "GPIO",
37337a8d LB	439	.irq_ack = tegra_gpio_irq_ack,
	440	.irq_mask = tegra_gpio_irq_mask,
	441	.irq_unmask = tegra_gpio_irq_unmask,
	442	.irq_set_type = tegra_gpio_irq_set_type,
df231f28	443	.irq_shutdown = tegra_gpio_irq_shutdown,
8939ddc7	444	#ifdef CONFIG_PM_SLEEP
203f31cb	445	.irq_set_wake = tegra_gpio_irq_set_wake,
2e47b8b3	446	#endif
3c92db9a EG	447	};
3c92db9a EG	448
8939ddc7 LD	449	static const struct dev_pm_ops tegra_gpio_pm_ops = {
	450	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
	451	};
	452
3c92db9a EG	453	/* This lock class tells lockdep that GPIO irqs are in a different
	454	* category than their parents, so it won't report false recursion.
	455	*/
	456	static struct lock_class_key gpio_lock_class;
	457
3836309d	458	static int tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	459	{
171b92c8	460	const struct tegra_gpio_soc_config *config;
88d8951e	461	struct resource *res;
3c92db9a	462	struct tegra_gpio_bank *bank;
f57f98a6	463	int ret;
47008001	464	int gpio;
3c92db9a EG	465	int i;
	466	int j;
	467
df231f28 SW	468	dev = &pdev->dev;
df231f28 SW	469
171b92c8 LD	470	config = of_device_get_match_data(&pdev->dev);
171b92c8 LD	471	if (!config) {
165b6c2f SW	472	dev_err(&pdev->dev, "Error: No device match found\n");
	473	return -ENODEV;
	474	}
5c1e2c9d SW	475
	476	tegra_gpio_bank_stride = config->bank_stride;
	477	tegra_gpio_upper_offset = config->upper_offset;
	478
3391811c SW	479	for (;;) {
	480	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	481	if (!res)
	482	break;
	483	tegra_gpio_bank_count++;
	484	}
	485	if (!tegra_gpio_bank_count) {
	486	dev_err(&pdev->dev, "Missing IRQ resource\n");
	487	return -ENODEV;
	488	}
	489
	490	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	491
	492	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	493	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	494	GFP_KERNEL);
c88a73b3	495	if (!tegra_gpio_banks)
3391811c	496	return -ENODEV;
3391811c	497
d0235677 LW	498	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
d0235677 LW	499	tegra_gpio_chip.ngpio,
bdc93a77	500	&irq_domain_simple_ops, NULL);
d0235677 LW	501	if (!irq_domain)
d0235677 LW	502	return -ENODEV;
6f74dc9b	503
3391811c	504	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	505	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	506	if (!res) {
	507	dev_err(&pdev->dev, "Missing IRQ resource\n");
	508	return -ENODEV;
	509	}
	510
	511	bank = &tegra_gpio_banks[i];
	512	bank->bank = i;
	513	bank->irq = res->start;
	514	}
	515
	516	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641d0342 TR	517	regs = devm_ioremap_resource(&pdev->dev, res);
	518	if (IS_ERR(regs))
	519	return PTR_ERR(regs);
88d8951e	520
4a3398ee	521	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	522	for (j = 0; j < 4; j++) {
3c92db9a EG	523	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	524	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	525	}
	526	}
	527
88d8951e	528	tegra_gpio_chip.of_node = pdev->dev.of_node;
df221227	529
8b4acf3a	530	ret = devm_gpiochip_add_data(&pdev->dev, &tegra_gpio_chip, NULL);
f57f98a6 SW	531	if (ret < 0) {
	532	irq_domain_remove(irq_domain);
	533	return ret;
	534	}
3c92db9a	535
3391811c	536	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
d0235677	537	int irq = irq_create_mapping(irq_domain, gpio);
47008001	538	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	539
47008001	540	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	541
47008001 SW	542	irq_set_lockdep_class(irq, &gpio_lock_class);
	543	irq_set_chip_data(irq, bank);
	544	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	545	handle_simple_irq);
3c92db9a EG	546	}
3c92db9a EG	547
3391811c	548	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	549	bank = &tegra_gpio_banks[i];
3c92db9a EG	550
e88d251d RK	551	irq_set_chained_handler_and_data(bank->irq,
e88d251d RK	552	tegra_gpio_irq_handler, bank);
3c92db9a EG	553
	554	for (j = 0; j < 4; j++)
	555	spin_lock_init(&bank->lvl_lock[j]);
	556	}
	557
b59d5fb7 SP	558	tegra_gpio_debuginit();
b59d5fb7 SP	559
3c92db9a EG	560	return 0;
	561	}
	562
804f5680	563	static const struct tegra_gpio_soc_config tegra20_gpio_config = {
171b92c8 LD	564	.bank_stride = 0x80,
	565	.upper_offset = 0x800,
	566	};
	567
804f5680	568	static const struct tegra_gpio_soc_config tegra30_gpio_config = {
171b92c8 LD	569	.bank_stride = 0x100,
	570	.upper_offset = 0x80,
	571	};
	572
	573	static const struct of_device_id tegra_gpio_of_match[] = {
	574	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	575	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	576	{ },
	577	};
	578
88d8951e SW	579	static struct platform_driver tegra_gpio_driver = {
	580	.driver = {
	581	.name = "tegra-gpio",
8939ddc7	582	.pm = &tegra_gpio_pm_ops,
88d8951e SW	583	.of_match_table = tegra_gpio_of_match,
	584	},
	585	.probe = tegra_gpio_probe,
	586	};
	587
	588	static int __init tegra_gpio_init(void)
	589	{
	590	return platform_driver_register(&tegra_gpio_driver);
	591	}
3c92db9a	592	postcore_initcall(tegra_gpio_init);