[deliverable/linux.git] / drivers / gpio / gpio-wcove.c

/*
 * Intel Whiskey Cove PMIC GPIO Driver
 *
 * This driver is written based on gpio-crystalcove.c
 *
 * Copyright (C) 2016 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>

/*
 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
 * Bank 0: Pin 0 - 6
 * Bank 1: Pin 7 - 10
 * Bank 2: Pin 11 -12
 * Each pin has one output control register and one input control register.
 */
#define BANK0_NR_PINS		7
#define BANK1_NR_PINS		4
#define BANK2_NR_PINS		2
#define WCOVE_GPIO_NUM		(BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
#define WCOVE_VGPIO_NUM		94
/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
#define GPIO_OUT_CTRL_BASE	0x4e44
/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
#define GPIO_IN_CTRL_BASE	0x4e51

/*
 * GPIO interrupts are organized in two groups:
 * Group 0: Bank 0 pins (Pin 0 - 6)
 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
 * Each group has two registers (one bit per pin): status and mask.
 */
#define GROUP0_NR_IRQS		7
#define GROUP1_NR_IRQS		6
#define IRQ_MASK_BASE		0x4e19
#define IRQ_STATUS_BASE		0x4e0b
#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define CTLI_INTCNT_DIS		(0 << 1)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0 << 5)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_MASK		(1 << 4)
#define CTLO_DRV_OD		(0 << 4)
#define CTLO_DRV_CMOS		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDOWN	(0 << 1)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDOWN	(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
};

/*
 * struct wcove_gpio - Whiskey Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @dev: the gpio device
 * @regmap: the regmap from the parent device.
 * @regmap_irq_chip: the regmap of the gpio irq chip.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct wcove_gpio {
	struct mutex buslock;
	struct gpio_chip chip;
	struct device *dev;
	struct regmap *regmap;
	struct regmap_irq_chip_data *regmap_irq_chip;
	int update;
	int intcnt;
	bool set_irq_mask;
};

static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
{
	unsigned int reg;
	int bank;

	if (gpio < BANK0_NR_PINS)
		bank = 0;
	else if (gpio < BANK0_NR_PINS + BANK1_NR_PINS)
		bank = 1;
	else
		bank = 2;

	if (reg_type == CTRL_IN)
		reg = GPIO_IN_CTRL_BASE + bank;
	else
		reg = GPIO_OUT_CTRL_BASE + bank;

	return reg;
}

static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
{
	unsigned int reg, mask;

	if (gpio < GROUP0_NR_IRQS) {
		reg = IRQ_MASK_BASE;
		mask = BIT(gpio % GROUP0_NR_IRQS);
	} else {
		reg = IRQ_MASK_BASE + 1;
		mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
	}

	if (wg->set_irq_mask)
		regmap_update_bits(wg->regmap, reg, mask, mask);
	else
		regmap_update_bits(wg->regmap, reg, mask, 0);
}

static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
{
	unsigned int reg = to_reg(gpio, CTRL_IN);

	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
}

static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
			    CTLO_INPUT_SET);
}

static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
				    int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
			    CTLO_OUTPUT_SET | value);
}

static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &val);
	if (ret)
		return ret;

	return !(val & CTLO_DIR_OUT);
}

static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void wcove_gpio_set(struct gpio_chip *chip,
				 unsigned int gpio, int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (value)
		regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
	else
		regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
}

static int wcove_gpio_set_single_ended(struct gpio_chip *chip,
					unsigned int gpio,
					enum single_ended_mode mode)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	switch (mode) {
	case LINE_MODE_OPEN_DRAIN:
		return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
						CTLO_DRV_MASK, CTLO_DRV_OD);
	case LINE_MODE_PUSH_PULL:
		return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
						CTLO_DRV_MASK, CTLO_DRV_CMOS);
	default:
		break;
	}

	return -ENOTSUPP;
}

static int wcove_irq_type(struct irq_data *data, unsigned int type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	switch (type) {
	case IRQ_TYPE_NONE:
		wg->intcnt = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		wg->intcnt = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		wg->intcnt = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		wg->intcnt = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	wg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void wcove_bus_lock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	mutex_lock(&wg->buslock);
}

static void wcove_bus_sync_unlock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio = data->hwirq;

	if (wg->update & UPDATE_IRQ_TYPE)
		wcove_update_irq_ctrl(wg, gpio);
	if (wg->update & UPDATE_IRQ_MASK)
		wcove_update_irq_mask(wg, gpio);
	wg->update = 0;

	mutex_unlock(&wg->buslock);
}

static void wcove_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	wg->set_irq_mask = false;
	wg->update |= UPDATE_IRQ_MASK;
}

static void wcove_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	wg->set_irq_mask = true;
	wg->update |= UPDATE_IRQ_MASK;
}

static struct irq_chip wcove_irqchip = {
	.name			= "Whiskey Cove",
	.irq_mask		= wcove_irq_mask,
	.irq_unmask		= wcove_irq_unmask,
	.irq_set_type		= wcove_irq_type,
	.irq_bus_lock		= wcove_bus_lock,
	.irq_bus_sync_unlock	= wcove_bus_sync_unlock,
};

static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
{
	struct wcove_gpio *wg = (struct wcove_gpio *)data;
	unsigned int pending, virq, gpio, mask, offset;
	u8 p[2];

	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
		dev_err(wg->dev, "Failed to read irq status register\n");
		return IRQ_NONE;
	}

	pending = p[0] | (p[1] << 8);
	if (!pending)
		return IRQ_NONE;

	/* Iterate until no interrupt is pending */
	while (pending) {
		/* One iteration is for all pending bits */
		for_each_set_bit(gpio, (const unsigned long *)&pending,
						 GROUP0_NR_IRQS) {
			offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
			mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
								BIT(gpio);
			virq = irq_find_mapping(wg->chip.irqdomain, gpio);
			handle_nested_irq(virq);
			regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
								mask, mask);
		}

		/* Next iteration */
		if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
			dev_err(wg->dev, "Failed to read irq status\n");
			break;
		}

		pending = p[0] | (p[1] << 8);
	}

	return IRQ_HANDLED;
}

static void wcove_gpio_dbg_show(struct seq_file *s,
				      struct gpio_chip *chip)
{
	unsigned int ctlo, ctli, irq_mask, irq_status;
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio, offset, group, ret = 0;

	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
		group = gpio < GROUP0_NR_IRQS ? 0 : 1;
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
							&irq_mask);
		ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
							&irq_status);
		if (ret) {
			pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
			break;
		}

		offset = gpio % 8;
		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   irq_mask & BIT(offset) ? "mask  " : "unmask",
			   irq_status & BIT(offset) ? "pending" : "       ");
	}
}

static int wcove_gpio_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic;
	struct wcove_gpio *wg;
	int virq, ret, irq;
	struct device *dev;

	/*
	 * This gpio platform device is created by a mfd device (see
	 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	 * shared by all sub-devices created by the mfd device, the regmap
	 * pointer for instance, is stored as driver data of the mfd device
	 * driver.
	 */
	pmic = dev_get_drvdata(pdev->dev.parent);
	if (!pmic)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	dev = &pdev->dev;

	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	if (!wg)
		return -ENOMEM;

	wg->regmap_irq_chip = pmic->irq_chip_data_level2;

	platform_set_drvdata(pdev, wg);

	mutex_init(&wg->buslock);
	wg->chip.label = KBUILD_MODNAME;
	wg->chip.direction_input = wcove_gpio_dir_in;
	wg->chip.direction_output = wcove_gpio_dir_out;
	wg->chip.get_direction = wcove_gpio_get_direction;
	wg->chip.get = wcove_gpio_get;
	wg->chip.set = wcove_gpio_set;
	wg->chip.set_single_ended = wcove_gpio_set_single_ended,
	wg->chip.base = -1;
	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	wg->chip.can_sleep = true;
	wg->chip.parent = pdev->dev.parent;
	wg->chip.dbg_show = wcove_gpio_dbg_show;
	wg->dev = dev;
	wg->regmap = pmic->regmap;

	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	if (ret) {
		dev_err(dev, "Failed to add gpiochip: %d\n", ret);
		return ret;
	}

	ret = gpiochip_irqchip_add(&wg->chip, &wcove_irqchip, 0,
			     handle_simple_irq, IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "Failed to add irqchip: %d\n", ret);
		return ret;
	}

	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	if (virq < 0) {
		dev_err(dev, "Failed to get virq by irq %d\n", irq);
		return virq;
	}

	ret = devm_request_threaded_irq(dev, virq, NULL,
		wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
	if (ret) {
		dev_err(dev, "Failed to request irq %d\n", virq);
		return ret;
	}

	return 0;
}

/*
 * Whiskey Cove PMIC itself is a analog device(but with digital control
 * interface) providing power management support for other devices in
 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
 */
static struct platform_driver wcove_gpio_driver = {
	.driver = {
		.name = "bxt_wcove_gpio",
	},
	.probe = wcove_gpio_probe,
};

module_platform_driver(wcove_gpio_driver);

MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:bxt_wcove_gpio");
Commit	Line	Data
0ba19cfc BG	1	/*
	2	* Intel Whiskey Cove PMIC GPIO Driver
	3	*
	4	* This driver is written based on gpio-crystalcove.c
	5	*
	6	* Copyright (C) 2016 Intel Corporation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License version
	10	* 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/bitops.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/gpio/driver.h>
	21	#include <linux/mfd/intel_soc_pmic.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/seq_file.h>
	25
	26	/*
	27	* Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
	28	* Bank 0: Pin 0 - 6
	29	* Bank 1: Pin 7 - 10
	30	* Bank 2: Pin 11 -12
	31	* Each pin has one output control register and one input control register.
	32	*/
	33	#define BANK0_NR_PINS 7
	34	#define BANK1_NR_PINS 4
	35	#define BANK2_NR_PINS 2
	36	#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
	37	#define WCOVE_VGPIO_NUM 94
	38	/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
	39	#define GPIO_OUT_CTRL_BASE 0x4e44
	40	/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
	41	#define GPIO_IN_CTRL_BASE 0x4e51
	42
	43	/*
	44	* GPIO interrupts are organized in two groups:
	45	* Group 0: Bank 0 pins (Pin 0 - 6)
	46	* Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
	47	* Each group has two registers (one bit per pin): status and mask.
	48	*/
	49	#define GROUP0_NR_IRQS 7
	50	#define GROUP1_NR_IRQS 6
	51	#define IRQ_MASK_BASE 0x4e19
	52	#define IRQ_STATUS_BASE 0x4e0b
	53	#define UPDATE_IRQ_TYPE BIT(0)
	54	#define UPDATE_IRQ_MASK BIT(1)
	55
	56	#define CTLI_INTCNT_DIS (0 << 1)
	57	#define CTLI_INTCNT_NE (1 << 1)
	58	#define CTLI_INTCNT_PE (2 << 1)
	59	#define CTLI_INTCNT_BE (3 << 1)
	60
	61	#define CTLO_DIR_IN (0 << 5)
	62	#define CTLO_DIR_OUT (1 << 5)
	63
	64	#define CTLO_DRV_MASK (1 << 4)
65	#define CTLO_DRV_OD (0 << 4)
66	#define CTLO_DRV_CMOS (1 << 4)
67
68	#define CTLO_DRV_REN (1 << 3)
69
70	#define CTLO_RVAL_2KDOWN (0 << 1)
71	#define CTLO_RVAL_2KUP (1 << 1)
72	#define CTLO_RVAL_50KDOWN (2 << 1)
73	#define CTLO_RVAL_50KUP (3 << 1)
74
75	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
76	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
77
78	enum ctrl_register {
79	CTRL_IN,
80	CTRL_OUT,
81	};
82
83	/*
84	* struct wcove_gpio - Whiskey Cove GPIO controller
85	* @buslock: for bus lock/sync and unlock.
86	* @chip: the abstract gpio_chip structure.
87	* @dev: the gpio device
88	* @regmap: the regmap from the parent device.
89	* @regmap_irq_chip: the regmap of the gpio irq chip.
90	* @update: pending IRQ setting update, to be written to the chip upon unlock.
91	* @intcnt: the Interrupt Detect value to be written.
92	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
93	*/
94	struct wcove_gpio {
95	struct mutex buslock;
96	struct gpio_chip chip;
97	struct device *dev;
98	struct regmap *regmap;
99	struct regmap_irq_chip_data *regmap_irq_chip;
100	int update;
101	int intcnt;
102	bool set_irq_mask;
103	};
104
105	static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
106	{
107	unsigned int reg;
108	int bank;
109
110	if (gpio < BANK0_NR_PINS)
111	bank = 0;
112	else if (gpio < BANK0_NR_PINS + BANK1_NR_PINS)
113	bank = 1;
114	else
115	bank = 2;
116
117	if (reg_type == CTRL_IN)
118	reg = GPIO_IN_CTRL_BASE + bank;
119	else
120	reg = GPIO_OUT_CTRL_BASE + bank;
121
122	return reg;
123	}
124
125	static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
126	{
127	unsigned int reg, mask;
128
129	if (gpio < GROUP0_NR_IRQS) {
130	reg = IRQ_MASK_BASE;
131	mask = BIT(gpio % GROUP0_NR_IRQS);
132	} else {
133	reg = IRQ_MASK_BASE + 1;
134	mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
135	}
136
137	if (wg->set_irq_mask)
138	regmap_update_bits(wg->regmap, reg, mask, mask);
139	else
140	regmap_update_bits(wg->regmap, reg, mask, 0);
141	}
142
143	static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
144	{
145	unsigned int reg = to_reg(gpio, CTRL_IN);
146
147	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
148	}
149
150	static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
151	{
152	struct wcove_gpio *wg = gpiochip_get_data(chip);
153
154	return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
155	CTLO_INPUT_SET);
156	}
157
158	static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
159	int value)
160	{
161	struct wcove_gpio *wg = gpiochip_get_data(chip);
162
163	return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
164	CTLO_OUTPUT_SET \| value);
165	}
166
7d9e59ce BG	167	static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
	168	{
	169	struct wcove_gpio *wg = gpiochip_get_data(chip);
	170	unsigned int val;
	171	int ret;
	172
	173	ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &val);
	174	if (ret)
	175	return ret;
	176
	177	return !(val & CTLO_DIR_OUT);
	178	}
	179
0ba19cfc BG	180	static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
	181	{
	182	struct wcove_gpio *wg = gpiochip_get_data(chip);
	183	unsigned int val;
	184	int ret;
	185
	186	ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &val);
	187	if (ret)
	188	return ret;
	189
	190	return val & 0x1;
	191	}
	192
	193	static void wcove_gpio_set(struct gpio_chip *chip,
	194	unsigned int gpio, int value)
	195	{
	196	struct wcove_gpio *wg = gpiochip_get_data(chip);
	197
	198	if (value)
	199	regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
	200	else
	201	regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
	202	}
	203
	204	static int wcove_gpio_set_single_ended(struct gpio_chip *chip,
	205	unsigned int gpio,
	206	enum single_ended_mode mode)
	207	{
	208	struct wcove_gpio *wg = gpiochip_get_data(chip);
	209
	210	switch (mode) {
	211	case LINE_MODE_OPEN_DRAIN:
	212	return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
	213	CTLO_DRV_MASK, CTLO_DRV_OD);
	214	case LINE_MODE_PUSH_PULL:
	215	return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
	216	CTLO_DRV_MASK, CTLO_DRV_CMOS);
	217	default:
	218	break;
	219	}
	220
	221	return -ENOTSUPP;
	222	}
	223
	224	static int wcove_irq_type(struct irq_data *data, unsigned int type)
	225	{
	226	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	227	struct wcove_gpio *wg = gpiochip_get_data(chip);
	228
	229	switch (type) {
	230	case IRQ_TYPE_NONE:
	231	wg->intcnt = CTLI_INTCNT_DIS;
	232	break;
	233	case IRQ_TYPE_EDGE_BOTH:
	234	wg->intcnt = CTLI_INTCNT_BE;
	235	break;
	236	case IRQ_TYPE_EDGE_RISING:
	237	wg->intcnt = CTLI_INTCNT_PE;
	238	break;
	239	case IRQ_TYPE_EDGE_FALLING:
	240	wg->intcnt = CTLI_INTCNT_NE;
	241	break;
	242	default:
	243	return -EINVAL;
244	}
245
246	wg->update \|= UPDATE_IRQ_TYPE;
247
248	return 0;
249	}
250
251	static void wcove_bus_lock(struct irq_data *data)
252	{
253	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
254	struct wcove_gpio *wg = gpiochip_get_data(chip);
255
256	mutex_lock(&wg->buslock);
257	}
258
259	static void wcove_bus_sync_unlock(struct irq_data *data)
260	{
261	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
262	struct wcove_gpio *wg = gpiochip_get_data(chip);
263	int gpio = data->hwirq;
264
265	if (wg->update & UPDATE_IRQ_TYPE)
266	wcove_update_irq_ctrl(wg, gpio);
267	if (wg->update & UPDATE_IRQ_MASK)
268	wcove_update_irq_mask(wg, gpio);
269	wg->update = 0;
270
271	mutex_unlock(&wg->buslock);
272	}
273
274	static void wcove_irq_unmask(struct irq_data *data)
275	{
276	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
277	struct wcove_gpio *wg = gpiochip_get_data(chip);
278
279	wg->set_irq_mask = false;
280	wg->update \|= UPDATE_IRQ_MASK;
281	}
282
283	static void wcove_irq_mask(struct irq_data *data)
284	{
285	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
286	struct wcove_gpio *wg = gpiochip_get_data(chip);
287
288	wg->set_irq_mask = true;
289	wg->update \|= UPDATE_IRQ_MASK;
290	}
291
292	static struct irq_chip wcove_irqchip = {
293	.name = "Whiskey Cove",
294	.irq_mask = wcove_irq_mask,
295	.irq_unmask = wcove_irq_unmask,
296	.irq_set_type = wcove_irq_type,
297	.irq_bus_lock = wcove_bus_lock,
298	.irq_bus_sync_unlock = wcove_bus_sync_unlock,
299	};
300
301	static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
302	{
303	struct wcove_gpio wg = (struct wcove_gpio )data;
304	unsigned int pending, virq, gpio, mask, offset;
305	u8 p[2];
306
307	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
308	dev_err(wg->dev, "Failed to read irq status register\n");
309	return IRQ_NONE;
310	}
311
312	pending = p[0] \| (p[1] << 8);
313	if (!pending)
314	return IRQ_NONE;
315
316	/* Iterate until no interrupt is pending */
317	while (pending) {
318	/* One iteration is for all pending bits */
319	for_each_set_bit(gpio, (const unsigned long *)&pending,
320	GROUP0_NR_IRQS) {
321	offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
322	mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
323	BIT(gpio);
324	virq = irq_find_mapping(wg->chip.irqdomain, gpio);
325	handle_nested_irq(virq);
326	regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
327	mask, mask);
328	}
329
330	/* Next iteration */
331	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
332	dev_err(wg->dev, "Failed to read irq status\n");
333	break;
334	}
335
336	pending = p[0] \| (p[1] << 8);
337	}
338
339	return IRQ_HANDLED;
340	}
341
342	static void wcove_gpio_dbg_show(struct seq_file *s,
343	struct gpio_chip *chip)
344	{
345	unsigned int ctlo, ctli, irq_mask, irq_status;
346	struct wcove_gpio *wg = gpiochip_get_data(chip);
347	int gpio, offset, group, ret = 0;
348
349	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
350	group = gpio < GROUP0_NR_IRQS ? 0 : 1;
351	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
352	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
353	ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
354	&irq_mask);
355	ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
356	&irq_status);
357	if (ret) {
358	pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
359	break;
360	}
361
362	offset = gpio % 8;
363	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
364	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
365	ctli & 0x1 ? "hi" : "lo",
366	ctli & CTLI_INTCNT_NE ? "fall" : " ",
367	ctli & CTLI_INTCNT_PE ? "rise" : " ",
368	ctlo,
369	irq_mask & BIT(offset) ? "mask " : "unmask",
370	irq_status & BIT(offset) ? "pending" : " ");
371	}
372	}
373
374	static int wcove_gpio_probe(struct platform_device *pdev)
375	{
376	struct intel_soc_pmic *pmic;
377	struct wcove_gpio *wg;
378	int virq, ret, irq;
379	struct device *dev;
380
381	/*
382	* This gpio platform device is created by a mfd device (see
383	* drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
384	* shared by all sub-devices created by the mfd device, the regmap
385	* pointer for instance, is stored as driver data of the mfd device
386	* driver.
387	*/
388	pmic = dev_get_drvdata(pdev->dev.parent);
389	if (!pmic)
390	return -ENODEV;
391
392	irq = platform_get_irq(pdev, 0);
393	if (irq < 0)
394	return irq;
395
396	dev = &pdev->dev;
397
398	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
399	if (!wg)
400	return -ENOMEM;
401
402	wg->regmap_irq_chip = pmic->irq_chip_data_level2;
403
404	platform_set_drvdata(pdev, wg);
405
406	mutex_init(&wg->buslock);
407	wg->chip.label = KBUILD_MODNAME;
408	wg->chip.direction_input = wcove_gpio_dir_in;
409	wg->chip.direction_output = wcove_gpio_dir_out;
7d9e59ce	410	wg->chip.get_direction = wcove_gpio_get_direction;
0ba19cfc BG	411	wg->chip.get = wcove_gpio_get;
	412	wg->chip.set = wcove_gpio_set;
	413	wg->chip.set_single_ended = wcove_gpio_set_single_ended,
	414	wg->chip.base = -1;
	415	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	416	wg->chip.can_sleep = true;
	417	wg->chip.parent = pdev->dev.parent;
	418	wg->chip.dbg_show = wcove_gpio_dbg_show;
	419	wg->dev = dev;
	420	wg->regmap = pmic->regmap;
	421
	422	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	423	if (ret) {
	424	dev_err(dev, "Failed to add gpiochip: %d\n", ret);
	425	return ret;
	426	}
	427
	428	ret = gpiochip_irqchip_add(&wg->chip, &wcove_irqchip, 0,
	429	handle_simple_irq, IRQ_TYPE_NONE);
	430	if (ret) {
	431	dev_err(dev, "Failed to add irqchip: %d\n", ret);
	432	return ret;
	433	}
	434
	435	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	436	if (virq < 0) {
	437	dev_err(dev, "Failed to get virq by irq %d\n", irq);
	438	return virq;
	439	}
	440
	441	ret = devm_request_threaded_irq(dev, virq, NULL,
	442	wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
	443	if (ret) {
	444	dev_err(dev, "Failed to request irq %d\n", virq);
	445	return ret;
	446	}
	447
	448	return 0;
	449	}
	450
	451	/*
	452	* Whiskey Cove PMIC itself is a analog device(but with digital control
	453	* interface) providing power management support for other devices in
	454	* the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
	455	*/
	456	static struct platform_driver wcove_gpio_driver = {
	457	.driver = {
	458	.name = "bxt_wcove_gpio",
	459	},
	460	.probe = wcove_gpio_probe,
	461	};
	462
	463	module_platform_driver(wcove_gpio_driver);
	464
	465	MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
	466	MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
	467	MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
	468	MODULE_LICENSE("GPL v2");
	469	MODULE_ALIAS("platform:bxt_wcove_gpio");