projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gpio: zynq: Take bank offset into account when reporting a IRQ
[deliverable/linux.git] / drivers / gpio / gpio-zynq.c
CommitLineData
3242ba11
HK		 1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21
22#define DRIVER_NAME "zynq-gpio"
23
24/* Maximum banks */
25#define ZYNQ_GPIO_MAX_BANK 4
26
27#define ZYNQ_GPIO_BANK0_NGPIO 32
28#define ZYNQ_GPIO_BANK1_NGPIO 22
29#define ZYNQ_GPIO_BANK2_NGPIO 32
30#define ZYNQ_GPIO_BANK3_NGPIO 32
31
32#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
33 ZYNQ_GPIO_BANK1_NGPIO + \
34 ZYNQ_GPIO_BANK2_NGPIO + \
35 ZYNQ_GPIO_BANK3_NGPIO)
36
37#define ZYNQ_GPIO_BANK0_PIN_MIN 0
38#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
39 ZYNQ_GPIO_BANK0_NGPIO - 1)
40#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
41#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
42 ZYNQ_GPIO_BANK1_NGPIO - 1)
43#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
44#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
45 ZYNQ_GPIO_BANK2_NGPIO - 1)
46#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
47#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
48 ZYNQ_GPIO_BANK3_NGPIO - 1)
49
50
51/* Register offsets for the GPIO device */
52/* LSW Mask & Data -WO */
53#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
54/* MSW Mask & Data -WO */
55#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
56/* Data Register-RW */
57#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
58/* Direction mode reg-RW */
59#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
60/* Output enable reg-RW */
61#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
62/* Interrupt mask reg-RO */
63#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
64/* Interrupt enable reg-WO */
65#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
66/* Interrupt disable reg-WO */
67#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
68/* Interrupt status reg-RO */
69#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
70/* Interrupt type reg-RW */
71#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
72/* Interrupt polarity reg-RW */
73#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
74/* Interrupt on any, reg-RW */
75#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
76
77/* Disable all interrupts mask */
78#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
79
80/* Mid pin number of a bank */
81#define ZYNQ_GPIO_MID_PIN_NUM 16
82
83/* GPIO upper 16 bit mask */
84#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
85
86/**
87 * struct zynq_gpio - gpio device private data structure
88 * @chip: instance of the gpio_chip
89 * @base_addr: base address of the GPIO device
90 * @clk: clock resource for this controller
91 */
92struct zynq_gpio {
93 struct gpio_chip chip;
94 void __iomem *base_addr;
95 struct clk *clk;
96};
97
6dd85950
LPC		 98static struct irq_chip zynq_gpio_level_irqchip;
99static struct irq_chip zynq_gpio_edge_irqchip;
100
3242ba11
HK		 101/**
102 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
103 * for a given pin in the GPIO device
104 * @pin_num: gpio pin number within the device
105 * @bank_num: an output parameter used to return the bank number of the gpio
106 * pin
107 * @bank_pin_num: an output parameter used to return pin number within a bank
108 * for the given gpio pin
109 *
110 * Returns the bank number and pin offset within the bank.
111 */
112static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
113 unsigned int *bank_num,
114 unsigned int *bank_pin_num)
115{
116 switch (pin_num) {
117 case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
118 *bank_num = 0;
119 *bank_pin_num = pin_num;
120 break;
121 case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
122 *bank_num = 1;
123 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
124 break;
125 case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
126 *bank_num = 2;
127 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
128 break;
129 case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
130 *bank_num = 3;
131 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
132 break;
133 default:
134 WARN(true, "invalid GPIO pin number: %u", pin_num);
135 *bank_num = 0;
136 *bank_pin_num = 0;
137 break;
138 }
139}
140
016da144
LPC		 141static const unsigned int zynq_gpio_bank_offset[] = {
142 ZYNQ_GPIO_BANK0_PIN_MIN,
143 ZYNQ_GPIO_BANK1_PIN_MIN,
144 ZYNQ_GPIO_BANK2_PIN_MIN,
145 ZYNQ_GPIO_BANK3_PIN_MIN,
146};
147
3242ba11
HK		 148/**
149 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
150 * @chip: gpio_chip instance to be worked on
151 * @pin: gpio pin number within the device
152 *
153 * This function reads the state of the specified pin of the GPIO device.
154 *
155 * Return: 0 if the pin is low, 1 if pin is high.
156 */
157static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
158{
159 u32 data;
160 unsigned int bank_num, bank_pin_num;
161 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
162
163 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
164
165 data = readl_relaxed(gpio->base_addr +
166 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
167
168 return (data >> bank_pin_num) & 1;
169}
170
171/**
172 * zynq_gpio_set_value - Modify the state of the pin with specified value
173 * @chip: gpio_chip instance to be worked on
174 * @pin: gpio pin number within the device
175 * @state: value used to modify the state of the specified pin
176 *
177 * This function calculates the register offset (i.e to lower 16 bits or
178 * upper 16 bits) based on the given pin number and sets the state of a
179 * gpio pin to the specified value. The state is either 0 or non-zero.
180 */
181static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
182 int state)
183{
184 unsigned int reg_offset, bank_num, bank_pin_num;
185 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
186
187 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
188
189 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
190 /* only 16 data bits in bit maskable reg */
191 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
192 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
193 } else {
194 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
195 }
196
197 /*
198 * get the 32 bit value to be written to the mask/data register where
199 * the upper 16 bits is the mask and lower 16 bits is the data
200 */
201 state = !!state;
202 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
203 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
204
205 writel_relaxed(state, gpio->base_addr + reg_offset);
206}
207
208/**
209 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
210 * @chip: gpio_chip instance to be worked on
211 * @pin: gpio pin number within the device
212 *
213 * This function uses the read-modify-write sequence to set the direction of
214 * the gpio pin as input.
215 *
216 * Return: 0 always
217 */
218static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
219{
220 u32 reg;
221 unsigned int bank_num, bank_pin_num;
222 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
223
224 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
225
226 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
227 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
228 return -EINVAL;
229
230 /* clear the bit in direction mode reg to set the pin as input */
231 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
232 reg &= ~BIT(bank_pin_num);
233 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
234
235 return 0;
236}
237
238/**
239 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
240 * @chip: gpio_chip instance to be worked on
241 * @pin: gpio pin number within the device
242 * @state: value to be written to specified pin
243 *
244 * This function sets the direction of specified GPIO pin as output, configures
245 * the Output Enable register for the pin and uses zynq_gpio_set to set
246 * the state of the pin to the value specified.
247 *
248 * Return: 0 always
249 */
250static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
251 int state)
252{
253 u32 reg;
254 unsigned int bank_num, bank_pin_num;
255 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
256
257 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
258
259 /* set the GPIO pin as output */
260 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
261 reg |= BIT(bank_pin_num);
262 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
263
264 /* configure the output enable reg for the pin */
265 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
266 reg |= BIT(bank_pin_num);
267 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
268
269 /* set the state of the pin */
270 zynq_gpio_set_value(chip, pin, state);
271 return 0;
272}
273
274/**
275 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
276 * @irq_data: per irq and chip data passed down to chip functions
277 *
278 * This function calculates gpio pin number from irq number and sets the
279 * bit in the Interrupt Disable register of the corresponding bank to disable
280 * interrupts for that pin.
281 */
282static void zynq_gpio_irq_mask(struct irq_data *irq_data)
283{
284 unsigned int device_pin_num, bank_num, bank_pin_num;
285 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
286
287 device_pin_num = irq_data->hwirq;
288 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
289 writel_relaxed(BIT(bank_pin_num),
290 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
291}
292
293/**
294 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
295 * @irq_data: irq data containing irq number of gpio pin for the interrupt
296 * to enable
297 *
298 * This function calculates the gpio pin number from irq number and sets the
299 * bit in the Interrupt Enable register of the corresponding bank to enable
300 * interrupts for that pin.
301 */
302static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
303{
304 unsigned int device_pin_num, bank_num, bank_pin_num;
305 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
306
307 device_pin_num = irq_data->hwirq;
308 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
309 writel_relaxed(BIT(bank_pin_num),
310 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
311}
312
190dc2e6
LPC		 313/**
314 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
315 * @irq_data: irq data containing irq number of gpio pin for the interrupt
316 * to ack
317 *
318 * This function calculates gpio pin number from irq number and sets the bit
319 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
320 */
321static void zynq_gpio_irq_ack(struct irq_data *irq_data)
322{
323 unsigned int device_pin_num, bank_num, bank_pin_num;
324 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
325
326 device_pin_num = irq_data->hwirq;
327 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
328 writel_relaxed(BIT(bank_pin_num),
329 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
330}
331
332/**
333 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
334 * @irq_data: irq data containing irq number of gpio pin for the interrupt
335 * to enable
336 *
337 * Clears the INTSTS bit and unmasks the given interrrupt.
338 */
339static void zynq_gpio_irq_enable(struct irq_data *irq_data)
340{
341 /*
342 * The Zynq GPIO controller does not disable interrupt detection when
343 * the interrupt is masked and only disables the propagation of the
344 * interrupt. This means when the controller detects an interrupt
345 * condition while the interrupt is logically disabled it will propagate
346 * that interrupt event once the interrupt is enabled. This will cause
347 * the interrupt consumer to see spurious interrupts to prevent this
348 * first make sure that the interrupt is not asserted and then enable
349 * it.
350 */
351 zynq_gpio_irq_ack(irq_data);
352 zynq_gpio_irq_unmask(irq_data);
353}
354
3242ba11
HK		 355/**
356 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
357 * @irq_data: irq data containing irq number of gpio pin
358 * @type: interrupt type that is to be set for the gpio pin
359 *
360 * This function gets the gpio pin number and its bank from the gpio pin number
361 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
362 *
363 * Return: 0, negative error otherwise.
364 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
365 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
366 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
367 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
368 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
369 */
370static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
371{
372 u32 int_type, int_pol, int_any;
373 unsigned int device_pin_num, bank_num, bank_pin_num;
374 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
375
376 device_pin_num = irq_data->hwirq;
377 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
378
379 int_type = readl_relaxed(gpio->base_addr +
380 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
381 int_pol = readl_relaxed(gpio->base_addr +
382 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
383 int_any = readl_relaxed(gpio->base_addr +
384 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
385
386 /*
387 * based on the type requested, configure the INT_TYPE, INT_POLARITY
388 * and INT_ANY registers
389 */
390 switch (type) {
391 case IRQ_TYPE_EDGE_RISING:
392 int_type |= BIT(bank_pin_num);
393 int_pol |= BIT(bank_pin_num);
394 int_any &= ~BIT(bank_pin_num);
395 break;
396 case IRQ_TYPE_EDGE_FALLING:
397 int_type |= BIT(bank_pin_num);
398 int_pol &= ~BIT(bank_pin_num);
399 int_any &= ~BIT(bank_pin_num);
400 break;
401 case IRQ_TYPE_EDGE_BOTH:
402 int_type |= BIT(bank_pin_num);
403 int_any |= BIT(bank_pin_num);
404 break;
405 case IRQ_TYPE_LEVEL_HIGH:
406 int_type &= ~BIT(bank_pin_num);
407 int_pol |= BIT(bank_pin_num);
408 break;
409 case IRQ_TYPE_LEVEL_LOW:
410 int_type &= ~BIT(bank_pin_num);
411 int_pol &= ~BIT(bank_pin_num);
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 writel_relaxed(int_type,
418 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
419 writel_relaxed(int_pol,
420 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
421 writel_relaxed(int_any,
422 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
6dd85950
LPC		 423
424 if (type & IRQ_TYPE_LEVEL_MASK) {
425 __irq_set_chip_handler_name_locked(irq_data->irq,
426 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
427 } else {
428 __irq_set_chip_handler_name_locked(irq_data->irq,
429 &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
430 }
431
3242ba11
HK		 432 return 0;
433}
434
435static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
436{
437 if (on)
438 zynq_gpio_irq_unmask(data);
439 else
440 zynq_gpio_irq_mask(data);
441
442 return 0;
443}
444
445/* irq chip descriptor */
6dd85950 446static struct irq_chip zynq_gpio_level_irqchip = {
3242ba11 447 .name = DRIVER_NAME,
190dc2e6 448 .irq_enable = zynq_gpio_irq_enable,
6dd85950
LPC		 449 .irq_eoi = zynq_gpio_irq_ack,
450 .irq_mask = zynq_gpio_irq_mask,
451 .irq_unmask = zynq_gpio_irq_unmask,
452 .irq_set_type = zynq_gpio_set_irq_type,
453 .irq_set_wake = zynq_gpio_set_wake,
454 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
455};
456
457static struct irq_chip zynq_gpio_edge_irqchip = {
458 .name = DRIVER_NAME,
459 .irq_enable = zynq_gpio_irq_enable,
460 .irq_ack = zynq_gpio_irq_ack,
3242ba11
HK		 461 .irq_mask = zynq_gpio_irq_mask,
462 .irq_unmask = zynq_gpio_irq_unmask,
463 .irq_set_type = zynq_gpio_set_irq_type,
464 .irq_set_wake = zynq_gpio_set_wake,
465};
466
5a2533a7
LPC		 467static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
468 unsigned int bank_num,
469 unsigned long pending)
470{
016da144 471 unsigned int bank_offset = zynq_gpio_bank_offset[bank_num];
5a2533a7
LPC		 472 struct irq_domain *irqdomain = gpio->chip.irqdomain;
473 int offset;
474
475 if (!pending)
476 return;
477
478 for_each_set_bit(offset, &pending, 32) {
479 unsigned int gpio_irq;
480
016da144 481 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
5a2533a7
LPC		 482 generic_handle_irq(gpio_irq);
483 }
484}
485
3242ba11
HK		 486/**
487 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
488 * @irq: irq number of the gpio bank where interrupt has occurred
489 * @desc: irq descriptor instance of the 'irq'
490 *
491 * This function reads the Interrupt Status Register of each bank to get the
492 * gpio pin number which has triggered an interrupt. It then acks the triggered
493 * interrupt and calls the pin specific handler set by the higher layer
494 * application for that pin.
495 * Note: A bug is reported if no handler is set for the gpio pin.
496 */
497static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
498{
499 u32 int_sts, int_enb;
500 unsigned int bank_num;
501 struct zynq_gpio *gpio = irq_get_handler_data(irq);
502 struct irq_chip *irqchip = irq_desc_get_chip(desc);
503
504 chained_irq_enter(irqchip, desc);
505
506 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) {
507 int_sts = readl_relaxed(gpio->base_addr +
508 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
509 int_enb = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
5a2533a7 511 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
3242ba11
HK		 512 }
513
514 chained_irq_exit(irqchip, desc);
515}
516
517static int __maybe_unused zynq_gpio_suspend(struct device *dev)
518{
519 if (!device_may_wakeup(dev))
520 return pm_runtime_force_suspend(dev);
521
522 return 0;
523}
524
525static int __maybe_unused zynq_gpio_resume(struct device *dev)
526{
527 if (!device_may_wakeup(dev))
528 return pm_runtime_force_resume(dev);
529
530 return 0;
531}
532
533static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
534{
535 struct platform_device *pdev = to_platform_device(dev);
536 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
537
538 clk_disable_unprepare(gpio->clk);
539
540 return 0;
541}
542
543static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
544{
545 struct platform_device *pdev = to_platform_device(dev);
546 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
547
548 return clk_prepare_enable(gpio->clk);
549}
550
551static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
552{
553 int ret;
554
555 ret = pm_runtime_get_sync(chip->dev);
556
557 /*
558 * If the device is already active pm_runtime_get() will return 1 on
559 * success, but gpio_request still needs to return 0.
560 */
561 return ret < 0 ? ret : 0;
562}
563
564static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
565{
566 pm_runtime_put(chip->dev);
567}
568
569static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
570 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
571 SET_PM_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
572 zynq_gpio_runtime_resume, NULL)
573};
574
575/**
576 * zynq_gpio_probe - Initialization method for a zynq_gpio device
577 * @pdev: platform device instance
578 *
579 * This function allocates memory resources for the gpio device and registers
580 * all the banks of the device. It will also set up interrupts for the gpio
581 * pins.
582 * Note: Interrupts are disabled for all the banks during initialization.
583 *
584 * Return: 0 on success, negative error otherwise.
585 */
586static int zynq_gpio_probe(struct platform_device *pdev)
587{
588 int ret, bank_num, irq;
589 struct zynq_gpio *gpio;
590 struct gpio_chip *chip;
591 struct resource *res;
592
593 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
594 if (!gpio)
595 return -ENOMEM;
596
597 platform_set_drvdata(pdev, gpio);
598
599 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
600 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
601 if (IS_ERR(gpio->base_addr))
602 return PTR_ERR(gpio->base_addr);
603
604 irq = platform_get_irq(pdev, 0);
605 if (irq < 0) {
606 dev_err(&pdev->dev, "invalid IRQ\n");
607 return irq;
608 }
609
610 /* configure the gpio chip */
611 chip = &gpio->chip;
612 chip->label = "zynq_gpio";
613 chip->owner = THIS_MODULE;
614 chip->dev = &pdev->dev;
615 chip->get = zynq_gpio_get_value;
616 chip->set = zynq_gpio_set_value;
617 chip->request = zynq_gpio_request;
618 chip->free = zynq_gpio_free;
619 chip->direction_input = zynq_gpio_dir_in;
620 chip->direction_output = zynq_gpio_dir_out;
621 chip->base = -1;
622 chip->ngpio = ZYNQ_GPIO_NR_GPIOS;
623
624 /* Enable GPIO clock */
625 gpio->clk = devm_clk_get(&pdev->dev, NULL);
626 if (IS_ERR(gpio->clk)) {
627 dev_err(&pdev->dev, "input clock not found.\n");
628 return PTR_ERR(gpio->clk);
629 }
630 ret = clk_prepare_enable(gpio->clk);
631 if (ret) {
632 dev_err(&pdev->dev, "Unable to enable clock.\n");
633 return ret;
634 }
635
636 /* report a bug if gpio chip registration fails */
637 ret = gpiochip_add(chip);
638 if (ret) {
639 dev_err(&pdev->dev, "Failed to add gpio chip\n");
640 goto err_disable_clk;
641 }
642
643 /* disable interrupts for all banks */
644 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++)
645 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
646 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
647
6dd85950
LPC		 648 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
649 handle_level_irq, IRQ_TYPE_NONE);
3242ba11
HK		 650 if (ret) {
651 dev_err(&pdev->dev, "Failed to add irq chip\n");
652 goto err_rm_gpiochip;
653 }
654
6dd85950 655 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, irq,
3242ba11
HK		 656 zynq_gpio_irqhandler);
657
658 pm_runtime_set_active(&pdev->dev);
659 pm_runtime_enable(&pdev->dev);
660
661 device_set_wakeup_capable(&pdev->dev, 1);
662
663 return 0;
664
665err_rm_gpiochip:
666 if (gpiochip_remove(chip))
667 dev_err(&pdev->dev, "Failed to remove gpio chip\n");
668err_disable_clk:
669 clk_disable_unprepare(gpio->clk);
670
671 return ret;
672}
673
674/**
675 * zynq_gpio_remove - Driver removal function
676 * @pdev: platform device instance
677 *
678 * Return: 0 always
679 */
680static int zynq_gpio_remove(struct platform_device *pdev)
681{
682 int ret;
683 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
684
685 pm_runtime_get_sync(&pdev->dev);
686
687 ret = gpiochip_remove(&gpio->chip);
688 if (ret) {
689 dev_err(&pdev->dev, "Failed to remove gpio chip\n");
690 return ret;
691 }
692 clk_disable_unprepare(gpio->clk);
693 device_set_wakeup_capable(&pdev->dev, 0);
694 return 0;
695}
696
697static struct of_device_id zynq_gpio_of_match[] = {
698 { .compatible = "xlnx,zynq-gpio-1.0", },
699 { /* end of table */ }
700};
701MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
702
703static struct platform_driver zynq_gpio_driver = {
704 .driver = {
705 .name = DRIVER_NAME,
3242ba11
HK		 706 .pm = &zynq_gpio_dev_pm_ops,
707 .of_match_table = zynq_gpio_of_match,
708 },
709 .probe = zynq_gpio_probe,
710 .remove = zynq_gpio_remove,
711};
712
713/**
714 * zynq_gpio_init - Initial driver registration call
715 *
716 * Return: value from platform_driver_register
717 */
718static int __init zynq_gpio_init(void)
719{
720 return platform_driver_register(&zynq_gpio_driver);
721}
722postcore_initcall(zynq_gpio_init);
723
724MODULE_AUTHOR("Xilinx Inc.");
725MODULE_DESCRIPTION("Zynq GPIO driver");
726MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.058274 seconds and 5 git commands to generate.