projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: rework GEM info printing
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
97b2e202 88
4b559c90 89#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 90#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93#define AMDGPU_IB_POOL_SIZE 16
94#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95#define AMDGPUFB_CONN_LIMIT 4
96#define AMDGPU_BIOS_NUM_SCRATCH 8
97
97b2e202
AD		 98/* max number of rings */
99#define AMDGPU_MAX_RINGS 16
100#define AMDGPU_MAX_GFX_RINGS 1
101#define AMDGPU_MAX_COMPUTE_RINGS 8
102#define AMDGPU_MAX_VCE_RINGS 2
103
36f523a7
JZ		 104/* max number of IP instances */
105#define AMDGPU_MAX_SDMA_INSTANCES 2
106
97b2e202
AD		 107/* hardcode that limit for now */
108#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
109
110/* hard reset data */
111#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
112
113/* reset flags */
114#define AMDGPU_RESET_GFX (1 << 0)
115#define AMDGPU_RESET_COMPUTE (1 << 1)
116#define AMDGPU_RESET_DMA (1 << 2)
117#define AMDGPU_RESET_CP (1 << 3)
118#define AMDGPU_RESET_GRBM (1 << 4)
119#define AMDGPU_RESET_DMA1 (1 << 5)
120#define AMDGPU_RESET_RLC (1 << 6)
121#define AMDGPU_RESET_SEM (1 << 7)
122#define AMDGPU_RESET_IH (1 << 8)
123#define AMDGPU_RESET_VMC (1 << 9)
124#define AMDGPU_RESET_MC (1 << 10)
125#define AMDGPU_RESET_DISPLAY (1 << 11)
126#define AMDGPU_RESET_UVD (1 << 12)
127#define AMDGPU_RESET_VCE (1 << 13)
128#define AMDGPU_RESET_VCE1 (1 << 14)
129
130/* CG block flags */
131#define AMDGPU_CG_BLOCK_GFX (1 << 0)
132#define AMDGPU_CG_BLOCK_MC (1 << 1)
133#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134#define AMDGPU_CG_BLOCK_UVD (1 << 3)
135#define AMDGPU_CG_BLOCK_VCE (1 << 4)
136#define AMDGPU_CG_BLOCK_HDP (1 << 5)
137#define AMDGPU_CG_BLOCK_BIF (1 << 6)
138
139/* CG flags */
140#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
157
158/* PG flags */
159#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164#define AMDGPU_PG_SUPPORT_CP (1 << 5)
165#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
170
171/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L
174#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
177
178/* max cursor sizes (in pixels) */
179#define CIK_CURSOR_WIDTH 128
180#define CIK_CURSOR_HEIGHT 128
181
182struct amdgpu_device;
183struct amdgpu_fence;
184struct amdgpu_ib;
185struct amdgpu_vm;
186struct amdgpu_ring;
97b2e202 187struct amdgpu_cs_parser;
bb977d37 188struct amdgpu_job;
97b2e202 189struct amdgpu_irq_src;
0b492a4c 190struct amdgpu_fpriv;
97b2e202
AD		 191
192enum amdgpu_cp_irq {
193 AMDGPU_CP_IRQ_GFX_EOP = 0,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
202
203 AMDGPU_CP_IRQ_LAST
204};
205
206enum amdgpu_sdma_irq {
207 AMDGPU_SDMA_IRQ_TRAP0 = 0,
208 AMDGPU_SDMA_IRQ_TRAP1,
209
210 AMDGPU_SDMA_IRQ_LAST
211};
212
213enum amdgpu_thermal_irq {
214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
216
217 AMDGPU_THERMAL_IRQ_LAST
218};
219
97b2e202 220int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_clockgating_state state);
97b2e202 223int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 224 enum amd_ip_block_type block_type,
225 enum amd_powergating_state state);
97b2e202
AD		 226
227struct amdgpu_ip_block_version {
5fc3aeeb 228 enum amd_ip_block_type type;
97b2e202
AD		 229 u32 major;
230 u32 minor;
231 u32 rev;
5fc3aeeb 232 const struct amd_ip_funcs *funcs;
97b2e202
AD		 233};
234
235int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 236 enum amd_ip_block_type type,
97b2e202
AD		 237 u32 major, u32 minor);
238
239const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
240 struct amdgpu_device *adev,
5fc3aeeb 241 enum amd_ip_block_type type);
97b2e202
AD		 242
243/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244struct amdgpu_buffer_funcs {
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes;
247
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw;
250
251 /* used for buffer migration */
c7ae72c0 252 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 253 /* src addr in bytes */
254 uint64_t src_offset,
255 /* dst addr in bytes */
256 uint64_t dst_offset,
257 /* number of byte to transfer */
258 uint32_t byte_count);
259
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes;
262
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw;
265
266 /* used for buffer clearing */
6e7a3840 267 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 268 /* value to write to memory */
269 uint32_t src_data,
270 /* dst addr in bytes */
271 uint64_t dst_offset,
272 /* number of byte to fill */
273 uint32_t byte_count);
274};
275
276/* provided by hw blocks that can write ptes, e.g., sdma */
277struct amdgpu_vm_pte_funcs {
278 /* copy pte entries from GART */
279 void (*copy_pte)(struct amdgpu_ib *ib,
280 uint64_t pe, uint64_t src,
281 unsigned count);
282 /* write pte one entry at a time with addr mapping */
283 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 284 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 285 uint64_t addr, unsigned count,
286 uint32_t incr, uint32_t flags);
287 /* for linear pte/pde updates without addr mapping */
288 void (*set_pte_pde)(struct amdgpu_ib *ib,
289 uint64_t pe,
290 uint64_t addr, unsigned count,
291 uint32_t incr, uint32_t flags);
97b2e202
AD		 292};
293
294/* provided by the gmc block */
295struct amdgpu_gart_funcs {
296 /* flush the vm tlb via mmio */
297 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
298 uint32_t vmid);
299 /* write pte/pde updates using the cpu */
300 int (*set_pte_pde)(struct amdgpu_device *adev,
301 void *cpu_pt_addr, /* cpu addr of page table */
302 uint32_t gpu_page_idx, /* pte/pde to update */
303 uint64_t addr, /* addr to write into pte/pde */
304 uint32_t flags); /* access flags */
305};
306
307/* provided by the ih block */
308struct amdgpu_ih_funcs {
309 /* ring read/write ptr handling, called from interrupt context */
310 u32 (*get_wptr)(struct amdgpu_device *adev);
311 void (*decode_iv)(struct amdgpu_device *adev,
312 struct amdgpu_iv_entry *entry);
313 void (*set_rptr)(struct amdgpu_device *adev);
314};
315
316/* provided by hw blocks that expose a ring buffer for commands */
317struct amdgpu_ring_funcs {
318 /* ring read/write ptr handling */
319 u32 (*get_rptr)(struct amdgpu_ring *ring);
320 u32 (*get_wptr)(struct amdgpu_ring *ring);
321 void (*set_wptr)(struct amdgpu_ring *ring);
322 /* validating and patching of IBs */
323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
324 /* command emit functions */
325 void (*emit_ib)(struct amdgpu_ring *ring,
326 struct amdgpu_ib *ib);
327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 328 uint64_t seq, unsigned flags);
97b2e202
AD		 329 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
330 uint64_t pd_addr);
d2edb07b 331 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 332 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
333 uint32_t gds_base, uint32_t gds_size,
334 uint32_t gws_base, uint32_t gws_size,
335 uint32_t oa_base, uint32_t oa_size);
336 /* testing functions */
337 int (*test_ring)(struct amdgpu_ring *ring);
338 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 339 /* insert NOP packets */
340 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 341 /* pad the indirect buffer to the necessary number of dw */
342 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202
AD		 343};
344
345/*
346 * BIOS.
347 */
348bool amdgpu_get_bios(struct amdgpu_device *adev);
349bool amdgpu_read_bios(struct amdgpu_device *adev);
350
351/*
352 * Dummy page
353 */
354struct amdgpu_dummy_page {
355 struct page *page;
356 dma_addr_t addr;
357};
358int amdgpu_dummy_page_init(struct amdgpu_device *adev);
359void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
360
361
362/*
363 * Clocks
364 */
365
366#define AMDGPU_MAX_PPLL 3
367
368struct amdgpu_clock {
369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
370 struct amdgpu_pll spll;
371 struct amdgpu_pll mpll;
372 /* 10 Khz units */
373 uint32_t default_mclk;
374 uint32_t default_sclk;
375 uint32_t default_dispclk;
376 uint32_t current_dispclk;
377 uint32_t dp_extclk;
378 uint32_t max_pixel_clock;
379};
380
381/*
382 * Fences.
383 */
384struct amdgpu_fence_driver {
97b2e202
AD		 385 uint64_t gpu_addr;
386 volatile uint32_t *cpu_addr;
387 /* sync_seq is protected by ring emission lock */
5907a0d8 388 uint64_t sync_seq;
97b2e202
AD		 389 atomic64_t last_seq;
390 bool initialized;
97b2e202
AD		 391 struct amdgpu_irq_src *irq_src;
392 unsigned irq_type;
c2776afe 393 struct timer_list fallback_timer;
7f06c236 394 wait_queue_head_t fence_queue;
97b2e202
AD		 395};
396
397/* some special values for the owner field */
398#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
399#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 400
890ee23f
CZ		 401#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
402#define AMDGPU_FENCE_FLAG_INT (1 << 1)
403
97b2e202
AD		 404struct amdgpu_fence {
405 struct fence base;
4cef9267 406
97b2e202
AD		 407 /* RB, DMA, etc. */
408 struct amdgpu_ring *ring;
409 uint64_t seq;
410
411 /* filp or special value for fence creator */
412 void *owner;
413
414 wait_queue_t fence_wake;
415};
416
417struct amdgpu_user_fence {
418 /* write-back bo */
419 struct amdgpu_bo *bo;
420 /* write-back address offset to bo start */
421 uint32_t offset;
422};
423
424int amdgpu_fence_driver_init(struct amdgpu_device *adev);
425void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
426void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
427
4f839a24 428int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 429int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
430 struct amdgpu_irq_src *irq_src,
431 unsigned irq_type);
5ceb54c6
AD		 432void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
433void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 434int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
435 struct amdgpu_fence **fence);
436void amdgpu_fence_process(struct amdgpu_ring *ring);
437int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
438int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
439unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
440
97b2e202
AD		 441/*
442 * TTM.
443 */
444struct amdgpu_mman {
445 struct ttm_bo_global_ref bo_global_ref;
446 struct drm_global_reference mem_global_ref;
447 struct ttm_bo_device bdev;
448 bool mem_global_referenced;
449 bool initialized;
450
451#if defined(CONFIG_DEBUG_FS)
452 struct dentry *vram;
453 struct dentry *gtt;
454#endif
455
456 /* buffer handling */
457 const struct amdgpu_buffer_funcs *buffer_funcs;
458 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 459 /* Scheduler entity for buffer moves */
460 struct amd_sched_entity entity;
97b2e202
AD		 461};
462
463int amdgpu_copy_buffer(struct amdgpu_ring *ring,
464 uint64_t src_offset,
465 uint64_t dst_offset,
466 uint32_t byte_count,
467 struct reservation_object *resv,
c7ae72c0 468 struct fence **fence);
97b2e202
AD		 469int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
470
471struct amdgpu_bo_list_entry {
472 struct amdgpu_bo *robj;
473 struct ttm_validate_buffer tv;
474 struct amdgpu_bo_va *bo_va;
97b2e202
AD		 475 uint32_t priority;
476};
477
478struct amdgpu_bo_va_mapping {
479 struct list_head list;
480 struct interval_tree_node it;
481 uint64_t offset;
482 uint32_t flags;
483};
484
485/* bo virtual addresses in a specific vm */
486struct amdgpu_bo_va {
69b576a1 487 struct mutex mutex;
97b2e202
AD		 488 /* protected by bo being reserved */
489 struct list_head bo_list;
bb1e38a4 490 struct fence *last_pt_update;
97b2e202
AD		 491 unsigned ref_count;
492
7fc11959 493 /* protected by vm mutex and spinlock */
97b2e202
AD		 494 struct list_head vm_status;
495
7fc11959
CK		 496 /* mappings for this bo_va */
497 struct list_head invalids;
498 struct list_head valids;
499
97b2e202
AD		 500 /* constant after initialization */
501 struct amdgpu_vm *vm;
502 struct amdgpu_bo *bo;
503};
504
7e5a547f
CZ		 505#define AMDGPU_GEM_DOMAIN_MAX 0x3
506
97b2e202
AD		 507struct amdgpu_bo {
508 /* Protected by gem.mutex */
509 struct list_head list;
510 /* Protected by tbo.reserved */
1ea863fd
CK		 511 u32 prefered_domains;
512 u32 allowed_domains;
7e5a547f 513 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 514 struct ttm_placement placement;
515 struct ttm_buffer_object tbo;
516 struct ttm_bo_kmap_obj kmap;
517 u64 flags;
518 unsigned pin_count;
519 void *kptr;
520 u64 tiling_flags;
521 u64 metadata_flags;
522 void *metadata;
523 u32 metadata_size;
524 /* list of all virtual address to which this bo
525 * is associated to
526 */
527 struct list_head va;
528 /* Constant after initialization */
529 struct amdgpu_device *adev;
530 struct drm_gem_object gem_base;
82b9c55b 531 struct amdgpu_bo *parent;
97b2e202
AD		 532
533 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 534 struct amdgpu_mn *mn;
535 struct list_head mn_list;
536};
537#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
538
539void amdgpu_gem_object_free(struct drm_gem_object *obj);
540int amdgpu_gem_object_open(struct drm_gem_object *obj,
541 struct drm_file *file_priv);
542void amdgpu_gem_object_close(struct drm_gem_object *obj,
543 struct drm_file *file_priv);
544unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
545struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
546struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
547 struct dma_buf_attachment *attach,
548 struct sg_table *sg);
549struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
550 struct drm_gem_object *gobj,
551 int flags);
552int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
553void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
554struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
555void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
556void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
557int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
558
559/* sub-allocation manager, it has to be protected by another lock.
560 * By conception this is an helper for other part of the driver
561 * like the indirect buffer or semaphore, which both have their
562 * locking.
563 *
564 * Principe is simple, we keep a list of sub allocation in offset
565 * order (first entry has offset == 0, last entry has the highest
566 * offset).
567 *
568 * When allocating new object we first check if there is room at
569 * the end total_size - (last_object_offset + last_object_size) >=
570 * alloc_size. If so we allocate new object there.
571 *
572 * When there is not enough room at the end, we start waiting for
573 * each sub object until we reach object_offset+object_size >=
574 * alloc_size, this object then become the sub object we return.
575 *
576 * Alignment can't be bigger than page size.
577 *
578 * Hole are not considered for allocation to keep things simple.
579 * Assumption is that there won't be hole (all object on same
580 * alignment).
581 */
582struct amdgpu_sa_manager {
583 wait_queue_head_t wq;
584 struct amdgpu_bo *bo;
585 struct list_head *hole;
586 struct list_head flist[AMDGPU_MAX_RINGS];
587 struct list_head olist;
588 unsigned size;
589 uint64_t gpu_addr;
590 void *cpu_ptr;
591 uint32_t domain;
592 uint32_t align;
593};
594
595struct amdgpu_sa_bo;
596
597/* sub-allocation buffer */
598struct amdgpu_sa_bo {
599 struct list_head olist;
600 struct list_head flist;
601 struct amdgpu_sa_manager *manager;
602 unsigned soffset;
603 unsigned eoffset;
4ce9891e 604 struct fence *fence;
97b2e202
AD		 605};
606
607/*
608 * GEM objects.
609 */
610struct amdgpu_gem {
611 struct mutex mutex;
612 struct list_head objects;
613};
614
615int amdgpu_gem_init(struct amdgpu_device *adev);
616void amdgpu_gem_fini(struct amdgpu_device *adev);
617int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
618 int alignment, u32 initial_domain,
619 u64 flags, bool kernel,
620 struct drm_gem_object **obj);
621
622int amdgpu_mode_dumb_create(struct drm_file *file_priv,
623 struct drm_device *dev,
624 struct drm_mode_create_dumb *args);
625int amdgpu_mode_dumb_mmap(struct drm_file *filp,
626 struct drm_device *dev,
627 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 628/*
629 * Synchronization
630 */
631struct amdgpu_sync {
f91b3a69 632 DECLARE_HASHTABLE(fences, 4);
3c62338c 633 struct fence *last_vm_update;
97b2e202
AD		 634};
635
636void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 637int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
638 struct fence *f);
97b2e202
AD		 639int amdgpu_sync_resv(struct amdgpu_device *adev,
640 struct amdgpu_sync *sync,
641 struct reservation_object *resv,
642 void *owner);
e61235db 643struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 644int amdgpu_sync_wait(struct amdgpu_sync *sync);
8a8f0b48 645void amdgpu_sync_free(struct amdgpu_sync *sync);
97b2e202
AD		 646
647/*
648 * GART structures, functions & helpers
649 */
650struct amdgpu_mc;
651
652#define AMDGPU_GPU_PAGE_SIZE 4096
653#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
654#define AMDGPU_GPU_PAGE_SHIFT 12
655#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
656
657struct amdgpu_gart {
658 dma_addr_t table_addr;
659 struct amdgpu_bo *robj;
660 void *ptr;
661 unsigned num_gpu_pages;
662 unsigned num_cpu_pages;
663 unsigned table_size;
664 struct page **pages;
665 dma_addr_t *pages_addr;
666 bool ready;
667 const struct amdgpu_gart_funcs *gart_funcs;
668};
669
670int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
671void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
672int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
673void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
674int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
675void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
676int amdgpu_gart_init(struct amdgpu_device *adev);
677void amdgpu_gart_fini(struct amdgpu_device *adev);
678void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
679 int pages);
680int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
681 int pages, struct page **pagelist,
682 dma_addr_t *dma_addr, uint32_t flags);
683
684/*
685 * GPU MC structures, functions & helpers
686 */
687struct amdgpu_mc {
688 resource_size_t aper_size;
689 resource_size_t aper_base;
690 resource_size_t agp_base;
691 /* for some chips with <= 32MB we need to lie
692 * about vram size near mc fb location */
693 u64 mc_vram_size;
694 u64 visible_vram_size;
695 u64 gtt_size;
696 u64 gtt_start;
697 u64 gtt_end;
698 u64 vram_start;
699 u64 vram_end;
700 unsigned vram_width;
701 u64 real_vram_size;
702 int vram_mtrr;
703 u64 gtt_base_align;
704 u64 mc_mask;
705 const struct firmware *fw; /* MC firmware */
706 uint32_t fw_version;
707 struct amdgpu_irq_src vm_fault;
81c59f54 708 uint32_t vram_type;
97b2e202
AD		 709};
710
711/*
712 * GPU doorbell structures, functions & helpers
713 */
714typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
715{
716 AMDGPU_DOORBELL_KIQ = 0x000,
717 AMDGPU_DOORBELL_HIQ = 0x001,
718 AMDGPU_DOORBELL_DIQ = 0x002,
719 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
720 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
721 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
722 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
723 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
724 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
725 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
726 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
727 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
728 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
729 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
730 AMDGPU_DOORBELL_IH = 0x1E8,
731 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
732 AMDGPU_DOORBELL_INVALID = 0xFFFF
733} AMDGPU_DOORBELL_ASSIGNMENT;
734
735struct amdgpu_doorbell {
736 /* doorbell mmio */
737 resource_size_t base;
738 resource_size_t size;
739 u32 __iomem *ptr;
740 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
741};
742
743void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
744 phys_addr_t *aperture_base,
745 size_t *aperture_size,
746 size_t *start_offset);
747
748/*
749 * IRQS.
750 */
751
752struct amdgpu_flip_work {
753 struct work_struct flip_work;
754 struct work_struct unpin_work;
755 struct amdgpu_device *adev;
756 int crtc_id;
757 uint64_t base;
758 struct drm_pending_vblank_event *event;
759 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 760 struct fence *excl;
761 unsigned shared_count;
762 struct fence **shared;
c3874b75 763 struct fence_cb cb;
97b2e202
AD		 764};
765
766
767/*
768 * CP & rings.
769 */
770
771struct amdgpu_ib {
772 struct amdgpu_sa_bo *sa_bo;
773 uint32_t length_dw;
774 uint64_t gpu_addr;
775 uint32_t *ptr;
97b2e202
AD		 776 struct amdgpu_fence *fence;
777 struct amdgpu_user_fence *user;
8d0a7cea 778 bool grabbed_vmid;
97b2e202 779 struct amdgpu_vm *vm;
3cb485f3 780 struct amdgpu_ctx *ctx;
97b2e202
AD		 781 uint32_t gds_base, gds_size;
782 uint32_t gws_base, gws_size;
783 uint32_t oa_base, oa_size;
de807f81 784 uint32_t flags;
5430a3ff
CK		 785 /* resulting sequence number */
786 uint64_t sequence;
97b2e202
AD		 787};
788
789enum amdgpu_ring_type {
790 AMDGPU_RING_TYPE_GFX,
791 AMDGPU_RING_TYPE_COMPUTE,
792 AMDGPU_RING_TYPE_SDMA,
793 AMDGPU_RING_TYPE_UVD,
794 AMDGPU_RING_TYPE_VCE
795};
796
c1b69ed0
CZ		 797extern struct amd_sched_backend_ops amdgpu_sched_ops;
798
50838c8c
CK		 799int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
800 struct amdgpu_job **job);
d71518b5
CK		 801int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
802 struct amdgpu_job **job);
50838c8c 803void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 804int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 805 struct amd_sched_entity *entity, void *owner,
806 struct fence **f);
3c704e93 807
97b2e202
AD		 808struct amdgpu_ring {
809 struct amdgpu_device *adev;
810 const struct amdgpu_ring_funcs *funcs;
811 struct amdgpu_fence_driver fence_drv;
4f839a24 812 struct amd_gpu_scheduler sched;
97b2e202 813
176e1ab1 814 spinlock_t fence_lock;
97b2e202
AD		 815 struct amdgpu_bo *ring_obj;
816 volatile uint32_t *ring;
817 unsigned rptr_offs;
818 u64 next_rptr_gpu_addr;
819 volatile u32 *next_rptr_cpu_addr;
820 unsigned wptr;
821 unsigned wptr_old;
822 unsigned ring_size;
c7e6be23 823 unsigned max_dw;
97b2e202 824 int count_dw;
97b2e202
AD		 825 uint64_t gpu_addr;
826 uint32_t align_mask;
827 uint32_t ptr_mask;
828 bool ready;
829 u32 nop;
830 u32 idx;
97b2e202
AD		 831 u32 me;
832 u32 pipe;
833 u32 queue;
834 struct amdgpu_bo *mqd_obj;
835 u32 doorbell_index;
836 bool use_doorbell;
837 unsigned wptr_offs;
838 unsigned next_rptr_offs;
839 unsigned fence_offs;
3cb485f3 840 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 841 enum amdgpu_ring_type type;
842 char name[16];
843};
844
845/*
846 * VM
847 */
848
849/* maximum number of VMIDs */
850#define AMDGPU_NUM_VM 16
851
852/* number of entries in page table */
853#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
854
855/* PTBs (Page Table Blocks) need to be aligned to 32K */
856#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
857#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
858#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
859
860#define AMDGPU_PTE_VALID (1 << 0)
861#define AMDGPU_PTE_SYSTEM (1 << 1)
862#define AMDGPU_PTE_SNOOPED (1 << 2)
863
864/* VI only */
865#define AMDGPU_PTE_EXECUTABLE (1 << 4)
866
867#define AMDGPU_PTE_READABLE (1 << 5)
868#define AMDGPU_PTE_WRITEABLE (1 << 6)
869
870/* PTE (Page Table Entry) fragment field for different page sizes */
871#define AMDGPU_PTE_FRAG_4KB (0 << 7)
872#define AMDGPU_PTE_FRAG_64KB (4 << 7)
873#define AMDGPU_LOG2_PAGES_PER_FRAG 4
874
d9c13156
CK		 875/* How to programm VM fault handling */
876#define AMDGPU_VM_FAULT_STOP_NEVER 0
877#define AMDGPU_VM_FAULT_STOP_FIRST 1
878#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
879
97b2e202 880struct amdgpu_vm_pt {
ee1782c3
CK		 881 struct amdgpu_bo_list_entry entry;
882 uint64_t addr;
97b2e202
AD		 883};
884
885struct amdgpu_vm_id {
886 unsigned id;
887 uint64_t pd_gpu_addr;
888 /* last flushed PD/PT update */
3c62338c 889 struct fence *flushed_updates;
97b2e202
AD		 890};
891
892struct amdgpu_vm {
25cfc3c2
CK		 893 /* tree of virtual addresses mapped */
894 spinlock_t it_lock;
97b2e202
AD		 895 struct rb_root va;
896
7fc11959 897 /* protecting invalidated */
97b2e202
AD		 898 spinlock_t status_lock;
899
900 /* BOs moved, but not yet updated in the PT */
901 struct list_head invalidated;
902
7fc11959
CK		 903 /* BOs cleared in the PT because of a move */
904 struct list_head cleared;
905
906 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 907 struct list_head freed;
908
909 /* contains the page directory */
910 struct amdgpu_bo *page_directory;
911 unsigned max_pde_used;
05906dec 912 struct fence *page_directory_fence;
97b2e202
AD		 913
914 /* array of page tables, one for each page directory entry */
915 struct amdgpu_vm_pt *page_tables;
916
917 /* for id and flush management per ring */
918 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 919
81d75a30 920 /* protecting freed */
921 spinlock_t freed_lock;
2bd9ccfa
CK		 922
923 /* Scheduler entity for page table updates */
924 struct amd_sched_entity entity;
97b2e202
AD		 925};
926
a9a78b32
CK		 927struct amdgpu_vm_manager_id {
928 struct list_head list;
929 struct fence *active;
930 atomic_long_t owner;
931};
932
97b2e202 933struct amdgpu_vm_manager {
a9a78b32 934 /* Handling of VMIDs */
8d0a7cea 935 struct mutex lock;
a9a78b32
CK		 936 unsigned num_ids;
937 struct list_head ids_lru;
938 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
1c16c0a7 939
8b4fb00b 940 uint32_t max_pfn;
97b2e202 941 /* vram base address for page table entry */
8b4fb00b 942 u64 vram_base_offset;
97b2e202 943 /* is vm enabled? */
8b4fb00b 944 bool enabled;
97b2e202
AD		 945 /* vm pte handling */
946 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 947 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
948 unsigned vm_pte_num_rings;
949 atomic_t vm_pte_next_ring;
97b2e202
AD		 950};
951
a9a78b32 952void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 953void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 954int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
955void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 956void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
957 struct list_head *validated,
958 struct amdgpu_bo_list_entry *entry);
ee1782c3 959void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 960void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
961 struct amdgpu_vm *vm);
8b4fb00b 962int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
94dd0a4a 963 struct amdgpu_sync *sync, struct fence *fence);
8b4fb00b
CK		 964void amdgpu_vm_flush(struct amdgpu_ring *ring,
965 struct amdgpu_vm *vm,
966 struct fence *updates);
b07c9d2a 967uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 968int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
969 struct amdgpu_vm *vm);
970int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
971 struct amdgpu_vm *vm);
972int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
973 struct amdgpu_sync *sync);
974int amdgpu_vm_bo_update(struct amdgpu_device *adev,
975 struct amdgpu_bo_va *bo_va,
976 struct ttm_mem_reg *mem);
977void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
978 struct amdgpu_bo *bo);
979struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
980 struct amdgpu_bo *bo);
981struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
982 struct amdgpu_vm *vm,
983 struct amdgpu_bo *bo);
984int amdgpu_vm_bo_map(struct amdgpu_device *adev,
985 struct amdgpu_bo_va *bo_va,
986 uint64_t addr, uint64_t offset,
987 uint64_t size, uint32_t flags);
988int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
989 struct amdgpu_bo_va *bo_va,
990 uint64_t addr);
991void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
992 struct amdgpu_bo_va *bo_va);
8b4fb00b 993
97b2e202
AD		 994/*
995 * context related structures
996 */
997
21c16bf6 998struct amdgpu_ctx_ring {
91404fb2 999 uint64_t sequence;
37cd0ca2 1000 struct fence **fences;
91404fb2 1001 struct amd_sched_entity entity;
21c16bf6
CK		 1002};
1003
97b2e202 1004struct amdgpu_ctx {
0b492a4c 1005 struct kref refcount;
9cb7e5a9 1006 struct amdgpu_device *adev;
0b492a4c 1007 unsigned reset_counter;
21c16bf6 1008 spinlock_t ring_lock;
37cd0ca2 1009 struct fence **fences;
21c16bf6 1010 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1011};
1012
1013struct amdgpu_ctx_mgr {
0b492a4c
AD		 1014 struct amdgpu_device *adev;
1015 struct mutex lock;
1016 /* protected by lock */
1017 struct idr ctx_handles;
97b2e202
AD		 1018};
1019
0b492a4c
AD		 1020struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1021int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1022
21c16bf6 1023uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1024 struct fence *fence);
21c16bf6
CK		 1025struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1026 struct amdgpu_ring *ring, uint64_t seq);
1027
0b492a4c
AD		 1028int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1029 struct drm_file *filp);
1030
efd4ccb5
CK		 1031void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1032void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1033
97b2e202
AD		 1034/*
1035 * file private structure
1036 */
1037
1038struct amdgpu_fpriv {
1039 struct amdgpu_vm vm;
1040 struct mutex bo_list_lock;
1041 struct idr bo_list_handles;
0b492a4c 1042 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1043};
1044
1045/*
1046 * residency list
1047 */
1048
1049struct amdgpu_bo_list {
1050 struct mutex lock;
1051 struct amdgpu_bo *gds_obj;
1052 struct amdgpu_bo *gws_obj;
1053 struct amdgpu_bo *oa_obj;
1054 bool has_userptr;
1055 unsigned num_entries;
1056 struct amdgpu_bo_list_entry *array;
1057};
1058
1059struct amdgpu_bo_list *
1060amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1061void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1062 struct list_head *validated);
97b2e202
AD		 1063void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1064void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1065
1066/*
1067 * GFX stuff
1068 */
1069#include "clearstate_defs.h"
1070
1071struct amdgpu_rlc {
1072 /* for power gating */
1073 struct amdgpu_bo *save_restore_obj;
1074 uint64_t save_restore_gpu_addr;
1075 volatile uint32_t *sr_ptr;
1076 const u32 *reg_list;
1077 u32 reg_list_size;
1078 /* for clear state */
1079 struct amdgpu_bo *clear_state_obj;
1080 uint64_t clear_state_gpu_addr;
1081 volatile uint32_t *cs_ptr;
1082 const struct cs_section_def *cs_data;
1083 u32 clear_state_size;
1084 /* for cp tables */
1085 struct amdgpu_bo *cp_table_obj;
1086 uint64_t cp_table_gpu_addr;
1087 volatile uint32_t *cp_table_ptr;
1088 u32 cp_table_size;
1089};
1090
1091struct amdgpu_mec {
1092 struct amdgpu_bo *hpd_eop_obj;
1093 u64 hpd_eop_gpu_addr;
1094 u32 num_pipe;
1095 u32 num_mec;
1096 u32 num_queue;
1097};
1098
1099/*
1100 * GPU scratch registers structures, functions & helpers
1101 */
1102struct amdgpu_scratch {
1103 unsigned num_reg;
1104 uint32_t reg_base;
1105 bool free[32];
1106 uint32_t reg[32];
1107};
1108
1109/*
1110 * GFX configurations
1111 */
1112struct amdgpu_gca_config {
1113 unsigned max_shader_engines;
1114 unsigned max_tile_pipes;
1115 unsigned max_cu_per_sh;
1116 unsigned max_sh_per_se;
1117 unsigned max_backends_per_se;
1118 unsigned max_texture_channel_caches;
1119 unsigned max_gprs;
1120 unsigned max_gs_threads;
1121 unsigned max_hw_contexts;
1122 unsigned sc_prim_fifo_size_frontend;
1123 unsigned sc_prim_fifo_size_backend;
1124 unsigned sc_hiz_tile_fifo_size;
1125 unsigned sc_earlyz_tile_fifo_size;
1126
1127 unsigned num_tile_pipes;
1128 unsigned backend_enable_mask;
1129 unsigned mem_max_burst_length_bytes;
1130 unsigned mem_row_size_in_kb;
1131 unsigned shader_engine_tile_size;
1132 unsigned num_gpus;
1133 unsigned multi_gpu_tile_size;
1134 unsigned mc_arb_ramcfg;
1135 unsigned gb_addr_config;
8f8e00c1 1136 unsigned num_rbs;
97b2e202
AD		 1137
1138 uint32_t tile_mode_array[32];
1139 uint32_t macrotile_mode_array[16];
1140};
1141
1142struct amdgpu_gfx {
1143 struct mutex gpu_clock_mutex;
1144 struct amdgpu_gca_config config;
1145 struct amdgpu_rlc rlc;
1146 struct amdgpu_mec mec;
1147 struct amdgpu_scratch scratch;
1148 const struct firmware *me_fw; /* ME firmware */
1149 uint32_t me_fw_version;
1150 const struct firmware *pfp_fw; /* PFP firmware */
1151 uint32_t pfp_fw_version;
1152 const struct firmware *ce_fw; /* CE firmware */
1153 uint32_t ce_fw_version;
1154 const struct firmware *rlc_fw; /* RLC firmware */
1155 uint32_t rlc_fw_version;
1156 const struct firmware *mec_fw; /* MEC firmware */
1157 uint32_t mec_fw_version;
1158 const struct firmware *mec2_fw; /* MEC2 firmware */
1159 uint32_t mec2_fw_version;
02558a00
KW		 1160 uint32_t me_feature_version;
1161 uint32_t ce_feature_version;
1162 uint32_t pfp_feature_version;
351643d7
JZ		 1163 uint32_t rlc_feature_version;
1164 uint32_t mec_feature_version;
1165 uint32_t mec2_feature_version;
97b2e202
AD		 1166 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1167 unsigned num_gfx_rings;
1168 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1169 unsigned num_compute_rings;
1170 struct amdgpu_irq_src eop_irq;
1171 struct amdgpu_irq_src priv_reg_irq;
1172 struct amdgpu_irq_src priv_inst_irq;
1173 /* gfx status */
1174 uint32_t gfx_current_status;
a101a899
KW		 1175 /* ce ram size*/
1176 unsigned ce_ram_size;
97b2e202
AD		 1177};
1178
b07c60c0 1179int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202
AD		 1180 unsigned size, struct amdgpu_ib *ib);
1181void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
b07c60c0 1182int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
ec72b800 1183 struct amdgpu_ib *ib, void *owner,
e86f9cee 1184 struct fence *last_vm_update,
ec72b800 1185 struct fence **f);
97b2e202
AD		 1186int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1187void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1188int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1189int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1190void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1191void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1192void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1193void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1194unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1195 uint32_t **data);
1196int amdgpu_ring_restore(struct amdgpu_ring *ring,
1197 unsigned size, uint32_t *data);
1198int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1199 unsigned ring_size, u32 nop, u32 align_mask,
1200 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1201 enum amdgpu_ring_type ring_type);
1202void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1203struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1204
1205/*
1206 * CS.
1207 */
1208struct amdgpu_cs_chunk {
1209 uint32_t chunk_id;
1210 uint32_t length_dw;
1211 uint32_t *kdata;
97b2e202
AD		 1212};
1213
1214struct amdgpu_cs_parser {
1215 struct amdgpu_device *adev;
1216 struct drm_file *filp;
3cb485f3 1217 struct amdgpu_ctx *ctx;
c3cca41e 1218
97b2e202
AD		 1219 /* chunks */
1220 unsigned nchunks;
1221 struct amdgpu_cs_chunk *chunks;
97b2e202 1222
50838c8c
CK		 1223 /* scheduler job object */
1224 struct amdgpu_job *job;
97b2e202 1225
c3cca41e
CK		 1226 /* buffer objects */
1227 struct ww_acquire_ctx ticket;
1228 struct amdgpu_bo_list *bo_list;
1229 struct amdgpu_bo_list_entry vm_pd;
1230 struct list_head validated;
1231 struct fence *fence;
1232 uint64_t bytes_moved_threshold;
1233 uint64_t bytes_moved;
97b2e202
AD		 1234
1235 /* user fence */
91acbeb6 1236 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1237};
1238
bb977d37
CZ		 1239struct amdgpu_job {
1240 struct amd_sched_job base;
1241 struct amdgpu_device *adev;
b07c60c0 1242 struct amdgpu_ring *ring;
e86f9cee 1243 struct amdgpu_sync sync;
bb977d37
CZ		 1244 struct amdgpu_ib *ibs;
1245 uint32_t num_ibs;
e2840221 1246 void *owner;
bb977d37 1247 struct amdgpu_user_fence uf;
bb977d37 1248};
a6db8a33
JZ		 1249#define to_amdgpu_job(sched_job) \
1250 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1251
7270f839
CK		 1252static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1253 uint32_t ib_idx, int idx)
97b2e202 1254{
50838c8c 1255 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1256}
1257
7270f839
CK		 1258static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1259 uint32_t ib_idx, int idx,
1260 uint32_t value)
1261{
50838c8c 1262 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1263}
1264
97b2e202
AD		 1265/*
1266 * Writeback
1267 */
1268#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1269
1270struct amdgpu_wb {
1271 struct amdgpu_bo *wb_obj;
1272 volatile uint32_t *wb;
1273 uint64_t gpu_addr;
1274 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1275 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1276};
1277
1278int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1279void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1280
97b2e202 1281
97b2e202
AD		 1282
1283enum amdgpu_int_thermal_type {
1284 THERMAL_TYPE_NONE,
1285 THERMAL_TYPE_EXTERNAL,
1286 THERMAL_TYPE_EXTERNAL_GPIO,
1287 THERMAL_TYPE_RV6XX,
1288 THERMAL_TYPE_RV770,
1289 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1290 THERMAL_TYPE_EVERGREEN,
1291 THERMAL_TYPE_SUMO,
1292 THERMAL_TYPE_NI,
1293 THERMAL_TYPE_SI,
1294 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1295 THERMAL_TYPE_CI,
1296 THERMAL_TYPE_KV,
1297};
1298
1299enum amdgpu_dpm_auto_throttle_src {
1300 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1301 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1302};
1303
1304enum amdgpu_dpm_event_src {
1305 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1306 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1307 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1308 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1309 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1310};
1311
1312#define AMDGPU_MAX_VCE_LEVELS 6
1313
1314enum amdgpu_vce_level {
1315 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1316 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1317 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1318 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1319 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1320 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1321};
1322
1323struct amdgpu_ps {
1324 u32 caps; /* vbios flags */
1325 u32 class; /* vbios flags */
1326 u32 class2; /* vbios flags */
1327 /* UVD clocks */
1328 u32 vclk;
1329 u32 dclk;
1330 /* VCE clocks */
1331 u32 evclk;
1332 u32 ecclk;
1333 bool vce_active;
1334 enum amdgpu_vce_level vce_level;
1335 /* asic priv */
1336 void *ps_priv;
1337};
1338
1339struct amdgpu_dpm_thermal {
1340 /* thermal interrupt work */
1341 struct work_struct work;
1342 /* low temperature threshold */
1343 int min_temp;
1344 /* high temperature threshold */
1345 int max_temp;
1346 /* was last interrupt low to high or high to low */
1347 bool high_to_low;
1348 /* interrupt source */
1349 struct amdgpu_irq_src irq;
1350};
1351
1352enum amdgpu_clk_action
1353{
1354 AMDGPU_SCLK_UP = 1,
1355 AMDGPU_SCLK_DOWN
1356};
1357
1358struct amdgpu_blacklist_clocks
1359{
1360 u32 sclk;
1361 u32 mclk;
1362 enum amdgpu_clk_action action;
1363};
1364
1365struct amdgpu_clock_and_voltage_limits {
1366 u32 sclk;
1367 u32 mclk;
1368 u16 vddc;
1369 u16 vddci;
1370};
1371
1372struct amdgpu_clock_array {
1373 u32 count;
1374 u32 *values;
1375};
1376
1377struct amdgpu_clock_voltage_dependency_entry {
1378 u32 clk;
1379 u16 v;
1380};
1381
1382struct amdgpu_clock_voltage_dependency_table {
1383 u32 count;
1384 struct amdgpu_clock_voltage_dependency_entry *entries;
1385};
1386
1387union amdgpu_cac_leakage_entry {
1388 struct {
1389 u16 vddc;
1390 u32 leakage;
1391 };
1392 struct {
1393 u16 vddc1;
1394 u16 vddc2;
1395 u16 vddc3;
1396 };
1397};
1398
1399struct amdgpu_cac_leakage_table {
1400 u32 count;
1401 union amdgpu_cac_leakage_entry *entries;
1402};
1403
1404struct amdgpu_phase_shedding_limits_entry {
1405 u16 voltage;
1406 u32 sclk;
1407 u32 mclk;
1408};
1409
1410struct amdgpu_phase_shedding_limits_table {
1411 u32 count;
1412 struct amdgpu_phase_shedding_limits_entry *entries;
1413};
1414
1415struct amdgpu_uvd_clock_voltage_dependency_entry {
1416 u32 vclk;
1417 u32 dclk;
1418 u16 v;
1419};
1420
1421struct amdgpu_uvd_clock_voltage_dependency_table {
1422 u8 count;
1423 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1424};
1425
1426struct amdgpu_vce_clock_voltage_dependency_entry {
1427 u32 ecclk;
1428 u32 evclk;
1429 u16 v;
1430};
1431
1432struct amdgpu_vce_clock_voltage_dependency_table {
1433 u8 count;
1434 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1435};
1436
1437struct amdgpu_ppm_table {
1438 u8 ppm_design;
1439 u16 cpu_core_number;
1440 u32 platform_tdp;
1441 u32 small_ac_platform_tdp;
1442 u32 platform_tdc;
1443 u32 small_ac_platform_tdc;
1444 u32 apu_tdp;
1445 u32 dgpu_tdp;
1446 u32 dgpu_ulv_power;
1447 u32 tj_max;
1448};
1449
1450struct amdgpu_cac_tdp_table {
1451 u16 tdp;
1452 u16 configurable_tdp;
1453 u16 tdc;
1454 u16 battery_power_limit;
1455 u16 small_power_limit;
1456 u16 low_cac_leakage;
1457 u16 high_cac_leakage;
1458 u16 maximum_power_delivery_limit;
1459};
1460
1461struct amdgpu_dpm_dynamic_state {
1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1463 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1464 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1465 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1466 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1467 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1468 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1469 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1470 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1471 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1472 struct amdgpu_clock_array valid_sclk_values;
1473 struct amdgpu_clock_array valid_mclk_values;
1474 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1475 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1476 u32 mclk_sclk_ratio;
1477 u32 sclk_mclk_delta;
1478 u16 vddc_vddci_delta;
1479 u16 min_vddc_for_pcie_gen2;
1480 struct amdgpu_cac_leakage_table cac_leakage_table;
1481 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1482 struct amdgpu_ppm_table *ppm_table;
1483 struct amdgpu_cac_tdp_table *cac_tdp_table;
1484};
1485
1486struct amdgpu_dpm_fan {
1487 u16 t_min;
1488 u16 t_med;
1489 u16 t_high;
1490 u16 pwm_min;
1491 u16 pwm_med;
1492 u16 pwm_high;
1493 u8 t_hyst;
1494 u32 cycle_delay;
1495 u16 t_max;
1496 u8 control_mode;
1497 u16 default_max_fan_pwm;
1498 u16 default_fan_output_sensitivity;
1499 u16 fan_output_sensitivity;
1500 bool ucode_fan_control;
1501};
1502
1503enum amdgpu_pcie_gen {
1504 AMDGPU_PCIE_GEN1 = 0,
1505 AMDGPU_PCIE_GEN2 = 1,
1506 AMDGPU_PCIE_GEN3 = 2,
1507 AMDGPU_PCIE_GEN_INVALID = 0xffff
1508};
1509
1510enum amdgpu_dpm_forced_level {
1511 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1512 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1513 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1514 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1515};
1516
1517struct amdgpu_vce_state {
1518 /* vce clocks */
1519 u32 evclk;
1520 u32 ecclk;
1521 /* gpu clocks */
1522 u32 sclk;
1523 u32 mclk;
1524 u8 clk_idx;
1525 u8 pstate;
1526};
1527
1528struct amdgpu_dpm_funcs {
1529 int (*get_temperature)(struct amdgpu_device *adev);
1530 int (*pre_set_power_state)(struct amdgpu_device *adev);
1531 int (*set_power_state)(struct amdgpu_device *adev);
1532 void (*post_set_power_state)(struct amdgpu_device *adev);
1533 void (*display_configuration_changed)(struct amdgpu_device *adev);
1534 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1535 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1536 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1537 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1538 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1539 bool (*vblank_too_short)(struct amdgpu_device *adev);
1540 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1541 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1542 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1543 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1544 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1545 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1546 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1547};
1548
1549struct amdgpu_dpm {
1550 struct amdgpu_ps *ps;
1551 /* number of valid power states */
1552 int num_ps;
1553 /* current power state that is active */
1554 struct amdgpu_ps *current_ps;
1555 /* requested power state */
1556 struct amdgpu_ps *requested_ps;
1557 /* boot up power state */
1558 struct amdgpu_ps *boot_ps;
1559 /* default uvd power state */
1560 struct amdgpu_ps *uvd_ps;
1561 /* vce requirements */
1562 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1563 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1564 enum amd_pm_state_type state;
1565 enum amd_pm_state_type user_state;
97b2e202
AD		 1566 u32 platform_caps;
1567 u32 voltage_response_time;
1568 u32 backbias_response_time;
1569 void *priv;
1570 u32 new_active_crtcs;
1571 int new_active_crtc_count;
1572 u32 current_active_crtcs;
1573 int current_active_crtc_count;
1574 struct amdgpu_dpm_dynamic_state dyn_state;
1575 struct amdgpu_dpm_fan fan;
1576 u32 tdp_limit;
1577 u32 near_tdp_limit;
1578 u32 near_tdp_limit_adjusted;
1579 u32 sq_ramping_threshold;
1580 u32 cac_leakage;
1581 u16 tdp_od_limit;
1582 u32 tdp_adjustment;
1583 u16 load_line_slope;
1584 bool power_control;
1585 bool ac_power;
1586 /* special states active */
1587 bool thermal_active;
1588 bool uvd_active;
1589 bool vce_active;
1590 /* thermal handling */
1591 struct amdgpu_dpm_thermal thermal;
1592 /* forced levels */
1593 enum amdgpu_dpm_forced_level forced_level;
1594};
1595
1596struct amdgpu_pm {
1597 struct mutex mutex;
97b2e202
AD		 1598 u32 current_sclk;
1599 u32 current_mclk;
1600 u32 default_sclk;
1601 u32 default_mclk;
1602 struct amdgpu_i2c_chan *i2c_bus;
1603 /* internal thermal controller on rv6xx+ */
1604 enum amdgpu_int_thermal_type int_thermal_type;
1605 struct device *int_hwmon_dev;
1606 /* fan control parameters */
1607 bool no_fan;
1608 u8 fan_pulses_per_revolution;
1609 u8 fan_min_rpm;
1610 u8 fan_max_rpm;
1611 /* dpm */
1612 bool dpm_enabled;
c86f5ebf 1613 bool sysfs_initialized;
97b2e202
AD		 1614 struct amdgpu_dpm dpm;
1615 const struct firmware *fw; /* SMC firmware */
1616 uint32_t fw_version;
1617 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1618 uint32_t pcie_gen_mask;
1619 uint32_t pcie_mlw_mask;
7fb72a1f 1620 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1621};
1622
d0dd7f0c
AD		 1623void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1624
97b2e202
AD		 1625/*
1626 * UVD
1627 */
1628#define AMDGPU_MAX_UVD_HANDLES 10
1629#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1630#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1631#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1632
1633struct amdgpu_uvd {
1634 struct amdgpu_bo *vcpu_bo;
1635 void *cpu_addr;
1636 uint64_t gpu_addr;
97b2e202
AD		 1637 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1638 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1639 struct delayed_work idle_work;
1640 const struct firmware *fw; /* UVD firmware */
1641 struct amdgpu_ring ring;
1642 struct amdgpu_irq_src irq;
1643 bool address_64_bit;
ead833ec 1644 struct amd_sched_entity entity;
97b2e202
AD		 1645};
1646
1647/*
1648 * VCE
1649 */
1650#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1651#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1652
6a585777
AD		 1653#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1654#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1655
97b2e202
AD		 1656struct amdgpu_vce {
1657 struct amdgpu_bo *vcpu_bo;
1658 uint64_t gpu_addr;
1659 unsigned fw_version;
1660 unsigned fb_version;
1661 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1662 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1663 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1664 struct delayed_work idle_work;
1665 const struct firmware *fw; /* VCE firmware */
1666 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1667 struct amdgpu_irq_src irq;
6a585777 1668 unsigned harvest_config;
c594989c 1669 struct amd_sched_entity entity;
97b2e202
AD		 1670};
1671
1672/*
1673 * SDMA
1674 */
c113ea1c 1675struct amdgpu_sdma_instance {
97b2e202
AD		 1676 /* SDMA firmware */
1677 const struct firmware *fw;
1678 uint32_t fw_version;
cfa2104f 1679 uint32_t feature_version;
97b2e202
AD		 1680
1681 struct amdgpu_ring ring;
18111de0 1682 bool burst_nop;
97b2e202
AD		 1683};
1684
c113ea1c
AD		 1685struct amdgpu_sdma {
1686 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1687 struct amdgpu_irq_src trap_irq;
1688 struct amdgpu_irq_src illegal_inst_irq;
1689 int num_instances;
1690};
1691
97b2e202
AD		 1692/*
1693 * Firmware
1694 */
1695struct amdgpu_firmware {
1696 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1697 bool smu_load;
1698 struct amdgpu_bo *fw_buf;
1699 unsigned int fw_size;
1700};
1701
1702/*
1703 * Benchmarking
1704 */
1705void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1706
1707
1708/*
1709 * Testing
1710 */
1711void amdgpu_test_moves(struct amdgpu_device *adev);
1712void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1713 struct amdgpu_ring *cpA,
1714 struct amdgpu_ring *cpB);
1715void amdgpu_test_syncing(struct amdgpu_device *adev);
1716
1717/*
1718 * MMU Notifier
1719 */
1720#if defined(CONFIG_MMU_NOTIFIER)
1721int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1722void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1723#else
1d1106b0 1724static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1725{
1726 return -ENODEV;
1727}
1d1106b0 1728static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1729#endif
1730
1731/*
1732 * Debugfs
1733 */
1734struct amdgpu_debugfs {
1735 struct drm_info_list *files;
1736 unsigned num_files;
1737};
1738
1739int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1740 struct drm_info_list *files,
1741 unsigned nfiles);
1742int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1743
1744#if defined(CONFIG_DEBUG_FS)
1745int amdgpu_debugfs_init(struct drm_minor *minor);
1746void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1747#endif
1748
1749/*
1750 * amdgpu smumgr functions
1751 */
1752struct amdgpu_smumgr_funcs {
1753 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1754 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1755 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1756};
1757
1758/*
1759 * amdgpu smumgr
1760 */
1761struct amdgpu_smumgr {
1762 struct amdgpu_bo *toc_buf;
1763 struct amdgpu_bo *smu_buf;
1764 /* asic priv smu data */
1765 void *priv;
1766 spinlock_t smu_lock;
1767 /* smumgr functions */
1768 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1769 /* ucode loading complete flag */
1770 uint32_t fw_flags;
1771};
1772
1773/*
1774 * ASIC specific register table accessible by UMD
1775 */
1776struct amdgpu_allowed_register_entry {
1777 uint32_t reg_offset;
1778 bool untouched;
1779 bool grbm_indexed;
1780};
1781
1782struct amdgpu_cu_info {
1783 uint32_t number; /* total active CU number */
1784 uint32_t ao_cu_mask;
1785 uint32_t bitmap[4][4];
1786};
1787
1788
1789/*
1790 * ASIC specific functions.
1791 */
1792struct amdgpu_asic_funcs {
1793 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1794 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1795 u8 *bios, u32 length_bytes);
97b2e202
AD		 1796 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1797 u32 sh_num, u32 reg_offset, u32 *value);
1798 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1799 int (*reset)(struct amdgpu_device *adev);
1800 /* wait for mc_idle */
1801 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1802 /* get the reference clock */
1803 u32 (*get_xclk)(struct amdgpu_device *adev);
1804 /* get the gpu clock counter */
1805 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1806 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1807 /* MM block clocks */
1808 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1809 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1810};
1811
1812/*
1813 * IOCTL.
1814 */
1815int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *filp);
1817int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819
1820int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1825 struct drm_file *filp);
1826int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1827 struct drm_file *filp);
1828int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1829 struct drm_file *filp);
1830int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1831 struct drm_file *filp);
1832int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1833int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1834
1835int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *filp);
1837
1838/* VRAM scratch page for HDP bug, default vram page */
1839struct amdgpu_vram_scratch {
1840 struct amdgpu_bo *robj;
1841 volatile uint32_t *ptr;
1842 u64 gpu_addr;
1843};
1844
1845/*
1846 * ACPI
1847 */
1848struct amdgpu_atif_notification_cfg {
1849 bool enabled;
1850 int command_code;
1851};
1852
1853struct amdgpu_atif_notifications {
1854 bool display_switch;
1855 bool expansion_mode_change;
1856 bool thermal_state;
1857 bool forced_power_state;
1858 bool system_power_state;
1859 bool display_conf_change;
1860 bool px_gfx_switch;
1861 bool brightness_change;
1862 bool dgpu_display_event;
1863};
1864
1865struct amdgpu_atif_functions {
1866 bool system_params;
1867 bool sbios_requests;
1868 bool select_active_disp;
1869 bool lid_state;
1870 bool get_tv_standard;
1871 bool set_tv_standard;
1872 bool get_panel_expansion_mode;
1873 bool set_panel_expansion_mode;
1874 bool temperature_change;
1875 bool graphics_device_types;
1876};
1877
1878struct amdgpu_atif {
1879 struct amdgpu_atif_notifications notifications;
1880 struct amdgpu_atif_functions functions;
1881 struct amdgpu_atif_notification_cfg notification_cfg;
1882 struct amdgpu_encoder *encoder_for_bl;
1883};
1884
1885struct amdgpu_atcs_functions {
1886 bool get_ext_state;
1887 bool pcie_perf_req;
1888 bool pcie_dev_rdy;
1889 bool pcie_bus_width;
1890};
1891
1892struct amdgpu_atcs {
1893 struct amdgpu_atcs_functions functions;
1894};
1895
d03846af
CZ		 1896/*
1897 * CGS
1898 */
1899void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1900void amdgpu_cgs_destroy_device(void *cgs_device);
1901
1902
a8fe58ce
MB		 1903/*
1904 * CGS
1905 */
1906void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1907void amdgpu_cgs_destroy_device(void *cgs_device);
1908
1909
7e471e6f
AD		 1910/* GPU virtualization */
1911struct amdgpu_virtualization {
1912 bool supports_sr_iov;
1913};
1914
97b2e202
AD		 1915/*
1916 * Core structure, functions and helpers.
1917 */
1918typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1919typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1920
1921typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1922typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1923
8faf0e08
AD		 1924struct amdgpu_ip_block_status {
1925 bool valid;
1926 bool sw;
1927 bool hw;
1928};
1929
97b2e202
AD		 1930struct amdgpu_device {
1931 struct device *dev;
1932 struct drm_device *ddev;
1933 struct pci_dev *pdev;
97b2e202 1934
a8fe58ce
MB		 1935#ifdef CONFIG_DRM_AMD_ACP
1936 struct amdgpu_acp acp;
1937#endif
1938
97b2e202 1939 /* ASIC */
2f7d10b3 1940 enum amd_asic_type asic_type;
97b2e202
AD		 1941 uint32_t family;
1942 uint32_t rev_id;
1943 uint32_t external_rev_id;
1944 unsigned long flags;
1945 int usec_timeout;
1946 const struct amdgpu_asic_funcs *asic_funcs;
1947 bool shutdown;
1948 bool suspend;
1949 bool need_dma32;
1950 bool accel_working;
97b2e202
AD		 1951 struct work_struct reset_work;
1952 struct notifier_block acpi_nb;
1953 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1954 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1955 unsigned debugfs_count;
1956#if defined(CONFIG_DEBUG_FS)
1957 struct dentry *debugfs_regs;
1958#endif
1959 struct amdgpu_atif atif;
1960 struct amdgpu_atcs atcs;
1961 struct mutex srbm_mutex;
1962 /* GRBM index mutex. Protects concurrent access to GRBM index */
1963 struct mutex grbm_idx_mutex;
1964 struct dev_pm_domain vga_pm_domain;
1965 bool have_disp_power_ref;
1966
1967 /* BIOS */
1968 uint8_t *bios;
1969 bool is_atom_bios;
1970 uint16_t bios_header_start;
1971 struct amdgpu_bo *stollen_vga_memory;
1972 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1973
1974 /* Register/doorbell mmio */
1975 resource_size_t rmmio_base;
1976 resource_size_t rmmio_size;
1977 void __iomem *rmmio;
1978 /* protects concurrent MM_INDEX/DATA based register access */
1979 spinlock_t mmio_idx_lock;
1980 /* protects concurrent SMC based register access */
1981 spinlock_t smc_idx_lock;
1982 amdgpu_rreg_t smc_rreg;
1983 amdgpu_wreg_t smc_wreg;
1984 /* protects concurrent PCIE register access */
1985 spinlock_t pcie_idx_lock;
1986 amdgpu_rreg_t pcie_rreg;
1987 amdgpu_wreg_t pcie_wreg;
1988 /* protects concurrent UVD register access */
1989 spinlock_t uvd_ctx_idx_lock;
1990 amdgpu_rreg_t uvd_ctx_rreg;
1991 amdgpu_wreg_t uvd_ctx_wreg;
1992 /* protects concurrent DIDT register access */
1993 spinlock_t didt_idx_lock;
1994 amdgpu_rreg_t didt_rreg;
1995 amdgpu_wreg_t didt_wreg;
1996 /* protects concurrent ENDPOINT (audio) register access */
1997 spinlock_t audio_endpt_idx_lock;
1998 amdgpu_block_rreg_t audio_endpt_rreg;
1999 amdgpu_block_wreg_t audio_endpt_wreg;
2000 void __iomem *rio_mem;
2001 resource_size_t rio_mem_size;
2002 struct amdgpu_doorbell doorbell;
2003
2004 /* clock/pll info */
2005 struct amdgpu_clock clock;
2006
2007 /* MC */
2008 struct amdgpu_mc mc;
2009 struct amdgpu_gart gart;
2010 struct amdgpu_dummy_page dummy_page;
2011 struct amdgpu_vm_manager vm_manager;
2012
2013 /* memory management */
2014 struct amdgpu_mman mman;
2015 struct amdgpu_gem gem;
2016 struct amdgpu_vram_scratch vram_scratch;
2017 struct amdgpu_wb wb;
2018 atomic64_t vram_usage;
2019 atomic64_t vram_vis_usage;
2020 atomic64_t gtt_usage;
2021 atomic64_t num_bytes_moved;
d94aed5a 2022 atomic_t gpu_reset_counter;
97b2e202
AD		 2023
2024 /* display */
2025 struct amdgpu_mode_info mode_info;
2026 struct work_struct hotplug_work;
2027 struct amdgpu_irq_src crtc_irq;
2028 struct amdgpu_irq_src pageflip_irq;
2029 struct amdgpu_irq_src hpd_irq;
2030
2031 /* rings */
97b2e202 2032 unsigned fence_context;
97b2e202
AD		 2033 unsigned num_rings;
2034 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2035 bool ib_pool_ready;
2036 struct amdgpu_sa_manager ring_tmp_bo;
2037
2038 /* interrupts */
2039 struct amdgpu_irq irq;
2040
1f7371b2
AD		 2041 /* powerplay */
2042 struct amd_powerplay powerplay;
e61710c5 2043 bool pp_enabled;
f3898ea1 2044 bool pp_force_state_enabled;
1f7371b2 2045
97b2e202
AD		 2046 /* dpm */
2047 struct amdgpu_pm pm;
2048 u32 cg_flags;
2049 u32 pg_flags;
2050
2051 /* amdgpu smumgr */
2052 struct amdgpu_smumgr smu;
2053
2054 /* gfx */
2055 struct amdgpu_gfx gfx;
2056
2057 /* sdma */
c113ea1c 2058 struct amdgpu_sdma sdma;
97b2e202
AD		 2059
2060 /* uvd */
2061 bool has_uvd;
2062 struct amdgpu_uvd uvd;
2063
2064 /* vce */
2065 struct amdgpu_vce vce;
2066
2067 /* firmwares */
2068 struct amdgpu_firmware firmware;
2069
2070 /* GDS */
2071 struct amdgpu_gds gds;
2072
2073 const struct amdgpu_ip_block_version *ip_blocks;
2074 int num_ip_blocks;
8faf0e08 2075 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2076 struct mutex mn_lock;
2077 DECLARE_HASHTABLE(mn_hash, 7);
2078
2079 /* tracking pinned memory */
2080 u64 vram_pin_size;
2081 u64 gart_pin_size;
130e0371
OG		 2082
2083 /* amdkfd interface */
2084 struct kfd_dev *kfd;
23ca0e4e 2085
7e471e6f 2086 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2087};
2088
2089bool amdgpu_device_is_px(struct drm_device *dev);
2090int amdgpu_device_init(struct amdgpu_device *adev,
2091 struct drm_device *ddev,
2092 struct pci_dev *pdev,
2093 uint32_t flags);
2094void amdgpu_device_fini(struct amdgpu_device *adev);
2095int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2096
2097uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2098 bool always_indirect);
2099void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2100 bool always_indirect);
2101u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2102void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2103
2104u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2105void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2106
2107/*
2108 * Cast helper
2109 */
2110extern const struct fence_ops amdgpu_fence_ops;
2111static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2112{
2113 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2114
2115 if (__f->base.ops == &amdgpu_fence_ops)
2116 return __f;
2117
2118 return NULL;
2119}
2120
2121/*
2122 * Registers read & write functions.
2123 */
2124#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2125#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2126#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2127#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2128#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2129#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2130#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2131#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2132#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2133#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2134#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2135#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2136#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2137#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2138#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2139#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2140#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2141#define WREG32_P(reg, val, mask) \
2142 do { \
2143 uint32_t tmp_ = RREG32(reg); \
2144 tmp_ &= (mask); \
2145 tmp_ |= ((val) & ~(mask)); \
2146 WREG32(reg, tmp_); \
2147 } while (0)
2148#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2149#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2150#define WREG32_PLL_P(reg, val, mask) \
2151 do { \
2152 uint32_t tmp_ = RREG32_PLL(reg); \
2153 tmp_ &= (mask); \
2154 tmp_ |= ((val) & ~(mask)); \
2155 WREG32_PLL(reg, tmp_); \
2156 } while (0)
2157#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2158#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2159#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2160
2161#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2162#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2163
2164#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2165#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2166
2167#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2168 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2169 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2170
2171#define REG_GET_FIELD(value, reg, field) \
2172 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2173
2174/*
2175 * BIOS helpers.
2176 */
2177#define RBIOS8(i) (adev->bios[i])
2178#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2179#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2180
2181/*
2182 * RING helpers.
2183 */
2184static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2185{
2186 if (ring->count_dw <= 0)
86c2b790 2187 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2188 ring->ring[ring->wptr++] = v;
2189 ring->wptr &= ring->ptr_mask;
2190 ring->count_dw--;
97b2e202
AD		 2191}
2192
c113ea1c
AD		 2193static inline struct amdgpu_sdma_instance *
2194amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2195{
2196 struct amdgpu_device *adev = ring->adev;
2197 int i;
2198
c113ea1c
AD		 2199 for (i = 0; i < adev->sdma.num_instances; i++)
2200 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2201 break;
2202
2203 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2204 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2205 else
2206 return NULL;
2207}
2208
97b2e202
AD		 2209/*
2210 * ASICs macro.
2211 */
2212#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2213#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2214#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2215#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2216#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2217#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2218#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2219#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2220#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2221#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2222#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2223#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2224#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2225#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2226#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2227#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2228#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2229#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2230#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2231#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2232#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2233#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2234#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2235#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2236#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2237#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2238#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
9e5d5309 2239#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
97b2e202
AD		 2240#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2241#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2242#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2243#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2244#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2245#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2246#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2247#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2248#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2249#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2250#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2251#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2252#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2253#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2254#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2255#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2256#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2257#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2258#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2259#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2260#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2261#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2262#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2263#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2264#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2265#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2266#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2267#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2268
2269#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2270 ((adev)->pp_enabled ? \
e61710c5 2271 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2272 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2273
2274#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2275 ((adev)->pp_enabled ? \
e61710c5 2276 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2277 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2278
2279#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2280 ((adev)->pp_enabled ? \
e61710c5 2281 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2282 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2283
2284#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2285 ((adev)->pp_enabled ? \
e61710c5 2286 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2287 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2288
2289#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2290 ((adev)->pp_enabled ? \
e61710c5 2291 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2292 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2293
1b5708ff 2294#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2295 ((adev)->pp_enabled ? \
e61710c5 2296 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2297 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2298
2299#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2300 ((adev)->pp_enabled ? \
e61710c5 2301 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2302 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2303
2304
2305#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2306 ((adev)->pp_enabled ? \
e61710c5 2307 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2308 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2309
2310#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2311 ((adev)->pp_enabled ? \
e61710c5 2312 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2313 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2314
2315#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2316 ((adev)->pp_enabled ? \
e61710c5 2317 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2318 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2319
2320#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2321 ((adev)->pp_enabled ? \
e61710c5 2322 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2323 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2324
2325#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2326 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2327
2328#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2329 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2330
f3898ea1
EH		 2331#define amdgpu_dpm_get_pp_num_states(adev, data) \
2332 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2333
2334#define amdgpu_dpm_get_pp_table(adev, table) \
2335 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2336
2337#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2338 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2339
2340#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2341 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2342
2343#define amdgpu_dpm_force_clock_level(adev, type, level) \
2344 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2345
e61710c5 2346#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2347 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2348
2349#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2350
2351/* Common functions */
2352int amdgpu_gpu_reset(struct amdgpu_device *adev);
2353void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2354bool amdgpu_card_posted(struct amdgpu_device *adev);
2355void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2356
97b2e202
AD		 2357int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2358int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2359 u32 ip_instance, u32 ring,
2360 struct amdgpu_ring **out_ring);
2361void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2362bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2363int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2364 uint32_t flags);
cc325d19 2365struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2366bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2367 unsigned long end);
97b2e202
AD		 2368bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2369uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2370 struct ttm_mem_reg *mem);
2371void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2372void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2373void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2374void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2375 const u32 *registers,
2376 const u32 array_size);
2377
2378bool amdgpu_device_is_px(struct drm_device *dev);
2379/* atpx handler */
2380#if defined(CONFIG_VGA_SWITCHEROO)
2381void amdgpu_register_atpx_handler(void);
2382void amdgpu_unregister_atpx_handler(void);
2383#else
2384static inline void amdgpu_register_atpx_handler(void) {}
2385static inline void amdgpu_unregister_atpx_handler(void) {}
2386#endif
2387
2388/*
2389 * KMS
2390 */
2391extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2392extern int amdgpu_max_kms_ioctl;
2393
2394int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2395int amdgpu_driver_unload_kms(struct drm_device *dev);
2396void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2397int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2398void amdgpu_driver_postclose_kms(struct drm_device *dev,
2399 struct drm_file *file_priv);
2400void amdgpu_driver_preclose_kms(struct drm_device *dev,
2401 struct drm_file *file_priv);
2402int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2403int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2404u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2405int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2406void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2407int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2408 int *max_error,
2409 struct timeval *vblank_time,
2410 unsigned flags);
2411long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2412 unsigned long arg);
2413
97b2e202
AD		 2414/*
2415 * functions used by amdgpu_encoder.c
2416 */
2417struct amdgpu_afmt_acr {
2418 u32 clock;
2419
2420 int n_32khz;
2421 int cts_32khz;
2422
2423 int n_44_1khz;
2424 int cts_44_1khz;
2425
2426 int n_48khz;
2427 int cts_48khz;
2428
2429};
2430
2431struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2432
2433/* amdgpu_acpi.c */
2434#if defined(CONFIG_ACPI)
2435int amdgpu_acpi_init(struct amdgpu_device *adev);
2436void amdgpu_acpi_fini(struct amdgpu_device *adev);
2437bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2438int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2439 u8 perf_req, bool advertise);
2440int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2441#else
2442static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2443static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2444#endif
2445
2446struct amdgpu_bo_va_mapping *
2447amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2448 uint64_t addr, struct amdgpu_bo **bo);
2449
2450#include "amdgpu_object.h"
2451
2452#endif
Linux kernel - Deliverables
This page took 0.214217 seconds and 5 git commands to generate.