Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
568d7c76 | 27 | #include <linux/pagemap.h> |
d38ceaf9 AD |
28 | #include <drm/drmP.h> |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
d38ceaf9 AD |
33 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, |
34 | u32 ip_instance, u32 ring, | |
35 | struct amdgpu_ring **out_ring) | |
36 | { | |
37 | /* Right now all IPs have only one instance - multiple rings. */ | |
38 | if (ip_instance != 0) { | |
39 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
40 | return -EINVAL; | |
41 | } | |
42 | ||
43 | switch (ip_type) { | |
44 | default: | |
45 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
46 | return -EINVAL; | |
47 | case AMDGPU_HW_IP_GFX: | |
48 | if (ring < adev->gfx.num_gfx_rings) { | |
49 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
50 | } else { | |
51 | DRM_ERROR("only %d gfx rings are supported now\n", | |
52 | adev->gfx.num_gfx_rings); | |
53 | return -EINVAL; | |
54 | } | |
55 | break; | |
56 | case AMDGPU_HW_IP_COMPUTE: | |
57 | if (ring < adev->gfx.num_compute_rings) { | |
58 | *out_ring = &adev->gfx.compute_ring[ring]; | |
59 | } else { | |
60 | DRM_ERROR("only %d compute rings are supported now\n", | |
61 | adev->gfx.num_compute_rings); | |
62 | return -EINVAL; | |
63 | } | |
64 | break; | |
65 | case AMDGPU_HW_IP_DMA: | |
c113ea1c AD |
66 | if (ring < adev->sdma.num_instances) { |
67 | *out_ring = &adev->sdma.instance[ring].ring; | |
d38ceaf9 | 68 | } else { |
c113ea1c AD |
69 | DRM_ERROR("only %d SDMA rings are supported\n", |
70 | adev->sdma.num_instances); | |
d38ceaf9 AD |
71 | return -EINVAL; |
72 | } | |
73 | break; | |
74 | case AMDGPU_HW_IP_UVD: | |
75 | *out_ring = &adev->uvd.ring; | |
76 | break; | |
77 | case AMDGPU_HW_IP_VCE: | |
78 | if (ring < 2){ | |
79 | *out_ring = &adev->vce.ring[ring]; | |
80 | } else { | |
81 | DRM_ERROR("only two VCE rings are supported\n"); | |
82 | return -EINVAL; | |
83 | } | |
84 | break; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
91acbeb6 | 89 | static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, |
758ac17f CK |
90 | struct drm_amdgpu_cs_chunk_fence *data, |
91 | uint32_t *offset) | |
91acbeb6 CK |
92 | { |
93 | struct drm_gem_object *gobj; | |
91acbeb6 | 94 | |
a8ad0bd8 | 95 | gobj = drm_gem_object_lookup(p->filp, data->handle); |
91acbeb6 CK |
96 | if (gobj == NULL) |
97 | return -EINVAL; | |
98 | ||
758ac17f | 99 | p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); |
91acbeb6 CK |
100 | p->uf_entry.priority = 0; |
101 | p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; | |
102 | p->uf_entry.tv.shared = true; | |
2f568dbd | 103 | p->uf_entry.user_pages = NULL; |
758ac17f | 104 | *offset = data->offset; |
91acbeb6 CK |
105 | |
106 | drm_gem_object_unreference_unlocked(gobj); | |
758ac17f CK |
107 | |
108 | if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { | |
109 | amdgpu_bo_unref(&p->uf_entry.robj); | |
110 | return -EINVAL; | |
111 | } | |
112 | ||
91acbeb6 CK |
113 | return 0; |
114 | } | |
115 | ||
d38ceaf9 AD |
116 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
117 | { | |
4c0b242c | 118 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
c5637837 | 119 | struct amdgpu_vm *vm = &fpriv->vm; |
d38ceaf9 AD |
120 | union drm_amdgpu_cs *cs = data; |
121 | uint64_t *chunk_array_user; | |
1d263474 | 122 | uint64_t *chunk_array; |
50838c8c | 123 | unsigned size, num_ibs = 0; |
758ac17f | 124 | uint32_t uf_offset = 0; |
54313503 | 125 | int i; |
1d263474 | 126 | int ret; |
d38ceaf9 | 127 | |
1d263474 DC |
128 | if (cs->in.num_chunks == 0) |
129 | return 0; | |
130 | ||
131 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
132 | if (!chunk_array) | |
133 | return -ENOMEM; | |
d38ceaf9 | 134 | |
3cb485f3 CK |
135 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
136 | if (!p->ctx) { | |
1d263474 DC |
137 | ret = -EINVAL; |
138 | goto free_chunk; | |
3cb485f3 | 139 | } |
1d263474 | 140 | |
d38ceaf9 | 141 | /* get chunks */ |
028423b0 | 142 | chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); |
d38ceaf9 AD |
143 | if (copy_from_user(chunk_array, chunk_array_user, |
144 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 | 145 | ret = -EFAULT; |
2a7d9bda | 146 | goto put_ctx; |
d38ceaf9 AD |
147 | } |
148 | ||
149 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 150 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 151 | GFP_KERNEL); |
1d263474 DC |
152 | if (!p->chunks) { |
153 | ret = -ENOMEM; | |
2a7d9bda | 154 | goto put_ctx; |
d38ceaf9 AD |
155 | } |
156 | ||
157 | for (i = 0; i < p->nchunks; i++) { | |
158 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
159 | struct drm_amdgpu_cs_chunk user_chunk; | |
160 | uint32_t __user *cdata; | |
161 | ||
028423b0 | 162 | chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; |
d38ceaf9 AD |
163 | if (copy_from_user(&user_chunk, chunk_ptr, |
164 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
165 | ret = -EFAULT; |
166 | i--; | |
167 | goto free_partial_kdata; | |
d38ceaf9 AD |
168 | } |
169 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
170 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
171 | |
172 | size = p->chunks[i].length_dw; | |
028423b0 | 173 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
d38ceaf9 AD |
174 | |
175 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
176 | if (p->chunks[i].kdata == NULL) { | |
1d263474 DC |
177 | ret = -ENOMEM; |
178 | i--; | |
179 | goto free_partial_kdata; | |
d38ceaf9 AD |
180 | } |
181 | size *= sizeof(uint32_t); | |
182 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
183 | ret = -EFAULT; |
184 | goto free_partial_kdata; | |
d38ceaf9 AD |
185 | } |
186 | ||
9a5e8fb1 CK |
187 | switch (p->chunks[i].chunk_id) { |
188 | case AMDGPU_CHUNK_ID_IB: | |
50838c8c | 189 | ++num_ibs; |
9a5e8fb1 CK |
190 | break; |
191 | ||
192 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 | 193 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
91acbeb6 | 194 | if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { |
1d263474 DC |
195 | ret = -EINVAL; |
196 | goto free_partial_kdata; | |
d38ceaf9 | 197 | } |
91acbeb6 | 198 | |
758ac17f CK |
199 | ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, |
200 | &uf_offset); | |
91acbeb6 CK |
201 | if (ret) |
202 | goto free_partial_kdata; | |
203 | ||
9a5e8fb1 CK |
204 | break; |
205 | ||
2b48d323 CK |
206 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
207 | break; | |
208 | ||
9a5e8fb1 | 209 | default: |
1d263474 DC |
210 | ret = -EINVAL; |
211 | goto free_partial_kdata; | |
d38ceaf9 AD |
212 | } |
213 | } | |
214 | ||
c5637837 | 215 | ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); |
50838c8c | 216 | if (ret) |
4acabfe3 | 217 | goto free_all_kdata; |
d38ceaf9 | 218 | |
b5f5acbc CK |
219 | if (p->uf_entry.robj) |
220 | p->job->uf_addr = uf_offset; | |
d38ceaf9 | 221 | kfree(chunk_array); |
1d263474 DC |
222 | return 0; |
223 | ||
224 | free_all_kdata: | |
225 | i = p->nchunks - 1; | |
226 | free_partial_kdata: | |
227 | for (; i >= 0; i--) | |
228 | drm_free_large(p->chunks[i].kdata); | |
229 | kfree(p->chunks); | |
2a7d9bda | 230 | put_ctx: |
1d263474 DC |
231 | amdgpu_ctx_put(p->ctx); |
232 | free_chunk: | |
233 | kfree(chunk_array); | |
234 | ||
235 | return ret; | |
d38ceaf9 AD |
236 | } |
237 | ||
238 | /* Returns how many bytes TTM can move per IB. | |
239 | */ | |
240 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
241 | { | |
242 | u64 real_vram_size = adev->mc.real_vram_size; | |
243 | u64 vram_usage = atomic64_read(&adev->vram_usage); | |
244 | ||
245 | /* This function is based on the current VRAM usage. | |
246 | * | |
247 | * - If all of VRAM is free, allow relocating the number of bytes that | |
248 | * is equal to 1/4 of the size of VRAM for this IB. | |
249 | ||
250 | * - If more than one half of VRAM is occupied, only allow relocating | |
251 | * 1 MB of data for this IB. | |
252 | * | |
253 | * - From 0 to one half of used VRAM, the threshold decreases | |
254 | * linearly. | |
255 | * __________________ | |
256 | * 1/4 of -|\ | | |
257 | * VRAM | \ | | |
258 | * | \ | | |
259 | * | \ | | |
260 | * | \ | | |
261 | * | \ | | |
262 | * | \ | | |
263 | * | \________|1 MB | |
264 | * |----------------| | |
265 | * VRAM 0 % 100 % | |
266 | * used used | |
267 | * | |
268 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
269 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
270 | * can be moved as long as the threshold isn't crossed before | |
271 | * the relocation takes place. We don't want to disable buffer | |
272 | * relocations completely. | |
273 | * | |
274 | * The idea is that buffers should be placed in VRAM at creation time | |
275 | * and TTM should only do a minimum number of relocations during | |
276 | * command submission. In practice, you need to submit at least | |
277 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
278 | * | |
279 | * Also, things can get pretty crazy under memory pressure and actual | |
280 | * VRAM usage can change a lot, so playing safe even at 50% does | |
281 | * consistently increase performance. | |
282 | */ | |
283 | ||
284 | u64 half_vram = real_vram_size >> 1; | |
285 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
286 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
287 | return max(bytes_moved_threshold, 1024*1024ull); | |
288 | } | |
289 | ||
f69f90a1 | 290 | int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, |
a5b75058 | 291 | struct list_head *validated) |
d38ceaf9 | 292 | { |
d38ceaf9 | 293 | struct amdgpu_bo_list_entry *lobj; |
f69f90a1 | 294 | u64 initial_bytes_moved; |
d38ceaf9 AD |
295 | int r; |
296 | ||
a5b75058 | 297 | list_for_each_entry(lobj, validated, tv.head) { |
36409d12 | 298 | struct amdgpu_bo *bo = lobj->robj; |
2f568dbd | 299 | bool binding_userptr = false; |
cc325d19 | 300 | struct mm_struct *usermm; |
36409d12 | 301 | uint32_t domain; |
d38ceaf9 | 302 | |
cc325d19 CK |
303 | usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); |
304 | if (usermm && usermm != current->mm) | |
305 | return -EPERM; | |
306 | ||
2f568dbd CK |
307 | /* Check if we have user pages and nobody bound the BO already */ |
308 | if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) { | |
309 | size_t size = sizeof(struct page *); | |
310 | ||
311 | size *= bo->tbo.ttm->num_pages; | |
312 | memcpy(bo->tbo.ttm->pages, lobj->user_pages, size); | |
313 | binding_userptr = true; | |
314 | } | |
315 | ||
36409d12 CK |
316 | if (bo->pin_count) |
317 | continue; | |
318 | ||
319 | /* Avoid moving this one if we have moved too many buffers | |
320 | * for this IB already. | |
321 | * | |
322 | * Note that this allows moving at least one buffer of | |
323 | * any size, because it doesn't take the current "bo" | |
324 | * into account. We don't want to disallow buffer moves | |
325 | * completely. | |
326 | */ | |
327 | if (p->bytes_moved <= p->bytes_moved_threshold) | |
1ea863fd | 328 | domain = bo->prefered_domains; |
36409d12 | 329 | else |
1ea863fd | 330 | domain = bo->allowed_domains; |
36409d12 CK |
331 | |
332 | retry: | |
333 | amdgpu_ttm_placement_from_domain(bo, domain); | |
334 | initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); | |
335 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
336 | p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - | |
337 | initial_bytes_moved; | |
338 | ||
339 | if (unlikely(r)) { | |
1ea863fd CK |
340 | if (r != -ERESTARTSYS && domain != bo->allowed_domains) { |
341 | domain = bo->allowed_domains; | |
36409d12 | 342 | goto retry; |
d38ceaf9 | 343 | } |
36409d12 | 344 | return r; |
d38ceaf9 | 345 | } |
2f568dbd CK |
346 | |
347 | if (binding_userptr) { | |
348 | drm_free_large(lobj->user_pages); | |
349 | lobj->user_pages = NULL; | |
350 | } | |
d38ceaf9 AD |
351 | } |
352 | return 0; | |
353 | } | |
354 | ||
2a7d9bda CK |
355 | static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, |
356 | union drm_amdgpu_cs *cs) | |
d38ceaf9 AD |
357 | { |
358 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
2f568dbd | 359 | struct amdgpu_bo_list_entry *e; |
a5b75058 | 360 | struct list_head duplicates; |
840d5144 | 361 | bool need_mmap_lock = false; |
2f568dbd | 362 | unsigned i, tries = 10; |
636ce25c | 363 | int r; |
d38ceaf9 | 364 | |
2a7d9bda CK |
365 | INIT_LIST_HEAD(&p->validated); |
366 | ||
367 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); | |
840d5144 | 368 | if (p->bo_list) { |
211dff55 CK |
369 | need_mmap_lock = p->bo_list->first_userptr != |
370 | p->bo_list->num_entries; | |
636ce25c | 371 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); |
840d5144 | 372 | } |
d38ceaf9 | 373 | |
3c0eea6c | 374 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 375 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 376 | |
758ac17f | 377 | if (p->uf_entry.robj) |
91acbeb6 CK |
378 | list_add(&p->uf_entry.tv.head, &p->validated); |
379 | ||
d38ceaf9 AD |
380 | if (need_mmap_lock) |
381 | down_read(¤t->mm->mmap_sem); | |
382 | ||
2f568dbd CK |
383 | while (1) { |
384 | struct list_head need_pages; | |
385 | unsigned i; | |
386 | ||
387 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
388 | &duplicates); | |
f1037950 MO |
389 | if (unlikely(r != 0)) { |
390 | DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); | |
2f568dbd | 391 | goto error_free_pages; |
f1037950 | 392 | } |
2f568dbd CK |
393 | |
394 | /* Without a BO list we don't have userptr BOs */ | |
395 | if (!p->bo_list) | |
396 | break; | |
397 | ||
398 | INIT_LIST_HEAD(&need_pages); | |
399 | for (i = p->bo_list->first_userptr; | |
400 | i < p->bo_list->num_entries; ++i) { | |
401 | ||
402 | e = &p->bo_list->array[i]; | |
403 | ||
404 | if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm, | |
405 | &e->user_invalidated) && e->user_pages) { | |
406 | ||
407 | /* We acquired a page array, but somebody | |
408 | * invalidated it. Free it an try again | |
409 | */ | |
410 | release_pages(e->user_pages, | |
411 | e->robj->tbo.ttm->num_pages, | |
412 | false); | |
413 | drm_free_large(e->user_pages); | |
414 | e->user_pages = NULL; | |
415 | } | |
416 | ||
417 | if (e->robj->tbo.ttm->state != tt_bound && | |
418 | !e->user_pages) { | |
419 | list_del(&e->tv.head); | |
420 | list_add(&e->tv.head, &need_pages); | |
421 | ||
422 | amdgpu_bo_unreserve(e->robj); | |
423 | } | |
424 | } | |
425 | ||
426 | if (list_empty(&need_pages)) | |
427 | break; | |
428 | ||
429 | /* Unreserve everything again. */ | |
430 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
431 | ||
f1037950 | 432 | /* We tried too many times, just abort */ |
2f568dbd CK |
433 | if (!--tries) { |
434 | r = -EDEADLK; | |
f1037950 | 435 | DRM_ERROR("deadlock in %s\n", __func__); |
2f568dbd CK |
436 | goto error_free_pages; |
437 | } | |
438 | ||
439 | /* Fill the page arrays for all useptrs. */ | |
440 | list_for_each_entry(e, &need_pages, tv.head) { | |
441 | struct ttm_tt *ttm = e->robj->tbo.ttm; | |
442 | ||
443 | e->user_pages = drm_calloc_large(ttm->num_pages, | |
444 | sizeof(struct page*)); | |
445 | if (!e->user_pages) { | |
446 | r = -ENOMEM; | |
f1037950 | 447 | DRM_ERROR("calloc failure in %s\n", __func__); |
2f568dbd CK |
448 | goto error_free_pages; |
449 | } | |
450 | ||
451 | r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); | |
452 | if (r) { | |
f1037950 | 453 | DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); |
2f568dbd CK |
454 | drm_free_large(e->user_pages); |
455 | e->user_pages = NULL; | |
456 | goto error_free_pages; | |
457 | } | |
458 | } | |
459 | ||
460 | /* And try again. */ | |
461 | list_splice(&need_pages, &p->validated); | |
462 | } | |
a5b75058 | 463 | |
5a712a87 | 464 | amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates); |
56467ebf | 465 | |
f69f90a1 CK |
466 | p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); |
467 | p->bytes_moved = 0; | |
468 | ||
469 | r = amdgpu_cs_list_validate(p, &duplicates); | |
f1037950 MO |
470 | if (r) { |
471 | DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n"); | |
a5b75058 | 472 | goto error_validate; |
f1037950 | 473 | } |
a5b75058 | 474 | |
f69f90a1 | 475 | r = amdgpu_cs_list_validate(p, &p->validated); |
f1037950 MO |
476 | if (r) { |
477 | DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n"); | |
a8480309 | 478 | goto error_validate; |
f1037950 | 479 | } |
a8480309 | 480 | |
5a712a87 CK |
481 | fpriv->vm.last_eviction_counter = |
482 | atomic64_read(&p->adev->num_evictions); | |
483 | ||
a8480309 | 484 | if (p->bo_list) { |
d88bf583 CK |
485 | struct amdgpu_bo *gds = p->bo_list->gds_obj; |
486 | struct amdgpu_bo *gws = p->bo_list->gws_obj; | |
487 | struct amdgpu_bo *oa = p->bo_list->oa_obj; | |
a8480309 CK |
488 | struct amdgpu_vm *vm = &fpriv->vm; |
489 | unsigned i; | |
490 | ||
491 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
492 | struct amdgpu_bo *bo = p->bo_list->array[i].robj; | |
493 | ||
494 | p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); | |
495 | } | |
d88bf583 CK |
496 | |
497 | if (gds) { | |
498 | p->job->gds_base = amdgpu_bo_gpu_offset(gds); | |
499 | p->job->gds_size = amdgpu_bo_size(gds); | |
500 | } | |
501 | if (gws) { | |
502 | p->job->gws_base = amdgpu_bo_gpu_offset(gws); | |
503 | p->job->gws_size = amdgpu_bo_size(gws); | |
504 | } | |
505 | if (oa) { | |
506 | p->job->oa_base = amdgpu_bo_gpu_offset(oa); | |
507 | p->job->oa_size = amdgpu_bo_size(oa); | |
508 | } | |
a8480309 | 509 | } |
a5b75058 | 510 | |
b5f5acbc CK |
511 | if (p->uf_entry.robj) |
512 | p->job->uf_addr += amdgpu_bo_gpu_offset(p->uf_entry.robj); | |
513 | ||
a5b75058 | 514 | error_validate: |
eceb8a15 CK |
515 | if (r) { |
516 | amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); | |
a5b75058 | 517 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); |
eceb8a15 | 518 | } |
d38ceaf9 | 519 | |
2f568dbd CK |
520 | error_free_pages: |
521 | ||
d38ceaf9 AD |
522 | if (need_mmap_lock) |
523 | up_read(¤t->mm->mmap_sem); | |
524 | ||
2f568dbd CK |
525 | if (p->bo_list) { |
526 | for (i = p->bo_list->first_userptr; | |
527 | i < p->bo_list->num_entries; ++i) { | |
528 | e = &p->bo_list->array[i]; | |
529 | ||
530 | if (!e->user_pages) | |
531 | continue; | |
532 | ||
533 | release_pages(e->user_pages, | |
534 | e->robj->tbo.ttm->num_pages, | |
535 | false); | |
536 | drm_free_large(e->user_pages); | |
537 | } | |
538 | } | |
539 | ||
d38ceaf9 AD |
540 | return r; |
541 | } | |
542 | ||
543 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
544 | { | |
545 | struct amdgpu_bo_list_entry *e; | |
546 | int r; | |
547 | ||
548 | list_for_each_entry(e, &p->validated, tv.head) { | |
549 | struct reservation_object *resv = e->robj->tbo.resv; | |
e86f9cee | 550 | r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp); |
d38ceaf9 AD |
551 | |
552 | if (r) | |
553 | return r; | |
554 | } | |
555 | return 0; | |
556 | } | |
557 | ||
984810fc CK |
558 | /** |
559 | * cs_parser_fini() - clean parser states | |
560 | * @parser: parser structure holding parsing context. | |
561 | * @error: error number | |
562 | * | |
563 | * If error is set than unvalidate buffer, otherwise just free memory | |
564 | * used by parsing context. | |
565 | **/ | |
566 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
049fc527 | 567 | { |
eceb8a15 | 568 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; |
984810fc CK |
569 | unsigned i; |
570 | ||
d38ceaf9 | 571 | if (!error) { |
28b8d66e NH |
572 | amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); |
573 | ||
d38ceaf9 | 574 | ttm_eu_fence_buffer_objects(&parser->ticket, |
984810fc CK |
575 | &parser->validated, |
576 | parser->fence); | |
d38ceaf9 AD |
577 | } else if (backoff) { |
578 | ttm_eu_backoff_reservation(&parser->ticket, | |
579 | &parser->validated); | |
580 | } | |
984810fc | 581 | fence_put(parser->fence); |
7e52a81c | 582 | |
3cb485f3 CK |
583 | if (parser->ctx) |
584 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
585 | if (parser->bo_list) |
586 | amdgpu_bo_list_put(parser->bo_list); | |
587 | ||
d38ceaf9 AD |
588 | for (i = 0; i < parser->nchunks; i++) |
589 | drm_free_large(parser->chunks[i].kdata); | |
590 | kfree(parser->chunks); | |
50838c8c CK |
591 | if (parser->job) |
592 | amdgpu_job_free(parser->job); | |
91acbeb6 | 593 | amdgpu_bo_unref(&parser->uf_entry.robj); |
d38ceaf9 AD |
594 | } |
595 | ||
596 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, | |
597 | struct amdgpu_vm *vm) | |
598 | { | |
599 | struct amdgpu_device *adev = p->adev; | |
600 | struct amdgpu_bo_va *bo_va; | |
601 | struct amdgpu_bo *bo; | |
602 | int i, r; | |
603 | ||
604 | r = amdgpu_vm_update_page_directory(adev, vm); | |
605 | if (r) | |
606 | return r; | |
607 | ||
e86f9cee | 608 | r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence); |
05906dec BN |
609 | if (r) |
610 | return r; | |
611 | ||
d38ceaf9 AD |
612 | r = amdgpu_vm_clear_freed(adev, vm); |
613 | if (r) | |
614 | return r; | |
615 | ||
616 | if (p->bo_list) { | |
617 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
618 | struct fence *f; |
619 | ||
d38ceaf9 AD |
620 | /* ignore duplicates */ |
621 | bo = p->bo_list->array[i].robj; | |
622 | if (!bo) | |
623 | continue; | |
624 | ||
625 | bo_va = p->bo_list->array[i].bo_va; | |
626 | if (bo_va == NULL) | |
627 | continue; | |
628 | ||
629 | r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); | |
630 | if (r) | |
631 | return r; | |
632 | ||
bb1e38a4 | 633 | f = bo_va->last_pt_update; |
e86f9cee | 634 | r = amdgpu_sync_fence(adev, &p->job->sync, f); |
91e1a520 CK |
635 | if (r) |
636 | return r; | |
d38ceaf9 | 637 | } |
b495bd3a CK |
638 | |
639 | } | |
640 | ||
e86f9cee | 641 | r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); |
b495bd3a CK |
642 | |
643 | if (amdgpu_vm_debug && p->bo_list) { | |
644 | /* Invalidate all BOs to test for userspace bugs */ | |
645 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
646 | /* ignore duplicates */ | |
647 | bo = p->bo_list->array[i].robj; | |
648 | if (!bo) | |
649 | continue; | |
650 | ||
651 | amdgpu_vm_bo_invalidate(adev, bo); | |
652 | } | |
d38ceaf9 AD |
653 | } |
654 | ||
b495bd3a | 655 | return r; |
d38ceaf9 AD |
656 | } |
657 | ||
658 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
b07c60c0 | 659 | struct amdgpu_cs_parser *p) |
d38ceaf9 | 660 | { |
b07c60c0 | 661 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
d38ceaf9 | 662 | struct amdgpu_vm *vm = &fpriv->vm; |
b07c60c0 | 663 | struct amdgpu_ring *ring = p->job->ring; |
d38ceaf9 AD |
664 | int i, r; |
665 | ||
d38ceaf9 | 666 | /* Only for UVD/VCE VM emulation */ |
b07c60c0 | 667 | if (ring->funcs->parse_cs) { |
9a79588c | 668 | p->job->vm = NULL; |
b07c60c0 CK |
669 | for (i = 0; i < p->job->num_ibs; i++) { |
670 | r = amdgpu_ring_parse_cs(ring, p, i); | |
d38ceaf9 AD |
671 | if (r) |
672 | return r; | |
673 | } | |
9a79588c CK |
674 | } else { |
675 | p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
281d144d | 676 | |
9a79588c CK |
677 | r = amdgpu_bo_vm_update_pte(p, vm); |
678 | if (r) | |
679 | return r; | |
680 | } | |
d38ceaf9 | 681 | |
9a79588c | 682 | return amdgpu_cs_sync_rings(p); |
d38ceaf9 AD |
683 | } |
684 | ||
685 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
686 | { | |
687 | if (r == -EDEADLK) { | |
688 | r = amdgpu_gpu_reset(adev); | |
689 | if (!r) | |
690 | r = -EAGAIN; | |
691 | } | |
692 | return r; | |
693 | } | |
694 | ||
695 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
696 | struct amdgpu_cs_parser *parser) | |
697 | { | |
698 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
699 | struct amdgpu_vm *vm = &fpriv->vm; | |
700 | int i, j; | |
701 | int r; | |
702 | ||
50838c8c | 703 | for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { |
d38ceaf9 AD |
704 | struct amdgpu_cs_chunk *chunk; |
705 | struct amdgpu_ib *ib; | |
706 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 707 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
708 | |
709 | chunk = &parser->chunks[i]; | |
50838c8c | 710 | ib = &parser->job->ibs[j]; |
d38ceaf9 AD |
711 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; |
712 | ||
713 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
714 | continue; | |
715 | ||
d38ceaf9 AD |
716 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
717 | chunk_ib->ip_instance, chunk_ib->ring, | |
718 | &ring); | |
3ccec53c | 719 | if (r) |
d38ceaf9 | 720 | return r; |
d38ceaf9 | 721 | |
b07c60c0 CK |
722 | if (parser->job->ring && parser->job->ring != ring) |
723 | return -EINVAL; | |
724 | ||
725 | parser->job->ring = ring; | |
726 | ||
d38ceaf9 | 727 | if (ring->funcs->parse_cs) { |
4802ce11 | 728 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 729 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
730 | uint64_t offset; |
731 | uint8_t *kptr; | |
3ccec53c | 732 | |
4802ce11 CK |
733 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
734 | &aobj); | |
3ccec53c MO |
735 | if (!aobj) { |
736 | DRM_ERROR("IB va_start is invalid\n"); | |
737 | return -EINVAL; | |
d38ceaf9 AD |
738 | } |
739 | ||
4802ce11 CK |
740 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
741 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
742 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
743 | return -EINVAL; | |
744 | } | |
745 | ||
3ccec53c | 746 | /* the IB should be reserved at this point */ |
4802ce11 | 747 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 748 | if (r) { |
d38ceaf9 AD |
749 | return r; |
750 | } | |
751 | ||
4802ce11 CK |
752 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
753 | kptr += chunk_ib->va_start - offset; | |
754 | ||
b07c60c0 | 755 | r = amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib); |
d38ceaf9 AD |
756 | if (r) { |
757 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
758 | return r; |
759 | } | |
760 | ||
761 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
762 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 | 763 | } else { |
b07c60c0 | 764 | r = amdgpu_ib_get(adev, vm, 0, ib); |
d38ceaf9 AD |
765 | if (r) { |
766 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
767 | return r; |
768 | } | |
769 | ||
770 | ib->gpu_addr = chunk_ib->va_start; | |
771 | } | |
d38ceaf9 | 772 | |
3ccec53c | 773 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 774 | ib->flags = chunk_ib->flags; |
d38ceaf9 AD |
775 | j++; |
776 | } | |
777 | ||
758ac17f | 778 | /* UVD & VCE fw doesn't support user fences */ |
b5f5acbc | 779 | if (parser->job->uf_addr && ( |
758ac17f CK |
780 | parser->job->ring->type == AMDGPU_RING_TYPE_UVD || |
781 | parser->job->ring->type == AMDGPU_RING_TYPE_VCE)) | |
782 | return -EINVAL; | |
d38ceaf9 AD |
783 | |
784 | return 0; | |
785 | } | |
786 | ||
2b48d323 CK |
787 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
788 | struct amdgpu_cs_parser *p) | |
789 | { | |
76a1ea61 | 790 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
791 | int i, j, r; |
792 | ||
2b48d323 CK |
793 | for (i = 0; i < p->nchunks; ++i) { |
794 | struct drm_amdgpu_cs_chunk_dep *deps; | |
795 | struct amdgpu_cs_chunk *chunk; | |
796 | unsigned num_deps; | |
797 | ||
798 | chunk = &p->chunks[i]; | |
799 | ||
800 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
801 | continue; | |
802 | ||
803 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
804 | num_deps = chunk->length_dw * 4 / | |
805 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
806 | ||
807 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 808 | struct amdgpu_ring *ring; |
76a1ea61 | 809 | struct amdgpu_ctx *ctx; |
21c16bf6 | 810 | struct fence *fence; |
2b48d323 CK |
811 | |
812 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
813 | deps[j].ip_instance, | |
814 | deps[j].ring, &ring); | |
815 | if (r) | |
816 | return r; | |
817 | ||
76a1ea61 CK |
818 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
819 | if (ctx == NULL) | |
820 | return -EINVAL; | |
821 | ||
21c16bf6 CK |
822 | fence = amdgpu_ctx_get_fence(ctx, ring, |
823 | deps[j].handle); | |
824 | if (IS_ERR(fence)) { | |
825 | r = PTR_ERR(fence); | |
76a1ea61 | 826 | amdgpu_ctx_put(ctx); |
2b48d323 | 827 | return r; |
91e1a520 | 828 | |
21c16bf6 | 829 | } else if (fence) { |
e86f9cee CK |
830 | r = amdgpu_sync_fence(adev, &p->job->sync, |
831 | fence); | |
21c16bf6 CK |
832 | fence_put(fence); |
833 | amdgpu_ctx_put(ctx); | |
834 | if (r) | |
835 | return r; | |
836 | } | |
2b48d323 CK |
837 | } |
838 | } | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
cd75dc68 CK |
843 | static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, |
844 | union drm_amdgpu_cs *cs) | |
845 | { | |
b07c60c0 | 846 | struct amdgpu_ring *ring = p->job->ring; |
92f25098 | 847 | struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; |
cd75dc68 | 848 | struct amdgpu_job *job; |
e686941a | 849 | int r; |
cd75dc68 | 850 | |
50838c8c CK |
851 | job = p->job; |
852 | p->job = NULL; | |
cd75dc68 | 853 | |
595a9cd6 | 854 | r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp); |
e686941a | 855 | if (r) { |
d71518b5 | 856 | amdgpu_job_free(job); |
e686941a | 857 | return r; |
cd75dc68 CK |
858 | } |
859 | ||
e686941a | 860 | job->owner = p->filp; |
92f25098 | 861 | job->ctx = entity->fence_context; |
595a9cd6 CK |
862 | p->fence = fence_get(&job->base.s_fence->finished); |
863 | cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); | |
758ac17f | 864 | job->uf_sequence = cs->out.handle; |
a5fb4ec2 | 865 | amdgpu_job_free_resources(job); |
cd75dc68 CK |
866 | |
867 | trace_amdgpu_cs_ioctl(job); | |
868 | amd_sched_entity_push_job(&job->base); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
049fc527 CZ |
873 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
874 | { | |
875 | struct amdgpu_device *adev = dev->dev_private; | |
876 | union drm_amdgpu_cs *cs = data; | |
7e52a81c | 877 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
878 | bool reserved_buffers = false; |
879 | int i, r; | |
049fc527 | 880 | |
0c418f10 | 881 | if (!adev->accel_working) |
049fc527 | 882 | return -EBUSY; |
2b48d323 | 883 | |
7e52a81c CK |
884 | parser.adev = adev; |
885 | parser.filp = filp; | |
886 | ||
887 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 888 | if (r) { |
049fc527 | 889 | DRM_ERROR("Failed to initialize parser !\n"); |
7e52a81c | 890 | amdgpu_cs_parser_fini(&parser, r, false); |
d38ceaf9 AD |
891 | r = amdgpu_cs_handle_lockup(adev, r); |
892 | return r; | |
893 | } | |
2a7d9bda | 894 | r = amdgpu_cs_parser_bos(&parser, data); |
26a6980c CK |
895 | if (r == -ENOMEM) |
896 | DRM_ERROR("Not enough memory for command submission!\n"); | |
897 | else if (r && r != -ERESTARTSYS) | |
898 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
899 | else if (!r) { | |
900 | reserved_buffers = true; | |
7e52a81c | 901 | r = amdgpu_cs_ib_fill(adev, &parser); |
26a6980c CK |
902 | } |
903 | ||
904 | if (!r) { | |
7e52a81c | 905 | r = amdgpu_cs_dependencies(adev, &parser); |
26a6980c CK |
906 | if (r) |
907 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
908 | } | |
909 | ||
910 | if (r) | |
911 | goto out; | |
912 | ||
50838c8c | 913 | for (i = 0; i < parser.job->num_ibs; i++) |
7e52a81c | 914 | trace_amdgpu_cs(&parser, i); |
26a6980c | 915 | |
7e52a81c | 916 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
917 | if (r) |
918 | goto out; | |
919 | ||
4acabfe3 | 920 | r = amdgpu_cs_submit(&parser, cs); |
d38ceaf9 | 921 | |
d38ceaf9 | 922 | out: |
7e52a81c | 923 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
924 | r = amdgpu_cs_handle_lockup(adev, r); |
925 | return r; | |
926 | } | |
927 | ||
928 | /** | |
929 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
930 | * | |
931 | * @dev: drm device | |
932 | * @data: data from userspace | |
933 | * @filp: file private | |
934 | * | |
935 | * Wait for the command submission identified by handle to finish. | |
936 | */ | |
937 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
938 | struct drm_file *filp) | |
939 | { | |
940 | union drm_amdgpu_wait_cs *wait = data; | |
941 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 942 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 943 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 944 | struct amdgpu_ctx *ctx; |
21c16bf6 | 945 | struct fence *fence; |
d38ceaf9 AD |
946 | long r; |
947 | ||
21c16bf6 CK |
948 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
949 | wait->in.ring, &ring); | |
950 | if (r) | |
951 | return r; | |
952 | ||
66b3cf2a JZ |
953 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
954 | if (ctx == NULL) | |
955 | return -EINVAL; | |
d38ceaf9 | 956 | |
4b559c90 CZ |
957 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
958 | if (IS_ERR(fence)) | |
959 | r = PTR_ERR(fence); | |
960 | else if (fence) { | |
961 | r = fence_wait_timeout(fence, true, timeout); | |
962 | fence_put(fence); | |
963 | } else | |
964 | r = 1; | |
049fc527 | 965 | |
66b3cf2a | 966 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
967 | if (r < 0) |
968 | return r; | |
969 | ||
970 | memset(wait, 0, sizeof(*wait)); | |
971 | wait->out.status = (r == 0); | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
976 | /** | |
977 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
978 | * | |
979 | * @parser: command submission parser context | |
980 | * @addr: VM address | |
981 | * @bo: resulting BO of the mapping found | |
982 | * | |
983 | * Search the buffer objects in the command submission context for a certain | |
984 | * virtual memory address. Returns allocation structure when found, NULL | |
985 | * otherwise. | |
986 | */ | |
987 | struct amdgpu_bo_va_mapping * | |
988 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
989 | uint64_t addr, struct amdgpu_bo **bo) | |
990 | { | |
d38ceaf9 | 991 | struct amdgpu_bo_va_mapping *mapping; |
15486fd2 CK |
992 | unsigned i; |
993 | ||
994 | if (!parser->bo_list) | |
995 | return NULL; | |
d38ceaf9 AD |
996 | |
997 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
998 | ||
15486fd2 CK |
999 | for (i = 0; i < parser->bo_list->num_entries; i++) { |
1000 | struct amdgpu_bo_list_entry *lobj; | |
1001 | ||
1002 | lobj = &parser->bo_list->array[i]; | |
1003 | if (!lobj->bo_va) | |
d38ceaf9 AD |
1004 | continue; |
1005 | ||
15486fd2 | 1006 | list_for_each_entry(mapping, &lobj->bo_va->valids, list) { |
7fc11959 CK |
1007 | if (mapping->it.start > addr || |
1008 | addr > mapping->it.last) | |
1009 | continue; | |
1010 | ||
15486fd2 | 1011 | *bo = lobj->bo_va->bo; |
7fc11959 CK |
1012 | return mapping; |
1013 | } | |
1014 | ||
15486fd2 | 1015 | list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { |
d38ceaf9 AD |
1016 | if (mapping->it.start > addr || |
1017 | addr > mapping->it.last) | |
1018 | continue; | |
1019 | ||
15486fd2 | 1020 | *bo = lobj->bo_va->bo; |
d38ceaf9 AD |
1021 | return mapping; |
1022 | } | |
1023 | } | |
1024 | ||
1025 | return NULL; | |
1026 | } |