Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: monk liu <monk.liu@amd.com> | |
23 | */ | |
24 | ||
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | ||
28 | static void amdgpu_ctx_do_release(struct kref *ref) | |
29 | { | |
30 | struct amdgpu_ctx *ctx; | |
9cb7e5a9 | 31 | struct amdgpu_device *adev; |
21c16bf6 | 32 | unsigned i, j; |
d38ceaf9 AD |
33 | |
34 | ctx = container_of(ref, struct amdgpu_ctx, refcount); | |
9cb7e5a9 CZ |
35 | adev = ctx->adev; |
36 | ||
21c16bf6 CK |
37 | |
38 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
39 | for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j) | |
40 | fence_put(ctx->rings[i].fences[j]); | |
9cb7e5a9 CZ |
41 | |
42 | if (amdgpu_enable_scheduler) { | |
43 | for (i = 0; i < adev->num_rings; i++) | |
44 | amd_context_entity_fini(adev->rings[i]->scheduler, | |
45 | &ctx->rings[i].c_entity); | |
46 | } | |
47 | ||
d38ceaf9 AD |
48 | kfree(ctx); |
49 | } | |
50 | ||
0b492a4c AD |
51 | int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, |
52 | uint32_t *id) | |
d38ceaf9 | 53 | { |
d38ceaf9 AD |
54 | struct amdgpu_ctx *ctx; |
55 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
9cb7e5a9 | 56 | int i, j, r; |
d38ceaf9 AD |
57 | |
58 | ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); | |
59 | if (!ctx) | |
60 | return -ENOMEM; | |
61 | ||
0147ee0f | 62 | mutex_lock(&mgr->lock); |
d38ceaf9 AD |
63 | r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL); |
64 | if (r < 0) { | |
0147ee0f | 65 | mutex_unlock(&mgr->lock); |
d38ceaf9 AD |
66 | kfree(ctx); |
67 | return r; | |
68 | } | |
d38ceaf9 AD |
69 | *id = (uint32_t)r; |
70 | ||
71 | memset(ctx, 0, sizeof(*ctx)); | |
9cb7e5a9 | 72 | ctx->adev = adev; |
d38ceaf9 | 73 | kref_init(&ctx->refcount); |
21c16bf6 CK |
74 | spin_lock_init(&ctx->ring_lock); |
75 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
76 | ctx->rings[i].sequence = 1; | |
0147ee0f | 77 | mutex_unlock(&mgr->lock); |
9cb7e5a9 CZ |
78 | if (amdgpu_enable_scheduler) { |
79 | /* create context entity for each ring */ | |
80 | for (i = 0; i < adev->num_rings; i++) { | |
81 | struct amd_run_queue *rq; | |
82 | if (fpriv) | |
83 | rq = &adev->rings[i]->scheduler->sched_rq; | |
84 | else | |
85 | rq = &adev->rings[i]->scheduler->kernel_rq; | |
86 | r = amd_context_entity_init(adev->rings[i]->scheduler, | |
87 | &ctx->rings[i].c_entity, | |
88 | NULL, rq, *id); | |
89 | if (r) | |
90 | break; | |
91 | } | |
92 | ||
93 | if (i < adev->num_rings) { | |
94 | for (j = 0; j < i; j++) | |
95 | amd_context_entity_fini(adev->rings[j]->scheduler, | |
96 | &ctx->rings[j].c_entity); | |
97 | kfree(ctx); | |
98 | return -EINVAL; | |
99 | } | |
100 | } | |
d38ceaf9 AD |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
105 | int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id) | |
106 | { | |
d38ceaf9 AD |
107 | struct amdgpu_ctx *ctx; |
108 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
109 | ||
0147ee0f | 110 | mutex_lock(&mgr->lock); |
d38ceaf9 | 111 | ctx = idr_find(&mgr->ctx_handles, id); |
d38ceaf9 | 112 | if (ctx) { |
0b492a4c | 113 | idr_remove(&mgr->ctx_handles, id); |
f11358da | 114 | kref_put(&ctx->refcount, amdgpu_ctx_do_release); |
0147ee0f | 115 | mutex_unlock(&mgr->lock); |
f11358da | 116 | return 0; |
d38ceaf9 | 117 | } |
0147ee0f | 118 | mutex_unlock(&mgr->lock); |
d38ceaf9 AD |
119 | return -EINVAL; |
120 | } | |
121 | ||
d94aed5a MO |
122 | static int amdgpu_ctx_query(struct amdgpu_device *adev, |
123 | struct amdgpu_fpriv *fpriv, uint32_t id, | |
124 | union drm_amdgpu_ctx_out *out) | |
d38ceaf9 AD |
125 | { |
126 | struct amdgpu_ctx *ctx; | |
127 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
d94aed5a | 128 | unsigned reset_counter; |
d38ceaf9 | 129 | |
0147ee0f | 130 | mutex_lock(&mgr->lock); |
d38ceaf9 | 131 | ctx = idr_find(&mgr->ctx_handles, id); |
d94aed5a | 132 | if (!ctx) { |
0147ee0f | 133 | mutex_unlock(&mgr->lock); |
d94aed5a | 134 | return -EINVAL; |
d38ceaf9 | 135 | } |
d94aed5a MO |
136 | |
137 | /* TODO: these two are always zero */ | |
0b492a4c AD |
138 | out->state.flags = 0x0; |
139 | out->state.hangs = 0x0; | |
d94aed5a MO |
140 | |
141 | /* determine if a GPU reset has occured since the last call */ | |
142 | reset_counter = atomic_read(&adev->gpu_reset_counter); | |
143 | /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ | |
144 | if (ctx->reset_counter == reset_counter) | |
145 | out->state.reset_status = AMDGPU_CTX_NO_RESET; | |
146 | else | |
147 | out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; | |
148 | ctx->reset_counter = reset_counter; | |
149 | ||
0147ee0f | 150 | mutex_unlock(&mgr->lock); |
d94aed5a | 151 | return 0; |
d38ceaf9 AD |
152 | } |
153 | ||
154 | void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv) | |
155 | { | |
156 | struct idr *idp; | |
157 | struct amdgpu_ctx *ctx; | |
158 | uint32_t id; | |
159 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
160 | idp = &mgr->ctx_handles; | |
161 | ||
162 | idr_for_each_entry(idp,ctx,id) { | |
163 | if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) | |
0b492a4c | 164 | DRM_ERROR("ctx %p is still alive\n", ctx); |
d38ceaf9 AD |
165 | } |
166 | ||
cdecb65b | 167 | idr_destroy(&mgr->ctx_handles); |
0147ee0f | 168 | mutex_destroy(&mgr->lock); |
d38ceaf9 AD |
169 | } |
170 | ||
171 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, | |
d94aed5a | 172 | struct drm_file *filp) |
d38ceaf9 AD |
173 | { |
174 | int r; | |
175 | uint32_t id; | |
d38ceaf9 AD |
176 | |
177 | union drm_amdgpu_ctx *args = data; | |
178 | struct amdgpu_device *adev = dev->dev_private; | |
179 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
180 | ||
181 | r = 0; | |
182 | id = args->in.ctx_id; | |
d38ceaf9 AD |
183 | |
184 | switch (args->in.op) { | |
185 | case AMDGPU_CTX_OP_ALLOC_CTX: | |
0b492a4c | 186 | r = amdgpu_ctx_alloc(adev, fpriv, &id); |
d38ceaf9 AD |
187 | args->out.alloc.ctx_id = id; |
188 | break; | |
189 | case AMDGPU_CTX_OP_FREE_CTX: | |
190 | r = amdgpu_ctx_free(adev, fpriv, id); | |
191 | break; | |
192 | case AMDGPU_CTX_OP_QUERY_STATE: | |
d94aed5a | 193 | r = amdgpu_ctx_query(adev, fpriv, id, &args->out); |
d38ceaf9 AD |
194 | break; |
195 | default: | |
196 | return -EINVAL; | |
197 | } | |
198 | ||
199 | return r; | |
200 | } | |
66b3cf2a JZ |
201 | |
202 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) | |
203 | { | |
204 | struct amdgpu_ctx *ctx; | |
205 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
206 | ||
207 | mutex_lock(&mgr->lock); | |
208 | ctx = idr_find(&mgr->ctx_handles, id); | |
209 | if (ctx) | |
210 | kref_get(&ctx->refcount); | |
211 | mutex_unlock(&mgr->lock); | |
212 | return ctx; | |
213 | } | |
214 | ||
215 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx) | |
216 | { | |
66b3cf2a JZ |
217 | if (ctx == NULL) |
218 | return -EINVAL; | |
219 | ||
66b3cf2a | 220 | kref_put(&ctx->refcount, amdgpu_ctx_do_release); |
66b3cf2a JZ |
221 | return 0; |
222 | } | |
21c16bf6 CK |
223 | |
224 | uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, | |
225 | struct fence *fence) | |
226 | { | |
227 | struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; | |
b43a9a7e CZ |
228 | uint64_t seq = 0; |
229 | unsigned idx = 0; | |
230 | struct fence *other = NULL; | |
21c16bf6 | 231 | |
b43a9a7e CZ |
232 | if (amdgpu_enable_scheduler) |
233 | seq = atomic64_read(&cring->c_entity.last_queued_v_seq); | |
234 | else | |
235 | seq = cring->sequence; | |
236 | idx = seq % AMDGPU_CTX_MAX_CS_PENDING; | |
237 | other = cring->fences[idx]; | |
21c16bf6 CK |
238 | if (other) { |
239 | signed long r; | |
240 | r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); | |
241 | if (r < 0) | |
242 | DRM_ERROR("Error (%ld) waiting for fence!\n", r); | |
243 | } | |
244 | ||
245 | fence_get(fence); | |
246 | ||
247 | spin_lock(&ctx->ring_lock); | |
248 | cring->fences[idx] = fence; | |
b43a9a7e CZ |
249 | if (!amdgpu_enable_scheduler) |
250 | cring->sequence++; | |
21c16bf6 CK |
251 | spin_unlock(&ctx->ring_lock); |
252 | ||
253 | fence_put(other); | |
254 | ||
255 | return seq; | |
256 | } | |
257 | ||
258 | struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, | |
259 | struct amdgpu_ring *ring, uint64_t seq) | |
260 | { | |
261 | struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; | |
262 | struct fence *fence; | |
b43a9a7e | 263 | uint64_t queued_seq; |
21c16bf6 CK |
264 | |
265 | spin_lock(&ctx->ring_lock); | |
b43a9a7e CZ |
266 | if (amdgpu_enable_scheduler) |
267 | queued_seq = atomic64_read(&cring->c_entity.last_queued_v_seq) + 1; | |
268 | else | |
269 | queued_seq = cring->sequence; | |
270 | ||
271 | if (seq >= queued_seq) { | |
21c16bf6 CK |
272 | spin_unlock(&ctx->ring_lock); |
273 | return ERR_PTR(-EINVAL); | |
274 | } | |
275 | ||
b43a9a7e CZ |
276 | |
277 | if (seq + AMDGPU_CTX_MAX_CS_PENDING < queued_seq) { | |
21c16bf6 CK |
278 | spin_unlock(&ctx->ring_lock); |
279 | return NULL; | |
280 | } | |
281 | ||
282 | fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]); | |
283 | spin_unlock(&ctx->ring_lock); | |
284 | ||
285 | return fence; | |
286 | } |