[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gem.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/ktime.h>
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"

void amdgpu_gem_object_free(struct drm_gem_object *gobj)
{
	struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);

	if (robj) {
		if (robj->gem_base.import_attach)
			drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
		amdgpu_mn_unregister(robj);
		amdgpu_bo_unref(&robj);
	}
}

int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
				int alignment, u32 initial_domain,
				u64 flags, bool kernel,
				struct drm_gem_object **obj)
{
	struct amdgpu_bo *robj;
	unsigned long max_size;
	int r;

	*obj = NULL;
	/* At least align on page size */
	if (alignment < PAGE_SIZE) {
		alignment = PAGE_SIZE;
	}

	if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
		/* Maximum bo size is the unpinned gtt size since we use the gtt to
		 * handle vram to system pool migrations.
		 */
		max_size = adev->mc.gtt_size - adev->gart_pin_size;
		if (size > max_size) {
			DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
				  size >> 20, max_size >> 20);
			return -ENOMEM;
		}
	}
retry:
	r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
			     flags, NULL, NULL, &robj);
	if (r) {
		if (r != -ERESTARTSYS) {
			if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
				initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
				goto retry;
			}
			DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
				  size, initial_domain, alignment, r);
		}
		return r;
	}
	*obj = &robj->gem_base;
	robj->pid = task_pid_nr(current);

	mutex_lock(&adev->gem.mutex);
	list_add_tail(&robj->list, &adev->gem.objects);
	mutex_unlock(&adev->gem.mutex);

	return 0;
}

int amdgpu_gem_init(struct amdgpu_device *adev)
{
	INIT_LIST_HEAD(&adev->gem.objects);
	return 0;
}

void amdgpu_gem_fini(struct amdgpu_device *adev)
{
	amdgpu_bo_force_delete(adev);
}

/*
 * Call from drm_gem_handle_create which appear in both new and open ioctl
 * case.
 */
int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
{
	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
	struct amdgpu_device *adev = rbo->adev;
	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
	struct amdgpu_bo_va *bo_va;
	int r;

	r = amdgpu_bo_reserve(rbo, false);
	if (r) {
		return r;
	}

	bo_va = amdgpu_vm_bo_find(vm, rbo);
	if (!bo_va) {
		bo_va = amdgpu_vm_bo_add(adev, vm, rbo);
	} else {
		++bo_va->ref_count;
	}
	amdgpu_bo_unreserve(rbo);

	return 0;
}

void amdgpu_gem_object_close(struct drm_gem_object *obj,
			     struct drm_file *file_priv)
{
	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
	struct amdgpu_device *adev = rbo->adev;
	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
	struct amdgpu_bo_va *bo_va;
	int r;

	r = amdgpu_bo_reserve(rbo, true);
	if (r) {
		dev_err(adev->dev, "leaking bo va because "
			"we fail to reserve bo (%d)\n", r);
		return;
	}
	bo_va = amdgpu_vm_bo_find(vm, rbo);
	if (bo_va) {
		if (--bo_va->ref_count == 0) {
			amdgpu_vm_bo_rmv(adev, bo_va);
		}
	}
	amdgpu_bo_unreserve(rbo);
}

static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
{
	if (r == -EDEADLK) {
		r = amdgpu_gpu_reset(adev);
		if (!r)
			r = -EAGAIN;
	}
	return r;
}

/*
 * GEM ioctls.
 */
int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_gem_create *args = data;
	uint64_t size = args->in.bo_size;
	struct drm_gem_object *gobj;
	uint32_t handle;
	bool kernel = false;
	int r;

	down_read(&adev->exclusive_lock);
	/* create a gem object to contain this object in */
	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
		kernel = true;
		if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
			size = size << AMDGPU_GDS_SHIFT;
		else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
			size = size << AMDGPU_GWS_SHIFT;
		else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
			size = size << AMDGPU_OA_SHIFT;
		else {
			r = -EINVAL;
			goto error_unlock;
		}
	}
	size = roundup(size, PAGE_SIZE);

	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
				     (u32)(0xffffffff & args->in.domains),
				     args->in.domain_flags,
				     kernel, &gobj);
	if (r)
		goto error_unlock;

	r = drm_gem_handle_create(filp, gobj, &handle);
	/* drop reference from allocate - handle holds it now */
	drm_gem_object_unreference_unlocked(gobj);
	if (r)
		goto error_unlock;

	memset(args, 0, sizeof(*args));
	args->out.handle = handle;
	up_read(&adev->exclusive_lock);
	return 0;

error_unlock:
	up_read(&adev->exclusive_lock);
	r = amdgpu_gem_handle_lockup(adev, r);
	return r;
}

int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	struct drm_amdgpu_gem_userptr *args = data;
	struct drm_gem_object *gobj;
	struct amdgpu_bo *bo;
	uint32_t handle;
	int r;

	if (offset_in_page(args->addr | args->size))
		return -EINVAL;

	/* reject unknown flag values */
	if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
	    AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
	    AMDGPU_GEM_USERPTR_REGISTER))
		return -EINVAL;

	if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
		   !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {

		/* if we want to write to it we must require anonymous
		   memory and install a MMU notifier */
		return -EACCES;
	}

	down_read(&adev->exclusive_lock);

	/* create a gem object to contain this object in */
	r = amdgpu_gem_object_create(adev, args->size, 0,
				     AMDGPU_GEM_DOMAIN_CPU, 0,
				     0, &gobj);
	if (r)
		goto handle_lockup;

	bo = gem_to_amdgpu_bo(gobj);
	r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
	if (r)
		goto release_object;

	if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
		r = amdgpu_mn_register(bo, args->addr);
		if (r)
			goto release_object;
	}

	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
		down_read(&current->mm->mmap_sem);
		r = amdgpu_bo_reserve(bo, true);
		if (r) {
			up_read(&current->mm->mmap_sem);
			goto release_object;
		}

		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
		amdgpu_bo_unreserve(bo);
		up_read(&current->mm->mmap_sem);
		if (r)
			goto release_object;
	}

	r = drm_gem_handle_create(filp, gobj, &handle);
	/* drop reference from allocate - handle holds it now */
	drm_gem_object_unreference_unlocked(gobj);
	if (r)
		goto handle_lockup;

	args->handle = handle;
	up_read(&adev->exclusive_lock);
	return 0;

release_object:
	drm_gem_object_unreference_unlocked(gobj);

handle_lockup:
	up_read(&adev->exclusive_lock);
	r = amdgpu_gem_handle_lockup(adev, r);

	return r;
}

int amdgpu_mode_dumb_mmap(struct drm_file *filp,
			  struct drm_device *dev,
			  uint32_t handle, uint64_t *offset_p)
{
	struct drm_gem_object *gobj;
	struct amdgpu_bo *robj;

	gobj = drm_gem_object_lookup(dev, filp, handle);
	if (gobj == NULL) {
		return -ENOENT;
	}
	robj = gem_to_amdgpu_bo(gobj);
	if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) ||
	    (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
		drm_gem_object_unreference_unlocked(gobj);
		return -EPERM;
	}
	*offset_p = amdgpu_bo_mmap_offset(robj);
	drm_gem_object_unreference_unlocked(gobj);
	return 0;
}

int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp)
{
	union drm_amdgpu_gem_mmap *args = data;
	uint32_t handle = args->in.handle;
	memset(args, 0, sizeof(*args));
	return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
}

/**
 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 *
 * @timeout_ns: timeout in ns
 *
 * Calculate the timeout in jiffies from an absolute timeout in ns.
 */
unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
{
	unsigned long timeout_jiffies;
	ktime_t timeout;

	/* clamp timeout if it's to large */
	if (((int64_t)timeout_ns) < 0)
		return MAX_SCHEDULE_TIMEOUT;

	timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
	if (ktime_to_ns(timeout) < 0)
		return 0;

	timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
	/*  clamp timeout to avoid unsigned-> signed overflow */
	if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
		return MAX_SCHEDULE_TIMEOUT - 1;

	return timeout_jiffies;
}

int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_gem_wait_idle *args = data;
	struct drm_gem_object *gobj;
	struct amdgpu_bo *robj;
	uint32_t handle = args->in.handle;
	unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
	int r = 0;
	long ret;

	gobj = drm_gem_object_lookup(dev, filp, handle);
	if (gobj == NULL) {
		return -ENOENT;
	}
	robj = gem_to_amdgpu_bo(gobj);
	if (timeout == 0)
		ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
	else
		ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);

	/* ret == 0 means not signaled,
	 * ret > 0 means signaled
	 * ret < 0 means interrupted before timeout
	 */
	if (ret >= 0) {
		memset(args, 0, sizeof(*args));
		args->out.status = (ret == 0);
	} else
		r = ret;

	drm_gem_object_unreference_unlocked(gobj);
	r = amdgpu_gem_handle_lockup(adev, r);
	return r;
}

int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp)
{
	struct drm_amdgpu_gem_metadata *args = data;
	struct drm_gem_object *gobj;
	struct amdgpu_bo *robj;
	int r = -1;

	DRM_DEBUG("%d \n", args->handle);
	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL)
		return -ENOENT;
	robj = gem_to_amdgpu_bo(gobj);

	r = amdgpu_bo_reserve(robj, false);
	if (unlikely(r != 0))
		goto out;

	if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
		amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
		r = amdgpu_bo_get_metadata(robj, args->data.data,
					   sizeof(args->data.data),
					   &args->data.data_size_bytes,
					   &args->data.flags);
	} else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
		r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
		if (!r)
			r = amdgpu_bo_set_metadata(robj, args->data.data,
						   args->data.data_size_bytes,
						   args->data.flags);
	}

	amdgpu_bo_unreserve(robj);
out:
	drm_gem_object_unreference_unlocked(gobj);
	return r;
}

/**
 * amdgpu_gem_va_update_vm -update the bo_va in its VM
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to update
 *
 * Update the bo_va directly after setting it's address. Errors are not
 * vital here, so they are not reported back to userspace.
 */
static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
				    struct amdgpu_bo_va *bo_va, uint32_t operation)
{
	struct ttm_validate_buffer tv, *entry;
	struct amdgpu_bo_list_entry *vm_bos;
	struct ww_acquire_ctx ticket;
	struct list_head list;
	unsigned domain;
	int r;

	INIT_LIST_HEAD(&list);

	tv.bo = &bo_va->bo->tbo;
	tv.shared = true;
	list_add(&tv.head, &list);

	vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
	if (!vm_bos)
		return;

	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
	if (r)
		goto error_free;

	list_for_each_entry(entry, &list, head) {
		domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
		/* if anything is swapped out don't swap it in here,
		   just abort and wait for the next CS */
		if (domain == AMDGPU_GEM_DOMAIN_CPU)
			goto error_unreserve;
	}

	mutex_lock(&bo_va->vm->mutex);
	r = amdgpu_vm_clear_freed(adev, bo_va->vm);
	if (r)
		goto error_unlock;


	if (operation == AMDGPU_VA_OP_MAP)
		r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);

error_unlock:
	mutex_unlock(&bo_va->vm->mutex);

error_unreserve:
	ttm_eu_backoff_reservation(&ticket, &list);

error_free:
	drm_free_large(vm_bos);

	if (r && r != -ERESTARTSYS)
		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
}


int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp)
{
	struct drm_amdgpu_gem_va *args = data;
	struct drm_gem_object *gobj;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	struct amdgpu_bo *rbo;
	struct amdgpu_bo_va *bo_va;
	uint32_t invalid_flags, va_flags = 0;
	int r = 0;

	if (!adev->vm_manager.enabled)
		return -ENOTTY;

	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
		dev_err(&dev->pdev->dev,
			"va_address 0x%lX is in reserved area 0x%X\n",
			(unsigned long)args->va_address,
			AMDGPU_VA_RESERVED_SIZE);
		return -EINVAL;
	}

	invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
			AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
	if ((args->flags & invalid_flags)) {
		dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
			args->flags, invalid_flags);
		return -EINVAL;
	}

	switch (args->operation) {
	case AMDGPU_VA_OP_MAP:
	case AMDGPU_VA_OP_UNMAP:
		break;
	default:
		dev_err(&dev->pdev->dev, "unsupported operation %d\n",
			args->operation);
		return -EINVAL;
	}

	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL)
		return -ENOENT;

	rbo = gem_to_amdgpu_bo(gobj);
	r = amdgpu_bo_reserve(rbo, false);
	if (r) {
		drm_gem_object_unreference_unlocked(gobj);
		return r;
	}

	bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
	if (!bo_va) {
		amdgpu_bo_unreserve(rbo);
		return -ENOENT;
	}

	switch (args->operation) {
	case AMDGPU_VA_OP_MAP:
		if (args->flags & AMDGPU_VM_PAGE_READABLE)
			va_flags |= AMDGPU_PTE_READABLE;
		if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
			va_flags |= AMDGPU_PTE_WRITEABLE;
		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
			va_flags |= AMDGPU_PTE_EXECUTABLE;
		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
				     args->offset_in_bo, args->map_size,
				     va_flags);
		break;
	case AMDGPU_VA_OP_UNMAP:
		r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
		break;
	default:
		break;
	}

	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
		amdgpu_gem_va_update_vm(adev, bo_va, args->operation);

	drm_gem_object_unreference_unlocked(gobj);
	return r;
}

int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
			struct drm_file *filp)
{
	struct drm_amdgpu_gem_op *args = data;
	struct drm_gem_object *gobj;
	struct amdgpu_bo *robj;
	int r;

	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL) {
		return -ENOENT;
	}
	robj = gem_to_amdgpu_bo(gobj);

	r = amdgpu_bo_reserve(robj, false);
	if (unlikely(r))
		goto out;

	switch (args->op) {
	case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
		struct drm_amdgpu_gem_create_in info;
		void __user *out = (void __user *)(long)args->value;

		info.bo_size = robj->gem_base.size;
		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
		info.domains = robj->initial_domain;
		info.domain_flags = robj->flags;
		amdgpu_bo_unreserve(robj);
		if (copy_to_user(out, &info, sizeof(info)))
			r = -EFAULT;
		break;
	}
	case AMDGPU_GEM_OP_SET_PLACEMENT:
		if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
			r = -EPERM;
			amdgpu_bo_unreserve(robj);
			break;
		}
		robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
						      AMDGPU_GEM_DOMAIN_GTT |
						      AMDGPU_GEM_DOMAIN_CPU);
		amdgpu_bo_unreserve(robj);
		break;
	default:
		amdgpu_bo_unreserve(robj);
		r = -EINVAL;
	}

out:
	drm_gem_object_unreference_unlocked(gobj);
	return r;
}

int amdgpu_mode_dumb_create(struct drm_file *file_priv,
			    struct drm_device *dev,
			    struct drm_mode_create_dumb *args)
{
	struct amdgpu_device *adev = dev->dev_private;
	struct drm_gem_object *gobj;
	uint32_t handle;
	int r;

	args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
	args->size = args->pitch * args->height;
	args->size = ALIGN(args->size, PAGE_SIZE);

	r = amdgpu_gem_object_create(adev, args->size, 0,
				     AMDGPU_GEM_DOMAIN_VRAM,
				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
				     ttm_bo_type_device,
				     &gobj);
	if (r)
		return -ENOMEM;

	r = drm_gem_handle_create(file_priv, gobj, &handle);
	/* drop reference from allocate - handle holds it now */
	drm_gem_object_unreference_unlocked(gobj);
	if (r) {
		return r;
	}
	args->handle = handle;
	return 0;
}

#if defined(CONFIG_DEBUG_FS)
static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_bo *rbo;
	unsigned i = 0;

	mutex_lock(&adev->gem.mutex);
	list_for_each_entry(rbo, &adev->gem.objects, list) {
		unsigned domain;
		const char *placement;

		domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
		switch (domain) {
		case AMDGPU_GEM_DOMAIN_VRAM:
			placement = "VRAM";
			break;
		case AMDGPU_GEM_DOMAIN_GTT:
			placement = " GTT";
			break;
		case AMDGPU_GEM_DOMAIN_CPU:
		default:
			placement = " CPU";
			break;
		}
		seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
			   i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
			   placement, (unsigned long)rbo->pid);
		i++;
	}
	mutex_unlock(&adev->gem.mutex);
	return 0;
}

static struct drm_info_list amdgpu_debugfs_gem_list[] = {
	{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
};
#endif

int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
#endif
	return 0;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <linux/ktime.h>
	29	#include <drm/drmP.h>
	30	#include <drm/amdgpu_drm.h>
	31	#include "amdgpu.h"
	32
	33	void amdgpu_gem_object_free(struct drm_gem_object *gobj)
	34	{
	35	struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
	36
	37	if (robj) {
	38	if (robj->gem_base.import_attach)
	39	drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
9298e52f	40	amdgpu_mn_unregister(robj);
d38ceaf9 AD	41	amdgpu_bo_unref(&robj);
	42	}
	43	}
	44
	45	int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
	46	int alignment, u32 initial_domain,
	47	u64 flags, bool kernel,
	48	struct drm_gem_object **obj)
	49	{
	50	struct amdgpu_bo *robj;
	51	unsigned long max_size;
	52	int r;
	53
	54	*obj = NULL;
	55	/* At least align on page size */
	56	if (alignment < PAGE_SIZE) {
	57	alignment = PAGE_SIZE;
	58	}
	59
	60	if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS \| AMDGPU_GEM_DOMAIN_GWS \| AMDGPU_GEM_DOMAIN_OA))) {
	61	/* Maximum bo size is the unpinned gtt size since we use the gtt to
	62	* handle vram to system pool migrations.
	63	*/
	64	max_size = adev->mc.gtt_size - adev->gart_pin_size;
	65	if (size > max_size) {
	66	DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
	67	size >> 20, max_size >> 20);
	68	return -ENOMEM;
	69	}
	70	}
	71	retry:
72d7668b CK	72	r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
72d7668b CK	73	flags, NULL, NULL, &robj);
d38ceaf9 AD	74	if (r) {
	75	if (r != -ERESTARTSYS) {
	76	if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
	77	initial_domain \|= AMDGPU_GEM_DOMAIN_GTT;
	78	goto retry;
	79	}
	80	DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
	81	size, initial_domain, alignment, r);
	82	}
	83	return r;
	84	}
	85	*obj = &robj->gem_base;
	86	robj->pid = task_pid_nr(current);
	87
	88	mutex_lock(&adev->gem.mutex);
	89	list_add_tail(&robj->list, &adev->gem.objects);
	90	mutex_unlock(&adev->gem.mutex);
	91
	92	return 0;
	93	}
	94
	95	int amdgpu_gem_init(struct amdgpu_device *adev)
	96	{
	97	INIT_LIST_HEAD(&adev->gem.objects);
	98	return 0;
	99	}
	100
	101	void amdgpu_gem_fini(struct amdgpu_device *adev)
	102	{
	103	amdgpu_bo_force_delete(adev);
	104	}
	105
	106	/*
	107	* Call from drm_gem_handle_create which appear in both new and open ioctl
	108	* case.
	109	*/
	110	int amdgpu_gem_object_open(struct drm_gem_object obj, struct drm_file file_priv)
	111	{
	112	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
	113	struct amdgpu_device *adev = rbo->adev;
	114	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
	115	struct amdgpu_vm *vm = &fpriv->vm;
	116	struct amdgpu_bo_va *bo_va;
	117	int r;
	118
	119	r = amdgpu_bo_reserve(rbo, false);
	120	if (r) {
	121	return r;
	122	}
	123
	124	bo_va = amdgpu_vm_bo_find(vm, rbo);
	125	if (!bo_va) {
	126	bo_va = amdgpu_vm_bo_add(adev, vm, rbo);
	127	} else {
	128	++bo_va->ref_count;
	129	}
	130	amdgpu_bo_unreserve(rbo);
	131
	132	return 0;
	133	}
	134
	135	void amdgpu_gem_object_close(struct drm_gem_object *obj,
	136	struct drm_file *file_priv)
	137	{
138	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
139	struct amdgpu_device *adev = rbo->adev;
140	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
141	struct amdgpu_vm *vm = &fpriv->vm;
142	struct amdgpu_bo_va *bo_va;
143	int r;
144
145	r = amdgpu_bo_reserve(rbo, true);
146	if (r) {
147	dev_err(adev->dev, "leaking bo va because "
148	"we fail to reserve bo (%d)\n", r);
149	return;
150	}
151	bo_va = amdgpu_vm_bo_find(vm, rbo);
152	if (bo_va) {
153	if (--bo_va->ref_count == 0) {
154	amdgpu_vm_bo_rmv(adev, bo_va);
155	}
156	}
157	amdgpu_bo_unreserve(rbo);
158	}
159
160	static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
161	{
162	if (r == -EDEADLK) {
163	r = amdgpu_gpu_reset(adev);
164	if (!r)
165	r = -EAGAIN;
166	}
167	return r;
168	}
169
170	/*
171	* GEM ioctls.
172	*/
173	int amdgpu_gem_create_ioctl(struct drm_device dev, void data,
174	struct drm_file *filp)
175	{
176	struct amdgpu_device *adev = dev->dev_private;
177	union drm_amdgpu_gem_create *args = data;
178	uint64_t size = args->in.bo_size;
179	struct drm_gem_object *gobj;
180	uint32_t handle;
181	bool kernel = false;
182	int r;
183
184	down_read(&adev->exclusive_lock);
185	/* create a gem object to contain this object in */
186	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS \|
187	AMDGPU_GEM_DOMAIN_GWS \| AMDGPU_GEM_DOMAIN_OA)) {
188	kernel = true;
189	if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
190	size = size << AMDGPU_GDS_SHIFT;
191	else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
192	size = size << AMDGPU_GWS_SHIFT;
193	else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
194	size = size << AMDGPU_OA_SHIFT;
195	else {
196	r = -EINVAL;
197	goto error_unlock;
198	}
199	}
200	size = roundup(size, PAGE_SIZE);
201
202	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
203	(u32)(0xffffffff & args->in.domains),
204	args->in.domain_flags,
205	kernel, &gobj);
206	if (r)
207	goto error_unlock;
208
209	r = drm_gem_handle_create(filp, gobj, &handle);
210	/* drop reference from allocate - handle holds it now */
211	drm_gem_object_unreference_unlocked(gobj);
212	if (r)
213	goto error_unlock;
214
215	memset(args, 0, sizeof(*args));
216	args->out.handle = handle;
217	up_read(&adev->exclusive_lock);
218	return 0;
219
220	error_unlock:
221	up_read(&adev->exclusive_lock);
222	r = amdgpu_gem_handle_lockup(adev, r);
223	return r;
224	}
225
226	int amdgpu_gem_userptr_ioctl(struct drm_device dev, void data,
227	struct drm_file *filp)
228	{
229	struct amdgpu_device *adev = dev->dev_private;
230	struct drm_amdgpu_gem_userptr *args = data;
231	struct drm_gem_object *gobj;
232	struct amdgpu_bo *bo;
233	uint32_t handle;
234	int r;
235
236	if (offset_in_page(args->addr \| args->size))
237	return -EINVAL;
238
239	/* reject unknown flag values */
240	if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY \|
241	AMDGPU_GEM_USERPTR_ANONONLY \| AMDGPU_GEM_USERPTR_VALIDATE \|
242	AMDGPU_GEM_USERPTR_REGISTER))
243	return -EINVAL;
244
245	if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) \|\|
246	!(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
247
248	/* if we want to write to it we must require anonymous
249	memory and install a MMU notifier */
250	return -EACCES;
251	}
252
253	down_read(&adev->exclusive_lock);
254
255	/* create a gem object to contain this object in */
256	r = amdgpu_gem_object_create(adev, args->size, 0,
257	AMDGPU_GEM_DOMAIN_CPU, 0,
258	0, &gobj);
259	if (r)
260	goto handle_lockup;
261
262	bo = gem_to_amdgpu_bo(gobj);
263	r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
264	if (r)
265	goto release_object;
266
267	if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
268	r = amdgpu_mn_register(bo, args->addr);
269	if (r)
270	goto release_object;
271	}
272
273	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
274	down_read(&current->mm->mmap_sem);
275	r = amdgpu_bo_reserve(bo, true);
276	if (r) {
277	up_read(&current->mm->mmap_sem);
278	goto release_object;
279	}
280
281	amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
282	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
283	amdgpu_bo_unreserve(bo);
284	up_read(&current->mm->mmap_sem);
285	if (r)
286	goto release_object;
287	}
288
289	r = drm_gem_handle_create(filp, gobj, &handle);
290	/* drop reference from allocate - handle holds it now */
291	drm_gem_object_unreference_unlocked(gobj);
292	if (r)
293	goto handle_lockup;
294
295	args->handle = handle;
296	up_read(&adev->exclusive_lock);
297	return 0;
298
299	release_object:
300	drm_gem_object_unreference_unlocked(gobj);
301
302	handle_lockup:
303	up_read(&adev->exclusive_lock);
304	r = amdgpu_gem_handle_lockup(adev, r);
305
306	return r;
307	}
308
309	int amdgpu_mode_dumb_mmap(struct drm_file *filp,
310	struct drm_device *dev,
311	uint32_t handle, uint64_t *offset_p)
312	{
313	struct drm_gem_object *gobj;
314	struct amdgpu_bo *robj;
315
316	gobj = drm_gem_object_lookup(dev, filp, handle);
317	if (gobj == NULL) {
318	return -ENOENT;
319	}
320	robj = gem_to_amdgpu_bo(gobj);
271c8125 CK	321	if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) \|\|
271c8125 CK	322	(robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
d38ceaf9 AD	323	drm_gem_object_unreference_unlocked(gobj);
	324	return -EPERM;
	325	}
	326	*offset_p = amdgpu_bo_mmap_offset(robj);
	327	drm_gem_object_unreference_unlocked(gobj);
	328	return 0;
	329	}
	330
	331	int amdgpu_gem_mmap_ioctl(struct drm_device dev, void data,
	332	struct drm_file *filp)
	333	{
	334	union drm_amdgpu_gem_mmap *args = data;
	335	uint32_t handle = args->in.handle;
	336	memset(args, 0, sizeof(*args));
	337	return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
	338	}
	339
	340	/**
	341	* amdgpu_gem_timeout - calculate jiffies timeout from absolute value
	342	*
	343	* @timeout_ns: timeout in ns
	344	*
	345	* Calculate the timeout in jiffies from an absolute timeout in ns.
	346	*/
	347	unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
	348	{
	349	unsigned long timeout_jiffies;
	350	ktime_t timeout;
	351
	352	/* clamp timeout if it's to large */
	353	if (((int64_t)timeout_ns) < 0)
	354	return MAX_SCHEDULE_TIMEOUT;
	355
0f117704	356	timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
d38ceaf9 AD	357	if (ktime_to_ns(timeout) < 0)
	358	return 0;
	359
	360	timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
	361	/* clamp timeout to avoid unsigned-> signed overflow */
	362	if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
	363	return MAX_SCHEDULE_TIMEOUT - 1;
	364
	365	return timeout_jiffies;
	366	}
	367
	368	int amdgpu_gem_wait_idle_ioctl(struct drm_device dev, void data,
	369	struct drm_file *filp)
	370	{
	371	struct amdgpu_device *adev = dev->dev_private;
	372	union drm_amdgpu_gem_wait_idle *args = data;
	373	struct drm_gem_object *gobj;
	374	struct amdgpu_bo *robj;
	375	uint32_t handle = args->in.handle;
	376	unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
	377	int r = 0;
	378	long ret;
	379
	380	gobj = drm_gem_object_lookup(dev, filp, handle);
	381	if (gobj == NULL) {
	382	return -ENOENT;
	383	}
	384	robj = gem_to_amdgpu_bo(gobj);
	385	if (timeout == 0)
	386	ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
	387	else
	388	ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
	389
	390	/* ret == 0 means not signaled,
	391	* ret > 0 means signaled
	392	* ret < 0 means interrupted before timeout
	393	*/
	394	if (ret >= 0) {
	395	memset(args, 0, sizeof(*args));
	396	args->out.status = (ret == 0);
	397	} else
	398	r = ret;
	399
	400	drm_gem_object_unreference_unlocked(gobj);
	401	r = amdgpu_gem_handle_lockup(adev, r);
	402	return r;
	403	}
	404
	405	int amdgpu_gem_metadata_ioctl(struct drm_device dev, void data,
	406	struct drm_file *filp)
	407	{
	408	struct drm_amdgpu_gem_metadata *args = data;
	409	struct drm_gem_object *gobj;
	410	struct amdgpu_bo *robj;
	411	int r = -1;
	412
	413	DRM_DEBUG("%d \n", args->handle);
	414	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	415	if (gobj == NULL)
	416	return -ENOENT;
	417	robj = gem_to_amdgpu_bo(gobj);
	418
	419	r = amdgpu_bo_reserve(robj, false);
	420	if (unlikely(r != 0))
421	goto out;
422
423	if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
424	amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
425	r = amdgpu_bo_get_metadata(robj, args->data.data,
426	sizeof(args->data.data),
427	&args->data.data_size_bytes,
428	&args->data.flags);
429	} else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
430	r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
431	if (!r)
432	r = amdgpu_bo_set_metadata(robj, args->data.data,
433	args->data.data_size_bytes,
434	args->data.flags);
435	}
436
437	amdgpu_bo_unreserve(robj);
438	out:
439	drm_gem_object_unreference_unlocked(gobj);
440	return r;
441	}
442
443	/**
444	* amdgpu_gem_va_update_vm -update the bo_va in its VM
445	*
446	* @adev: amdgpu_device pointer
447	* @bo_va: bo_va to update
448	*
449	* Update the bo_va directly after setting it's address. Errors are not
450	* vital here, so they are not reported back to userspace.
451	*/
452	static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
194a3364	453	struct amdgpu_bo_va *bo_va, uint32_t operation)
d38ceaf9 AD	454	{
	455	struct ttm_validate_buffer tv, *entry;
	456	struct amdgpu_bo_list_entry *vm_bos;
	457	struct ww_acquire_ctx ticket;
	458	struct list_head list;
	459	unsigned domain;
	460	int r;
	461
	462	INIT_LIST_HEAD(&list);
	463
	464	tv.bo = &bo_va->bo->tbo;
	465	tv.shared = true;
	466	list_add(&tv.head, &list);
	467
	468	vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
	469	if (!vm_bos)
	470	return;
	471
	472	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
	473	if (r)
	474	goto error_free;
	475
	476	list_for_each_entry(entry, &list, head) {
	477	domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
	478	/* if anything is swapped out don't swap it in here,
	479	just abort and wait for the next CS */
	480	if (domain == AMDGPU_GEM_DOMAIN_CPU)
	481	goto error_unreserve;
	482	}
	483
	484	mutex_lock(&bo_va->vm->mutex);
	485	r = amdgpu_vm_clear_freed(adev, bo_va->vm);
	486	if (r)
	487	goto error_unlock;
	488
194a3364	489
	490	if (operation == AMDGPU_VA_OP_MAP)
	491	r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
d38ceaf9 AD	492
	493	error_unlock:
	494	mutex_unlock(&bo_va->vm->mutex);
	495
	496	error_unreserve:
	497	ttm_eu_backoff_reservation(&ticket, &list);
	498
	499	error_free:
	500	drm_free_large(vm_bos);
	501
68fdd3df	502	if (r && r != -ERESTARTSYS)
d38ceaf9 AD	503	DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
	504	}
	505
	506
	507
	508	int amdgpu_gem_va_ioctl(struct drm_device dev, void data,
	509	struct drm_file *filp)
	510	{
34b5f6a6	511	struct drm_amdgpu_gem_va *args = data;
d38ceaf9 AD	512	struct drm_gem_object *gobj;
	513	struct amdgpu_device *adev = dev->dev_private;
	514	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	515	struct amdgpu_bo *rbo;
	516	struct amdgpu_bo_va *bo_va;
	517	uint32_t invalid_flags, va_flags = 0;
	518	int r = 0;
	519
34b5f6a6	520	if (!adev->vm_manager.enabled)
d38ceaf9	521	return -ENOTTY;
d38ceaf9	522
34b5f6a6	523	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
d38ceaf9 AD	524	dev_err(&dev->pdev->dev,
d38ceaf9 AD	525	"va_address 0x%lX is in reserved area 0x%X\n",
34b5f6a6	526	(unsigned long)args->va_address,
d38ceaf9	527	AMDGPU_VA_RESERVED_SIZE);
d38ceaf9 AD	528	return -EINVAL;
	529	}
	530
fc220f65 CK	531	invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE \| AMDGPU_VM_PAGE_READABLE \|
fc220f65 CK	532	AMDGPU_VM_PAGE_WRITEABLE \| AMDGPU_VM_PAGE_EXECUTABLE);
34b5f6a6	533	if ((args->flags & invalid_flags)) {
d38ceaf9	534	dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
34b5f6a6	535	args->flags, invalid_flags);
d38ceaf9 AD	536	return -EINVAL;
	537	}
	538
34b5f6a6	539	switch (args->operation) {
d38ceaf9 AD	540	case AMDGPU_VA_OP_MAP:
	541	case AMDGPU_VA_OP_UNMAP:
	542	break;
	543	default:
	544	dev_err(&dev->pdev->dev, "unsupported operation %d\n",
34b5f6a6	545	args->operation);
d38ceaf9 AD	546	return -EINVAL;
	547	}
	548
34b5f6a6 CK	549	gobj = drm_gem_object_lookup(dev, filp, args->handle);
34b5f6a6 CK	550	if (gobj == NULL)
d38ceaf9	551	return -ENOENT;
34b5f6a6	552
d38ceaf9 AD	553	rbo = gem_to_amdgpu_bo(gobj);
	554	r = amdgpu_bo_reserve(rbo, false);
	555	if (r) {
d38ceaf9 AD	556	drm_gem_object_unreference_unlocked(gobj);
	557	return r;
	558	}
34b5f6a6	559
d38ceaf9 AD	560	bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
d38ceaf9 AD	561	if (!bo_va) {
34b5f6a6	562	amdgpu_bo_unreserve(rbo);
d38ceaf9 AD	563	return -ENOENT;
	564	}
	565
34b5f6a6	566	switch (args->operation) {
d38ceaf9	567	case AMDGPU_VA_OP_MAP:
34b5f6a6	568	if (args->flags & AMDGPU_VM_PAGE_READABLE)
d38ceaf9	569	va_flags \|= AMDGPU_PTE_READABLE;
34b5f6a6	570	if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
d38ceaf9	571	va_flags \|= AMDGPU_PTE_WRITEABLE;
34b5f6a6	572	if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
d38ceaf9	573	va_flags \|= AMDGPU_PTE_EXECUTABLE;
34b5f6a6 CK	574	r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
34b5f6a6 CK	575	args->offset_in_bo, args->map_size,
9f7eb536	576	va_flags);
d38ceaf9 AD	577	break;
d38ceaf9 AD	578	case AMDGPU_VA_OP_UNMAP:
34b5f6a6	579	r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
d38ceaf9 AD	580	break;
	581	default:
	582	break;
	583	}
	584
fc220f65	585	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
194a3364	586	amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
d38ceaf9 AD	587
	588	drm_gem_object_unreference_unlocked(gobj);
	589	return r;
	590	}
	591
	592	int amdgpu_gem_op_ioctl(struct drm_device dev, void data,
	593	struct drm_file *filp)
	594	{
	595	struct drm_amdgpu_gem_op *args = data;
	596	struct drm_gem_object *gobj;
	597	struct amdgpu_bo *robj;
	598	int r;
	599
	600	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	601	if (gobj == NULL) {
	602	return -ENOENT;
	603	}
	604	robj = gem_to_amdgpu_bo(gobj);
	605
	606	r = amdgpu_bo_reserve(robj, false);
	607	if (unlikely(r))
	608	goto out;
	609
	610	switch (args->op) {
	611	case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
	612	struct drm_amdgpu_gem_create_in info;
	613	void __user out = (void __user )(long)args->value;
	614
	615	info.bo_size = robj->gem_base.size;
	616	info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
	617	info.domains = robj->initial_domain;
	618	info.domain_flags = robj->flags;
4c28fb0b	619	amdgpu_bo_unreserve(robj);
d38ceaf9 AD	620	if (copy_to_user(out, &info, sizeof(info)))
	621	r = -EFAULT;
	622	break;
	623	}
d8f65a23	624	case AMDGPU_GEM_OP_SET_PLACEMENT:
d38ceaf9 AD	625	if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
d38ceaf9 AD	626	r = -EPERM;
4c28fb0b	627	amdgpu_bo_unreserve(robj);
d38ceaf9 AD	628	break;
	629	}
	630	robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM \|
	631	AMDGPU_GEM_DOMAIN_GTT \|
	632	AMDGPU_GEM_DOMAIN_CPU);
4c28fb0b	633	amdgpu_bo_unreserve(robj);
d38ceaf9 AD	634	break;
d38ceaf9 AD	635	default:
4c28fb0b	636	amdgpu_bo_unreserve(robj);
d38ceaf9 AD	637	r = -EINVAL;
	638	}
	639
d38ceaf9 AD	640	out:
	641	drm_gem_object_unreference_unlocked(gobj);
	642	return r;
	643	}
	644
	645	int amdgpu_mode_dumb_create(struct drm_file *file_priv,
	646	struct drm_device *dev,
	647	struct drm_mode_create_dumb *args)
	648	{
	649	struct amdgpu_device *adev = dev->dev_private;
	650	struct drm_gem_object *gobj;
	651	uint32_t handle;
	652	int r;
	653
	654	args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
	655	args->size = args->pitch * args->height;
	656	args->size = ALIGN(args->size, PAGE_SIZE);
	657
	658	r = amdgpu_gem_object_create(adev, args->size, 0,
	659	AMDGPU_GEM_DOMAIN_VRAM,
857d913d AD	660	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
857d913d AD	661	ttm_bo_type_device,
d38ceaf9 AD	662	&gobj);
	663	if (r)
	664	return -ENOMEM;
	665
	666	r = drm_gem_handle_create(file_priv, gobj, &handle);
	667	/* drop reference from allocate - handle holds it now */
	668	drm_gem_object_unreference_unlocked(gobj);
	669	if (r) {
	670	return r;
	671	}
	672	args->handle = handle;
	673	return 0;
	674	}
	675
	676	#if defined(CONFIG_DEBUG_FS)
	677	static int amdgpu_debugfs_gem_info(struct seq_file m, void data)
	678	{
	679	struct drm_info_node node = (struct drm_info_node )m->private;
	680	struct drm_device *dev = node->minor->dev;
	681	struct amdgpu_device *adev = dev->dev_private;
	682	struct amdgpu_bo *rbo;
	683	unsigned i = 0;
	684
	685	mutex_lock(&adev->gem.mutex);
	686	list_for_each_entry(rbo, &adev->gem.objects, list) {
	687	unsigned domain;
	688	const char *placement;
	689
	690	domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
	691	switch (domain) {
	692	case AMDGPU_GEM_DOMAIN_VRAM:
	693	placement = "VRAM";
	694	break;
	695	case AMDGPU_GEM_DOMAIN_GTT:
	696	placement = " GTT";
	697	break;
	698	case AMDGPU_GEM_DOMAIN_CPU:
	699	default:
	700	placement = " CPU";
	701	break;
	702	}
	703	seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
	704	i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
	705	placement, (unsigned long)rbo->pid);
	706	i++;
	707	}
	708	mutex_unlock(&adev->gem.mutex);
	709	return 0;
	710	}
	711
	712	static struct drm_info_list amdgpu_debugfs_gem_list[] = {
	713	{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
	714	};
	715	#endif
	716
	717	int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
	718	{
	719	#if defined(CONFIG_DEBUG_FS)
	720	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
	721	#endif
	722	return 0;
	723	}