Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include "amdgpu.h" | |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu_uvd.h" | |
32 | #include "amdgpu_vce.h" | |
33 | ||
34 | #include <linux/vga_switcheroo.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/pm_runtime.h> | |
130e0371 | 37 | #include "amdgpu_amdkfd.h" |
d38ceaf9 AD |
38 | |
39 | #if defined(CONFIG_VGA_SWITCHEROO) | |
40 | bool amdgpu_has_atpx(void); | |
41 | #else | |
42 | static inline bool amdgpu_has_atpx(void) { return false; } | |
43 | #endif | |
44 | ||
45 | /** | |
46 | * amdgpu_driver_unload_kms - Main unload function for KMS. | |
47 | * | |
48 | * @dev: drm dev pointer | |
49 | * | |
50 | * This is the main unload function for KMS (all asics). | |
51 | * Returns 0 on success. | |
52 | */ | |
53 | int amdgpu_driver_unload_kms(struct drm_device *dev) | |
54 | { | |
55 | struct amdgpu_device *adev = dev->dev_private; | |
56 | ||
57 | if (adev == NULL) | |
58 | return 0; | |
59 | ||
60 | if (adev->rmmio == NULL) | |
61 | goto done_free; | |
62 | ||
63 | pm_runtime_get_sync(dev->dev); | |
64 | ||
130e0371 OG |
65 | amdgpu_amdkfd_device_fini(adev); |
66 | ||
d38ceaf9 AD |
67 | amdgpu_acpi_fini(adev); |
68 | ||
69 | amdgpu_device_fini(adev); | |
70 | ||
71 | done_free: | |
72 | kfree(adev); | |
73 | dev->dev_private = NULL; | |
74 | return 0; | |
75 | } | |
76 | ||
77 | /** | |
78 | * amdgpu_driver_load_kms - Main load function for KMS. | |
79 | * | |
80 | * @dev: drm dev pointer | |
81 | * @flags: device flags | |
82 | * | |
83 | * This is the main load function for KMS (all asics). | |
84 | * Returns 0 on success, error on failure. | |
85 | */ | |
86 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) | |
87 | { | |
88 | struct amdgpu_device *adev; | |
89 | int r, acpi_status; | |
90 | ||
91 | adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); | |
92 | if (adev == NULL) { | |
93 | return -ENOMEM; | |
94 | } | |
95 | dev->dev_private = (void *)adev; | |
96 | ||
97 | if ((amdgpu_runtime_pm != 0) && | |
98 | amdgpu_has_atpx() && | |
2f7d10b3 JZ |
99 | ((flags & AMD_IS_APU) == 0)) |
100 | flags |= AMD_IS_PX; | |
d38ceaf9 AD |
101 | |
102 | /* amdgpu_device_init should report only fatal error | |
103 | * like memory allocation failure or iomapping failure, | |
104 | * or memory manager initialization failure, it must | |
105 | * properly initialize the GPU MC controller and permit | |
106 | * VRAM allocation | |
107 | */ | |
108 | r = amdgpu_device_init(adev, dev, dev->pdev, flags); | |
109 | if (r) { | |
110 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); | |
111 | goto out; | |
112 | } | |
113 | ||
114 | /* Call ACPI methods: require modeset init | |
115 | * but failure is not fatal | |
116 | */ | |
117 | if (!r) { | |
118 | acpi_status = amdgpu_acpi_init(adev); | |
119 | if (acpi_status) | |
120 | dev_dbg(&dev->pdev->dev, | |
121 | "Error during ACPI methods call\n"); | |
122 | } | |
123 | ||
130e0371 OG |
124 | amdgpu_amdkfd_load_interface(adev); |
125 | amdgpu_amdkfd_device_probe(adev); | |
126 | amdgpu_amdkfd_device_init(adev); | |
127 | ||
d38ceaf9 AD |
128 | if (amdgpu_device_is_px(dev)) { |
129 | pm_runtime_use_autosuspend(dev->dev); | |
130 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
131 | pm_runtime_set_active(dev->dev); | |
132 | pm_runtime_allow(dev->dev); | |
133 | pm_runtime_mark_last_busy(dev->dev); | |
134 | pm_runtime_put_autosuspend(dev->dev); | |
135 | } | |
136 | ||
137 | out: | |
138 | if (r) | |
139 | amdgpu_driver_unload_kms(dev); | |
140 | ||
141 | ||
142 | return r; | |
143 | } | |
144 | ||
145 | /* | |
146 | * Userspace get information ioctl | |
147 | */ | |
148 | /** | |
149 | * amdgpu_info_ioctl - answer a device specific request. | |
150 | * | |
151 | * @adev: amdgpu device pointer | |
152 | * @data: request object | |
153 | * @filp: drm filp | |
154 | * | |
155 | * This function is used to pass device specific parameters to the userspace | |
156 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
157 | * etc. (all asics). | |
158 | * Returns 0 on success, -EINVAL on failure. | |
159 | */ | |
160 | static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
161 | { | |
162 | struct amdgpu_device *adev = dev->dev_private; | |
163 | struct drm_amdgpu_info *info = data; | |
164 | struct amdgpu_mode_info *minfo = &adev->mode_info; | |
165 | void __user *out = (void __user *)(long)info->return_pointer; | |
166 | uint32_t size = info->return_size; | |
167 | struct drm_crtc *crtc; | |
168 | uint32_t ui32 = 0; | |
169 | uint64_t ui64 = 0; | |
170 | int i, found; | |
171 | ||
172 | if (!info->return_size || !info->return_pointer) | |
173 | return -EINVAL; | |
174 | ||
175 | switch (info->query) { | |
176 | case AMDGPU_INFO_ACCEL_WORKING: | |
177 | ui32 = adev->accel_working; | |
178 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
179 | case AMDGPU_INFO_CRTC_FROM_ID: | |
180 | for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { | |
181 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
182 | if (crtc && crtc->base.id == info->mode_crtc.id) { | |
183 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
184 | ui32 = amdgpu_crtc->crtc_id; | |
185 | found = 1; | |
186 | break; | |
187 | } | |
188 | } | |
189 | if (!found) { | |
190 | DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); | |
191 | return -EINVAL; | |
192 | } | |
193 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
194 | case AMDGPU_INFO_HW_IP_INFO: { | |
195 | struct drm_amdgpu_info_hw_ip ip = {}; | |
5fc3aeeb | 196 | enum amd_ip_block_type type; |
d38ceaf9 | 197 | uint32_t ring_mask = 0; |
71062f43 KW |
198 | uint32_t ib_start_alignment = 0; |
199 | uint32_t ib_size_alignment = 0; | |
d38ceaf9 AD |
200 | |
201 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | |
202 | return -EINVAL; | |
203 | ||
204 | switch (info->query_hw_ip.type) { | |
205 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 206 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
207 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
208 | ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
209 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
210 | ib_size_alignment = 8; | |
d38ceaf9 AD |
211 | break; |
212 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 213 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
214 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
215 | ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
216 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
217 | ib_size_alignment = 8; | |
d38ceaf9 AD |
218 | break; |
219 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 220 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
221 | ring_mask = adev->sdma[0].ring.ready ? 1 : 0; |
222 | ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1); | |
71062f43 KW |
223 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
224 | ib_size_alignment = 1; | |
d38ceaf9 AD |
225 | break; |
226 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 227 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 | 228 | ring_mask = adev->uvd.ring.ready ? 1 : 0; |
71062f43 KW |
229 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
230 | ib_size_alignment = 8; | |
d38ceaf9 AD |
231 | break; |
232 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 233 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 AD |
234 | for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) |
235 | ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
236 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
237 | ib_size_alignment = 8; | |
d38ceaf9 AD |
238 | break; |
239 | default: | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
244 | if (adev->ip_blocks[i].type == type && | |
8faf0e08 | 245 | adev->ip_block_status[i].valid) { |
d38ceaf9 AD |
246 | ip.hw_ip_version_major = adev->ip_blocks[i].major; |
247 | ip.hw_ip_version_minor = adev->ip_blocks[i].minor; | |
248 | ip.capabilities_flags = 0; | |
249 | ip.available_rings = ring_mask; | |
71062f43 KW |
250 | ip.ib_start_alignment = ib_start_alignment; |
251 | ip.ib_size_alignment = ib_size_alignment; | |
d38ceaf9 AD |
252 | break; |
253 | } | |
254 | } | |
255 | return copy_to_user(out, &ip, | |
256 | min((size_t)size, sizeof(ip))) ? -EFAULT : 0; | |
257 | } | |
258 | case AMDGPU_INFO_HW_IP_COUNT: { | |
5fc3aeeb | 259 | enum amd_ip_block_type type; |
d38ceaf9 AD |
260 | uint32_t count = 0; |
261 | ||
262 | switch (info->query_hw_ip.type) { | |
263 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 264 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
265 | break; |
266 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 267 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
268 | break; |
269 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 270 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
271 | break; |
272 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 273 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 AD |
274 | break; |
275 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 276 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 AD |
277 | break; |
278 | default: | |
279 | return -EINVAL; | |
280 | } | |
281 | ||
282 | for (i = 0; i < adev->num_ip_blocks; i++) | |
283 | if (adev->ip_blocks[i].type == type && | |
8faf0e08 | 284 | adev->ip_block_status[i].valid && |
d38ceaf9 AD |
285 | count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
286 | count++; | |
287 | ||
288 | return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; | |
289 | } | |
290 | case AMDGPU_INFO_TIMESTAMP: | |
291 | ui64 = amdgpu_asic_get_gpu_clock_counter(adev); | |
292 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
293 | case AMDGPU_INFO_FW_VERSION: { | |
294 | struct drm_amdgpu_info_firmware fw_info; | |
295 | ||
296 | /* We only support one instance of each IP block right now. */ | |
297 | if (info->query_fw.ip_instance != 0) | |
298 | return -EINVAL; | |
299 | ||
300 | switch (info->query_fw.fw_type) { | |
301 | case AMDGPU_INFO_FW_VCE: | |
302 | fw_info.ver = adev->vce.fw_version; | |
303 | fw_info.feature = adev->vce.fb_version; | |
304 | break; | |
305 | case AMDGPU_INFO_FW_UVD: | |
306 | fw_info.ver = 0; | |
307 | fw_info.feature = 0; | |
308 | break; | |
309 | case AMDGPU_INFO_FW_GMC: | |
310 | fw_info.ver = adev->mc.fw_version; | |
311 | fw_info.feature = 0; | |
312 | break; | |
313 | case AMDGPU_INFO_FW_GFX_ME: | |
314 | fw_info.ver = adev->gfx.me_fw_version; | |
02558a00 | 315 | fw_info.feature = adev->gfx.me_feature_version; |
d38ceaf9 AD |
316 | break; |
317 | case AMDGPU_INFO_FW_GFX_PFP: | |
318 | fw_info.ver = adev->gfx.pfp_fw_version; | |
02558a00 | 319 | fw_info.feature = adev->gfx.pfp_feature_version; |
d38ceaf9 AD |
320 | break; |
321 | case AMDGPU_INFO_FW_GFX_CE: | |
322 | fw_info.ver = adev->gfx.ce_fw_version; | |
02558a00 | 323 | fw_info.feature = adev->gfx.ce_feature_version; |
d38ceaf9 AD |
324 | break; |
325 | case AMDGPU_INFO_FW_GFX_RLC: | |
326 | fw_info.ver = adev->gfx.rlc_fw_version; | |
351643d7 | 327 | fw_info.feature = adev->gfx.rlc_feature_version; |
d38ceaf9 AD |
328 | break; |
329 | case AMDGPU_INFO_FW_GFX_MEC: | |
351643d7 | 330 | if (info->query_fw.index == 0) { |
d38ceaf9 | 331 | fw_info.ver = adev->gfx.mec_fw_version; |
351643d7 JZ |
332 | fw_info.feature = adev->gfx.mec_feature_version; |
333 | } else if (info->query_fw.index == 1) { | |
d38ceaf9 | 334 | fw_info.ver = adev->gfx.mec2_fw_version; |
351643d7 JZ |
335 | fw_info.feature = adev->gfx.mec2_feature_version; |
336 | } else | |
d38ceaf9 | 337 | return -EINVAL; |
d38ceaf9 AD |
338 | break; |
339 | case AMDGPU_INFO_FW_SMC: | |
340 | fw_info.ver = adev->pm.fw_version; | |
341 | fw_info.feature = 0; | |
342 | break; | |
343 | case AMDGPU_INFO_FW_SDMA: | |
344 | if (info->query_fw.index >= 2) | |
345 | return -EINVAL; | |
346 | fw_info.ver = adev->sdma[info->query_fw.index].fw_version; | |
cfa2104f | 347 | fw_info.feature = adev->sdma[info->query_fw.index].feature_version; |
d38ceaf9 AD |
348 | break; |
349 | default: | |
350 | return -EINVAL; | |
351 | } | |
352 | return copy_to_user(out, &fw_info, | |
353 | min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; | |
354 | } | |
355 | case AMDGPU_INFO_NUM_BYTES_MOVED: | |
356 | ui64 = atomic64_read(&adev->num_bytes_moved); | |
357 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
358 | case AMDGPU_INFO_VRAM_USAGE: | |
359 | ui64 = atomic64_read(&adev->vram_usage); | |
360 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
361 | case AMDGPU_INFO_VIS_VRAM_USAGE: | |
362 | ui64 = atomic64_read(&adev->vram_vis_usage); | |
363 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
364 | case AMDGPU_INFO_GTT_USAGE: | |
365 | ui64 = atomic64_read(&adev->gtt_usage); | |
366 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
367 | case AMDGPU_INFO_GDS_CONFIG: { | |
368 | struct drm_amdgpu_info_gds gds_info; | |
369 | ||
c92b90cc | 370 | memset(&gds_info, 0, sizeof(gds_info)); |
d38ceaf9 AD |
371 | gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; |
372 | gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; | |
373 | gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; | |
374 | gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; | |
375 | gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; | |
376 | gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; | |
377 | gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; | |
378 | return copy_to_user(out, &gds_info, | |
379 | min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; | |
380 | } | |
381 | case AMDGPU_INFO_VRAM_GTT: { | |
382 | struct drm_amdgpu_info_vram_gtt vram_gtt; | |
383 | ||
384 | vram_gtt.vram_size = adev->mc.real_vram_size; | |
385 | vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; | |
386 | vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size; | |
387 | vram_gtt.gtt_size = adev->mc.gtt_size; | |
388 | vram_gtt.gtt_size -= adev->gart_pin_size; | |
389 | return copy_to_user(out, &vram_gtt, | |
390 | min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; | |
391 | } | |
392 | case AMDGPU_INFO_READ_MMR_REG: { | |
393 | unsigned n, alloc_size = info->read_mmr_reg.count * 4; | |
394 | uint32_t *regs; | |
395 | unsigned se_num = (info->read_mmr_reg.instance >> | |
396 | AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & | |
397 | AMDGPU_INFO_MMR_SE_INDEX_MASK; | |
398 | unsigned sh_num = (info->read_mmr_reg.instance >> | |
399 | AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & | |
400 | AMDGPU_INFO_MMR_SH_INDEX_MASK; | |
401 | ||
402 | /* set full masks if the userspace set all bits | |
403 | * in the bitfields */ | |
404 | if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) | |
405 | se_num = 0xffffffff; | |
406 | if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) | |
407 | sh_num = 0xffffffff; | |
408 | ||
409 | regs = kmalloc(alloc_size, GFP_KERNEL); | |
410 | if (!regs) | |
411 | return -ENOMEM; | |
412 | ||
413 | for (i = 0; i < info->read_mmr_reg.count; i++) | |
414 | if (amdgpu_asic_read_register(adev, se_num, sh_num, | |
415 | info->read_mmr_reg.dword_offset + i, | |
416 | ®s[i])) { | |
417 | DRM_DEBUG_KMS("unallowed offset %#x\n", | |
418 | info->read_mmr_reg.dword_offset + i); | |
419 | kfree(regs); | |
420 | return -EFAULT; | |
421 | } | |
422 | n = copy_to_user(out, regs, min(size, alloc_size)); | |
423 | kfree(regs); | |
424 | return n ? -EFAULT : 0; | |
425 | } | |
426 | case AMDGPU_INFO_DEV_INFO: { | |
c193fa91 | 427 | struct drm_amdgpu_info_device dev_info = {}; |
d38ceaf9 AD |
428 | struct amdgpu_cu_info cu_info; |
429 | ||
430 | dev_info.device_id = dev->pdev->device; | |
431 | dev_info.chip_rev = adev->rev_id; | |
432 | dev_info.external_rev = adev->external_rev_id; | |
433 | dev_info.pci_rev = dev->pdev->revision; | |
434 | dev_info.family = adev->family; | |
435 | dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; | |
436 | dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
437 | /* return all clocks in KHz */ | |
438 | dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; | |
32bf7106 | 439 | if (adev->pm.dpm_enabled) { |
d38ceaf9 AD |
440 | dev_info.max_engine_clock = |
441 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
32bf7106 KW |
442 | dev_info.max_memory_clock = |
443 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; | |
444 | } else { | |
d38ceaf9 | 445 | dev_info.max_engine_clock = adev->pm.default_sclk * 10; |
32bf7106 KW |
446 | dev_info.max_memory_clock = adev->pm.default_mclk * 10; |
447 | } | |
d38ceaf9 AD |
448 | dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; |
449 | dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * | |
450 | adev->gfx.config.max_shader_engines; | |
451 | dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; | |
452 | dev_info._pad = 0; | |
453 | dev_info.ids_flags = 0; | |
2f7d10b3 | 454 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 AD |
455 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; |
456 | dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; | |
02b70c8c | 457 | dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; |
d38ceaf9 AD |
458 | dev_info.virtual_address_alignment = max(PAGE_SIZE, 0x10000UL); |
459 | dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * | |
460 | AMDGPU_GPU_PAGE_SIZE; | |
461 | dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; | |
462 | ||
463 | amdgpu_asic_get_cu_info(adev, &cu_info); | |
464 | dev_info.cu_active_number = cu_info.number; | |
465 | dev_info.cu_ao_mask = cu_info.ao_cu_mask; | |
a101a899 | 466 | dev_info.ce_ram_size = adev->gfx.ce_ram_size; |
d38ceaf9 | 467 | memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); |
81c59f54 KW |
468 | dev_info.vram_type = adev->mc.vram_type; |
469 | dev_info.vram_bit_width = adev->mc.vram_width; | |
fa92754e | 470 | dev_info.vce_harvest_config = adev->vce.harvest_config; |
d38ceaf9 AD |
471 | |
472 | return copy_to_user(out, &dev_info, | |
473 | min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; | |
474 | } | |
475 | default: | |
476 | DRM_DEBUG_KMS("Invalid request %d\n", info->query); | |
477 | return -EINVAL; | |
478 | } | |
479 | return 0; | |
480 | } | |
481 | ||
482 | ||
483 | /* | |
484 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
485 | */ | |
486 | /** | |
487 | * amdgpu_driver_firstopen_kms - drm callback for last close | |
488 | * | |
489 | * @dev: drm dev pointer | |
490 | * | |
491 | * Switch vga switcheroo state after last close (all asics). | |
492 | */ | |
493 | void amdgpu_driver_lastclose_kms(struct drm_device *dev) | |
494 | { | |
495 | vga_switcheroo_process_delayed_switch(); | |
496 | } | |
497 | ||
498 | /** | |
499 | * amdgpu_driver_open_kms - drm callback for open | |
500 | * | |
501 | * @dev: drm dev pointer | |
502 | * @file_priv: drm file | |
503 | * | |
504 | * On device open, init vm on cayman+ (all asics). | |
505 | * Returns 0 on success, error on failure. | |
506 | */ | |
507 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
508 | { | |
509 | struct amdgpu_device *adev = dev->dev_private; | |
510 | struct amdgpu_fpriv *fpriv; | |
511 | int r; | |
512 | ||
513 | file_priv->driver_priv = NULL; | |
514 | ||
515 | r = pm_runtime_get_sync(dev->dev); | |
516 | if (r < 0) | |
517 | return r; | |
518 | ||
519 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
520 | if (unlikely(!fpriv)) | |
521 | return -ENOMEM; | |
522 | ||
523 | r = amdgpu_vm_init(adev, &fpriv->vm); | |
524 | if (r) | |
525 | goto error_free; | |
526 | ||
527 | mutex_init(&fpriv->bo_list_lock); | |
528 | idr_init(&fpriv->bo_list_handles); | |
529 | ||
efd4ccb5 | 530 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); |
d38ceaf9 AD |
531 | |
532 | file_priv->driver_priv = fpriv; | |
533 | ||
534 | pm_runtime_mark_last_busy(dev->dev); | |
535 | pm_runtime_put_autosuspend(dev->dev); | |
536 | return 0; | |
537 | ||
538 | error_free: | |
539 | kfree(fpriv); | |
540 | ||
541 | return r; | |
542 | } | |
543 | ||
544 | /** | |
545 | * amdgpu_driver_postclose_kms - drm callback for post close | |
546 | * | |
547 | * @dev: drm dev pointer | |
548 | * @file_priv: drm file | |
549 | * | |
550 | * On device post close, tear down vm on cayman+ (all asics). | |
551 | */ | |
552 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
553 | struct drm_file *file_priv) | |
554 | { | |
555 | struct amdgpu_device *adev = dev->dev_private; | |
556 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
557 | struct amdgpu_bo_list *list; | |
558 | int handle; | |
559 | ||
560 | if (!fpriv) | |
561 | return; | |
562 | ||
563 | amdgpu_vm_fini(adev, &fpriv->vm); | |
564 | ||
565 | idr_for_each_entry(&fpriv->bo_list_handles, list, handle) | |
566 | amdgpu_bo_list_free(list); | |
567 | ||
568 | idr_destroy(&fpriv->bo_list_handles); | |
569 | mutex_destroy(&fpriv->bo_list_lock); | |
570 | ||
efd4ccb5 | 571 | amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); |
d38ceaf9 AD |
572 | |
573 | kfree(fpriv); | |
574 | file_priv->driver_priv = NULL; | |
575 | } | |
576 | ||
577 | /** | |
578 | * amdgpu_driver_preclose_kms - drm callback for pre close | |
579 | * | |
580 | * @dev: drm dev pointer | |
581 | * @file_priv: drm file | |
582 | * | |
583 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
584 | * (all asics). | |
585 | */ | |
586 | void amdgpu_driver_preclose_kms(struct drm_device *dev, | |
587 | struct drm_file *file_priv) | |
588 | { | |
589 | struct amdgpu_device *adev = dev->dev_private; | |
590 | ||
591 | amdgpu_uvd_free_handles(adev, file_priv); | |
592 | amdgpu_vce_free_handles(adev, file_priv); | |
593 | } | |
594 | ||
595 | /* | |
596 | * VBlank related functions. | |
597 | */ | |
598 | /** | |
599 | * amdgpu_get_vblank_counter_kms - get frame count | |
600 | * | |
601 | * @dev: drm dev pointer | |
602 | * @crtc: crtc to get the frame count from | |
603 | * | |
604 | * Gets the frame count on the requested crtc (all asics). | |
605 | * Returns frame count on success, -EINVAL on failure. | |
606 | */ | |
607 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) | |
608 | { | |
609 | struct amdgpu_device *adev = dev->dev_private; | |
610 | ||
611 | if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { | |
612 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
616 | return amdgpu_display_vblank_get_counter(adev, crtc); | |
617 | } | |
618 | ||
619 | /** | |
620 | * amdgpu_enable_vblank_kms - enable vblank interrupt | |
621 | * | |
622 | * @dev: drm dev pointer | |
623 | * @crtc: crtc to enable vblank interrupt for | |
624 | * | |
625 | * Enable the interrupt on the requested crtc (all asics). | |
626 | * Returns 0 on success, -EINVAL on failure. | |
627 | */ | |
628 | int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) | |
629 | { | |
630 | struct amdgpu_device *adev = dev->dev_private; | |
631 | int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc); | |
632 | ||
633 | return amdgpu_irq_get(adev, &adev->crtc_irq, idx); | |
634 | } | |
635 | ||
636 | /** | |
637 | * amdgpu_disable_vblank_kms - disable vblank interrupt | |
638 | * | |
639 | * @dev: drm dev pointer | |
640 | * @crtc: crtc to disable vblank interrupt for | |
641 | * | |
642 | * Disable the interrupt on the requested crtc (all asics). | |
643 | */ | |
644 | void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) | |
645 | { | |
646 | struct amdgpu_device *adev = dev->dev_private; | |
647 | int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc); | |
648 | ||
649 | amdgpu_irq_put(adev, &adev->crtc_irq, idx); | |
650 | } | |
651 | ||
652 | /** | |
653 | * amdgpu_get_vblank_timestamp_kms - get vblank timestamp | |
654 | * | |
655 | * @dev: drm dev pointer | |
656 | * @crtc: crtc to get the timestamp for | |
657 | * @max_error: max error | |
658 | * @vblank_time: time value | |
659 | * @flags: flags passed to the driver | |
660 | * | |
661 | * Gets the timestamp on the requested crtc based on the | |
662 | * scanout position. (all asics). | |
663 | * Returns postive status flags on success, negative error on failure. | |
664 | */ | |
665 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, | |
666 | int *max_error, | |
667 | struct timeval *vblank_time, | |
668 | unsigned flags) | |
669 | { | |
670 | struct drm_crtc *drmcrtc; | |
671 | struct amdgpu_device *adev = dev->dev_private; | |
672 | ||
673 | if (crtc < 0 || crtc >= dev->num_crtcs) { | |
674 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
675 | return -EINVAL; | |
676 | } | |
677 | ||
678 | /* Get associated drm_crtc: */ | |
679 | drmcrtc = &adev->mode_info.crtcs[crtc]->base; | |
680 | ||
681 | /* Helper routine in DRM core does all the work: */ | |
682 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, | |
683 | vblank_time, flags, | |
684 | drmcrtc, &drmcrtc->hwmode); | |
685 | } | |
686 | ||
687 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { | |
688 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
689 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
690 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
691 | /* KMS */ | |
692 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
693 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
694 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
695 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
696 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
697 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
698 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
699 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
700 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
701 | }; | |
702 | int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); |