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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <christian.koenig@amd.com> | |
29 | */ | |
30 | ||
31 | #include <drm/drmP.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /** | |
36 | * amdgpu_sync_create - zero init sync object | |
37 | * | |
38 | * @sync: sync object to initialize | |
39 | * | |
40 | * Just clear the sync object for now. | |
41 | */ | |
42 | void amdgpu_sync_create(struct amdgpu_sync *sync) | |
43 | { | |
44 | unsigned i; | |
45 | ||
46 | for (i = 0; i < AMDGPU_NUM_SYNCS; ++i) | |
47 | sync->semaphores[i] = NULL; | |
48 | ||
49 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
50 | sync->sync_to[i] = NULL; | |
51 | ||
52 | sync->last_vm_update = NULL; | |
53 | } | |
54 | ||
55 | /** | |
91e1a520 | 56 | * amdgpu_sync_fence - remember to sync to this fence |
d38ceaf9 AD |
57 | * |
58 | * @sync: sync object to add fence to | |
59 | * @fence: fence to sync to | |
60 | * | |
d38ceaf9 | 61 | */ |
91e1a520 CK |
62 | int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
63 | struct fence *f) | |
d38ceaf9 | 64 | { |
91e1a520 | 65 | struct amdgpu_fence *fence; |
d38ceaf9 AD |
66 | struct amdgpu_fence *other; |
67 | ||
91e1a520 CK |
68 | if (!f) |
69 | return 0; | |
70 | ||
71 | fence = to_amdgpu_fence(f); | |
72 | if (!fence || fence->ring->adev != adev) | |
73 | return fence_wait(f, true); | |
d38ceaf9 AD |
74 | |
75 | other = sync->sync_to[fence->ring->idx]; | |
76 | sync->sync_to[fence->ring->idx] = amdgpu_fence_ref( | |
77 | amdgpu_fence_later(fence, other)); | |
78 | amdgpu_fence_unref(&other); | |
79 | ||
80 | if (fence->owner == AMDGPU_FENCE_OWNER_VM) { | |
81 | other = sync->last_vm_update; | |
82 | sync->last_vm_update = amdgpu_fence_ref( | |
83 | amdgpu_fence_later(fence, other)); | |
84 | amdgpu_fence_unref(&other); | |
85 | } | |
91e1a520 CK |
86 | |
87 | return 0; | |
d38ceaf9 AD |
88 | } |
89 | ||
90 | /** | |
91 | * amdgpu_sync_resv - use the semaphores to sync to a reservation object | |
92 | * | |
93 | * @sync: sync object to add fences from reservation object to | |
94 | * @resv: reservation object with embedded fence | |
95 | * @shared: true if we should only sync to the exclusive fence | |
96 | * | |
97 | * Sync to the fence using the semaphore objects | |
98 | */ | |
99 | int amdgpu_sync_resv(struct amdgpu_device *adev, | |
100 | struct amdgpu_sync *sync, | |
101 | struct reservation_object *resv, | |
102 | void *owner) | |
103 | { | |
104 | struct reservation_object_list *flist; | |
105 | struct fence *f; | |
106 | struct amdgpu_fence *fence; | |
107 | unsigned i; | |
108 | int r = 0; | |
109 | ||
4b095304 JZ |
110 | if (resv == NULL) |
111 | return -EINVAL; | |
112 | ||
d38ceaf9 AD |
113 | /* always sync to the exclusive fence */ |
114 | f = reservation_object_get_excl(resv); | |
91e1a520 | 115 | r = amdgpu_sync_fence(adev, sync, f); |
d38ceaf9 AD |
116 | |
117 | flist = reservation_object_get_list(resv); | |
118 | if (!flist || r) | |
119 | return r; | |
120 | ||
121 | for (i = 0; i < flist->shared_count; ++i) { | |
122 | f = rcu_dereference_protected(flist->shared[i], | |
123 | reservation_object_held(resv)); | |
4b095304 | 124 | fence = f ? to_amdgpu_fence(f) : NULL; |
91e1a520 CK |
125 | if (fence && fence->ring->adev == adev && |
126 | fence->owner == owner && | |
127 | fence->owner != AMDGPU_FENCE_OWNER_UNDEFINED) | |
128 | continue; | |
129 | ||
130 | r = amdgpu_sync_fence(adev, sync, f); | |
131 | if (r) | |
132 | break; | |
d38ceaf9 AD |
133 | } |
134 | return r; | |
135 | } | |
136 | ||
137 | /** | |
138 | * amdgpu_sync_rings - sync ring to all registered fences | |
139 | * | |
140 | * @sync: sync object to use | |
141 | * @ring: ring that needs sync | |
142 | * | |
143 | * Ensure that all registered fences are signaled before letting | |
144 | * the ring continue. The caller must hold the ring lock. | |
145 | */ | |
146 | int amdgpu_sync_rings(struct amdgpu_sync *sync, | |
147 | struct amdgpu_ring *ring) | |
148 | { | |
149 | struct amdgpu_device *adev = ring->adev; | |
150 | unsigned count = 0; | |
151 | int i, r; | |
152 | ||
153 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
154 | struct amdgpu_fence *fence = sync->sync_to[i]; | |
155 | struct amdgpu_semaphore *semaphore; | |
156 | struct amdgpu_ring *other = adev->rings[i]; | |
157 | ||
158 | /* check if we really need to sync */ | |
159 | if (!amdgpu_fence_need_sync(fence, ring)) | |
160 | continue; | |
161 | ||
162 | /* prevent GPU deadlocks */ | |
163 | if (!other->ready) { | |
164 | dev_err(adev->dev, "Syncing to a disabled ring!"); | |
165 | return -EINVAL; | |
166 | } | |
167 | ||
2c4888a0 | 168 | if (amdgpu_enable_scheduler || (count >= AMDGPU_NUM_SYNCS)) { |
d38ceaf9 AD |
169 | /* not enough room, wait manually */ |
170 | r = amdgpu_fence_wait(fence, false); | |
171 | if (r) | |
172 | return r; | |
173 | continue; | |
174 | } | |
175 | r = amdgpu_semaphore_create(adev, &semaphore); | |
176 | if (r) | |
177 | return r; | |
178 | ||
179 | sync->semaphores[count++] = semaphore; | |
180 | ||
181 | /* allocate enough space for sync command */ | |
182 | r = amdgpu_ring_alloc(other, 16); | |
183 | if (r) | |
184 | return r; | |
185 | ||
186 | /* emit the signal semaphore */ | |
187 | if (!amdgpu_semaphore_emit_signal(other, semaphore)) { | |
188 | /* signaling wasn't successful wait manually */ | |
189 | amdgpu_ring_undo(other); | |
190 | r = amdgpu_fence_wait(fence, false); | |
191 | if (r) | |
192 | return r; | |
193 | continue; | |
194 | } | |
195 | ||
196 | /* we assume caller has already allocated space on waiters ring */ | |
197 | if (!amdgpu_semaphore_emit_wait(ring, semaphore)) { | |
198 | /* waiting wasn't successful wait manually */ | |
199 | amdgpu_ring_undo(other); | |
200 | r = amdgpu_fence_wait(fence, false); | |
201 | if (r) | |
202 | return r; | |
203 | continue; | |
204 | } | |
205 | ||
206 | amdgpu_ring_commit(other); | |
207 | amdgpu_fence_note_sync(fence, ring); | |
208 | } | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | /** | |
214 | * amdgpu_sync_free - free the sync object | |
215 | * | |
216 | * @adev: amdgpu_device pointer | |
217 | * @sync: sync object to use | |
218 | * @fence: fence to use for the free | |
219 | * | |
220 | * Free the sync object by freeing all semaphores in it. | |
221 | */ | |
222 | void amdgpu_sync_free(struct amdgpu_device *adev, | |
223 | struct amdgpu_sync *sync, | |
224 | struct amdgpu_fence *fence) | |
225 | { | |
226 | unsigned i; | |
227 | ||
228 | for (i = 0; i < AMDGPU_NUM_SYNCS; ++i) | |
229 | amdgpu_semaphore_free(adev, &sync->semaphores[i], fence); | |
230 | ||
231 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
232 | amdgpu_fence_unref(&sync->sync_to[i]); | |
233 | ||
234 | amdgpu_fence_unref(&sync->last_vm_update); | |
235 | } |