Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
4ff37a83 CK |
53 | /* Special value that no flush is necessary */ |
54 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
55 | ||
d38ceaf9 AD |
56 | /** |
57 | * amdgpu_vm_num_pde - return the number of page directory entries | |
58 | * | |
59 | * @adev: amdgpu_device pointer | |
60 | * | |
8843dbbb | 61 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
62 | */ |
63 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
64 | { | |
65 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
66 | } | |
67 | ||
68 | /** | |
69 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
70 | * | |
71 | * @adev: amdgpu_device pointer | |
72 | * | |
8843dbbb | 73 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
74 | */ |
75 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
76 | { | |
77 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
78 | } | |
79 | ||
80 | /** | |
56467ebf | 81 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
82 | * |
83 | * @vm: vm providing the BOs | |
3c0eea6c | 84 | * @validated: head of validation list |
56467ebf | 85 | * @entry: entry to add |
d38ceaf9 AD |
86 | * |
87 | * Add the page directory to the list of BOs to | |
56467ebf | 88 | * validate for command submission. |
d38ceaf9 | 89 | */ |
56467ebf CK |
90 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
91 | struct list_head *validated, | |
92 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 93 | { |
56467ebf | 94 | entry->robj = vm->page_directory; |
56467ebf CK |
95 | entry->priority = 0; |
96 | entry->tv.bo = &vm->page_directory->tbo; | |
97 | entry->tv.shared = true; | |
2f568dbd | 98 | entry->user_pages = NULL; |
56467ebf CK |
99 | list_add(&entry->tv.head, validated); |
100 | } | |
d38ceaf9 | 101 | |
56467ebf | 102 | /** |
ee1782c3 | 103 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
104 | * |
105 | * @vm: vm providing the BOs | |
3c0eea6c | 106 | * @duplicates: head of duplicates list |
d38ceaf9 | 107 | * |
ee1782c3 CK |
108 | * Add the page directory to the BO duplicates list |
109 | * for command submission. | |
d38ceaf9 | 110 | */ |
ee1782c3 | 111 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 112 | { |
ee1782c3 | 113 | unsigned i; |
d38ceaf9 AD |
114 | |
115 | /* add the vm page table to the list */ | |
ee1782c3 CK |
116 | for (i = 0; i <= vm->max_pde_used; ++i) { |
117 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
118 | ||
119 | if (!entry->robj) | |
d38ceaf9 AD |
120 | continue; |
121 | ||
ee1782c3 | 122 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 123 | } |
eceb8a15 CK |
124 | |
125 | } | |
126 | ||
127 | /** | |
128 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
129 | * | |
130 | * @adev: amdgpu device instance | |
131 | * @vm: vm providing the BOs | |
132 | * | |
133 | * Move the PT BOs to the tail of the LRU. | |
134 | */ | |
135 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
136 | struct amdgpu_vm *vm) | |
137 | { | |
138 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
139 | unsigned i; | |
140 | ||
141 | spin_lock(&glob->lru_lock); | |
142 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
143 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
144 | ||
145 | if (!entry->robj) | |
146 | continue; | |
147 | ||
148 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
149 | } | |
150 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
151 | } |
152 | ||
153 | /** | |
154 | * amdgpu_vm_grab_id - allocate the next free VMID | |
155 | * | |
d38ceaf9 | 156 | * @vm: vm to allocate id for |
7f8a5290 CK |
157 | * @ring: ring we want to submit job to |
158 | * @sync: sync object where we add dependencies | |
94dd0a4a | 159 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 160 | * |
7f8a5290 | 161 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 162 | */ |
7f8a5290 | 163 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
164 | struct amdgpu_sync *sync, struct fence *fence, |
165 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 166 | { |
4ff37a83 | 167 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
d38ceaf9 | 168 | struct amdgpu_device *adev = ring->adev; |
4ff37a83 | 169 | struct fence *updates = sync->last_vm_update; |
794f50b9 CK |
170 | struct amdgpu_vm_id *id; |
171 | unsigned i = ring->idx; | |
a9a78b32 | 172 | int r; |
d38ceaf9 | 173 | |
94dd0a4a CK |
174 | mutex_lock(&adev->vm_manager.lock); |
175 | ||
794f50b9 CK |
176 | /* Check if we can use a VMID already assigned to this VM */ |
177 | do { | |
178 | struct fence *flushed; | |
4ff37a83 | 179 | |
794f50b9 CK |
180 | id = vm->ids[i++]; |
181 | if (i == AMDGPU_MAX_RINGS) | |
182 | i = 0; | |
4ff37a83 | 183 | |
794f50b9 CK |
184 | /* Check all the prerequisites to using this VMID */ |
185 | if (!id) | |
186 | continue; | |
187 | ||
188 | if (atomic_long_read(&id->owner) != (long)vm) | |
189 | continue; | |
190 | ||
191 | if (pd_addr != id->pd_gpu_addr) | |
192 | continue; | |
193 | ||
178d7cb8 | 194 | if (id->last_user != ring && |
794f50b9 CK |
195 | (!id->last_flush || !fence_is_signaled(id->last_flush))) |
196 | continue; | |
197 | ||
198 | flushed = id->flushed_updates; | |
199 | if (updates && (!flushed || fence_is_later(updates, flushed))) | |
200 | continue; | |
a8bd1bec | 201 | |
794f50b9 | 202 | /* Good we can use this VMID */ |
178d7cb8 | 203 | if (id->last_user == ring) { |
794f50b9 CK |
204 | r = amdgpu_sync_fence(ring->adev, sync, |
205 | id->first); | |
832a902f CK |
206 | if (r) |
207 | goto error; | |
794f50b9 CK |
208 | } |
209 | ||
210 | /* And remember this submission as user of the VMID */ | |
211 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
212 | if (r) | |
213 | goto error; | |
4ff37a83 | 214 | |
794f50b9 CK |
215 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
216 | vm->ids[ring->idx] = id; | |
d38ceaf9 | 217 | |
794f50b9 CK |
218 | *vm_id = id - adev->vm_manager.ids; |
219 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; | |
220 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); | |
d38ceaf9 | 221 | |
794f50b9 CK |
222 | mutex_unlock(&adev->vm_manager.lock); |
223 | return 0; | |
224 | ||
225 | } while (i != ring->idx); | |
d38ceaf9 | 226 | |
bcb1ba35 CK |
227 | id = list_first_entry(&adev->vm_manager.ids_lru, |
228 | struct amdgpu_vm_id, | |
229 | list); | |
7f8a5290 | 230 | |
832a902f | 231 | if (!amdgpu_sync_is_idle(&id->active)) { |
8e9fbeb5 | 232 | struct list_head *head = &adev->vm_manager.ids_lru; |
832a902f | 233 | struct amdgpu_vm_id *tmp; |
bcb1ba35 CK |
234 | |
235 | list_for_each_entry_safe(id, tmp, &adev->vm_manager.ids_lru, | |
236 | list) { | |
832a902f | 237 | if (amdgpu_sync_is_idle(&id->active)) { |
bcb1ba35 CK |
238 | list_move(&id->list, head); |
239 | head = &id->list; | |
8e9fbeb5 CZ |
240 | } |
241 | } | |
bcb1ba35 CK |
242 | id = list_first_entry(&adev->vm_manager.ids_lru, |
243 | struct amdgpu_vm_id, | |
244 | list); | |
8e9fbeb5 CZ |
245 | } |
246 | ||
832a902f CK |
247 | r = amdgpu_sync_cycle_fences(sync, &id->active, fence); |
248 | if (r) | |
249 | goto error; | |
94dd0a4a | 250 | |
832a902f CK |
251 | fence_put(id->first); |
252 | id->first = fence_get(fence); | |
94dd0a4a | 253 | |
41d9eb2c CK |
254 | fence_put(id->last_flush); |
255 | id->last_flush = NULL; | |
256 | ||
832a902f CK |
257 | fence_put(id->flushed_updates); |
258 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 259 | |
832a902f | 260 | id->pd_gpu_addr = pd_addr; |
4ff37a83 | 261 | |
832a902f | 262 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
68befebe | 263 | id->last_user = ring; |
794f50b9 | 264 | atomic_long_set(&id->owner, (long)vm); |
832a902f | 265 | vm->ids[ring->idx] = id; |
d38ceaf9 | 266 | |
832a902f CK |
267 | *vm_id = id - adev->vm_manager.ids; |
268 | *vm_pd_addr = pd_addr; | |
269 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); | |
270 | ||
271 | error: | |
94dd0a4a | 272 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 273 | return r; |
d38ceaf9 AD |
274 | } |
275 | ||
276 | /** | |
277 | * amdgpu_vm_flush - hardware flush the vm | |
278 | * | |
279 | * @ring: ring to use for flush | |
cffadc83 | 280 | * @vm_id: vmid number to use |
4ff37a83 | 281 | * @pd_addr: address of the page directory |
d38ceaf9 | 282 | * |
4ff37a83 | 283 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 284 | */ |
41d9eb2c CK |
285 | int amdgpu_vm_flush(struct amdgpu_ring *ring, |
286 | unsigned vm_id, uint64_t pd_addr, | |
287 | uint32_t gds_base, uint32_t gds_size, | |
288 | uint32_t gws_base, uint32_t gws_size, | |
289 | uint32_t oa_base, uint32_t oa_size) | |
d38ceaf9 | 290 | { |
971fe9a9 | 291 | struct amdgpu_device *adev = ring->adev; |
bcb1ba35 | 292 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
d564a06e | 293 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
bcb1ba35 CK |
294 | id->gds_base != gds_base || |
295 | id->gds_size != gds_size || | |
296 | id->gws_base != gws_base || | |
297 | id->gws_size != gws_size || | |
298 | id->oa_base != oa_base || | |
299 | id->oa_size != oa_size); | |
41d9eb2c | 300 | int r; |
d564a06e CK |
301 | |
302 | if (ring->funcs->emit_pipeline_sync && ( | |
303 | pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) | |
304 | amdgpu_ring_emit_pipeline_sync(ring); | |
971fe9a9 | 305 | |
4ff37a83 | 306 | if (pd_addr != AMDGPU_VM_NO_FLUSH) { |
41d9eb2c CK |
307 | struct fence *fence; |
308 | ||
cffadc83 CK |
309 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); |
310 | amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); | |
41d9eb2c CK |
311 | |
312 | mutex_lock(&adev->vm_manager.lock); | |
68befebe CZ |
313 | if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) { |
314 | r = amdgpu_fence_emit(ring, &fence); | |
315 | if (r) { | |
316 | mutex_unlock(&adev->vm_manager.lock); | |
317 | return r; | |
318 | } | |
319 | fence_put(id->last_flush); | |
320 | id->last_flush = fence; | |
321 | } | |
41d9eb2c | 322 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 323 | } |
cffadc83 | 324 | |
d564a06e | 325 | if (gds_switch_needed) { |
bcb1ba35 CK |
326 | id->gds_base = gds_base; |
327 | id->gds_size = gds_size; | |
328 | id->gws_base = gws_base; | |
329 | id->gws_size = gws_size; | |
330 | id->oa_base = oa_base; | |
331 | id->oa_size = oa_size; | |
cffadc83 CK |
332 | amdgpu_ring_emit_gds_switch(ring, vm_id, |
333 | gds_base, gds_size, | |
334 | gws_base, gws_size, | |
335 | oa_base, oa_size); | |
971fe9a9 | 336 | } |
41d9eb2c CK |
337 | |
338 | return 0; | |
971fe9a9 CK |
339 | } |
340 | ||
341 | /** | |
342 | * amdgpu_vm_reset_id - reset VMID to zero | |
343 | * | |
344 | * @adev: amdgpu device structure | |
345 | * @vm_id: vmid number to use | |
346 | * | |
347 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
348 | */ | |
349 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
350 | { | |
bcb1ba35 CK |
351 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
352 | ||
353 | id->gds_base = 0; | |
354 | id->gds_size = 0; | |
355 | id->gws_base = 0; | |
356 | id->gws_size = 0; | |
357 | id->oa_base = 0; | |
358 | id->oa_size = 0; | |
d38ceaf9 AD |
359 | } |
360 | ||
d38ceaf9 AD |
361 | /** |
362 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
363 | * | |
364 | * @vm: requested vm | |
365 | * @bo: requested buffer object | |
366 | * | |
8843dbbb | 367 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
368 | * Search inside the @bos vm list for the requested vm |
369 | * Returns the found bo_va or NULL if none is found | |
370 | * | |
371 | * Object has to be reserved! | |
372 | */ | |
373 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
374 | struct amdgpu_bo *bo) | |
375 | { | |
376 | struct amdgpu_bo_va *bo_va; | |
377 | ||
378 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
379 | if (bo_va->vm == vm) { | |
380 | return bo_va; | |
381 | } | |
382 | } | |
383 | return NULL; | |
384 | } | |
385 | ||
386 | /** | |
387 | * amdgpu_vm_update_pages - helper to call the right asic function | |
388 | * | |
389 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
390 | * @src: address where to copy page table entries from |
391 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 AD |
392 | * @ib: indirect buffer to fill with commands |
393 | * @pe: addr of the page entry | |
394 | * @addr: dst addr to write into pe | |
395 | * @count: number of page entries to update | |
396 | * @incr: increase next addr by incr bytes | |
397 | * @flags: hw access flags | |
d38ceaf9 AD |
398 | * |
399 | * Traces the parameters and calls the right asic functions | |
400 | * to setup the page table using the DMA. | |
401 | */ | |
402 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
403 | uint64_t src, |
404 | dma_addr_t *pages_addr, | |
d38ceaf9 AD |
405 | struct amdgpu_ib *ib, |
406 | uint64_t pe, uint64_t addr, | |
407 | unsigned count, uint32_t incr, | |
9ab21462 | 408 | uint32_t flags) |
d38ceaf9 AD |
409 | { |
410 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
411 | ||
fa3ab3c7 CK |
412 | if (src) { |
413 | src += (addr >> 12) * 8; | |
d38ceaf9 AD |
414 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); |
415 | ||
fa3ab3c7 | 416 | } else if (pages_addr) { |
b07c9d2a CK |
417 | amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, |
418 | count, incr, flags); | |
419 | ||
420 | } else if (count < 3) { | |
421 | amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, | |
422 | count, incr, flags); | |
d38ceaf9 AD |
423 | |
424 | } else { | |
425 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
426 | count, incr, flags); | |
427 | } | |
428 | } | |
429 | ||
430 | /** | |
431 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
432 | * | |
433 | * @adev: amdgpu_device pointer | |
434 | * @bo: bo to clear | |
ef9f0a83 CZ |
435 | * |
436 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
437 | */ |
438 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 439 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
440 | struct amdgpu_bo *bo) |
441 | { | |
2d55e45a | 442 | struct amdgpu_ring *ring; |
4af9f07c | 443 | struct fence *fence = NULL; |
d71518b5 | 444 | struct amdgpu_job *job; |
d38ceaf9 AD |
445 | unsigned entries; |
446 | uint64_t addr; | |
447 | int r; | |
448 | ||
2d55e45a CK |
449 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
450 | ||
ca952613 | 451 | r = reservation_object_reserve_shared(bo->tbo.resv); |
452 | if (r) | |
453 | return r; | |
454 | ||
d38ceaf9 AD |
455 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
456 | if (r) | |
ef9f0a83 | 457 | goto error; |
d38ceaf9 AD |
458 | |
459 | addr = amdgpu_bo_gpu_offset(bo); | |
460 | entries = amdgpu_bo_size(bo) / 8; | |
461 | ||
d71518b5 CK |
462 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
463 | if (r) | |
ef9f0a83 | 464 | goto error; |
d38ceaf9 | 465 | |
fa3ab3c7 | 466 | amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries, |
d71518b5 CK |
467 | 0, 0); |
468 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
469 | ||
470 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
471 | r = amdgpu_job_submit(job, ring, &vm->entity, |
472 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
473 | if (r) |
474 | goto error_free; | |
475 | ||
d71518b5 | 476 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 477 | fence_put(fence); |
cadf97b1 | 478 | return 0; |
ef9f0a83 | 479 | |
d38ceaf9 | 480 | error_free: |
d71518b5 | 481 | amdgpu_job_free(job); |
d38ceaf9 | 482 | |
ef9f0a83 | 483 | error: |
d38ceaf9 AD |
484 | return r; |
485 | } | |
486 | ||
487 | /** | |
b07c9d2a | 488 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 489 | * |
b07c9d2a | 490 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
491 | * @addr: the unmapped addr |
492 | * | |
493 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 494 | * to and return the pointer for the page table entry. |
d38ceaf9 | 495 | */ |
b07c9d2a | 496 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
497 | { |
498 | uint64_t result; | |
499 | ||
b07c9d2a CK |
500 | if (pages_addr) { |
501 | /* page table offset */ | |
502 | result = pages_addr[addr >> PAGE_SHIFT]; | |
503 | ||
504 | /* in case cpu page size != gpu page size*/ | |
505 | result |= addr & (~PAGE_MASK); | |
506 | ||
507 | } else { | |
508 | /* No mapping required */ | |
509 | result = addr; | |
510 | } | |
d38ceaf9 | 511 | |
b07c9d2a | 512 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
513 | |
514 | return result; | |
515 | } | |
516 | ||
517 | /** | |
518 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
519 | * | |
520 | * @adev: amdgpu_device pointer | |
521 | * @vm: requested vm | |
522 | * @start: start of GPU address range | |
523 | * @end: end of GPU address range | |
524 | * | |
525 | * Allocates new page tables if necessary | |
8843dbbb | 526 | * and updates the page directory. |
d38ceaf9 | 527 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
528 | */ |
529 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
530 | struct amdgpu_vm *vm) | |
531 | { | |
2d55e45a | 532 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
533 | struct amdgpu_bo *pd = vm->page_directory; |
534 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
535 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
536 | uint64_t last_pde = ~0, last_pt = ~0; | |
537 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 538 | struct amdgpu_job *job; |
d5fc5e82 | 539 | struct amdgpu_ib *ib; |
4af9f07c | 540 | struct fence *fence = NULL; |
d5fc5e82 | 541 | |
d38ceaf9 AD |
542 | int r; |
543 | ||
2d55e45a CK |
544 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
545 | ||
d38ceaf9 AD |
546 | /* padding, etc. */ |
547 | ndw = 64; | |
548 | ||
549 | /* assume the worst case */ | |
550 | ndw += vm->max_pde_used * 6; | |
551 | ||
d71518b5 CK |
552 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
553 | if (r) | |
d38ceaf9 | 554 | return r; |
d71518b5 CK |
555 | |
556 | ib = &job->ibs[0]; | |
d38ceaf9 AD |
557 | |
558 | /* walk over the address space and update the page directory */ | |
559 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 560 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
561 | uint64_t pde, pt; |
562 | ||
563 | if (bo == NULL) | |
564 | continue; | |
565 | ||
566 | pt = amdgpu_bo_gpu_offset(bo); | |
567 | if (vm->page_tables[pt_idx].addr == pt) | |
568 | continue; | |
569 | vm->page_tables[pt_idx].addr = pt; | |
570 | ||
571 | pde = pd_addr + pt_idx * 8; | |
572 | if (((last_pde + 8 * count) != pde) || | |
573 | ((last_pt + incr * count) != pt)) { | |
574 | ||
575 | if (count) { | |
fa3ab3c7 | 576 | amdgpu_vm_update_pages(adev, 0, NULL, ib, |
9ab21462 CK |
577 | last_pde, last_pt, |
578 | count, incr, | |
579 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
580 | } |
581 | ||
582 | count = 1; | |
583 | last_pde = pde; | |
584 | last_pt = pt; | |
585 | } else { | |
586 | ++count; | |
587 | } | |
588 | } | |
589 | ||
590 | if (count) | |
fa3ab3c7 | 591 | amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt, |
9ab21462 | 592 | count, incr, AMDGPU_PTE_VALID); |
d38ceaf9 | 593 | |
d5fc5e82 | 594 | if (ib->length_dw != 0) { |
9e5d5309 | 595 | amdgpu_ring_pad_ib(ring, ib); |
e86f9cee CK |
596 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
597 | AMDGPU_FENCE_OWNER_VM); | |
d5fc5e82 | 598 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
599 | r = amdgpu_job_submit(job, ring, &vm->entity, |
600 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
601 | if (r) |
602 | goto error_free; | |
05906dec | 603 | |
4af9f07c | 604 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
605 | fence_put(vm->page_directory_fence); |
606 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 607 | fence_put(fence); |
d5fc5e82 | 608 | |
d71518b5 CK |
609 | } else { |
610 | amdgpu_job_free(job); | |
d5fc5e82 | 611 | } |
d38ceaf9 AD |
612 | |
613 | return 0; | |
d5fc5e82 CZ |
614 | |
615 | error_free: | |
d71518b5 | 616 | amdgpu_job_free(job); |
4af9f07c | 617 | return r; |
d38ceaf9 AD |
618 | } |
619 | ||
620 | /** | |
621 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
622 | * | |
623 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
624 | * @src: address where to copy page table entries from |
625 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 AD |
626 | * @ib: IB for the update |
627 | * @pe_start: first PTE to handle | |
628 | * @pe_end: last PTE to handle | |
629 | * @addr: addr those PTEs should point to | |
630 | * @flags: hw mapping flags | |
d38ceaf9 AD |
631 | */ |
632 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
633 | uint64_t src, |
634 | dma_addr_t *pages_addr, | |
d38ceaf9 AD |
635 | struct amdgpu_ib *ib, |
636 | uint64_t pe_start, uint64_t pe_end, | |
9ab21462 | 637 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
638 | { |
639 | /** | |
640 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
641 | * field in the PTE. When this field is set to a non-zero value, page | |
642 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
643 | * flags are considered valid for all PTEs within the fragment range | |
644 | * and corresponding mappings are assumed to be physically contiguous. | |
645 | * | |
646 | * The L1 TLB can store a single PTE for the whole fragment, | |
647 | * significantly increasing the space available for translation | |
648 | * caching. This leads to large improvements in throughput when the | |
649 | * TLB is under pressure. | |
650 | * | |
651 | * The L2 TLB distributes small and large fragments into two | |
652 | * asymmetric partitions. The large fragment cache is significantly | |
653 | * larger. Thus, we try to use large fragments wherever possible. | |
654 | * Userspace can support this by aligning virtual base address and | |
655 | * allocation size to the fragment size. | |
656 | */ | |
657 | ||
658 | /* SI and newer are optimized for 64KB */ | |
659 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
660 | uint64_t frag_align = 0x80; | |
661 | ||
662 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
663 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
664 | ||
665 | unsigned count; | |
666 | ||
31f6c1fe CK |
667 | /* Abort early if there isn't anything to do */ |
668 | if (pe_start == pe_end) | |
669 | return; | |
670 | ||
d38ceaf9 | 671 | /* system pages are non continuously */ |
fa3ab3c7 CK |
672 | if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) || |
673 | (frag_start >= frag_end)) { | |
d38ceaf9 AD |
674 | |
675 | count = (pe_end - pe_start) / 8; | |
fa3ab3c7 | 676 | amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start, |
9ab21462 CK |
677 | addr, count, AMDGPU_GPU_PAGE_SIZE, |
678 | flags); | |
d38ceaf9 AD |
679 | return; |
680 | } | |
681 | ||
682 | /* handle the 4K area at the beginning */ | |
683 | if (pe_start != frag_start) { | |
684 | count = (frag_start - pe_start) / 8; | |
fa3ab3c7 | 685 | amdgpu_vm_update_pages(adev, 0, NULL, ib, pe_start, addr, |
9ab21462 | 686 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
687 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
688 | } | |
689 | ||
690 | /* handle the area in the middle */ | |
691 | count = (frag_end - frag_start) / 8; | |
fa3ab3c7 | 692 | amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_start, addr, count, |
9ab21462 | 693 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); |
d38ceaf9 AD |
694 | |
695 | /* handle the 4K area at the end */ | |
696 | if (frag_end != pe_end) { | |
697 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
698 | count = (pe_end - frag_end) / 8; | |
fa3ab3c7 | 699 | amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_end, addr, |
9ab21462 | 700 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
701 | } |
702 | } | |
703 | ||
704 | /** | |
705 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
706 | * | |
707 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
708 | * @src: address where to copy page table entries from |
709 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 AD |
710 | * @vm: requested vm |
711 | * @start: start of GPU address range | |
712 | * @end: end of GPU address range | |
713 | * @dst: destination address to map to | |
714 | * @flags: mapping flags | |
715 | * | |
8843dbbb | 716 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 717 | */ |
a1e08d3b | 718 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
fa3ab3c7 CK |
719 | uint64_t src, |
720 | dma_addr_t *pages_addr, | |
a1e08d3b CK |
721 | struct amdgpu_vm *vm, |
722 | struct amdgpu_ib *ib, | |
723 | uint64_t start, uint64_t end, | |
724 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 725 | { |
31f6c1fe CK |
726 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
727 | ||
728 | uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0; | |
d38ceaf9 AD |
729 | uint64_t addr; |
730 | ||
731 | /* walk over the address space and update the page tables */ | |
732 | for (addr = start; addr < end; ) { | |
733 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 734 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 | 735 | unsigned nptes; |
31f6c1fe | 736 | uint64_t pe_start; |
d38ceaf9 AD |
737 | |
738 | if ((addr & ~mask) == (end & ~mask)) | |
739 | nptes = end - addr; | |
740 | else | |
741 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
742 | ||
31f6c1fe CK |
743 | pe_start = amdgpu_bo_gpu_offset(pt); |
744 | pe_start += (addr & mask) * 8; | |
d38ceaf9 | 745 | |
31f6c1fe | 746 | if (last_pe_end != pe_start) { |
d38ceaf9 | 747 | |
fa3ab3c7 | 748 | amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, |
31f6c1fe CK |
749 | last_pe_start, last_pe_end, |
750 | last_dst, flags); | |
d38ceaf9 | 751 | |
31f6c1fe CK |
752 | last_pe_start = pe_start; |
753 | last_pe_end = pe_start + 8 * nptes; | |
d38ceaf9 AD |
754 | last_dst = dst; |
755 | } else { | |
31f6c1fe | 756 | last_pe_end += 8 * nptes; |
d38ceaf9 AD |
757 | } |
758 | ||
759 | addr += nptes; | |
760 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
761 | } | |
762 | ||
fa3ab3c7 CK |
763 | amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start, |
764 | last_pe_end, last_dst, flags); | |
d38ceaf9 AD |
765 | } |
766 | ||
d38ceaf9 AD |
767 | /** |
768 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
769 | * | |
770 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
771 | * @src: address where to copy page table entries from |
772 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 773 | * @vm: requested vm |
a14faa65 CK |
774 | * @start: start of mapped range |
775 | * @last: last mapped entry | |
776 | * @flags: flags for the entries | |
d38ceaf9 | 777 | * @addr: addr to set the area to |
d38ceaf9 AD |
778 | * @fence: optional resulting fence |
779 | * | |
a14faa65 | 780 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 781 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
782 | */ |
783 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
784 | uint64_t src, |
785 | dma_addr_t *pages_addr, | |
d38ceaf9 | 786 | struct amdgpu_vm *vm, |
a14faa65 CK |
787 | uint64_t start, uint64_t last, |
788 | uint32_t flags, uint64_t addr, | |
789 | struct fence **fence) | |
d38ceaf9 | 790 | { |
2d55e45a | 791 | struct amdgpu_ring *ring; |
a1e08d3b | 792 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 793 | unsigned nptes, ncmds, ndw; |
d71518b5 | 794 | struct amdgpu_job *job; |
d5fc5e82 | 795 | struct amdgpu_ib *ib; |
4af9f07c | 796 | struct fence *f = NULL; |
d38ceaf9 AD |
797 | int r; |
798 | ||
2d55e45a CK |
799 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
800 | ||
a1e08d3b CK |
801 | /* sync to everything on unmapping */ |
802 | if (!(flags & AMDGPU_PTE_VALID)) | |
803 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
804 | ||
a14faa65 | 805 | nptes = last - start + 1; |
d38ceaf9 AD |
806 | |
807 | /* | |
808 | * reserve space for one command every (1 << BLOCK_SIZE) | |
809 | * entries or 2k dwords (whatever is smaller) | |
810 | */ | |
811 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
812 | ||
813 | /* padding, etc. */ | |
814 | ndw = 64; | |
815 | ||
fa3ab3c7 | 816 | if (src) { |
d38ceaf9 AD |
817 | /* only copy commands needed */ |
818 | ndw += ncmds * 7; | |
819 | ||
fa3ab3c7 | 820 | } else if (pages_addr) { |
d38ceaf9 AD |
821 | /* header for write data commands */ |
822 | ndw += ncmds * 4; | |
823 | ||
824 | /* body of write data command */ | |
825 | ndw += nptes * 2; | |
826 | ||
827 | } else { | |
828 | /* set page commands needed */ | |
829 | ndw += ncmds * 10; | |
830 | ||
831 | /* two extra commands for begin/end of fragment */ | |
832 | ndw += 2 * 10; | |
833 | } | |
834 | ||
d71518b5 CK |
835 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
836 | if (r) | |
d38ceaf9 | 837 | return r; |
d71518b5 CK |
838 | |
839 | ib = &job->ibs[0]; | |
d5fc5e82 | 840 | |
e86f9cee | 841 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
842 | owner); |
843 | if (r) | |
844 | goto error_free; | |
d38ceaf9 | 845 | |
a1e08d3b CK |
846 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
847 | if (r) | |
848 | goto error_free; | |
849 | ||
fa3ab3c7 CK |
850 | amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start, |
851 | last + 1, addr, flags); | |
d38ceaf9 | 852 | |
9e5d5309 | 853 | amdgpu_ring_pad_ib(ring, ib); |
d5fc5e82 | 854 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
855 | r = amdgpu_job_submit(job, ring, &vm->entity, |
856 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
857 | if (r) |
858 | goto error_free; | |
d38ceaf9 | 859 | |
bf60efd3 | 860 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
861 | if (fence) { |
862 | fence_put(*fence); | |
863 | *fence = fence_get(f); | |
864 | } | |
281b4223 | 865 | fence_put(f); |
d38ceaf9 | 866 | return 0; |
d5fc5e82 CZ |
867 | |
868 | error_free: | |
d71518b5 | 869 | amdgpu_job_free(job); |
4af9f07c | 870 | return r; |
d38ceaf9 AD |
871 | } |
872 | ||
a14faa65 CK |
873 | /** |
874 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
875 | * | |
876 | * @adev: amdgpu_device pointer | |
8358dcee CK |
877 | * @gtt_flags: flags as they are used for GTT |
878 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
879 | * @vm: requested vm |
880 | * @mapping: mapped range and flags to use for the update | |
881 | * @addr: addr to set the area to | |
8358dcee | 882 | * @flags: HW flags for the mapping |
a14faa65 CK |
883 | * @fence: optional resulting fence |
884 | * | |
885 | * Split the mapping into smaller chunks so that each update fits | |
886 | * into a SDMA IB. | |
887 | * Returns 0 for success, -EINVAL for failure. | |
888 | */ | |
889 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
a14faa65 | 890 | uint32_t gtt_flags, |
8358dcee | 891 | dma_addr_t *pages_addr, |
a14faa65 CK |
892 | struct amdgpu_vm *vm, |
893 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
894 | uint32_t flags, uint64_t addr, |
895 | struct fence **fence) | |
a14faa65 CK |
896 | { |
897 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
898 | ||
fa3ab3c7 | 899 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
900 | int r; |
901 | ||
902 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
903 | * but in case of something, we filter the flags in first place | |
904 | */ | |
905 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
906 | flags &= ~AMDGPU_PTE_READABLE; | |
907 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
908 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
909 | ||
910 | trace_amdgpu_vm_bo_update(mapping); | |
911 | ||
8358dcee | 912 | if (pages_addr) { |
fa3ab3c7 CK |
913 | if (flags == gtt_flags) |
914 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
915 | addr = 0; |
916 | } | |
a14faa65 CK |
917 | addr += mapping->offset; |
918 | ||
8358dcee | 919 | if (!pages_addr || src) |
fa3ab3c7 | 920 | return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, |
a14faa65 CK |
921 | start, mapping->it.last, |
922 | flags, addr, fence); | |
923 | ||
924 | while (start != mapping->it.last + 1) { | |
925 | uint64_t last; | |
926 | ||
fb29b57c | 927 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
fa3ab3c7 | 928 | r = amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, |
a14faa65 CK |
929 | start, last, flags, addr, |
930 | fence); | |
931 | if (r) | |
932 | return r; | |
933 | ||
934 | start = last + 1; | |
fb29b57c | 935 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
936 | } |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
d38ceaf9 AD |
941 | /** |
942 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
943 | * | |
944 | * @adev: amdgpu_device pointer | |
945 | * @bo_va: requested BO and VM object | |
946 | * @mem: ttm mem | |
947 | * | |
948 | * Fill in the page table entries for @bo_va. | |
949 | * Returns 0 for success, -EINVAL for failure. | |
950 | * | |
951 | * Object have to be reserved and mutex must be locked! | |
952 | */ | |
953 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
954 | struct amdgpu_bo_va *bo_va, | |
955 | struct ttm_mem_reg *mem) | |
956 | { | |
957 | struct amdgpu_vm *vm = bo_va->vm; | |
958 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 959 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 960 | uint32_t gtt_flags, flags; |
d38ceaf9 AD |
961 | uint64_t addr; |
962 | int r; | |
963 | ||
964 | if (mem) { | |
8358dcee CK |
965 | struct ttm_dma_tt *ttm; |
966 | ||
b7d698d7 | 967 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
968 | switch (mem->mem_type) { |
969 | case TTM_PL_TT: | |
8358dcee CK |
970 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
971 | ttm_dma_tt, ttm); | |
972 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
973 | break; |
974 | ||
975 | case TTM_PL_VRAM: | |
d38ceaf9 | 976 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
977 | break; |
978 | ||
979 | default: | |
980 | break; | |
981 | } | |
d38ceaf9 AD |
982 | } else { |
983 | addr = 0; | |
984 | } | |
985 | ||
d38ceaf9 | 986 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 987 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 988 | |
7fc11959 CK |
989 | spin_lock(&vm->status_lock); |
990 | if (!list_empty(&bo_va->vm_status)) | |
991 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
992 | spin_unlock(&vm->status_lock); | |
993 | ||
994 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
8358dcee CK |
995 | r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm, |
996 | mapping, flags, addr, | |
997 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
998 | if (r) |
999 | return r; | |
1000 | } | |
1001 | ||
d6c10f6b CK |
1002 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1003 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1004 | trace_amdgpu_vm_bo_mapping(mapping); | |
1005 | ||
1006 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1007 | trace_amdgpu_vm_bo_mapping(mapping); | |
1008 | } | |
1009 | ||
d38ceaf9 | 1010 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1011 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1012 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
1013 | if (!mem) |
1014 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
1015 | spin_unlock(&vm->status_lock); |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
1020 | /** | |
1021 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1022 | * | |
1023 | * @adev: amdgpu_device pointer | |
1024 | * @vm: requested vm | |
1025 | * | |
1026 | * Make sure all freed BOs are cleared in the PT. | |
1027 | * Returns 0 for success. | |
1028 | * | |
1029 | * PTs have to be reserved and mutex must be locked! | |
1030 | */ | |
1031 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1032 | struct amdgpu_vm *vm) | |
1033 | { | |
1034 | struct amdgpu_bo_va_mapping *mapping; | |
1035 | int r; | |
1036 | ||
1037 | while (!list_empty(&vm->freed)) { | |
1038 | mapping = list_first_entry(&vm->freed, | |
1039 | struct amdgpu_bo_va_mapping, list); | |
1040 | list_del(&mapping->list); | |
e17841b9 | 1041 | |
8358dcee | 1042 | r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping, |
fa3ab3c7 | 1043 | 0, 0, NULL); |
d38ceaf9 AD |
1044 | kfree(mapping); |
1045 | if (r) | |
1046 | return r; | |
1047 | ||
1048 | } | |
1049 | return 0; | |
1050 | ||
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1055 | * | |
1056 | * @adev: amdgpu_device pointer | |
1057 | * @vm: requested vm | |
1058 | * | |
1059 | * Make sure all invalidated BOs are cleared in the PT. | |
1060 | * Returns 0 for success. | |
1061 | * | |
1062 | * PTs have to be reserved and mutex must be locked! | |
1063 | */ | |
1064 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1065 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1066 | { |
cfe2c978 | 1067 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1068 | int r = 0; |
d38ceaf9 AD |
1069 | |
1070 | spin_lock(&vm->status_lock); | |
1071 | while (!list_empty(&vm->invalidated)) { | |
1072 | bo_va = list_first_entry(&vm->invalidated, | |
1073 | struct amdgpu_bo_va, vm_status); | |
1074 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1075 | |
d38ceaf9 AD |
1076 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1077 | if (r) | |
1078 | return r; | |
1079 | ||
1080 | spin_lock(&vm->status_lock); | |
1081 | } | |
1082 | spin_unlock(&vm->status_lock); | |
1083 | ||
cfe2c978 | 1084 | if (bo_va) |
bb1e38a4 | 1085 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1086 | |
1087 | return r; | |
d38ceaf9 AD |
1088 | } |
1089 | ||
1090 | /** | |
1091 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1092 | * | |
1093 | * @adev: amdgpu_device pointer | |
1094 | * @vm: requested vm | |
1095 | * @bo: amdgpu buffer object | |
1096 | * | |
8843dbbb | 1097 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1098 | * Add @bo to the list of bos associated with the vm |
1099 | * Returns newly added bo_va or NULL for failure | |
1100 | * | |
1101 | * Object has to be reserved! | |
1102 | */ | |
1103 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1104 | struct amdgpu_vm *vm, | |
1105 | struct amdgpu_bo *bo) | |
1106 | { | |
1107 | struct amdgpu_bo_va *bo_va; | |
1108 | ||
1109 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1110 | if (bo_va == NULL) { | |
1111 | return NULL; | |
1112 | } | |
1113 | bo_va->vm = vm; | |
1114 | bo_va->bo = bo; | |
d38ceaf9 AD |
1115 | bo_va->ref_count = 1; |
1116 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1117 | INIT_LIST_HEAD(&bo_va->valids); |
1118 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1119 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1120 | |
d38ceaf9 | 1121 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1122 | |
1123 | return bo_va; | |
1124 | } | |
1125 | ||
1126 | /** | |
1127 | * amdgpu_vm_bo_map - map bo inside a vm | |
1128 | * | |
1129 | * @adev: amdgpu_device pointer | |
1130 | * @bo_va: bo_va to store the address | |
1131 | * @saddr: where to map the BO | |
1132 | * @offset: requested offset in the BO | |
1133 | * @flags: attributes of pages (read/write/valid/etc.) | |
1134 | * | |
1135 | * Add a mapping of the BO at the specefied addr into the VM. | |
1136 | * Returns 0 for success, error for failure. | |
1137 | * | |
49b02b18 | 1138 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1139 | */ |
1140 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1141 | struct amdgpu_bo_va *bo_va, | |
1142 | uint64_t saddr, uint64_t offset, | |
1143 | uint64_t size, uint32_t flags) | |
1144 | { | |
1145 | struct amdgpu_bo_va_mapping *mapping; | |
1146 | struct amdgpu_vm *vm = bo_va->vm; | |
1147 | struct interval_tree_node *it; | |
1148 | unsigned last_pfn, pt_idx; | |
1149 | uint64_t eaddr; | |
1150 | int r; | |
1151 | ||
0be52de9 CK |
1152 | /* validate the parameters */ |
1153 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1154 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1155 | return -EINVAL; |
0be52de9 | 1156 | |
d38ceaf9 | 1157 | /* make sure object fit at this offset */ |
005ae95e | 1158 | eaddr = saddr + size - 1; |
49b02b18 | 1159 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1160 | return -EINVAL; |
d38ceaf9 AD |
1161 | |
1162 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1163 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1164 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1165 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1166 | return -EINVAL; |
1167 | } | |
1168 | ||
d38ceaf9 AD |
1169 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1170 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1171 | ||
005ae95e | 1172 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1173 | if (it) { |
1174 | struct amdgpu_bo_va_mapping *tmp; | |
1175 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1176 | /* bo and tmp overlap, invalid addr */ | |
1177 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1178 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1179 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1180 | r = -EINVAL; |
f48b2659 | 1181 | goto error; |
d38ceaf9 AD |
1182 | } |
1183 | ||
1184 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1185 | if (!mapping) { | |
d38ceaf9 | 1186 | r = -ENOMEM; |
f48b2659 | 1187 | goto error; |
d38ceaf9 AD |
1188 | } |
1189 | ||
1190 | INIT_LIST_HEAD(&mapping->list); | |
1191 | mapping->it.start = saddr; | |
005ae95e | 1192 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1193 | mapping->offset = offset; |
1194 | mapping->flags = flags; | |
1195 | ||
7fc11959 | 1196 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1197 | interval_tree_insert(&mapping->it, &vm->va); |
1198 | ||
1199 | /* Make sure the page tables are allocated */ | |
1200 | saddr >>= amdgpu_vm_block_size; | |
1201 | eaddr >>= amdgpu_vm_block_size; | |
1202 | ||
1203 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1204 | ||
1205 | if (eaddr > vm->max_pde_used) | |
1206 | vm->max_pde_used = eaddr; | |
1207 | ||
d38ceaf9 AD |
1208 | /* walk over the address space and allocate the page tables */ |
1209 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1210 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1211 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1212 | struct amdgpu_bo *pt; |
1213 | ||
ee1782c3 CK |
1214 | entry = &vm->page_tables[pt_idx].entry; |
1215 | if (entry->robj) | |
d38ceaf9 AD |
1216 | continue; |
1217 | ||
d38ceaf9 AD |
1218 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1219 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1220 | AMDGPU_GEM_DOMAIN_VRAM, |
1221 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1222 | NULL, resv, &pt); |
49b02b18 | 1223 | if (r) |
d38ceaf9 | 1224 | goto error_free; |
49b02b18 | 1225 | |
82b9c55b CK |
1226 | /* Keep a reference to the page table to avoid freeing |
1227 | * them up in the wrong order. | |
1228 | */ | |
1229 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1230 | ||
2bd9ccfa | 1231 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1232 | if (r) { |
1233 | amdgpu_bo_unref(&pt); | |
1234 | goto error_free; | |
1235 | } | |
1236 | ||
ee1782c3 | 1237 | entry->robj = pt; |
ee1782c3 CK |
1238 | entry->priority = 0; |
1239 | entry->tv.bo = &entry->robj->tbo; | |
1240 | entry->tv.shared = true; | |
2f568dbd | 1241 | entry->user_pages = NULL; |
d38ceaf9 | 1242 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1243 | } |
1244 | ||
d38ceaf9 AD |
1245 | return 0; |
1246 | ||
1247 | error_free: | |
d38ceaf9 AD |
1248 | list_del(&mapping->list); |
1249 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1250 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1251 | kfree(mapping); |
1252 | ||
f48b2659 | 1253 | error: |
d38ceaf9 AD |
1254 | return r; |
1255 | } | |
1256 | ||
1257 | /** | |
1258 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1259 | * | |
1260 | * @adev: amdgpu_device pointer | |
1261 | * @bo_va: bo_va to remove the address from | |
1262 | * @saddr: where to the BO is mapped | |
1263 | * | |
1264 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1265 | * Returns 0 for success, error for failure. | |
1266 | * | |
49b02b18 | 1267 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1268 | */ |
1269 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1270 | struct amdgpu_bo_va *bo_va, | |
1271 | uint64_t saddr) | |
1272 | { | |
1273 | struct amdgpu_bo_va_mapping *mapping; | |
1274 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1275 | bool valid = true; |
d38ceaf9 | 1276 | |
6c7fc503 | 1277 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1278 | |
7fc11959 | 1279 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1280 | if (mapping->it.start == saddr) |
1281 | break; | |
1282 | } | |
1283 | ||
7fc11959 CK |
1284 | if (&mapping->list == &bo_va->valids) { |
1285 | valid = false; | |
1286 | ||
1287 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1288 | if (mapping->it.start == saddr) | |
1289 | break; | |
1290 | } | |
1291 | ||
32b41ac2 | 1292 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1293 | return -ENOENT; |
d38ceaf9 | 1294 | } |
32b41ac2 | 1295 | |
d38ceaf9 AD |
1296 | list_del(&mapping->list); |
1297 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1298 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1299 | |
e17841b9 | 1300 | if (valid) |
d38ceaf9 | 1301 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1302 | else |
d38ceaf9 | 1303 | kfree(mapping); |
d38ceaf9 AD |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1310 | * | |
1311 | * @adev: amdgpu_device pointer | |
1312 | * @bo_va: requested bo_va | |
1313 | * | |
8843dbbb | 1314 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1315 | * |
1316 | * Object have to be reserved! | |
1317 | */ | |
1318 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1319 | struct amdgpu_bo_va *bo_va) | |
1320 | { | |
1321 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1322 | struct amdgpu_vm *vm = bo_va->vm; | |
1323 | ||
1324 | list_del(&bo_va->bo_list); | |
1325 | ||
d38ceaf9 AD |
1326 | spin_lock(&vm->status_lock); |
1327 | list_del(&bo_va->vm_status); | |
1328 | spin_unlock(&vm->status_lock); | |
1329 | ||
7fc11959 | 1330 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1331 | list_del(&mapping->list); |
1332 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1333 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1334 | list_add(&mapping->list, &vm->freed); |
1335 | } | |
1336 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1337 | list_del(&mapping->list); | |
1338 | interval_tree_remove(&mapping->it, &vm->va); | |
1339 | kfree(mapping); | |
d38ceaf9 | 1340 | } |
32b41ac2 | 1341 | |
bb1e38a4 | 1342 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1343 | kfree(bo_va); |
d38ceaf9 AD |
1344 | } |
1345 | ||
1346 | /** | |
1347 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1348 | * | |
1349 | * @adev: amdgpu_device pointer | |
1350 | * @vm: requested vm | |
1351 | * @bo: amdgpu buffer object | |
1352 | * | |
8843dbbb | 1353 | * Mark @bo as invalid. |
d38ceaf9 AD |
1354 | */ |
1355 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1356 | struct amdgpu_bo *bo) | |
1357 | { | |
1358 | struct amdgpu_bo_va *bo_va; | |
1359 | ||
1360 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1361 | spin_lock(&bo_va->vm->status_lock); |
1362 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1363 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1364 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1365 | } |
1366 | } | |
1367 | ||
1368 | /** | |
1369 | * amdgpu_vm_init - initialize a vm instance | |
1370 | * | |
1371 | * @adev: amdgpu_device pointer | |
1372 | * @vm: requested vm | |
1373 | * | |
8843dbbb | 1374 | * Init @vm fields. |
d38ceaf9 AD |
1375 | */ |
1376 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1377 | { | |
1378 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1379 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1380 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1381 | unsigned ring_instance; |
1382 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1383 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1384 | int i, r; |
1385 | ||
bcb1ba35 CK |
1386 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1387 | vm->ids[i] = NULL; | |
d38ceaf9 AD |
1388 | vm->va = RB_ROOT; |
1389 | spin_lock_init(&vm->status_lock); | |
1390 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1391 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1392 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1393 | |
d38ceaf9 AD |
1394 | pd_size = amdgpu_vm_directory_size(adev); |
1395 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1396 | ||
1397 | /* allocate page table array */ | |
9571e1d8 | 1398 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1399 | if (vm->page_tables == NULL) { |
1400 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1401 | return -ENOMEM; | |
1402 | } | |
1403 | ||
2bd9ccfa | 1404 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1405 | |
1406 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1407 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1408 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1409 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1410 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1411 | rq, amdgpu_sched_jobs); | |
1412 | if (r) | |
1413 | return r; | |
1414 | ||
05906dec BN |
1415 | vm->page_directory_fence = NULL; |
1416 | ||
d38ceaf9 | 1417 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1418 | AMDGPU_GEM_DOMAIN_VRAM, |
1419 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1420 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1421 | if (r) |
2bd9ccfa CK |
1422 | goto error_free_sched_entity; |
1423 | ||
ef9f0a83 | 1424 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1425 | if (r) |
1426 | goto error_free_page_directory; | |
1427 | ||
1428 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1429 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1430 | if (r) |
1431 | goto error_free_page_directory; | |
d38ceaf9 AD |
1432 | |
1433 | return 0; | |
2bd9ccfa CK |
1434 | |
1435 | error_free_page_directory: | |
1436 | amdgpu_bo_unref(&vm->page_directory); | |
1437 | vm->page_directory = NULL; | |
1438 | ||
1439 | error_free_sched_entity: | |
1440 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1441 | ||
1442 | return r; | |
d38ceaf9 AD |
1443 | } |
1444 | ||
1445 | /** | |
1446 | * amdgpu_vm_fini - tear down a vm instance | |
1447 | * | |
1448 | * @adev: amdgpu_device pointer | |
1449 | * @vm: requested vm | |
1450 | * | |
8843dbbb | 1451 | * Tear down @vm. |
d38ceaf9 AD |
1452 | * Unbind the VM and remove all bos from the vm bo list |
1453 | */ | |
1454 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1455 | { | |
1456 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
444066b9 | 1457 | struct amdgpu_vm_id *id, *id_tmp; |
d38ceaf9 AD |
1458 | int i; |
1459 | ||
2d55e45a | 1460 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1461 | |
d38ceaf9 AD |
1462 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1463 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1464 | } | |
1465 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1466 | list_del(&mapping->list); | |
1467 | interval_tree_remove(&mapping->it, &vm->va); | |
1468 | kfree(mapping); | |
1469 | } | |
1470 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1471 | list_del(&mapping->list); | |
1472 | kfree(mapping); | |
1473 | } | |
1474 | ||
1475 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1476 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1477 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1478 | |
1479 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1480 | fence_put(vm->page_directory_fence); |
20250215 | 1481 | |
444066b9 CZ |
1482 | mutex_lock(&adev->vm_manager.lock); |
1483 | list_for_each_entry_safe(id, id_tmp, &adev->vm_manager.ids_lru, | |
1484 | list) { | |
bcb1ba35 CK |
1485 | if (!id) |
1486 | continue; | |
444066b9 CZ |
1487 | if (atomic_long_read(&id->owner) == (long)vm) { |
1488 | atomic_long_set(&id->owner, 0); | |
1489 | id->pd_gpu_addr = 0; | |
1490 | } | |
d38ceaf9 | 1491 | } |
444066b9 | 1492 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 1493 | } |
ea89f8c9 | 1494 | |
a9a78b32 CK |
1495 | /** |
1496 | * amdgpu_vm_manager_init - init the VM manager | |
1497 | * | |
1498 | * @adev: amdgpu_device pointer | |
1499 | * | |
1500 | * Initialize the VM manager structures | |
1501 | */ | |
1502 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1503 | { | |
1504 | unsigned i; | |
1505 | ||
1506 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1507 | ||
1508 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1509 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1510 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1511 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1512 | list_add_tail(&adev->vm_manager.ids[i].list, |
1513 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1514 | } |
2d55e45a CK |
1515 | |
1516 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); | |
a9a78b32 CK |
1517 | } |
1518 | ||
ea89f8c9 CK |
1519 | /** |
1520 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1521 | * | |
1522 | * @adev: amdgpu_device pointer | |
1523 | * | |
1524 | * Cleanup the VM manager and free resources. | |
1525 | */ | |
1526 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1527 | { | |
1528 | unsigned i; | |
1529 | ||
bcb1ba35 CK |
1530 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1531 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1532 | ||
832a902f CK |
1533 | fence_put(adev->vm_manager.ids[i].first); |
1534 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1535 | fence_put(id->flushed_updates); |
1536 | } | |
ea89f8c9 | 1537 | } |