projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: Don't print error on aux transaction timeouts
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / atombios_dp.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#include <drm/drmP.h>
28#include <drm/amdgpu_drm.h>
29#include "amdgpu.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include "atombios_encoders.h"
34#include "atombios_dp.h"
35#include "amdgpu_connectors.h"
36#include "amdgpu_atombios.h"
37#include <drm/drm_dp_helper.h>
38
39/* move these to drm_dp_helper.c/h */
40#define DP_LINK_CONFIGURATION_SIZE 9
41#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
42
43static char *voltage_names[] = {
44 "0.4V", "0.6V", "0.8V", "1.2V"
45};
46static char *pre_emph_names[] = {
47 "0dB", "3.5dB", "6dB", "9.5dB"
48};
49
50/***** amdgpu AUX functions *****/
51
52union aux_channel_transaction {
53 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
54 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
55};
56
57static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
58 u8 *send, int send_bytes,
59 u8 *recv, int recv_size,
60 u8 delay, u8 *ack)
61{
62 struct drm_device *dev = chan->dev;
63 struct amdgpu_device *adev = dev->dev_private;
64 union aux_channel_transaction args;
65 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
66 unsigned char *base;
67 int recv_bytes;
68 int r = 0;
69
70 memset(&args, 0, sizeof(args));
71
72 mutex_lock(&chan->mutex);
73
74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
75
76 amdgpu_atombios_copy_swap(base, send, send_bytes, true);
77
78 args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
79 args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
80 args.v2.ucDataOutLen = 0;
81 args.v2.ucChannelID = chan->rec.i2c_id;
82 args.v2.ucDelay = delay / 10;
83 args.v2.ucHPD_ID = chan->rec.hpd;
84
85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
86
87 *ack = args.v2.ucReplyStatus;
88
89 /* timeout */
90 if (args.v2.ucReplyStatus == 1) {
d38ceaf9
AD		 91 r = -ETIMEDOUT;
92 goto done;
93 }
94
95 /* flags not zero */
96 if (args.v2.ucReplyStatus == 2) {
97 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
98 r = -EIO;
99 goto done;
100 }
101
102 /* error */
103 if (args.v2.ucReplyStatus == 3) {
104 DRM_DEBUG_KMS("dp_aux_ch error\n");
105 r = -EIO;
106 goto done;
107 }
108
109 recv_bytes = args.v1.ucDataOutLen;
110 if (recv_bytes > recv_size)
111 recv_bytes = recv_size;
112
113 if (recv && recv_size)
114 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
115
116 r = recv_bytes;
117done:
118 mutex_unlock(&chan->mutex);
119
120 return r;
121}
122
123#define BARE_ADDRESS_SIZE 3
124#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
125
126static ssize_t
127amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
128{
129 struct amdgpu_i2c_chan *chan =
130 container_of(aux, struct amdgpu_i2c_chan, aux);
131 int ret;
132 u8 tx_buf[20];
133 size_t tx_size;
134 u8 ack, delay = 0;
135
136 if (WARN_ON(msg->size > 16))
137 return -E2BIG;
138
139 tx_buf[0] = msg->address & 0xff;
140 tx_buf[1] = msg->address >> 8;
e39daf2c
AD		 141 tx_buf[2] = (msg->request << 4) |
142 ((msg->address >> 16) & 0xf);
d38ceaf9
AD		 143 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
144
145 switch (msg->request & ~DP_AUX_I2C_MOT) {
146 case DP_AUX_NATIVE_WRITE:
147 case DP_AUX_I2C_WRITE:
148 /* tx_size needs to be 4 even for bare address packets since the atom
149 * table needs the info in tx_buf[3].
150 */
151 tx_size = HEADER_SIZE + msg->size;
152 if (msg->size == 0)
153 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
154 else
155 tx_buf[3] |= tx_size << 4;
156 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
157 ret = amdgpu_atombios_dp_process_aux_ch(chan,
158 tx_buf, tx_size, NULL, 0, delay, &ack);
159 if (ret >= 0)
160 /* Return payload size. */
161 ret = msg->size;
162 break;
163 case DP_AUX_NATIVE_READ:
164 case DP_AUX_I2C_READ:
165 /* tx_size needs to be 4 even for bare address packets since the atom
166 * table needs the info in tx_buf[3].
167 */
168 tx_size = HEADER_SIZE;
169 if (msg->size == 0)
170 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
171 else
172 tx_buf[3] |= tx_size << 4;
173 ret = amdgpu_atombios_dp_process_aux_ch(chan,
174 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
175 break;
176 default:
177 ret = -EINVAL;
178 break;
179 }
180
181 if (ret >= 0)
182 msg->reply = ack >> 4;
183
184 return ret;
185}
186
187void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
188{
189 int ret;
190
191 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
192 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
193 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
194 ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
195 if (!ret)
196 amdgpu_connector->ddc_bus->has_aux = true;
197
198 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
199}
200
201/***** general DP utility functions *****/
202
203#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
204#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
205
dc5f428d
AD		 206static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
207 int lane_count,
208 u8 train_set[4])
d38ceaf9
AD		 209{
210 u8 v = 0;
211 u8 p = 0;
212 int lane;
213
214 for (lane = 0; lane < lane_count; lane++) {
215 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
216 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
217
218 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
219 lane,
220 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
221 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
222
223 if (this_v > v)
224 v = this_v;
225 if (this_p > p)
226 p = this_p;
227 }
228
229 if (v >= DP_VOLTAGE_MAX)
230 v |= DP_TRAIN_MAX_SWING_REACHED;
231
232 if (p >= DP_PRE_EMPHASIS_MAX)
233 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
234
235 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
236 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
237 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
238
239 for (lane = 0; lane < 4; lane++)
240 train_set[lane] = v | p;
241}
242
243/* convert bits per color to bits per pixel */
244/* get bpc from the EDID */
41869c1c 245static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
d38ceaf9
AD		 246{
247 if (bpc == 0)
248 return 24;
249 else
250 return bpc * 3;
251}
252
d38ceaf9
AD		 253/***** amdgpu specific DP functions *****/
254
41869c1c 255static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
dc5f428d 256 const u8 dpcd[DP_DPCD_SIZE],
41869c1c
AD		 257 unsigned pix_clock,
258 unsigned *dp_lanes, unsigned *dp_rate)
d38ceaf9 259{
41869c1c
AD		 260 unsigned bpp =
261 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
262 static const unsigned link_rates[3] = { 162000, 270000, 540000 };
263 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
264 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
265 unsigned lane_num, i, max_pix_clock;
266
02d27234
AD		 267 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
268 ENCODER_OBJECT_ID_NUTMEG) {
269 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
270 max_pix_clock = (lane_num * 270000 * 8) / bpp;
41869c1c
AD		 271 if (max_pix_clock >= pix_clock) {
272 *dp_lanes = lane_num;
02d27234 273 *dp_rate = 270000;
41869c1c
AD		 274 return 0;
275 }
276 }
02d27234 277 } else {
c47b9e09
AD		 278 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
279 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
02d27234
AD		 280 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
281 if (max_pix_clock >= pix_clock) {
282 *dp_lanes = lane_num;
283 *dp_rate = link_rates[i];
284 return 0;
285 }
286 }
287 }
d38ceaf9
AD		 288 }
289
41869c1c 290 return -EINVAL;
d38ceaf9
AD		 291}
292
293static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
294 int action, int dp_clock,
295 u8 ucconfig, u8 lane_num)
296{
297 DP_ENCODER_SERVICE_PARAMETERS args;
298 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
299
300 memset(&args, 0, sizeof(args));
301 args.ucLinkClock = dp_clock / 10;
302 args.ucConfig = ucconfig;
303 args.ucAction = action;
304 args.ucLaneNum = lane_num;
305 args.ucStatus = 0;
306
307 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
308 return args.ucStatus;
309}
310
311u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
312{
313 struct drm_device *dev = amdgpu_connector->base.dev;
314 struct amdgpu_device *adev = dev->dev_private;
315
316 return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
317 amdgpu_connector->ddc_bus->rec.i2c_id, 0);
318}
319
320static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
321{
322 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
323 u8 buf[3];
324
325 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
326 return;
327
328 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
329 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
330 buf[0], buf[1], buf[2]);
331
332 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
333 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
334 buf[0], buf[1], buf[2]);
335}
336
337int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
338{
339 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
340 u8 msg[DP_DPCD_SIZE];
67ed0092 341 int ret, i;
d38ceaf9 342
67ed0092
AD		 343 for (i = 0; i < 7; i++) {
344 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg,
345 DP_DPCD_SIZE);
346 if (ret == DP_DPCD_SIZE) {
347 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
7af93b50 348
67ed0092
AD		 349 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
350 dig_connector->dpcd);
d38ceaf9 351
67ed0092 352 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
d38ceaf9 353
67ed0092
AD		 354 return 0;
355 }
d38ceaf9
AD		 356 }
357 dig_connector->dpcd[0] = 0;
358 return -EINVAL;
359}
360
361int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
362 struct drm_connector *connector)
363{
364 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
365 struct amdgpu_connector_atom_dig *dig_connector;
366 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
367 u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
368 u8 tmp;
369
370 if (!amdgpu_connector->con_priv)
371 return panel_mode;
372
373 dig_connector = amdgpu_connector->con_priv;
374
375 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
376 /* DP bridge chips */
377 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
378 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
379 if (tmp & 1)
380 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
381 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
382 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
383 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
384 else
385 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
386 }
387 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
388 /* eDP */
389 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
390 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
391 if (tmp & 1)
392 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
393 }
394 }
395
396 return panel_mode;
397}
398
399void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
400 const struct drm_display_mode *mode)
401{
402 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
403 struct amdgpu_connector_atom_dig *dig_connector;
41869c1c 404 int ret;
d38ceaf9
AD		 405
406 if (!amdgpu_connector->con_priv)
407 return;
408 dig_connector = amdgpu_connector->con_priv;
409
410 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
411 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
41869c1c
AD		 412 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
413 mode->clock,
414 &dig_connector->dp_lane_count,
415 &dig_connector->dp_clock);
416 if (ret) {
417 dig_connector->dp_clock = 0;
418 dig_connector->dp_lane_count = 0;
419 }
d38ceaf9
AD		 420 }
421}
422
423int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
424 struct drm_display_mode *mode)
425{
426 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
427 struct amdgpu_connector_atom_dig *dig_connector;
41869c1c
AD		 428 unsigned dp_lanes, dp_clock;
429 int ret;
d38ceaf9
AD		 430
431 if (!amdgpu_connector->con_priv)
432 return MODE_CLOCK_HIGH;
433 dig_connector = amdgpu_connector->con_priv;
434
41869c1c
AD		 435 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
436 mode->clock, &dp_lanes, &dp_clock);
437 if (ret)
438 return MODE_CLOCK_HIGH;
d38ceaf9
AD		 439
440 if ((dp_clock == 540000) &&
441 (!amdgpu_connector_is_dp12_capable(connector)))
442 return MODE_CLOCK_HIGH;
443
444 return MODE_OK;
445}
446
447bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
448{
449 u8 link_status[DP_LINK_STATUS_SIZE];
450 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
451
452 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
453 <= 0)
454 return false;
455 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
456 return false;
457 return true;
458}
459
460void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
461 u8 power_state)
462{
463 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
464 struct amdgpu_connector_atom_dig *dig_connector;
465
466 if (!amdgpu_connector->con_priv)
467 return;
468
469 dig_connector = amdgpu_connector->con_priv;
470
471 /* power up/down the sink */
472 if (dig_connector->dpcd[0] >= 0x11) {
473 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
474 DP_SET_POWER, power_state);
475 usleep_range(1000, 2000);
476 }
477}
478
479struct amdgpu_atombios_dp_link_train_info {
480 struct amdgpu_device *adev;
481 struct drm_encoder *encoder;
482 struct drm_connector *connector;
483 int dp_clock;
484 int dp_lane_count;
485 bool tp3_supported;
486 u8 dpcd[DP_RECEIVER_CAP_SIZE];
487 u8 train_set[4];
488 u8 link_status[DP_LINK_STATUS_SIZE];
489 u8 tries;
490 struct drm_dp_aux *aux;
491};
492
493static void
494amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
495{
496 /* set the initial vs/emph on the source */
497 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
498 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
499 0, dp_info->train_set[0]); /* sets all lanes at once */
500
501 /* set the vs/emph on the sink */
502 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
503 dp_info->train_set, dp_info->dp_lane_count);
504}
505
506static void
507amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
508{
509 int rtp = 0;
510
511 /* set training pattern on the source */
512 switch (tp) {
513 case DP_TRAINING_PATTERN_1:
514 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
515 break;
516 case DP_TRAINING_PATTERN_2:
517 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
518 break;
519 case DP_TRAINING_PATTERN_3:
520 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
521 break;
522 }
523 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
524
525 /* enable training pattern on the sink */
526 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
527}
528
529static int
530amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
531{
532 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
533 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
534 u8 tmp;
535
536 /* power up the sink */
537 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
538
539 /* possibly enable downspread on the sink */
540 if (dp_info->dpcd[3] & 0x1)
541 drm_dp_dpcd_writeb(dp_info->aux,
542 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
543 else
544 drm_dp_dpcd_writeb(dp_info->aux,
545 DP_DOWNSPREAD_CTRL, 0);
546
547 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
548 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
549
550 /* set the lane count on the sink */
551 tmp = dp_info->dp_lane_count;
552 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
553 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
554 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
555
556 /* set the link rate on the sink */
557 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
558 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
559
560 /* start training on the source */
561 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
562 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
563
564 /* disable the training pattern on the sink */
565 drm_dp_dpcd_writeb(dp_info->aux,
566 DP_TRAINING_PATTERN_SET,
567 DP_TRAINING_PATTERN_DISABLE);
568
569 return 0;
570}
571
572static int
573amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
574{
575 udelay(400);
576
577 /* disable the training pattern on the sink */
578 drm_dp_dpcd_writeb(dp_info->aux,
579 DP_TRAINING_PATTERN_SET,
580 DP_TRAINING_PATTERN_DISABLE);
581
582 /* disable the training pattern on the source */
583 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
584 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
585
586 return 0;
587}
588
589static int
590amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
591{
592 bool clock_recovery;
593 u8 voltage;
594 int i;
595
596 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
597 memset(dp_info->train_set, 0, 4);
598 amdgpu_atombios_dp_update_vs_emph(dp_info);
599
600 udelay(400);
601
602 /* clock recovery loop */
603 clock_recovery = false;
604 dp_info->tries = 0;
605 voltage = 0xff;
606 while (1) {
607 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
608
609 if (drm_dp_dpcd_read_link_status(dp_info->aux,
610 dp_info->link_status) <= 0) {
611 DRM_ERROR("displayport link status failed\n");
612 break;
613 }
614
615 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
616 clock_recovery = true;
617 break;
618 }
619
620 for (i = 0; i < dp_info->dp_lane_count; i++) {
621 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
622 break;
623 }
624 if (i == dp_info->dp_lane_count) {
625 DRM_ERROR("clock recovery reached max voltage\n");
626 break;
627 }
628
629 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
630 ++dp_info->tries;
631 if (dp_info->tries == 5) {
632 DRM_ERROR("clock recovery tried 5 times\n");
633 break;
634 }
635 } else
636 dp_info->tries = 0;
637
638 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
639
640 /* Compute new train_set as requested by sink */
641 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
642 dp_info->train_set);
643
644 amdgpu_atombios_dp_update_vs_emph(dp_info);
645 }
646 if (!clock_recovery) {
647 DRM_ERROR("clock recovery failed\n");
648 return -1;
649 } else {
650 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
651 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
652 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
653 DP_TRAIN_PRE_EMPHASIS_SHIFT);
654 return 0;
655 }
656}
657
658static int
659amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
660{
661 bool channel_eq;
662
663 if (dp_info->tp3_supported)
664 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
665 else
666 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
667
668 /* channel equalization loop */
669 dp_info->tries = 0;
670 channel_eq = false;
671 while (1) {
672 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
673
674 if (drm_dp_dpcd_read_link_status(dp_info->aux,
675 dp_info->link_status) <= 0) {
676 DRM_ERROR("displayport link status failed\n");
677 break;
678 }
679
680 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
681 channel_eq = true;
682 break;
683 }
684
685 /* Try 5 times */
686 if (dp_info->tries > 5) {
687 DRM_ERROR("channel eq failed: 5 tries\n");
688 break;
689 }
690
691 /* Compute new train_set as requested by sink */
692 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
693 dp_info->train_set);
694
695 amdgpu_atombios_dp_update_vs_emph(dp_info);
696 dp_info->tries++;
697 }
698
699 if (!channel_eq) {
700 DRM_ERROR("channel eq failed\n");
701 return -1;
702 } else {
703 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
704 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
705 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
706 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
707 return 0;
708 }
709}
710
711void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
712 struct drm_connector *connector)
713{
714 struct drm_device *dev = encoder->dev;
715 struct amdgpu_device *adev = dev->dev_private;
716 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
717 struct amdgpu_encoder_atom_dig *dig;
718 struct amdgpu_connector *amdgpu_connector;
719 struct amdgpu_connector_atom_dig *dig_connector;
720 struct amdgpu_atombios_dp_link_train_info dp_info;
721 u8 tmp;
722
723 if (!amdgpu_encoder->enc_priv)
724 return;
725 dig = amdgpu_encoder->enc_priv;
726
727 amdgpu_connector = to_amdgpu_connector(connector);
728 if (!amdgpu_connector->con_priv)
729 return;
730 dig_connector = amdgpu_connector->con_priv;
731
732 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
733 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
734 return;
735
736 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
737 == 1) {
738 if (tmp & DP_TPS3_SUPPORTED)
739 dp_info.tp3_supported = true;
740 else
741 dp_info.tp3_supported = false;
742 } else {
743 dp_info.tp3_supported = false;
744 }
745
746 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
747 dp_info.adev = adev;
748 dp_info.encoder = encoder;
749 dp_info.connector = connector;
750 dp_info.dp_lane_count = dig_connector->dp_lane_count;
751 dp_info.dp_clock = dig_connector->dp_clock;
752 dp_info.aux = &amdgpu_connector->ddc_bus->aux;
753
754 if (amdgpu_atombios_dp_link_train_init(&dp_info))
755 goto done;
756 if (amdgpu_atombios_dp_link_train_cr(&dp_info))
757 goto done;
758 if (amdgpu_atombios_dp_link_train_ce(&dp_info))
759 goto done;
760done:
761 if (amdgpu_atombios_dp_link_train_finish(&dp_info))
762 return;
763}
Linux kernel - Deliverables
This page took 0.114128 seconds and 5 git commands to generate.