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a2e73f56 AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "cikd.h" | |
30 | #include "cik.h" | |
31 | ||
32 | #include "bif/bif_4_1_d.h" | |
33 | #include "bif/bif_4_1_sh_mask.h" | |
34 | ||
35 | #include "gca/gfx_7_2_d.h" | |
74a5d165 JX |
36 | #include "gca/gfx_7_2_enum.h" |
37 | #include "gca/gfx_7_2_sh_mask.h" | |
a2e73f56 AD |
38 | |
39 | #include "gmc/gmc_7_1_d.h" | |
40 | #include "gmc/gmc_7_1_sh_mask.h" | |
41 | ||
42 | #include "oss/oss_2_0_d.h" | |
43 | #include "oss/oss_2_0_sh_mask.h" | |
44 | ||
45 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
46 | { | |
47 | SDMA0_REGISTER_OFFSET, | |
48 | SDMA1_REGISTER_OFFSET | |
49 | }; | |
50 | ||
51 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); | |
52 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); | |
53 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); | |
54 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); | |
55 | ||
56 | MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); | |
57 | MODULE_FIRMWARE("radeon/bonaire_sdma1.bin"); | |
58 | MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); | |
59 | MODULE_FIRMWARE("radeon/hawaii_sdma1.bin"); | |
60 | MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); | |
61 | MODULE_FIRMWARE("radeon/kaveri_sdma1.bin"); | |
62 | MODULE_FIRMWARE("radeon/kabini_sdma.bin"); | |
63 | MODULE_FIRMWARE("radeon/kabini_sdma1.bin"); | |
64 | MODULE_FIRMWARE("radeon/mullins_sdma.bin"); | |
65 | MODULE_FIRMWARE("radeon/mullins_sdma1.bin"); | |
66 | ||
67 | u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); | |
68 | ||
69 | /* | |
70 | * sDMA - System DMA | |
71 | * Starting with CIK, the GPU has new asynchronous | |
72 | * DMA engines. These engines are used for compute | |
73 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
74 | * and each one supports 1 ring buffer used for gfx | |
75 | * and 2 queues used for compute. | |
76 | * | |
77 | * The programming model is very similar to the CP | |
78 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
79 | * packet format that is different from the PM4 format | |
80 | * used by the CP. sDMA supports copying data, writing | |
81 | * embedded data, solid fills, and a number of other | |
82 | * things. It also has support for tiling/detiling of | |
83 | * buffers. | |
84 | */ | |
85 | ||
86 | /** | |
87 | * cik_sdma_init_microcode - load ucode images from disk | |
88 | * | |
89 | * @adev: amdgpu_device pointer | |
90 | * | |
91 | * Use the firmware interface to load the ucode images into | |
92 | * the driver (not loaded into hw). | |
93 | * Returns 0 on success, error on failure. | |
94 | */ | |
95 | static int cik_sdma_init_microcode(struct amdgpu_device *adev) | |
96 | { | |
97 | const char *chip_name; | |
98 | char fw_name[30]; | |
99 | int err, i; | |
100 | ||
101 | DRM_DEBUG("\n"); | |
102 | ||
103 | switch (adev->asic_type) { | |
104 | case CHIP_BONAIRE: | |
105 | chip_name = "bonaire"; | |
106 | break; | |
107 | case CHIP_HAWAII: | |
108 | chip_name = "hawaii"; | |
109 | break; | |
110 | case CHIP_KAVERI: | |
111 | chip_name = "kaveri"; | |
112 | break; | |
113 | case CHIP_KABINI: | |
114 | chip_name = "kabini"; | |
115 | break; | |
116 | case CHIP_MULLINS: | |
117 | chip_name = "mullins"; | |
118 | break; | |
119 | default: BUG(); | |
120 | } | |
121 | ||
122 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
123 | if (i == 0) | |
124 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); | |
125 | else | |
126 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); | |
127 | err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); | |
128 | if (err) | |
129 | goto out; | |
130 | err = amdgpu_ucode_validate(adev->sdma[i].fw); | |
131 | } | |
132 | out: | |
133 | if (err) { | |
134 | printk(KERN_ERR | |
135 | "cik_sdma: Failed to load firmware \"%s\"\n", | |
136 | fw_name); | |
137 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
138 | release_firmware(adev->sdma[i].fw); | |
139 | adev->sdma[i].fw = NULL; | |
140 | } | |
141 | } | |
142 | return err; | |
143 | } | |
144 | ||
145 | /** | |
146 | * cik_sdma_ring_get_rptr - get the current read pointer | |
147 | * | |
148 | * @ring: amdgpu ring pointer | |
149 | * | |
150 | * Get the current rptr from the hardware (CIK+). | |
151 | */ | |
152 | static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) | |
153 | { | |
154 | u32 rptr; | |
155 | ||
156 | rptr = ring->adev->wb.wb[ring->rptr_offs]; | |
157 | ||
158 | return (rptr & 0x3fffc) >> 2; | |
159 | } | |
160 | ||
161 | /** | |
162 | * cik_sdma_ring_get_wptr - get the current write pointer | |
163 | * | |
164 | * @ring: amdgpu ring pointer | |
165 | * | |
166 | * Get the current wptr from the hardware (CIK+). | |
167 | */ | |
168 | static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) | |
169 | { | |
170 | struct amdgpu_device *adev = ring->adev; | |
171 | u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1; | |
172 | ||
173 | return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; | |
174 | } | |
175 | ||
176 | /** | |
177 | * cik_sdma_ring_set_wptr - commit the write pointer | |
178 | * | |
179 | * @ring: amdgpu ring pointer | |
180 | * | |
181 | * Write the wptr back to the hardware (CIK+). | |
182 | */ | |
183 | static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) | |
184 | { | |
185 | struct amdgpu_device *adev = ring->adev; | |
186 | u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1; | |
187 | ||
188 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); | |
189 | } | |
190 | ||
a2e73f56 AD |
191 | /** |
192 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine | |
193 | * | |
194 | * @ring: amdgpu ring pointer | |
195 | * @ib: IB object to schedule | |
196 | * | |
197 | * Schedule an IB in the DMA ring (CIK). | |
198 | */ | |
199 | static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |
200 | struct amdgpu_ib *ib) | |
201 | { | |
202 | u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; | |
203 | u32 next_rptr = ring->wptr + 5; | |
204 | ||
a2e73f56 AD |
205 | while ((next_rptr & 7) != 4) |
206 | next_rptr++; | |
207 | ||
208 | next_rptr += 4; | |
209 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
210 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
211 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | |
212 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | |
213 | amdgpu_ring_write(ring, next_rptr); | |
214 | ||
a2e73f56 AD |
215 | /* IB packet must end on a 8 DW boundary */ |
216 | while ((ring->wptr & 7) != 4) | |
217 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); | |
218 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); | |
219 | amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ | |
220 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); | |
221 | amdgpu_ring_write(ring, ib->length_dw); | |
222 | ||
223 | } | |
224 | ||
225 | /** | |
d2edb07b | 226 | * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
a2e73f56 AD |
227 | * |
228 | * @ring: amdgpu ring pointer | |
229 | * | |
230 | * Emit an hdp flush packet on the requested DMA ring. | |
231 | */ | |
d2edb07b | 232 | static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
a2e73f56 AD |
233 | { |
234 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | | |
235 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | |
236 | u32 ref_and_mask; | |
237 | ||
238 | if (ring == &ring->adev->sdma[0].ring) | |
239 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; | |
240 | else | |
241 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; | |
242 | ||
243 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
244 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
245 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
246 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
247 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
248 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
249 | } | |
250 | ||
251 | /** | |
252 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring | |
253 | * | |
254 | * @ring: amdgpu ring pointer | |
255 | * @fence: amdgpu fence object | |
256 | * | |
257 | * Add a DMA fence packet to the ring to write | |
258 | * the fence seq number and DMA trap packet to generate | |
259 | * an interrupt if needed (CIK). | |
260 | */ | |
261 | static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
262 | bool write64bit) | |
263 | { | |
264 | /* write the fence */ | |
265 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
266 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
267 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
268 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
269 | ||
270 | /* optionally write high bits as well */ | |
271 | if (write64bit) { | |
272 | addr += 4; | |
273 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
274 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
275 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
276 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
277 | } | |
278 | ||
279 | /* generate an interrupt */ | |
280 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); | |
281 | } | |
282 | ||
283 | /** | |
284 | * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring | |
285 | * | |
286 | * @ring: amdgpu_ring structure holding ring information | |
287 | * @semaphore: amdgpu semaphore object | |
288 | * @emit_wait: wait or signal semaphore | |
289 | * | |
290 | * Add a DMA semaphore packet to the ring wait on or signal | |
291 | * other rings (CIK). | |
292 | */ | |
293 | static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring, | |
294 | struct amdgpu_semaphore *semaphore, | |
295 | bool emit_wait) | |
296 | { | |
297 | u64 addr = semaphore->gpu_addr; | |
298 | u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; | |
299 | ||
300 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); | |
301 | amdgpu_ring_write(ring, addr & 0xfffffff8); | |
302 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
303 | ||
304 | return true; | |
305 | } | |
306 | ||
307 | /** | |
308 | * cik_sdma_gfx_stop - stop the gfx async dma engines | |
309 | * | |
310 | * @adev: amdgpu_device pointer | |
311 | * | |
312 | * Stop the gfx async dma ring buffers (CIK). | |
313 | */ | |
314 | static void cik_sdma_gfx_stop(struct amdgpu_device *adev) | |
315 | { | |
316 | struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; | |
317 | struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; | |
318 | u32 rb_cntl; | |
319 | int i; | |
320 | ||
321 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
322 | (adev->mman.buffer_funcs_ring == sdma1)) | |
323 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
324 | ||
325 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
326 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); | |
327 | rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; | |
328 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
329 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); | |
330 | } | |
331 | sdma0->ready = false; | |
332 | sdma1->ready = false; | |
333 | } | |
334 | ||
335 | /** | |
336 | * cik_sdma_rlc_stop - stop the compute async dma engines | |
337 | * | |
338 | * @adev: amdgpu_device pointer | |
339 | * | |
340 | * Stop the compute async dma queues (CIK). | |
341 | */ | |
342 | static void cik_sdma_rlc_stop(struct amdgpu_device *adev) | |
343 | { | |
344 | /* XXX todo */ | |
345 | } | |
346 | ||
347 | /** | |
348 | * cik_sdma_enable - stop the async dma engines | |
349 | * | |
350 | * @adev: amdgpu_device pointer | |
351 | * @enable: enable/disable the DMA MEs. | |
352 | * | |
353 | * Halt or unhalt the async dma engines (CIK). | |
354 | */ | |
355 | static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) | |
356 | { | |
357 | u32 me_cntl; | |
358 | int i; | |
359 | ||
360 | if (enable == false) { | |
361 | cik_sdma_gfx_stop(adev); | |
362 | cik_sdma_rlc_stop(adev); | |
363 | } | |
364 | ||
365 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
366 | me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); | |
367 | if (enable) | |
368 | me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; | |
369 | else | |
370 | me_cntl |= SDMA0_F32_CNTL__HALT_MASK; | |
371 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); | |
372 | } | |
373 | } | |
374 | ||
375 | /** | |
376 | * cik_sdma_gfx_resume - setup and start the async dma engines | |
377 | * | |
378 | * @adev: amdgpu_device pointer | |
379 | * | |
380 | * Set up the gfx DMA ring buffers and enable them (CIK). | |
381 | * Returns 0 for success, error for failure. | |
382 | */ | |
383 | static int cik_sdma_gfx_resume(struct amdgpu_device *adev) | |
384 | { | |
385 | struct amdgpu_ring *ring; | |
386 | u32 rb_cntl, ib_cntl; | |
387 | u32 rb_bufsz; | |
388 | u32 wb_offset; | |
389 | int i, j, r; | |
390 | ||
391 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
392 | ring = &adev->sdma[i].ring; | |
393 | wb_offset = (ring->rptr_offs * 4); | |
394 | ||
395 | mutex_lock(&adev->srbm_mutex); | |
396 | for (j = 0; j < 16; j++) { | |
397 | cik_srbm_select(adev, 0, 0, 0, j); | |
398 | /* SDMA GFX */ | |
399 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
400 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
401 | /* XXX SDMA RLC - todo */ | |
402 | } | |
403 | cik_srbm_select(adev, 0, 0, 0, 0); | |
404 | mutex_unlock(&adev->srbm_mutex); | |
405 | ||
406 | WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); | |
407 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); | |
408 | ||
409 | /* Set ring buffer size in dwords */ | |
410 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
411 | rb_cntl = rb_bufsz << 1; | |
412 | #ifdef __BIG_ENDIAN | |
413 | rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; | |
414 | #endif | |
415 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
416 | ||
417 | /* Initialize the ring buffer's read and write pointers */ | |
418 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
419 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
420 | ||
421 | /* set the wb address whether it's enabled or not */ | |
422 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
423 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
424 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
425 | ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); | |
426 | ||
427 | rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; | |
428 | ||
429 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
430 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
431 | ||
432 | ring->wptr = 0; | |
433 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); | |
434 | ||
435 | /* enable DMA RB */ | |
436 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], | |
437 | rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); | |
438 | ||
439 | ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; | |
440 | #ifdef __BIG_ENDIAN | |
441 | ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; | |
442 | #endif | |
443 | /* enable DMA IBs */ | |
444 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
445 | ||
446 | ring->ready = true; | |
447 | ||
448 | r = amdgpu_ring_test_ring(ring); | |
449 | if (r) { | |
450 | ring->ready = false; | |
451 | return r; | |
452 | } | |
453 | ||
454 | if (adev->mman.buffer_funcs_ring == ring) | |
455 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); | |
456 | } | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | /** | |
462 | * cik_sdma_rlc_resume - setup and start the async dma engines | |
463 | * | |
464 | * @adev: amdgpu_device pointer | |
465 | * | |
466 | * Set up the compute DMA queues and enable them (CIK). | |
467 | * Returns 0 for success, error for failure. | |
468 | */ | |
469 | static int cik_sdma_rlc_resume(struct amdgpu_device *adev) | |
470 | { | |
471 | /* XXX todo */ | |
472 | return 0; | |
473 | } | |
474 | ||
475 | /** | |
476 | * cik_sdma_load_microcode - load the sDMA ME ucode | |
477 | * | |
478 | * @adev: amdgpu_device pointer | |
479 | * | |
480 | * Loads the sDMA0/1 ucode. | |
481 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
482 | */ | |
483 | static int cik_sdma_load_microcode(struct amdgpu_device *adev) | |
484 | { | |
485 | const struct sdma_firmware_header_v1_0 *hdr; | |
486 | const __le32 *fw_data; | |
487 | u32 fw_size; | |
488 | int i, j; | |
489 | ||
490 | if (!adev->sdma[0].fw || !adev->sdma[1].fw) | |
491 | return -EINVAL; | |
492 | ||
493 | /* halt the MEs */ | |
494 | cik_sdma_enable(adev, false); | |
495 | ||
496 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
497 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; | |
498 | amdgpu_ucode_print_sdma_hdr(&hdr->header); | |
499 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
500 | adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); | |
501 | fw_data = (const __le32 *) | |
502 | (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
503 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); | |
504 | for (j = 0; j < fw_size; j++) | |
505 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
506 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); | |
507 | } | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | /** | |
513 | * cik_sdma_start - setup and start the async dma engines | |
514 | * | |
515 | * @adev: amdgpu_device pointer | |
516 | * | |
517 | * Set up the DMA engines and enable them (CIK). | |
518 | * Returns 0 for success, error for failure. | |
519 | */ | |
520 | static int cik_sdma_start(struct amdgpu_device *adev) | |
521 | { | |
522 | int r; | |
523 | ||
524 | r = cik_sdma_load_microcode(adev); | |
525 | if (r) | |
526 | return r; | |
527 | ||
528 | /* unhalt the MEs */ | |
529 | cik_sdma_enable(adev, true); | |
530 | ||
531 | /* start the gfx rings and rlc compute queues */ | |
532 | r = cik_sdma_gfx_resume(adev); | |
533 | if (r) | |
534 | return r; | |
535 | r = cik_sdma_rlc_resume(adev); | |
536 | if (r) | |
537 | return r; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | /** | |
543 | * cik_sdma_ring_test_ring - simple async dma engine test | |
544 | * | |
545 | * @ring: amdgpu_ring structure holding ring information | |
546 | * | |
547 | * Test the DMA engine by writing using it to write an | |
548 | * value to memory. (CIK). | |
549 | * Returns 0 for success, error for failure. | |
550 | */ | |
551 | static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) | |
552 | { | |
553 | struct amdgpu_device *adev = ring->adev; | |
554 | unsigned i; | |
555 | unsigned index; | |
556 | int r; | |
557 | u32 tmp; | |
558 | u64 gpu_addr; | |
559 | ||
560 | r = amdgpu_wb_get(adev, &index); | |
561 | if (r) { | |
562 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
563 | return r; | |
564 | } | |
565 | ||
566 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
567 | tmp = 0xCAFEDEAD; | |
568 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
569 | ||
570 | r = amdgpu_ring_lock(ring, 5); | |
571 | if (r) { | |
572 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
573 | amdgpu_wb_free(adev, index); | |
574 | return r; | |
575 | } | |
576 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
577 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
578 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
579 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | |
580 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
581 | amdgpu_ring_unlock_commit(ring); | |
582 | ||
583 | for (i = 0; i < adev->usec_timeout; i++) { | |
584 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
585 | if (tmp == 0xDEADBEEF) | |
586 | break; | |
587 | DRM_UDELAY(1); | |
588 | } | |
589 | ||
590 | if (i < adev->usec_timeout) { | |
591 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
592 | } else { | |
593 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
594 | ring->idx, tmp); | |
595 | r = -EINVAL; | |
596 | } | |
597 | amdgpu_wb_free(adev, index); | |
598 | ||
599 | return r; | |
600 | } | |
601 | ||
602 | /** | |
603 | * cik_sdma_ring_test_ib - test an IB on the DMA engine | |
604 | * | |
605 | * @ring: amdgpu_ring structure holding ring information | |
606 | * | |
607 | * Test a simple IB in the DMA ring (CIK). | |
608 | * Returns 0 on success, error on failure. | |
609 | */ | |
610 | static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring) | |
611 | { | |
612 | struct amdgpu_device *adev = ring->adev; | |
613 | struct amdgpu_ib ib; | |
614 | unsigned i; | |
615 | unsigned index; | |
616 | int r; | |
617 | u32 tmp = 0; | |
618 | u64 gpu_addr; | |
619 | ||
620 | r = amdgpu_wb_get(adev, &index); | |
621 | if (r) { | |
622 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
623 | return r; | |
624 | } | |
625 | ||
626 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
627 | tmp = 0xCAFEDEAD; | |
628 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
629 | ||
630 | r = amdgpu_ib_get(ring, NULL, 256, &ib); | |
631 | if (r) { | |
632 | amdgpu_wb_free(adev, index); | |
633 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); | |
634 | return r; | |
635 | } | |
636 | ||
637 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
638 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
639 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
640 | ib.ptr[3] = 1; | |
641 | ib.ptr[4] = 0xDEADBEEF; | |
642 | ib.length_dw = 5; | |
643 | ||
644 | r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); | |
645 | if (r) { | |
646 | amdgpu_ib_free(adev, &ib); | |
647 | amdgpu_wb_free(adev, index); | |
648 | DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); | |
649 | return r; | |
650 | } | |
651 | r = amdgpu_fence_wait(ib.fence, false); | |
652 | if (r) { | |
653 | amdgpu_ib_free(adev, &ib); | |
654 | amdgpu_wb_free(adev, index); | |
655 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); | |
656 | return r; | |
657 | } | |
658 | for (i = 0; i < adev->usec_timeout; i++) { | |
659 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
660 | if (tmp == 0xDEADBEEF) | |
661 | break; | |
662 | DRM_UDELAY(1); | |
663 | } | |
664 | if (i < adev->usec_timeout) { | |
665 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", | |
666 | ib.fence->ring->idx, i); | |
667 | } else { | |
668 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
669 | r = -EINVAL; | |
670 | } | |
671 | amdgpu_ib_free(adev, &ib); | |
672 | amdgpu_wb_free(adev, index); | |
673 | return r; | |
674 | } | |
675 | ||
676 | /** | |
677 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART | |
678 | * | |
679 | * @ib: indirect buffer to fill with commands | |
680 | * @pe: addr of the page entry | |
681 | * @src: src addr to copy from | |
682 | * @count: number of page entries to update | |
683 | * | |
684 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
685 | */ | |
686 | static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, | |
687 | uint64_t pe, uint64_t src, | |
688 | unsigned count) | |
689 | { | |
690 | while (count) { | |
691 | unsigned bytes = count * 8; | |
692 | if (bytes > 0x1FFFF8) | |
693 | bytes = 0x1FFFF8; | |
694 | ||
695 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, | |
696 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
697 | ib->ptr[ib->length_dw++] = bytes; | |
698 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
699 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
700 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
701 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
702 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
703 | ||
704 | pe += bytes; | |
705 | src += bytes; | |
706 | count -= bytes / 8; | |
707 | } | |
708 | } | |
709 | ||
710 | /** | |
711 | * cik_sdma_vm_write_pages - update PTEs by writing them manually | |
712 | * | |
713 | * @ib: indirect buffer to fill with commands | |
714 | * @pe: addr of the page entry | |
715 | * @addr: dst addr to write into pe | |
716 | * @count: number of page entries to update | |
717 | * @incr: increase next addr by incr bytes | |
718 | * @flags: access flags | |
719 | * | |
720 | * Update PTEs by writing them manually using sDMA (CIK). | |
721 | */ | |
722 | static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, | |
723 | uint64_t pe, | |
724 | uint64_t addr, unsigned count, | |
725 | uint32_t incr, uint32_t flags) | |
726 | { | |
727 | uint64_t value; | |
728 | unsigned ndw; | |
729 | ||
730 | while (count) { | |
731 | ndw = count * 2; | |
732 | if (ndw > 0xFFFFE) | |
733 | ndw = 0xFFFFE; | |
734 | ||
735 | /* for non-physically contiguous pages (system) */ | |
736 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | |
737 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
738 | ib->ptr[ib->length_dw++] = pe; | |
739 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
740 | ib->ptr[ib->length_dw++] = ndw; | |
741 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
742 | if (flags & AMDGPU_PTE_SYSTEM) { | |
743 | value = amdgpu_vm_map_gart(ib->ring->adev, addr); | |
744 | value &= 0xFFFFFFFFFFFFF000ULL; | |
745 | } else if (flags & AMDGPU_PTE_VALID) { | |
746 | value = addr; | |
747 | } else { | |
748 | value = 0; | |
749 | } | |
750 | addr += incr; | |
751 | value |= flags; | |
752 | ib->ptr[ib->length_dw++] = value; | |
753 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
754 | } | |
755 | } | |
756 | } | |
757 | ||
758 | /** | |
759 | * cik_sdma_vm_set_pages - update the page tables using sDMA | |
760 | * | |
761 | * @ib: indirect buffer to fill with commands | |
762 | * @pe: addr of the page entry | |
763 | * @addr: dst addr to write into pe | |
764 | * @count: number of page entries to update | |
765 | * @incr: increase next addr by incr bytes | |
766 | * @flags: access flags | |
767 | * | |
768 | * Update the page tables using sDMA (CIK). | |
769 | */ | |
770 | static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, | |
771 | uint64_t pe, | |
772 | uint64_t addr, unsigned count, | |
773 | uint32_t incr, uint32_t flags) | |
774 | { | |
775 | uint64_t value; | |
776 | unsigned ndw; | |
777 | ||
778 | while (count) { | |
779 | ndw = count; | |
780 | if (ndw > 0x7FFFF) | |
781 | ndw = 0x7FFFF; | |
782 | ||
783 | if (flags & AMDGPU_PTE_VALID) | |
784 | value = addr; | |
785 | else | |
786 | value = 0; | |
787 | ||
788 | /* for physically contiguous pages (vram) */ | |
789 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); | |
790 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
791 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
792 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
793 | ib->ptr[ib->length_dw++] = 0; | |
794 | ib->ptr[ib->length_dw++] = value; /* value */ | |
795 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
796 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
797 | ib->ptr[ib->length_dw++] = 0; | |
798 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ | |
799 | ||
800 | pe += ndw * 8; | |
801 | addr += ndw * incr; | |
802 | count -= ndw; | |
803 | } | |
804 | } | |
805 | ||
806 | /** | |
807 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw | |
808 | * | |
809 | * @ib: indirect buffer to fill with padding | |
810 | * | |
811 | */ | |
812 | static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib) | |
813 | { | |
814 | while (ib->length_dw & 0x7) | |
815 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); | |
816 | } | |
817 | ||
818 | /** | |
819 | * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA | |
820 | * | |
821 | * @ring: amdgpu_ring pointer | |
822 | * @vm: amdgpu_vm pointer | |
823 | * | |
824 | * Update the page table base and flush the VM TLB | |
825 | * using sDMA (CIK). | |
826 | */ | |
827 | static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
828 | unsigned vm_id, uint64_t pd_addr) | |
829 | { | |
830 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | | |
831 | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ | |
74a5d165 JX |
832 | u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, |
833 | SH_MEM_ALIGNMENT_MODE_UNALIGNED); | |
a2e73f56 AD |
834 | |
835 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
836 | if (vm_id < 8) { | |
837 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
838 | } else { | |
839 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
840 | } | |
841 | amdgpu_ring_write(ring, pd_addr >> 12); | |
842 | ||
843 | /* update SH_MEM_* regs */ | |
844 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
845 | amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); | |
846 | amdgpu_ring_write(ring, VMID(vm_id)); | |
847 | ||
848 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
849 | amdgpu_ring_write(ring, mmSH_MEM_BASES); | |
850 | amdgpu_ring_write(ring, 0); | |
851 | ||
852 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
853 | amdgpu_ring_write(ring, mmSH_MEM_CONFIG); | |
74a5d165 | 854 | amdgpu_ring_write(ring, sh_mem_cfg); |
a2e73f56 AD |
855 | |
856 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
857 | amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); | |
858 | amdgpu_ring_write(ring, 1); | |
859 | ||
860 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
861 | amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); | |
862 | amdgpu_ring_write(ring, 0); | |
863 | ||
864 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
865 | amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); | |
866 | amdgpu_ring_write(ring, VMID(0)); | |
867 | ||
868 | /* flush TLB */ | |
869 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
870 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
871 | amdgpu_ring_write(ring, 1 << vm_id); | |
872 | ||
873 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
874 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
875 | amdgpu_ring_write(ring, 0); | |
876 | amdgpu_ring_write(ring, 0); /* reference */ | |
877 | amdgpu_ring_write(ring, 0); /* mask */ | |
878 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
879 | } | |
880 | ||
881 | static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, | |
882 | bool enable) | |
883 | { | |
884 | u32 orig, data; | |
885 | ||
886 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) { | |
887 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); | |
888 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); | |
889 | } else { | |
890 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); | |
891 | data |= 0xff000000; | |
892 | if (data != orig) | |
893 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); | |
894 | ||
895 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); | |
896 | data |= 0xff000000; | |
897 | if (data != orig) | |
898 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); | |
899 | } | |
900 | } | |
901 | ||
902 | static void cik_enable_sdma_mgls(struct amdgpu_device *adev, | |
903 | bool enable) | |
904 | { | |
905 | u32 orig, data; | |
906 | ||
907 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) { | |
908 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); | |
909 | data |= 0x100; | |
910 | if (orig != data) | |
911 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
912 | ||
913 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
914 | data |= 0x100; | |
915 | if (orig != data) | |
916 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
917 | } else { | |
918 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); | |
919 | data &= ~0x100; | |
920 | if (orig != data) | |
921 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
922 | ||
923 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
924 | data &= ~0x100; | |
925 | if (orig != data) | |
926 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
927 | } | |
928 | } | |
929 | ||
930 | static int cik_sdma_early_init(struct amdgpu_device *adev) | |
931 | { | |
932 | cik_sdma_set_ring_funcs(adev); | |
933 | cik_sdma_set_irq_funcs(adev); | |
934 | cik_sdma_set_buffer_funcs(adev); | |
935 | cik_sdma_set_vm_pte_funcs(adev); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static int cik_sdma_sw_init(struct amdgpu_device *adev) | |
941 | { | |
942 | struct amdgpu_ring *ring; | |
943 | int r; | |
944 | ||
945 | r = cik_sdma_init_microcode(adev); | |
946 | if (r) { | |
947 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
948 | return r; | |
949 | } | |
950 | ||
951 | /* SDMA trap event */ | |
952 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); | |
953 | if (r) | |
954 | return r; | |
955 | ||
956 | /* SDMA Privileged inst */ | |
957 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); | |
958 | if (r) | |
959 | return r; | |
960 | ||
961 | /* SDMA Privileged inst */ | |
962 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); | |
963 | if (r) | |
964 | return r; | |
965 | ||
966 | ring = &adev->sdma[0].ring; | |
967 | ring->ring_obj = NULL; | |
968 | ||
969 | ring = &adev->sdma[1].ring; | |
970 | ring->ring_obj = NULL; | |
971 | ||
972 | ring = &adev->sdma[0].ring; | |
973 | sprintf(ring->name, "sdma0"); | |
974 | r = amdgpu_ring_init(adev, ring, 256 * 1024, | |
975 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, | |
976 | &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, | |
977 | AMDGPU_RING_TYPE_SDMA); | |
978 | if (r) | |
979 | return r; | |
980 | ||
981 | ring = &adev->sdma[1].ring; | |
982 | sprintf(ring->name, "sdma1"); | |
983 | r = amdgpu_ring_init(adev, ring, 256 * 1024, | |
984 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, | |
985 | &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, | |
986 | AMDGPU_RING_TYPE_SDMA); | |
987 | if (r) | |
988 | return r; | |
989 | ||
990 | return r; | |
991 | } | |
992 | ||
993 | static int cik_sdma_sw_fini(struct amdgpu_device *adev) | |
994 | { | |
995 | amdgpu_ring_fini(&adev->sdma[0].ring); | |
996 | amdgpu_ring_fini(&adev->sdma[1].ring); | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | static int cik_sdma_hw_init(struct amdgpu_device *adev) | |
1002 | { | |
1003 | int r; | |
1004 | ||
1005 | r = cik_sdma_start(adev); | |
1006 | if (r) | |
1007 | return r; | |
1008 | ||
1009 | return r; | |
1010 | } | |
1011 | ||
1012 | static int cik_sdma_hw_fini(struct amdgpu_device *adev) | |
1013 | { | |
1014 | cik_sdma_enable(adev, false); | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | static int cik_sdma_suspend(struct amdgpu_device *adev) | |
1020 | { | |
1021 | ||
1022 | return cik_sdma_hw_fini(adev); | |
1023 | } | |
1024 | ||
1025 | static int cik_sdma_resume(struct amdgpu_device *adev) | |
1026 | { | |
1027 | ||
1028 | return cik_sdma_hw_init(adev); | |
1029 | } | |
1030 | ||
1031 | static bool cik_sdma_is_idle(struct amdgpu_device *adev) | |
1032 | { | |
1033 | u32 tmp = RREG32(mmSRBM_STATUS2); | |
1034 | ||
1035 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1036 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1037 | return false; | |
1038 | ||
1039 | return true; | |
1040 | } | |
1041 | ||
1042 | static int cik_sdma_wait_for_idle(struct amdgpu_device *adev) | |
1043 | { | |
1044 | unsigned i; | |
1045 | u32 tmp; | |
1046 | ||
1047 | for (i = 0; i < adev->usec_timeout; i++) { | |
1048 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1049 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1050 | ||
1051 | if (!tmp) | |
1052 | return 0; | |
1053 | udelay(1); | |
1054 | } | |
1055 | return -ETIMEDOUT; | |
1056 | } | |
1057 | ||
1058 | static void cik_sdma_print_status(struct amdgpu_device *adev) | |
1059 | { | |
1060 | int i, j; | |
1061 | ||
1062 | dev_info(adev->dev, "CIK SDMA registers\n"); | |
1063 | dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", | |
1064 | RREG32(mmSRBM_STATUS2)); | |
1065 | for (i = 0; i < SDMA_MAX_INSTANCE; i++) { | |
1066 | dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", | |
1067 | i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); | |
1068 | dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n", | |
1069 | i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); | |
1070 | dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", | |
1071 | i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); | |
1072 | dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", | |
1073 | i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i])); | |
1074 | dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", | |
1075 | i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); | |
1076 | dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", | |
1077 | i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); | |
1078 | dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", | |
1079 | i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); | |
1080 | dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", | |
1081 | i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); | |
1082 | dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", | |
1083 | i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); | |
1084 | dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", | |
1085 | i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); | |
1086 | dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", | |
1087 | i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); | |
1088 | dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", | |
1089 | i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); | |
1090 | dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", | |
1091 | i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); | |
1092 | mutex_lock(&adev->srbm_mutex); | |
1093 | for (j = 0; j < 16; j++) { | |
1094 | cik_srbm_select(adev, 0, 0, 0, j); | |
1095 | dev_info(adev->dev, " VM %d:\n", j); | |
1096 | dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n", | |
1097 | RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); | |
1098 | dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n", | |
1099 | RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); | |
1100 | } | |
1101 | cik_srbm_select(adev, 0, 0, 0, 0); | |
1102 | mutex_unlock(&adev->srbm_mutex); | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | static int cik_sdma_soft_reset(struct amdgpu_device *adev) | |
1107 | { | |
1108 | u32 srbm_soft_reset = 0; | |
1109 | u32 tmp = RREG32(mmSRBM_STATUS2); | |
1110 | ||
1111 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1112 | /* sdma0 */ | |
1113 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1114 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1115 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1116 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1117 | } | |
1118 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1119 | /* sdma1 */ | |
1120 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1121 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1122 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1123 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1124 | } | |
1125 | ||
1126 | if (srbm_soft_reset) { | |
1127 | cik_sdma_print_status(adev); | |
1128 | ||
1129 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1130 | tmp |= srbm_soft_reset; | |
1131 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1132 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1133 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1134 | ||
1135 | udelay(50); | |
1136 | ||
1137 | tmp &= ~srbm_soft_reset; | |
1138 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1139 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1140 | ||
1141 | /* Wait a little for things to settle down */ | |
1142 | udelay(50); | |
1143 | ||
1144 | cik_sdma_print_status(adev); | |
1145 | } | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, | |
1151 | struct amdgpu_irq_src *src, | |
1152 | unsigned type, | |
1153 | enum amdgpu_interrupt_state state) | |
1154 | { | |
1155 | u32 sdma_cntl; | |
1156 | ||
1157 | switch (type) { | |
1158 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1159 | switch (state) { | |
1160 | case AMDGPU_IRQ_STATE_DISABLE: | |
1161 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1162 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1163 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1164 | break; | |
1165 | case AMDGPU_IRQ_STATE_ENABLE: | |
1166 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1167 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1168 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1169 | break; | |
1170 | default: | |
1171 | break; | |
1172 | } | |
1173 | break; | |
1174 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1175 | switch (state) { | |
1176 | case AMDGPU_IRQ_STATE_DISABLE: | |
1177 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1178 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1179 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1180 | break; | |
1181 | case AMDGPU_IRQ_STATE_ENABLE: | |
1182 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1183 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1184 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1185 | break; | |
1186 | default: | |
1187 | break; | |
1188 | } | |
1189 | break; | |
1190 | default: | |
1191 | break; | |
1192 | } | |
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, | |
1197 | struct amdgpu_irq_src *source, | |
1198 | struct amdgpu_iv_entry *entry) | |
1199 | { | |
1200 | u8 instance_id, queue_id; | |
1201 | ||
1202 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1203 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1204 | DRM_DEBUG("IH: SDMA trap\n"); | |
1205 | switch (instance_id) { | |
1206 | case 0: | |
1207 | switch (queue_id) { | |
1208 | case 0: | |
1209 | amdgpu_fence_process(&adev->sdma[0].ring); | |
1210 | break; | |
1211 | case 1: | |
1212 | /* XXX compute */ | |
1213 | break; | |
1214 | case 2: | |
1215 | /* XXX compute */ | |
1216 | break; | |
1217 | } | |
1218 | break; | |
1219 | case 1: | |
1220 | switch (queue_id) { | |
1221 | case 0: | |
1222 | amdgpu_fence_process(&adev->sdma[1].ring); | |
1223 | break; | |
1224 | case 1: | |
1225 | /* XXX compute */ | |
1226 | break; | |
1227 | case 2: | |
1228 | /* XXX compute */ | |
1229 | break; | |
1230 | } | |
1231 | break; | |
1232 | } | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1238 | struct amdgpu_irq_src *source, | |
1239 | struct amdgpu_iv_entry *entry) | |
1240 | { | |
1241 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1242 | schedule_work(&adev->reset_work); | |
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev, | |
1247 | enum amdgpu_clockgating_state state) | |
1248 | { | |
1249 | bool gate = false; | |
1250 | ||
1251 | if (state == AMDGPU_CG_STATE_GATE) | |
1252 | gate = true; | |
1253 | ||
1254 | cik_enable_sdma_mgcg(adev, gate); | |
1255 | cik_enable_sdma_mgls(adev, gate); | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | static int cik_sdma_set_powergating_state(struct amdgpu_device *adev, | |
1261 | enum amdgpu_powergating_state state) | |
1262 | { | |
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | const struct amdgpu_ip_funcs cik_sdma_ip_funcs = { | |
1267 | .early_init = cik_sdma_early_init, | |
1268 | .late_init = NULL, | |
1269 | .sw_init = cik_sdma_sw_init, | |
1270 | .sw_fini = cik_sdma_sw_fini, | |
1271 | .hw_init = cik_sdma_hw_init, | |
1272 | .hw_fini = cik_sdma_hw_fini, | |
1273 | .suspend = cik_sdma_suspend, | |
1274 | .resume = cik_sdma_resume, | |
1275 | .is_idle = cik_sdma_is_idle, | |
1276 | .wait_for_idle = cik_sdma_wait_for_idle, | |
1277 | .soft_reset = cik_sdma_soft_reset, | |
1278 | .print_status = cik_sdma_print_status, | |
1279 | .set_clockgating_state = cik_sdma_set_clockgating_state, | |
1280 | .set_powergating_state = cik_sdma_set_powergating_state, | |
1281 | }; | |
1282 | ||
1283 | /** | |
1284 | * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up | |
1285 | * | |
1286 | * @ring: amdgpu_ring structure holding ring information | |
1287 | * | |
1288 | * Check if the async DMA engine is locked up (CIK). | |
1289 | * Returns true if the engine appears to be locked up, false if not. | |
1290 | */ | |
1291 | static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring) | |
1292 | { | |
1293 | ||
1294 | if (cik_sdma_is_idle(ring->adev)) { | |
1295 | amdgpu_ring_lockup_update(ring); | |
1296 | return false; | |
1297 | } | |
1298 | return amdgpu_ring_test_lockup(ring); | |
1299 | } | |
1300 | ||
1301 | static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { | |
1302 | .get_rptr = cik_sdma_ring_get_rptr, | |
1303 | .get_wptr = cik_sdma_ring_get_wptr, | |
1304 | .set_wptr = cik_sdma_ring_set_wptr, | |
1305 | .parse_cs = NULL, | |
1306 | .emit_ib = cik_sdma_ring_emit_ib, | |
1307 | .emit_fence = cik_sdma_ring_emit_fence, | |
1308 | .emit_semaphore = cik_sdma_ring_emit_semaphore, | |
1309 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, | |
d2edb07b | 1310 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
a2e73f56 AD |
1311 | .test_ring = cik_sdma_ring_test_ring, |
1312 | .test_ib = cik_sdma_ring_test_ib, | |
1313 | .is_lockup = cik_sdma_ring_is_lockup, | |
1314 | }; | |
1315 | ||
1316 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) | |
1317 | { | |
1318 | adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs; | |
1319 | adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs; | |
1320 | } | |
1321 | ||
1322 | static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { | |
1323 | .set = cik_sdma_set_trap_irq_state, | |
1324 | .process = cik_sdma_process_trap_irq, | |
1325 | }; | |
1326 | ||
1327 | static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { | |
1328 | .process = cik_sdma_process_illegal_inst_irq, | |
1329 | }; | |
1330 | ||
1331 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) | |
1332 | { | |
1333 | adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; | |
1334 | adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs; | |
1335 | adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; | |
1336 | } | |
1337 | ||
1338 | /** | |
1339 | * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine | |
1340 | * | |
1341 | * @ring: amdgpu_ring structure holding ring information | |
1342 | * @src_offset: src GPU address | |
1343 | * @dst_offset: dst GPU address | |
1344 | * @byte_count: number of bytes to xfer | |
1345 | * | |
1346 | * Copy GPU buffers using the DMA engine (CIK). | |
1347 | * Used by the amdgpu ttm implementation to move pages if | |
1348 | * registered as the asic copy callback. | |
1349 | */ | |
1350 | static void cik_sdma_emit_copy_buffer(struct amdgpu_ring *ring, | |
1351 | uint64_t src_offset, | |
1352 | uint64_t dst_offset, | |
1353 | uint32_t byte_count) | |
1354 | { | |
1355 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); | |
1356 | amdgpu_ring_write(ring, byte_count); | |
1357 | amdgpu_ring_write(ring, 0); /* src/dst endian swap */ | |
1358 | amdgpu_ring_write(ring, lower_32_bits(src_offset)); | |
1359 | amdgpu_ring_write(ring, upper_32_bits(src_offset)); | |
1360 | amdgpu_ring_write(ring, lower_32_bits(dst_offset)); | |
1361 | amdgpu_ring_write(ring, upper_32_bits(dst_offset)); | |
1362 | } | |
1363 | ||
1364 | /** | |
1365 | * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine | |
1366 | * | |
1367 | * @ring: amdgpu_ring structure holding ring information | |
1368 | * @src_data: value to write to buffer | |
1369 | * @dst_offset: dst GPU address | |
1370 | * @byte_count: number of bytes to xfer | |
1371 | * | |
1372 | * Fill GPU buffers using the DMA engine (CIK). | |
1373 | */ | |
1374 | static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring, | |
1375 | uint32_t src_data, | |
1376 | uint64_t dst_offset, | |
1377 | uint32_t byte_count) | |
1378 | { | |
1379 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0)); | |
1380 | amdgpu_ring_write(ring, lower_32_bits(dst_offset)); | |
1381 | amdgpu_ring_write(ring, upper_32_bits(dst_offset)); | |
1382 | amdgpu_ring_write(ring, src_data); | |
1383 | amdgpu_ring_write(ring, byte_count); | |
1384 | } | |
1385 | ||
1386 | static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { | |
1387 | .copy_max_bytes = 0x1fffff, | |
1388 | .copy_num_dw = 7, | |
1389 | .emit_copy_buffer = cik_sdma_emit_copy_buffer, | |
1390 | ||
1391 | .fill_max_bytes = 0x1fffff, | |
1392 | .fill_num_dw = 5, | |
1393 | .emit_fill_buffer = cik_sdma_emit_fill_buffer, | |
1394 | }; | |
1395 | ||
1396 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) | |
1397 | { | |
1398 | if (adev->mman.buffer_funcs == NULL) { | |
1399 | adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; | |
1400 | adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { | |
1405 | .copy_pte = cik_sdma_vm_copy_pte, | |
1406 | .write_pte = cik_sdma_vm_write_pte, | |
1407 | .set_pte_pde = cik_sdma_vm_set_pte_pde, | |
1408 | .pad_ib = cik_sdma_vm_pad_ib, | |
1409 | }; | |
1410 | ||
1411 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1412 | { | |
1413 | if (adev->vm_manager.vm_pte_funcs == NULL) { | |
1414 | adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; | |
1415 | adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; | |
1416 | } | |
1417 | } |