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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #ifndef CIK_H | |
25 | #define CIK_H | |
26 | ||
81c59f54 KW |
27 | #define MC_SEQ_MISC0__MT__MASK 0xf0000000 |
28 | #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 | |
29 | #define MC_SEQ_MISC0__MT__DDR2 0x20000000 | |
30 | #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 | |
31 | #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 | |
32 | #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 | |
33 | #define MC_SEQ_MISC0__MT__HBM 0x60000000 | |
34 | #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 | |
d38ceaf9 AD |
35 | |
36 | #define CP_ME_TABLE_SIZE 96 | |
37 | ||
38 | /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ | |
39 | #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) | |
40 | #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) | |
41 | #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) | |
42 | #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) | |
43 | #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) | |
44 | #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) | |
45 | ||
46 | #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 | |
47 | #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 | |
48 | ||
d38ceaf9 AD |
49 | #define AMDGPU_NUM_OF_VMIDS 8 |
50 | ||
51 | #define PIPEID(x) ((x) << 0) | |
52 | #define MEID(x) ((x) << 2) | |
53 | #define VMID(x) ((x) << 4) | |
54 | #define QUEUEID(x) ((x) << 8) | |
55 | ||
56 | #define mmCC_DRM_ID_STRAPS 0x1559 | |
57 | #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 | |
58 | ||
59 | #define mmCHUB_CONTROL 0x619 | |
60 | #define BYPASS_VM (1 << 0) | |
61 | ||
62 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
63 | ||
64 | #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 | |
65 | #define LUT_10BIT_BYPASS_EN (1 << 8) | |
66 | ||
67 | # define CURSOR_MONO 0 | |
68 | # define CURSOR_24_1 1 | |
69 | # define CURSOR_24_8_PRE_MULT 2 | |
70 | # define CURSOR_24_8_UNPRE_MULT 3 | |
71 | # define CURSOR_URGENT_ALWAYS 0 | |
72 | # define CURSOR_URGENT_1_8 1 | |
73 | # define CURSOR_URGENT_1_4 2 | |
74 | # define CURSOR_URGENT_3_8 3 | |
75 | # define CURSOR_URGENT_1_2 4 | |
76 | ||
77 | # define GRPH_DEPTH_8BPP 0 | |
78 | # define GRPH_DEPTH_16BPP 1 | |
79 | # define GRPH_DEPTH_32BPP 2 | |
80 | /* 8 BPP */ | |
81 | # define GRPH_FORMAT_INDEXED 0 | |
82 | /* 16 BPP */ | |
83 | # define GRPH_FORMAT_ARGB1555 0 | |
84 | # define GRPH_FORMAT_ARGB565 1 | |
85 | # define GRPH_FORMAT_ARGB4444 2 | |
86 | # define GRPH_FORMAT_AI88 3 | |
87 | # define GRPH_FORMAT_MONO16 4 | |
88 | # define GRPH_FORMAT_BGRA5551 5 | |
89 | /* 32 BPP */ | |
90 | # define GRPH_FORMAT_ARGB8888 0 | |
91 | # define GRPH_FORMAT_ARGB2101010 1 | |
92 | # define GRPH_FORMAT_32BPP_DIG 2 | |
93 | # define GRPH_FORMAT_8B_ARGB2101010 3 | |
94 | # define GRPH_FORMAT_BGRA1010102 4 | |
95 | # define GRPH_FORMAT_8B_BGRA1010102 5 | |
96 | # define GRPH_FORMAT_RGB111110 6 | |
97 | # define GRPH_FORMAT_BGR101111 7 | |
98 | # define ADDR_SURF_MACRO_TILE_ASPECT_1 0 | |
99 | # define ADDR_SURF_MACRO_TILE_ASPECT_2 1 | |
100 | # define ADDR_SURF_MACRO_TILE_ASPECT_4 2 | |
101 | # define ADDR_SURF_MACRO_TILE_ASPECT_8 3 | |
102 | # define GRPH_ARRAY_LINEAR_GENERAL 0 | |
103 | # define GRPH_ARRAY_LINEAR_ALIGNED 1 | |
104 | # define GRPH_ARRAY_1D_TILED_THIN1 2 | |
105 | # define GRPH_ARRAY_2D_TILED_THIN1 4 | |
106 | # define DISPLAY_MICRO_TILING 0 | |
107 | # define THIN_MICRO_TILING 1 | |
108 | # define DEPTH_MICRO_TILING 2 | |
109 | # define ROTATED_MICRO_TILING 4 | |
110 | # define GRPH_ENDIAN_NONE 0 | |
111 | # define GRPH_ENDIAN_8IN16 1 | |
112 | # define GRPH_ENDIAN_8IN32 2 | |
113 | # define GRPH_ENDIAN_8IN64 3 | |
114 | # define GRPH_RED_SEL_R 0 | |
115 | # define GRPH_RED_SEL_G 1 | |
116 | # define GRPH_RED_SEL_B 2 | |
117 | # define GRPH_RED_SEL_A 3 | |
118 | # define GRPH_GREEN_SEL_G 0 | |
119 | # define GRPH_GREEN_SEL_B 1 | |
120 | # define GRPH_GREEN_SEL_A 2 | |
121 | # define GRPH_GREEN_SEL_R 3 | |
122 | # define GRPH_BLUE_SEL_B 0 | |
123 | # define GRPH_BLUE_SEL_A 1 | |
124 | # define GRPH_BLUE_SEL_R 2 | |
125 | # define GRPH_BLUE_SEL_G 3 | |
126 | # define GRPH_ALPHA_SEL_A 0 | |
127 | # define GRPH_ALPHA_SEL_R 1 | |
128 | # define GRPH_ALPHA_SEL_G 2 | |
129 | # define GRPH_ALPHA_SEL_B 3 | |
130 | # define INPUT_GAMMA_USE_LUT 0 | |
131 | # define INPUT_GAMMA_BYPASS 1 | |
132 | # define INPUT_GAMMA_SRGB_24 2 | |
133 | # define INPUT_GAMMA_XVYCC_222 3 | |
134 | ||
135 | # define INPUT_CSC_BYPASS 0 | |
136 | # define INPUT_CSC_PROG_COEFF 1 | |
137 | # define INPUT_CSC_PROG_SHARED_MATRIXA 2 | |
138 | ||
139 | # define OUTPUT_CSC_BYPASS 0 | |
140 | # define OUTPUT_CSC_TV_RGB 1 | |
141 | # define OUTPUT_CSC_YCBCR_601 2 | |
142 | # define OUTPUT_CSC_YCBCR_709 3 | |
143 | # define OUTPUT_CSC_PROG_COEFF 4 | |
144 | # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 | |
145 | ||
146 | # define DEGAMMA_BYPASS 0 | |
147 | # define DEGAMMA_SRGB_24 1 | |
148 | # define DEGAMMA_XVYCC_222 2 | |
149 | # define GAMUT_REMAP_BYPASS 0 | |
150 | # define GAMUT_REMAP_PROG_COEFF 1 | |
151 | # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 | |
152 | # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 | |
153 | ||
154 | # define REGAMMA_BYPASS 0 | |
155 | # define REGAMMA_SRGB_24 1 | |
156 | # define REGAMMA_XVYCC_222 2 | |
157 | # define REGAMMA_PROG_A 3 | |
158 | # define REGAMMA_PROG_B 4 | |
159 | ||
160 | # define FMT_CLAMP_6BPC 0 | |
161 | # define FMT_CLAMP_8BPC 1 | |
162 | # define FMT_CLAMP_10BPC 2 | |
163 | ||
164 | # define HDMI_24BIT_DEEP_COLOR 0 | |
165 | # define HDMI_30BIT_DEEP_COLOR 1 | |
166 | # define HDMI_36BIT_DEEP_COLOR 2 | |
167 | # define HDMI_ACR_HW 0 | |
168 | # define HDMI_ACR_32 1 | |
169 | # define HDMI_ACR_44 2 | |
170 | # define HDMI_ACR_48 3 | |
171 | # define HDMI_ACR_X1 1 | |
172 | # define HDMI_ACR_X2 2 | |
173 | # define HDMI_ACR_X4 4 | |
174 | # define AFMT_AVI_INFO_Y_RGB 0 | |
175 | # define AFMT_AVI_INFO_Y_YCBCR422 1 | |
176 | # define AFMT_AVI_INFO_Y_YCBCR444 2 | |
177 | ||
178 | #define NO_AUTO 0 | |
179 | #define ES_AUTO 1 | |
180 | #define GS_AUTO 2 | |
181 | #define ES_AND_GS_AUTO 3 | |
182 | ||
183 | # define ARRAY_MODE(x) ((x) << 2) | |
184 | # define PIPE_CONFIG(x) ((x) << 6) | |
185 | # define TILE_SPLIT(x) ((x) << 11) | |
186 | # define MICRO_TILE_MODE_NEW(x) ((x) << 22) | |
187 | # define SAMPLE_SPLIT(x) ((x) << 25) | |
188 | # define BANK_WIDTH(x) ((x) << 0) | |
189 | # define BANK_HEIGHT(x) ((x) << 2) | |
190 | # define MACRO_TILE_ASPECT(x) ((x) << 4) | |
191 | # define NUM_BANKS(x) ((x) << 6) | |
192 | ||
edf600da CK |
193 | #define MSG_ENTER_RLC_SAFE_MODE 1 |
194 | #define MSG_EXIT_RLC_SAFE_MODE 0 | |
d38ceaf9 AD |
195 | |
196 | /* | |
197 | * PM4 | |
198 | */ | |
199 | #define PACKET_TYPE0 0 | |
200 | #define PACKET_TYPE1 1 | |
201 | #define PACKET_TYPE2 2 | |
202 | #define PACKET_TYPE3 3 | |
203 | ||
204 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) | |
205 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) | |
206 | #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) | |
207 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | |
208 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ | |
209 | ((reg) & 0xFFFF) | \ | |
210 | ((n) & 0x3FFF) << 16) | |
211 | #define CP_PACKET2 0x80000000 | |
212 | #define PACKET2_PAD_SHIFT 0 | |
213 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
214 | ||
215 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
216 | ||
217 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ | |
218 | (((op) & 0xFF) << 8) | \ | |
219 | ((n) & 0x3FFF) << 16) | |
220 | ||
221 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) | |
222 | ||
223 | /* Packet 3 types */ | |
224 | #define PACKET3_NOP 0x10 | |
225 | #define PACKET3_SET_BASE 0x11 | |
226 | #define PACKET3_BASE_INDEX(x) ((x) << 0) | |
227 | #define CE_PARTITION_BASE 3 | |
228 | #define PACKET3_CLEAR_STATE 0x12 | |
229 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 | |
230 | #define PACKET3_DISPATCH_DIRECT 0x15 | |
231 | #define PACKET3_DISPATCH_INDIRECT 0x16 | |
232 | #define PACKET3_ATOMIC_GDS 0x1D | |
233 | #define PACKET3_ATOMIC_MEM 0x1E | |
234 | #define PACKET3_OCCLUSION_QUERY 0x1F | |
235 | #define PACKET3_SET_PREDICATION 0x20 | |
236 | #define PACKET3_REG_RMW 0x21 | |
237 | #define PACKET3_COND_EXEC 0x22 | |
238 | #define PACKET3_PRED_EXEC 0x23 | |
239 | #define PACKET3_DRAW_INDIRECT 0x24 | |
240 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | |
241 | #define PACKET3_INDEX_BASE 0x26 | |
242 | #define PACKET3_DRAW_INDEX_2 0x27 | |
243 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
244 | #define PACKET3_INDEX_TYPE 0x2A | |
245 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C | |
246 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
247 | #define PACKET3_NUM_INSTANCES 0x2F | |
248 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | |
249 | #define PACKET3_INDIRECT_BUFFER_CONST 0x33 | |
250 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
251 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | |
252 | #define PACKET3_DRAW_PREAMBLE 0x36 | |
253 | #define PACKET3_WRITE_DATA 0x37 | |
254 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) | |
255 | /* 0 - register | |
256 | * 1 - memory (sync - via GRBM) | |
257 | * 2 - gl2 | |
258 | * 3 - gds | |
259 | * 4 - reserved | |
260 | * 5 - memory (async - direct) | |
261 | */ | |
262 | #define WR_ONE_ADDR (1 << 16) | |
263 | #define WR_CONFIRM (1 << 20) | |
264 | #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) | |
265 | /* 0 - LRU | |
266 | * 1 - Stream | |
267 | */ | |
268 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) | |
269 | /* 0 - me | |
270 | * 1 - pfp | |
271 | * 2 - ce | |
272 | */ | |
273 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 | |
274 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
275 | # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) | |
276 | # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ | |
277 | # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ | |
278 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) | |
279 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) | |
280 | #define PACKET3_COPY_DW 0x3B | |
281 | #define PACKET3_WAIT_REG_MEM 0x3C | |
282 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) | |
283 | /* 0 - always | |
284 | * 1 - < | |
285 | * 2 - <= | |
286 | * 3 - == | |
287 | * 4 - != | |
288 | * 5 - >= | |
289 | * 6 - > | |
290 | */ | |
291 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) | |
292 | /* 0 - reg | |
293 | * 1 - mem | |
294 | */ | |
295 | #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) | |
296 | /* 0 - wait_reg_mem | |
297 | * 1 - wr_wait_wr_reg | |
298 | */ | |
299 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) | |
300 | /* 0 - me | |
301 | * 1 - pfp | |
302 | */ | |
303 | #define PACKET3_INDIRECT_BUFFER 0x3F | |
304 | #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) | |
305 | #define INDIRECT_BUFFER_VALID (1 << 23) | |
306 | #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) | |
307 | /* 0 - LRU | |
308 | * 1 - Stream | |
309 | * 2 - Bypass | |
310 | */ | |
311 | #define PACKET3_COPY_DATA 0x40 | |
312 | #define PACKET3_PFP_SYNC_ME 0x42 | |
313 | #define PACKET3_SURFACE_SYNC 0x43 | |
314 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) | |
315 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) | |
316 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
317 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | |
318 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | |
319 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | |
320 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | |
321 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | |
322 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | |
323 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | |
324 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | |
325 | # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) | |
326 | # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ | |
327 | # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ | |
328 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) | |
329 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) | |
330 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) | |
331 | # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ | |
332 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
333 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
334 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) | |
335 | # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) | |
336 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) | |
337 | #define PACKET3_COND_WRITE 0x45 | |
338 | #define PACKET3_EVENT_WRITE 0x46 | |
339 | #define EVENT_TYPE(x) ((x) << 0) | |
340 | #define EVENT_INDEX(x) ((x) << 8) | |
341 | /* 0 - any non-TS event | |
342 | * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* | |
343 | * 2 - SAMPLE_PIPELINESTAT | |
344 | * 3 - SAMPLE_STREAMOUTSTAT* | |
345 | * 4 - *S_PARTIAL_FLUSH | |
346 | * 5 - EOP events | |
347 | * 6 - EOS events | |
348 | */ | |
349 | #define PACKET3_EVENT_WRITE_EOP 0x47 | |
350 | #define EOP_TCL1_VOL_ACTION_EN (1 << 12) | |
351 | #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ | |
352 | #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ | |
353 | #define EOP_TCL1_ACTION_EN (1 << 16) | |
354 | #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ | |
355 | #define EOP_TCL2_VOLATILE (1 << 24) | |
356 | #define EOP_CACHE_POLICY(x) ((x) << 25) | |
357 | /* 0 - LRU | |
358 | * 1 - Stream | |
359 | * 2 - Bypass | |
360 | */ | |
361 | #define DATA_SEL(x) ((x) << 29) | |
362 | /* 0 - discard | |
363 | * 1 - send low 32bit data | |
364 | * 2 - send 64bit data | |
365 | * 3 - send 64bit GPU counter value | |
366 | * 4 - send 64bit sys counter value | |
367 | */ | |
368 | #define INT_SEL(x) ((x) << 24) | |
369 | /* 0 - none | |
370 | * 1 - interrupt only (DATA_SEL = 0) | |
371 | * 2 - interrupt when data write is confirmed | |
372 | */ | |
373 | #define DST_SEL(x) ((x) << 16) | |
374 | /* 0 - MC | |
375 | * 1 - TC/L2 | |
376 | */ | |
377 | #define PACKET3_EVENT_WRITE_EOS 0x48 | |
378 | #define PACKET3_RELEASE_MEM 0x49 | |
379 | #define PACKET3_PREAMBLE_CNTL 0x4A | |
380 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) | |
381 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | |
382 | #define PACKET3_DMA_DATA 0x50 | |
383 | /* 1. header | |
384 | * 2. CONTROL | |
385 | * 3. SRC_ADDR_LO or DATA [31:0] | |
386 | * 4. SRC_ADDR_HI [31:0] | |
387 | * 5. DST_ADDR_LO [31:0] | |
388 | * 6. DST_ADDR_HI [7:0] | |
389 | * 7. COMMAND [30:21] | BYTE_COUNT [20:0] | |
390 | */ | |
391 | /* CONTROL */ | |
392 | # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) | |
393 | /* 0 - ME | |
394 | * 1 - PFP | |
395 | */ | |
396 | # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) | |
397 | /* 0 - LRU | |
398 | * 1 - Stream | |
399 | * 2 - Bypass | |
400 | */ | |
401 | # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) | |
402 | # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) | |
403 | /* 0 - DST_ADDR using DAS | |
404 | * 1 - GDS | |
405 | * 3 - DST_ADDR using L2 | |
406 | */ | |
407 | # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) | |
408 | /* 0 - LRU | |
409 | * 1 - Stream | |
410 | * 2 - Bypass | |
411 | */ | |
412 | # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) | |
413 | # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) | |
414 | /* 0 - SRC_ADDR using SAS | |
415 | * 1 - GDS | |
416 | * 2 - DATA | |
417 | * 3 - SRC_ADDR using L2 | |
418 | */ | |
419 | # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) | |
420 | /* COMMAND */ | |
421 | # define PACKET3_DMA_DATA_DIS_WC (1 << 21) | |
422 | # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) | |
423 | /* 0 - none | |
424 | * 1 - 8 in 16 | |
425 | * 2 - 8 in 32 | |
426 | * 3 - 8 in 64 | |
427 | */ | |
428 | # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) | |
429 | /* 0 - none | |
430 | * 1 - 8 in 16 | |
431 | * 2 - 8 in 32 | |
432 | * 3 - 8 in 64 | |
433 | */ | |
434 | # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) | |
435 | /* 0 - memory | |
436 | * 1 - register | |
437 | */ | |
438 | # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) | |
439 | /* 0 - memory | |
440 | * 1 - register | |
441 | */ | |
442 | # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) | |
443 | # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) | |
444 | # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) | |
445 | #define PACKET3_AQUIRE_MEM 0x58 | |
446 | #define PACKET3_REWIND 0x59 | |
447 | #define PACKET3_LOAD_UCONFIG_REG 0x5E | |
448 | #define PACKET3_LOAD_SH_REG 0x5F | |
449 | #define PACKET3_LOAD_CONFIG_REG 0x60 | |
450 | #define PACKET3_LOAD_CONTEXT_REG 0x61 | |
451 | #define PACKET3_SET_CONFIG_REG 0x68 | |
452 | #define PACKET3_SET_CONFIG_REG_START 0x00002000 | |
453 | #define PACKET3_SET_CONFIG_REG_END 0x00002c00 | |
454 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
455 | #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 | |
456 | #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 | |
457 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | |
458 | #define PACKET3_SET_SH_REG 0x76 | |
459 | #define PACKET3_SET_SH_REG_START 0x00002c00 | |
460 | #define PACKET3_SET_SH_REG_END 0x00003000 | |
461 | #define PACKET3_SET_SH_REG_OFFSET 0x77 | |
462 | #define PACKET3_SET_QUEUE_REG 0x78 | |
463 | #define PACKET3_SET_UCONFIG_REG 0x79 | |
464 | #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 | |
465 | #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 | |
466 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D | |
467 | #define PACKET3_SCRATCH_RAM_READ 0x7E | |
468 | #define PACKET3_LOAD_CONST_RAM 0x80 | |
469 | #define PACKET3_WRITE_CONST_RAM 0x81 | |
470 | #define PACKET3_DUMP_CONST_RAM 0x83 | |
471 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 | |
472 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 | |
473 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 | |
474 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 | |
475 | #define PACKET3_SWITCH_BUFFER 0x8B | |
476 | ||
477 | /* SDMA - first instance at 0xd000, second at 0xd800 */ | |
478 | #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ | |
479 | #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ | |
480 | #define SDMA_MAX_INSTANCE 2 | |
481 | ||
482 | #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ | |
483 | (((sub_op) & 0xFF) << 8) | \ | |
484 | (((op) & 0xFF) << 0)) | |
485 | /* sDMA opcodes */ | |
486 | #define SDMA_OPCODE_NOP 0 | |
4207a734 | 487 | # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) |
d38ceaf9 AD |
488 | #define SDMA_OPCODE_COPY 1 |
489 | # define SDMA_COPY_SUB_OPCODE_LINEAR 0 | |
490 | # define SDMA_COPY_SUB_OPCODE_TILED 1 | |
491 | # define SDMA_COPY_SUB_OPCODE_SOA 3 | |
492 | # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 | |
493 | # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 | |
494 | # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 | |
495 | #define SDMA_OPCODE_WRITE 2 | |
496 | # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 | |
497 | # define SDMA_WRTIE_SUB_OPCODE_TILED 1 | |
498 | #define SDMA_OPCODE_INDIRECT_BUFFER 4 | |
499 | #define SDMA_OPCODE_FENCE 5 | |
500 | #define SDMA_OPCODE_TRAP 6 | |
501 | #define SDMA_OPCODE_SEMAPHORE 7 | |
502 | # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) | |
503 | /* 0 - increment | |
504 | * 1 - write 1 | |
505 | */ | |
506 | # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) | |
507 | /* 0 - wait | |
508 | * 1 - signal | |
509 | */ | |
510 | # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) | |
511 | /* mailbox */ | |
512 | #define SDMA_OPCODE_POLL_REG_MEM 8 | |
513 | # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) | |
514 | /* 0 - wait_reg_mem | |
515 | * 1 - wr_wait_wr_reg | |
516 | */ | |
517 | # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) | |
518 | /* 0 - always | |
519 | * 1 - < | |
520 | * 2 - <= | |
521 | * 3 - == | |
522 | * 4 - != | |
523 | * 5 - >= | |
524 | * 6 - > | |
525 | */ | |
526 | # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) | |
527 | /* 0 = register | |
528 | * 1 = memory | |
529 | */ | |
530 | #define SDMA_OPCODE_COND_EXEC 9 | |
531 | #define SDMA_OPCODE_CONSTANT_FILL 11 | |
532 | # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) | |
533 | /* 0 = byte fill | |
534 | * 2 = DW fill | |
535 | */ | |
536 | #define SDMA_OPCODE_GENERATE_PTE_PDE 12 | |
537 | #define SDMA_OPCODE_TIMESTAMP 13 | |
538 | # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 | |
539 | # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 | |
540 | # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 | |
541 | #define SDMA_OPCODE_SRBM_WRITE 14 | |
542 | # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) | |
543 | /* byte mask */ | |
544 | ||
545 | #define VCE_CMD_NO_OP 0x00000000 | |
546 | #define VCE_CMD_END 0x00000001 | |
547 | #define VCE_CMD_IB 0x00000002 | |
548 | #define VCE_CMD_FENCE 0x00000003 | |
549 | #define VCE_CMD_TRAP 0x00000004 | |
550 | #define VCE_CMD_IB_AUTO 0x00000005 | |
551 | #define VCE_CMD_SEMAPHORE 0x00000006 | |
552 | ||
32c22e99 OG |
553 | /* if PTR32, these are the bases for scratch and lds */ |
554 | #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ | |
555 | #define SHARED_BASE(x) ((x) << 16) /* LDS */ | |
556 | ||
557 | #define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 | |
558 | ||
cd06bf68 BG |
559 | /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ |
560 | enum { | |
561 | MTYPE_CACHED = 0, | |
562 | MTYPE_NONCACHED = 3 | |
563 | }; | |
564 | ||
d38ceaf9 | 565 | #endif |