[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / vce_v2_0.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * Authors: Christian König <christian.koenig@amd.com>
 */

#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_vce.h"
#include "cikd.h"

#include "vce/vce_2_0_d.h"
#include "vce/vce_2_0_sh_mask.h"

#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"

#define VCE_V2_0_FW_SIZE	(256 * 1024)
#define VCE_V2_0_STACK_SIZE	(64 * 1024)
#define VCE_V2_0_DATA_SIZE	(23552 * AMDGPU_MAX_VCE_HANDLES)

static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
static int vce_v2_0_wait_for_idle(void *handle);
/**
 * vce_v2_0_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		return RREG32(mmVCE_RB_RPTR);
	else
		return RREG32(mmVCE_RB_RPTR2);
}

/**
 * vce_v2_0_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		return RREG32(mmVCE_RB_WPTR);
	else
		return RREG32(mmVCE_RB_WPTR2);
}

/**
 * vce_v2_0_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		WREG32(mmVCE_RB_WPTR, ring->wptr);
	else
		WREG32(mmVCE_RB_WPTR2, ring->wptr);
}

/**
 * vce_v2_0_start - start VCE block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the VCE block
 */
static int vce_v2_0_start(struct amdgpu_device *adev)
{
	struct amdgpu_ring *ring;
	int i, j, r;

	vce_v2_0_mc_resume(adev);

	/* set BUSY flag */
	WREG32_P(mmVCE_STATUS, 1, ~1);

	ring = &adev->vce.ring[0];
	WREG32(mmVCE_RB_RPTR, ring->wptr);
	WREG32(mmVCE_RB_WPTR, ring->wptr);
	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);

	ring = &adev->vce.ring[1];
	WREG32(mmVCE_RB_RPTR2, ring->wptr);
	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);

	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);

	WREG32_P(mmVCE_SOFT_RESET,
		 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
		 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);

	mdelay(100);

	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);

	for (i = 0; i < 10; ++i) {
		uint32_t status;
		for (j = 0; j < 100; ++j) {
			status = RREG32(mmVCE_STATUS);
			if (status & 2)
				break;
			mdelay(10);
		}
		r = 0;
		if (status & 2)
			break;

		DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
				~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(10);
		WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(10);
		r = -1;
	}

	/* clear BUSY flag */
	WREG32_P(mmVCE_STATUS, 0, ~1);

	if (r) {
		DRM_ERROR("VCE not responding, giving up!!!\n");
		return r;
	}

	return 0;
}

static int vce_v2_0_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	vce_v2_0_set_ring_funcs(adev);
	vce_v2_0_set_irq_funcs(adev);

	return 0;
}

static int vce_v2_0_sw_init(void *handle)
{
	struct amdgpu_ring *ring;
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* VCE */
	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
	if (r)
		return r;

	r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
		VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
	if (r)
		return r;

	r = amdgpu_vce_resume(adev);
	if (r)
		return r;

	ring = &adev->vce.ring[0];
	sprintf(ring->name, "vce0");
	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	if (r)
		return r;

	ring = &adev->vce.ring[1];
	sprintf(ring->name, "vce1");
	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_sw_fini(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	r = amdgpu_vce_sw_fini(adev);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_hw_init(void *handle)
{
	struct amdgpu_ring *ring;
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = vce_v2_0_start(adev);
	if (r)
/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
		return 0;

	ring = &adev->vce.ring[0];
	ring->ready = true;
	r = amdgpu_ring_test_ring(ring);
	if (r) {
		ring->ready = false;
		return r;
	}

	ring = &adev->vce.ring[1];
	ring->ready = true;
	r = amdgpu_ring_test_ring(ring);
	if (r) {
		ring->ready = false;
		return r;
	}

	DRM_INFO("VCE initialized successfully.\n");

	return 0;
}

static int vce_v2_0_hw_fini(void *handle)
{
	return 0;
}

static int vce_v2_0_suspend(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = vce_v2_0_hw_fini(adev);
	if (r)
		return r;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_resume(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_vce_resume(adev);
	if (r)
		return r;

	r = vce_v2_0_hw_init(adev);
	if (r)
		return r;

	return r;
}

static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
{
	u32 tmp;

	if (gated) {
		tmp = RREG32(mmVCE_CLOCK_GATING_B);
		tmp |= 0xe70000;
		WREG32(mmVCE_CLOCK_GATING_B, tmp);

		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
		tmp |= 0xff000000;
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
		tmp &= ~0x3fc;
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	} else {
		tmp = RREG32(mmVCE_CLOCK_GATING_B);
		tmp |= 0xe7;
		tmp &= ~0xe70000;
		WREG32(mmVCE_CLOCK_GATING_B, tmp);

		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
		tmp |= 0x1fe000;
		tmp &= ~0xff000000;
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
		tmp |= 0x3fc;
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	}
}

static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
{
	u32 orig, tmp;

	if (gated) {
		if (vce_v2_0_wait_for_idle(adev)) {
			DRM_INFO("VCE is busy, Can't set clock gateing");
			return;
		}
		WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(100);
		WREG32(mmVCE_STATUS, 0);
	} else {
		WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(100);
	}

	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	tmp &= ~0x00060006;
	if (gated) {
		tmp |= 0xe10000;
	} else {
		tmp |= 0xe1;
		tmp &= ~0xe10000;
	}
	WREG32(mmVCE_CLOCK_GATING_B, tmp);

	orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	tmp &= ~0x1fe000;
	tmp &= ~0xff000000;
	if (tmp != orig)
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

	orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	tmp &= ~0x3fc;
	if (tmp != orig)
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

	if (gated)
		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
}

static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
{
	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
}

static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
{
	bool sw_cg = false;

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
		if (sw_cg)
			vce_v2_0_set_sw_cg(adev, true);
		else
			vce_v2_0_set_dyn_cg(adev, true);
	} else {
		vce_v2_0_disable_cg(adev);

		if (sw_cg)
			vce_v2_0_set_sw_cg(adev, false);
		else
			vce_v2_0_set_dyn_cg(adev, false);
	}
}

static void vce_v2_0_init_cg(struct amdgpu_device *adev)
{
	u32 tmp;

	tmp = RREG32(mmVCE_CLOCK_GATING_A);
	tmp &= ~0xfff;
	tmp |= ((0 << 0) | (4 << 4));
	tmp |= 0x40000;
	WREG32(mmVCE_CLOCK_GATING_A, tmp);

	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	tmp &= ~0xfff;
	tmp |= ((0 << 0) | (4 << 4));
	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	tmp |= 0x10;
	tmp &= ~0x100000;
	WREG32(mmVCE_CLOCK_GATING_B, tmp);
}

static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
{
	uint64_t addr = adev->vce.gpu_addr;
	uint32_t size;

	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);

	WREG32(mmVCE_LMI_CTRL, 0x00398000);
	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
	WREG32(mmVCE_LMI_VM_CTRL, 0);

	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
	size = VCE_V2_0_FW_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);

	addr += size;
	size = VCE_V2_0_STACK_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);

	addr += size;
	size = VCE_V2_0_DATA_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);

	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);

	WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
		 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);

	vce_v2_0_init_cg(adev);
}

static bool vce_v2_0_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
}

static int vce_v2_0_wait_for_idle(void *handle)
{
	unsigned i;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
			return 0;
	}
	return -ETIMEDOUT;
}

static int vce_v2_0_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
			~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
	mdelay(5);

	return vce_v2_0_start(adev);
}

static void vce_v2_0_print_status(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	dev_info(adev->dev, "VCE 2.0 registers\n");
	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",
		 RREG32(mmVCE_STATUS));
	dev_info(adev->dev, "  VCE_VCPU_CNTL=0x%08X\n",
		 RREG32(mmVCE_VCPU_CNTL));
	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
		 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE0=0x%08X\n",
		 RREG32(mmVCE_VCPU_CACHE_SIZE0));
	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
		 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE1=0x%08X\n",
		 RREG32(mmVCE_VCPU_CACHE_SIZE1));
	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
		 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE2=0x%08X\n",
		 RREG32(mmVCE_VCPU_CACHE_SIZE2));
	dev_info(adev->dev, "  VCE_SOFT_RESET=0x%08X\n",
		 RREG32(mmVCE_SOFT_RESET));
	dev_info(adev->dev, "  VCE_RB_BASE_LO2=0x%08X\n",
		 RREG32(mmVCE_RB_BASE_LO2));
	dev_info(adev->dev, "  VCE_RB_BASE_HI2=0x%08X\n",
		 RREG32(mmVCE_RB_BASE_HI2));
	dev_info(adev->dev, "  VCE_RB_SIZE2=0x%08X\n",
		 RREG32(mmVCE_RB_SIZE2));
	dev_info(adev->dev, "  VCE_RB_RPTR2=0x%08X\n",
		 RREG32(mmVCE_RB_RPTR2));
	dev_info(adev->dev, "  VCE_RB_WPTR2=0x%08X\n",
		 RREG32(mmVCE_RB_WPTR2));
	dev_info(adev->dev, "  VCE_RB_BASE_LO=0x%08X\n",
		 RREG32(mmVCE_RB_BASE_LO));
	dev_info(adev->dev, "  VCE_RB_BASE_HI=0x%08X\n",
		 RREG32(mmVCE_RB_BASE_HI));
	dev_info(adev->dev, "  VCE_RB_SIZE=0x%08X\n",
		 RREG32(mmVCE_RB_SIZE));
	dev_info(adev->dev, "  VCE_RB_RPTR=0x%08X\n",
		 RREG32(mmVCE_RB_RPTR));
	dev_info(adev->dev, "  VCE_RB_WPTR=0x%08X\n",
		 RREG32(mmVCE_RB_WPTR));
	dev_info(adev->dev, "  VCE_CLOCK_GATING_A=0x%08X\n",
		 RREG32(mmVCE_CLOCK_GATING_A));
	dev_info(adev->dev, "  VCE_CLOCK_GATING_B=0x%08X\n",
		 RREG32(mmVCE_CLOCK_GATING_B));
	dev_info(adev->dev, "  VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
		 RREG32(mmVCE_CGTT_CLK_OVERRIDE));
	dev_info(adev->dev, "  VCE_UENC_CLOCK_GATING=0x%08X\n",
		 RREG32(mmVCE_UENC_CLOCK_GATING));
	dev_info(adev->dev, "  VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
		 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
	dev_info(adev->dev, "  VCE_SYS_INT_EN=0x%08X\n",
		 RREG32(mmVCE_SYS_INT_EN));
	dev_info(adev->dev, "  VCE_LMI_CTRL2=0x%08X\n",
		 RREG32(mmVCE_LMI_CTRL2));
	dev_info(adev->dev, "  VCE_LMI_CTRL=0x%08X\n",
		 RREG32(mmVCE_LMI_CTRL));
	dev_info(adev->dev, "  VCE_LMI_VM_CTRL=0x%08X\n",
		 RREG32(mmVCE_LMI_VM_CTRL));
	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL=0x%08X\n",
		 RREG32(mmVCE_LMI_SWAP_CNTL));
	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL1=0x%08X\n",
		 RREG32(mmVCE_LMI_SWAP_CNTL1));
	dev_info(adev->dev, "  VCE_LMI_CACHE_CTRL=0x%08X\n",
		 RREG32(mmVCE_LMI_CACHE_CTRL));
}

static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned type,
					enum amdgpu_interrupt_state state)
{
	uint32_t val = 0;

	if (state == AMDGPU_IRQ_STATE_ENABLE)
		val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;

	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
	return 0;
}

static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{
	DRM_DEBUG("IH: VCE\n");
	switch (entry->src_data) {
	case 0:
		amdgpu_fence_process(&adev->vce.ring[0]);
		break;
	case 1:
		amdgpu_fence_process(&adev->vce.ring[1]);
		break;
	default:
		DRM_ERROR("Unhandled interrupt: %d %d\n",
			  entry->src_id, entry->src_data);
		break;
	}

	return 0;
}

static int vce_v2_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	bool gate = false;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (state == AMD_CG_STATE_GATE)
		gate = true;

	vce_v2_0_enable_mgcg(adev, gate);

	return 0;
}

static int vce_v2_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	/* This doesn't actually powergate the VCE block.
	 * That's done in the dpm code via the SMC.  This
	 * just re-inits the block as necessary.  The actual
	 * gating still happens in the dpm code.  We should
	 * revisit this when there is a cleaner line between
	 * the smc and the hw blocks
	 */
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
		return 0;

	if (state == AMD_PG_STATE_GATE)
		/* XXX do we need a vce_v2_0_stop()? */
		return 0;
	else
		return vce_v2_0_start(adev);
}

const struct amd_ip_funcs vce_v2_0_ip_funcs = {
	.early_init = vce_v2_0_early_init,
	.late_init = NULL,
	.sw_init = vce_v2_0_sw_init,
	.sw_fini = vce_v2_0_sw_fini,
	.hw_init = vce_v2_0_hw_init,
	.hw_fini = vce_v2_0_hw_fini,
	.suspend = vce_v2_0_suspend,
	.resume = vce_v2_0_resume,
	.is_idle = vce_v2_0_is_idle,
	.wait_for_idle = vce_v2_0_wait_for_idle,
	.soft_reset = vce_v2_0_soft_reset,
	.print_status = vce_v2_0_print_status,
	.set_clockgating_state = vce_v2_0_set_clockgating_state,
	.set_powergating_state = vce_v2_0_set_powergating_state,
};

static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
	.get_rptr = vce_v2_0_ring_get_rptr,
	.get_wptr = vce_v2_0_ring_get_wptr,
	.set_wptr = vce_v2_0_ring_set_wptr,
	.parse_cs = amdgpu_vce_ring_parse_cs,
	.emit_ib = amdgpu_vce_ring_emit_ib,
	.emit_fence = amdgpu_vce_ring_emit_fence,
	.test_ring = amdgpu_vce_ring_test_ring,
	.test_ib = amdgpu_vce_ring_test_ib,
	.insert_nop = amdgpu_ring_insert_nop,
	.pad_ib = amdgpu_ring_generic_pad_ib,
};

static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
{
	adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
	adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
}

static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
	.set = vce_v2_0_set_interrupt_state,
	.process = vce_v2_0_process_interrupt,
};

static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
{
	adev->vce.irq.num_types = 1;
	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
};
Commit	Line	Data
a2e73f56 AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	* Authors: Christian König <christian.koenig@amd.com>
	26	*/
	27
	28	#include <linux/firmware.h>
	29	#include <drm/drmP.h>
	30	#include "amdgpu.h"
	31	#include "amdgpu_vce.h"
	32	#include "cikd.h"
	33
	34	#include "vce/vce_2_0_d.h"
	35	#include "vce/vce_2_0_sh_mask.h"
	36
	37	#include "oss/oss_2_0_d.h"
	38	#include "oss/oss_2_0_sh_mask.h"
	39
e9822622 LL	40	#define VCE_V2_0_FW_SIZE (256 * 1024)
	41	#define VCE_V2_0_STACK_SIZE (64 * 1024)
	42	#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
	43
a2e73f56 AD	44	static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
	45	static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
	46	static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
cb48a13e	47	static int vce_v2_0_wait_for_idle(void *handle);
a2e73f56 AD	48	/**
	49	* vce_v2_0_ring_get_rptr - get read pointer
	50	*
	51	* @ring: amdgpu_ring pointer
	52	*
	53	* Returns the current hardware read pointer
	54	*/
	55	static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
	56	{
	57	struct amdgpu_device *adev = ring->adev;
	58
	59	if (ring == &adev->vce.ring[0])
	60	return RREG32(mmVCE_RB_RPTR);
	61	else
	62	return RREG32(mmVCE_RB_RPTR2);
	63	}
	64
	65	/**
	66	* vce_v2_0_ring_get_wptr - get write pointer
	67	*
	68	* @ring: amdgpu_ring pointer
	69	*
	70	* Returns the current hardware write pointer
	71	*/
	72	static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
	73	{
	74	struct amdgpu_device *adev = ring->adev;
	75
	76	if (ring == &adev->vce.ring[0])
	77	return RREG32(mmVCE_RB_WPTR);
	78	else
	79	return RREG32(mmVCE_RB_WPTR2);
	80	}
	81
	82	/**
	83	* vce_v2_0_ring_set_wptr - set write pointer
	84	*
	85	* @ring: amdgpu_ring pointer
	86	*
	87	* Commits the write pointer to the hardware
	88	*/
	89	static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
	90	{
	91	struct amdgpu_device *adev = ring->adev;
	92
	93	if (ring == &adev->vce.ring[0])
	94	WREG32(mmVCE_RB_WPTR, ring->wptr);
	95	else
	96	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	97	}
	98
	99	/**
	100	* vce_v2_0_start - start VCE block
	101	*
	102	* @adev: amdgpu_device pointer
	103	*
	104	* Setup and start the VCE block
	105	*/
	106	static int vce_v2_0_start(struct amdgpu_device *adev)
	107	{
	108	struct amdgpu_ring *ring;
	109	int i, j, r;
	110
	111	vce_v2_0_mc_resume(adev);
112
113	/* set BUSY flag */
114	WREG32_P(mmVCE_STATUS, 1, ~1);
115
116	ring = &adev->vce.ring[0];
117	WREG32(mmVCE_RB_RPTR, ring->wptr);
118	WREG32(mmVCE_RB_WPTR, ring->wptr);
119	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
120	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
121	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
122
123	ring = &adev->vce.ring[1];
124	WREG32(mmVCE_RB_RPTR2, ring->wptr);
125	WREG32(mmVCE_RB_WPTR2, ring->wptr);
126	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
127	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
128	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
129
130	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
131
132	WREG32_P(mmVCE_SOFT_RESET,
133	VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
134	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
135
136	mdelay(100);
137
138	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
139
140	for (i = 0; i < 10; ++i) {
141	uint32_t status;
142	for (j = 0; j < 100; ++j) {
143	status = RREG32(mmVCE_STATUS);
144	if (status & 2)
145	break;
146	mdelay(10);
147	}
148	r = 0;
149	if (status & 2)
150	break;
151
152	DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
153	WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
154	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
155	mdelay(10);
156	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
157	mdelay(10);
158	r = -1;
159	}
160
161	/* clear BUSY flag */
162	WREG32_P(mmVCE_STATUS, 0, ~1);
163
164	if (r) {
165	DRM_ERROR("VCE not responding, giving up!!!\n");
166	return r;
167	}
168
169	return 0;
170	}
171
5fc3aeeb	172	static int vce_v2_0_early_init(void *handle)
a2e73f56	173	{
5fc3aeeb	174	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	175
a2e73f56 AD	176	vce_v2_0_set_ring_funcs(adev);
	177	vce_v2_0_set_irq_funcs(adev);
	178
	179	return 0;
	180	}
	181
5fc3aeeb	182	static int vce_v2_0_sw_init(void *handle)
a2e73f56 AD	183	{
	184	struct amdgpu_ring *ring;
	185	int r;
5fc3aeeb	186	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	187
	188	/* VCE */
	189	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
	190	if (r)
	191	return r;
	192
e9822622 LL	193	r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
e9822622 LL	194	VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
a2e73f56 AD	195	if (r)
	196	return r;
	197
	198	r = amdgpu_vce_resume(adev);
	199	if (r)
	200	return r;
	201
	202	ring = &adev->vce.ring[0];
	203	sprintf(ring->name, "vce0");
	204	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
	205	&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	206	if (r)
	207	return r;
	208
	209	ring = &adev->vce.ring[1];
	210	sprintf(ring->name, "vce1");
	211	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
	212	&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	213	if (r)
	214	return r;
	215
	216	return r;
	217	}
	218
5fc3aeeb	219	static int vce_v2_0_sw_fini(void *handle)
a2e73f56 AD	220	{
a2e73f56 AD	221	int r;
5fc3aeeb	222	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	223
	224	r = amdgpu_vce_suspend(adev);
	225	if (r)
	226	return r;
	227
	228	r = amdgpu_vce_sw_fini(adev);
	229	if (r)
	230	return r;
	231
	232	return r;
	233	}
	234
5fc3aeeb	235	static int vce_v2_0_hw_init(void *handle)
a2e73f56 AD	236	{
	237	struct amdgpu_ring *ring;
	238	int r;
5fc3aeeb	239	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	240
	241	r = vce_v2_0_start(adev);
	242	if (r)
976accc1 RZ	243	/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
976accc1 RZ	244	return 0;
a2e73f56 AD	245
	246	ring = &adev->vce.ring[0];
	247	ring->ready = true;
	248	r = amdgpu_ring_test_ring(ring);
	249	if (r) {
	250	ring->ready = false;
	251	return r;
	252	}
	253
	254	ring = &adev->vce.ring[1];
	255	ring->ready = true;
	256	r = amdgpu_ring_test_ring(ring);
	257	if (r) {
	258	ring->ready = false;
	259	return r;
	260	}
	261
	262	DRM_INFO("VCE initialized successfully.\n");
	263
	264	return 0;
	265	}
	266
5fc3aeeb	267	static int vce_v2_0_hw_fini(void *handle)
a2e73f56	268	{
a2e73f56 AD	269	return 0;
	270	}
	271
5fc3aeeb	272	static int vce_v2_0_suspend(void *handle)
a2e73f56 AD	273	{
a2e73f56 AD	274	int r;
5fc3aeeb	275	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	276
	277	r = vce_v2_0_hw_fini(adev);
	278	if (r)
	279	return r;
	280
	281	r = amdgpu_vce_suspend(adev);
	282	if (r)
	283	return r;
	284
	285	return r;
	286	}
	287
5fc3aeeb	288	static int vce_v2_0_resume(void *handle)
a2e73f56 AD	289	{
a2e73f56 AD	290	int r;
5fc3aeeb	291	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	292
	293	r = amdgpu_vce_resume(adev);
	294	if (r)
	295	return r;
	296
	297	r = vce_v2_0_hw_init(adev);
	298	if (r)
	299	return r;
	300
	301	return r;
	302	}
	303
	304	static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
	305	{
	306	u32 tmp;
	307
	308	if (gated) {
	309	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	310	tmp \|= 0xe70000;
	311	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	312
	313	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	314	tmp \|= 0xff000000;
	315	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	316
	317	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	318	tmp &= ~0x3fc;
	319	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	320
	321	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
70f0f5fb	322	} else {
a2e73f56 AD	323	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	324	tmp \|= 0xe7;
	325	tmp &= ~0xe70000;
	326	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	327
	328	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	329	tmp \|= 0x1fe000;
	330	tmp &= ~0xff000000;
	331	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	332
	333	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	334	tmp \|= 0x3fc;
	335	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	336	}
	337	}
	338
	339	static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
	340	{
	341	u32 orig, tmp;
	342
cb48a13e RZ	343	if (gated) {
	344	if (vce_v2_0_wait_for_idle(adev)) {
	345	DRM_INFO("VCE is busy, Can't set clock gateing");
	346	return;
	347	}
	348	WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	349	WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	350	mdelay(100);
	351	WREG32(mmVCE_STATUS, 0);
	352	} else {
	353	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	354	WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	355	mdelay(100);
	356	}
	357
a2e73f56 AD	358	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	359	tmp &= ~0x00060006;
	360	if (gated) {
	361	tmp \|= 0xe10000;
	362	} else {
	363	tmp \|= 0xe1;
	364	tmp &= ~0xe10000;
	365	}
	366	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	367
	368	orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	369	tmp &= ~0x1fe000;
	370	tmp &= ~0xff000000;
	371	if (tmp != orig)
	372	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	373
	374	orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	375	tmp &= ~0x3fc;
	376	if (tmp != orig)
	377	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	378
	379	if (gated)
	380	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
cb48a13e	381	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
a2e73f56 AD	382	}
	383
	384	static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
	385	{
	386	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
	387	}
	388
	389	static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
	390	{
	391	bool sw_cg = false;
	392
e3b04bc7	393	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
a2e73f56 AD	394	if (sw_cg)
	395	vce_v2_0_set_sw_cg(adev, true);
	396	else
	397	vce_v2_0_set_dyn_cg(adev, true);
	398	} else {
	399	vce_v2_0_disable_cg(adev);
	400
	401	if (sw_cg)
	402	vce_v2_0_set_sw_cg(adev, false);
	403	else
	404	vce_v2_0_set_dyn_cg(adev, false);
	405	}
	406	}
	407
	408	static void vce_v2_0_init_cg(struct amdgpu_device *adev)
	409	{
	410	u32 tmp;
	411
	412	tmp = RREG32(mmVCE_CLOCK_GATING_A);
	413	tmp &= ~0xfff;
	414	tmp \|= ((0 << 0) \| (4 << 4));
	415	tmp \|= 0x40000;
	416	WREG32(mmVCE_CLOCK_GATING_A, tmp);
	417
	418	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	419	tmp &= ~0xfff;
	420	tmp \|= ((0 << 0) \| (4 << 4));
	421	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	422
	423	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	424	tmp \|= 0x10;
	425	tmp &= ~0x100000;
	426	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	427	}
	428
	429	static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
	430	{
	431	uint64_t addr = adev->vce.gpu_addr;
	432	uint32_t size;
	433
	434	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
	435	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	436	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	437	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
	438
	439	WREG32(mmVCE_LMI_CTRL, 0x00398000);
	440	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	441	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
	442	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
	443	WREG32(mmVCE_LMI_VM_CTRL, 0);
	444
	445	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
e9822622	446	size = VCE_V2_0_FW_SIZE;
a2e73f56 AD	447	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	448	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
	449
	450	addr += size;
e9822622	451	size = VCE_V2_0_STACK_SIZE;
a2e73f56 AD	452	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	453	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
	454
	455	addr += size;
e9822622	456	size = VCE_V2_0_DATA_SIZE;
a2e73f56 AD	457	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	458	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
	459
	460	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
	461
	462	WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
	463	~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
	464
	465	vce_v2_0_init_cg(adev);
	466	}
	467
5fc3aeeb	468	static bool vce_v2_0_is_idle(void *handle)
a2e73f56	469	{
5fc3aeeb	470	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	471
a2e73f56 AD	472	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
	473	}
	474
5fc3aeeb	475	static int vce_v2_0_wait_for_idle(void *handle)
a2e73f56 AD	476	{
a2e73f56 AD	477	unsigned i;
5fc3aeeb	478	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	479
	480	for (i = 0; i < adev->usec_timeout; i++) {
	481	if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
	482	return 0;
	483	}
	484	return -ETIMEDOUT;
	485	}
	486
5fc3aeeb	487	static int vce_v2_0_soft_reset(void *handle)
a2e73f56	488	{
5fc3aeeb	489	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	490
a2e73f56 AD	491	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
	492	~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
	493	mdelay(5);
	494
	495	return vce_v2_0_start(adev);
	496	}
	497
5fc3aeeb	498	static void vce_v2_0_print_status(void *handle)
a2e73f56	499	{
5fc3aeeb	500	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	501
a2e73f56 AD	502	dev_info(adev->dev, "VCE 2.0 registers\n");
	503	dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
	504	RREG32(mmVCE_STATUS));
	505	dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
	506	RREG32(mmVCE_VCPU_CNTL));
	507	dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
	508	RREG32(mmVCE_VCPU_CACHE_OFFSET0));
	509	dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
	510	RREG32(mmVCE_VCPU_CACHE_SIZE0));
	511	dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
	512	RREG32(mmVCE_VCPU_CACHE_OFFSET1));
	513	dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
	514	RREG32(mmVCE_VCPU_CACHE_SIZE1));
	515	dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
	516	RREG32(mmVCE_VCPU_CACHE_OFFSET2));
	517	dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
	518	RREG32(mmVCE_VCPU_CACHE_SIZE2));
	519	dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
	520	RREG32(mmVCE_SOFT_RESET));
	521	dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
	522	RREG32(mmVCE_RB_BASE_LO2));
	523	dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
	524	RREG32(mmVCE_RB_BASE_HI2));
	525	dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
	526	RREG32(mmVCE_RB_SIZE2));
	527	dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
	528	RREG32(mmVCE_RB_RPTR2));
	529	dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
	530	RREG32(mmVCE_RB_WPTR2));
	531	dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
	532	RREG32(mmVCE_RB_BASE_LO));
	533	dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
	534	RREG32(mmVCE_RB_BASE_HI));
	535	dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
	536	RREG32(mmVCE_RB_SIZE));
	537	dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
	538	RREG32(mmVCE_RB_RPTR));
	539	dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
	540	RREG32(mmVCE_RB_WPTR));
	541	dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
	542	RREG32(mmVCE_CLOCK_GATING_A));
	543	dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
	544	RREG32(mmVCE_CLOCK_GATING_B));
	545	dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
	546	RREG32(mmVCE_CGTT_CLK_OVERRIDE));
	547	dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
	548	RREG32(mmVCE_UENC_CLOCK_GATING));
	549	dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
	550	RREG32(mmVCE_UENC_REG_CLOCK_GATING));
	551	dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
	552	RREG32(mmVCE_SYS_INT_EN));
	553	dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
	554	RREG32(mmVCE_LMI_CTRL2));
	555	dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
	556	RREG32(mmVCE_LMI_CTRL));
	557	dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
	558	RREG32(mmVCE_LMI_VM_CTRL));
	559	dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
	560	RREG32(mmVCE_LMI_SWAP_CNTL));
	561	dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
	562	RREG32(mmVCE_LMI_SWAP_CNTL1));
	563	dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
	564	RREG32(mmVCE_LMI_CACHE_CTRL));
	565	}
566
567	static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
568	struct amdgpu_irq_src *source,
569	unsigned type,
570	enum amdgpu_interrupt_state state)
571	{
572	uint32_t val = 0;
573
574	if (state == AMDGPU_IRQ_STATE_ENABLE)
575	val \|= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
576
577	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
578	return 0;
579	}
580
581	static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
582	struct amdgpu_irq_src *source,
583	struct amdgpu_iv_entry *entry)
584	{
585	DRM_DEBUG("IH: VCE\n");
586	switch (entry->src_data) {
587	case 0:
588	amdgpu_fence_process(&adev->vce.ring[0]);
589	break;
590	case 1:
591	amdgpu_fence_process(&adev->vce.ring[1]);
592	break;
593	default:
594	DRM_ERROR("Unhandled interrupt: %d %d\n",
595	entry->src_id, entry->src_data);
596	break;
597	}
598
599	return 0;
600	}
601
5fc3aeeb	602	static int vce_v2_0_set_clockgating_state(void *handle,
5fc3aeeb	603	enum amd_clockgating_state state)
a2e73f56 AD	604	{
a2e73f56 AD	605	bool gate = false;
5fc3aeeb	606	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56	607
5fc3aeeb	608	if (state == AMD_CG_STATE_GATE)
a2e73f56 AD	609	gate = true;
	610
	611	vce_v2_0_enable_mgcg(adev, gate);
	612
	613	return 0;
	614	}
	615
5fc3aeeb	616	static int vce_v2_0_set_powergating_state(void *handle,
5fc3aeeb	617	enum amd_powergating_state state)
a2e73f56 AD	618	{
	619	/* This doesn't actually powergate the VCE block.
	620	* That's done in the dpm code via the SMC. This
	621	* just re-inits the block as necessary. The actual
	622	* gating still happens in the dpm code. We should
	623	* revisit this when there is a cleaner line between
	624	* the smc and the hw blocks
	625	*/
5fc3aeeb	626	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	627
e3b04bc7	628	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
808a934f AD	629	return 0;
808a934f AD	630
5fc3aeeb	631	if (state == AMD_PG_STATE_GATE)
a2e73f56 AD	632	/* XXX do we need a vce_v2_0_stop()? */
	633	return 0;
	634	else
	635	return vce_v2_0_start(adev);
	636	}
	637
5fc3aeeb	638	const struct amd_ip_funcs vce_v2_0_ip_funcs = {
a2e73f56 AD	639	.early_init = vce_v2_0_early_init,
	640	.late_init = NULL,
	641	.sw_init = vce_v2_0_sw_init,
	642	.sw_fini = vce_v2_0_sw_fini,
	643	.hw_init = vce_v2_0_hw_init,
	644	.hw_fini = vce_v2_0_hw_fini,
	645	.suspend = vce_v2_0_suspend,
	646	.resume = vce_v2_0_resume,
	647	.is_idle = vce_v2_0_is_idle,
	648	.wait_for_idle = vce_v2_0_wait_for_idle,
	649	.soft_reset = vce_v2_0_soft_reset,
	650	.print_status = vce_v2_0_print_status,
	651	.set_clockgating_state = vce_v2_0_set_clockgating_state,
	652	.set_powergating_state = vce_v2_0_set_powergating_state,
	653	};
	654
	655	static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
	656	.get_rptr = vce_v2_0_ring_get_rptr,
	657	.get_wptr = vce_v2_0_ring_get_wptr,
	658	.set_wptr = vce_v2_0_ring_set_wptr,
	659	.parse_cs = amdgpu_vce_ring_parse_cs,
	660	.emit_ib = amdgpu_vce_ring_emit_ib,
	661	.emit_fence = amdgpu_vce_ring_emit_fence,
a2e73f56 AD	662	.test_ring = amdgpu_vce_ring_test_ring,
a2e73f56 AD	663	.test_ib = amdgpu_vce_ring_test_ib,
edff0e28	664	.insert_nop = amdgpu_ring_insert_nop,
9e5d5309	665	.pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56 AD	666	};
	667
	668	static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
	669	{
	670	adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
	671	adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
	672	}
	673
	674	static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
	675	.set = vce_v2_0_set_interrupt_state,
	676	.process = vce_v2_0_process_interrupt,
	677	};
	678
	679	static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
	680	{
	681	adev->vce.irq.num_types = 1;
	682	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
	683	};