[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / vid.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef VI_H
#define VI_H

#define SDMA0_REGISTER_OFFSET                             0x0 /* not a register */
#define SDMA1_REGISTER_OFFSET                             0x200 /* not a register */
#define SDMA_MAX_INSTANCE 2

/* crtc instance offsets */
#define CRTC0_REGISTER_OFFSET                 (0x1b9c - 0x1b9c)
#define CRTC1_REGISTER_OFFSET                 (0x1d9c - 0x1b9c)
#define CRTC2_REGISTER_OFFSET                 (0x1f9c - 0x1b9c)
#define CRTC3_REGISTER_OFFSET                 (0x419c - 0x1b9c)
#define CRTC4_REGISTER_OFFSET                 (0x439c - 0x1b9c)
#define CRTC5_REGISTER_OFFSET                 (0x459c - 0x1b9c)
#define CRTC6_REGISTER_OFFSET                 (0x479c - 0x1b9c)

/* dig instance offsets */
#define DIG0_REGISTER_OFFSET                 (0x4a00 - 0x4a00)
#define DIG1_REGISTER_OFFSET                 (0x4b00 - 0x4a00)
#define DIG2_REGISTER_OFFSET                 (0x4c00 - 0x4a00)
#define DIG3_REGISTER_OFFSET                 (0x4d00 - 0x4a00)
#define DIG4_REGISTER_OFFSET                 (0x4e00 - 0x4a00)
#define DIG5_REGISTER_OFFSET                 (0x4f00 - 0x4a00)
#define DIG6_REGISTER_OFFSET                 (0x5400 - 0x4a00)
#define DIG7_REGISTER_OFFSET                 (0x5600 - 0x4a00)
#define DIG8_REGISTER_OFFSET                 (0x5700 - 0x4a00)

/* audio endpt instance offsets */
#define AUD0_REGISTER_OFFSET                 (0x17a8 - 0x17a8)
#define AUD1_REGISTER_OFFSET                 (0x17ac - 0x17a8)
#define AUD2_REGISTER_OFFSET                 (0x17b0 - 0x17a8)
#define AUD3_REGISTER_OFFSET                 (0x17b4 - 0x17a8)
#define AUD4_REGISTER_OFFSET                 (0x17b8 - 0x17a8)
#define AUD5_REGISTER_OFFSET                 (0x17bc - 0x17a8)
#define AUD6_REGISTER_OFFSET                 (0x17c4 - 0x17a8)

/* hpd instance offsets */
#define HPD0_REGISTER_OFFSET                 (0x1898 - 0x1898)
#define HPD1_REGISTER_OFFSET                 (0x18a0 - 0x1898)
#define HPD2_REGISTER_OFFSET                 (0x18a8 - 0x1898)
#define HPD3_REGISTER_OFFSET                 (0x18b0 - 0x1898)
#define HPD4_REGISTER_OFFSET                 (0x18b8 - 0x1898)
#define HPD5_REGISTER_OFFSET                 (0x18c0 - 0x1898)

#define AMDGPU_NUM_OF_VMIDS			8

#define RB_BITMAP_WIDTH_PER_SH     2

#define MC_SEQ_MISC0__GDDR5__SHIFT	0x1c
#define MC_SEQ_MISC0__GDDR5_MASK	0xf0000000
#define MC_SEQ_MISC0__GDDR5_VALUE	5

/*
 * PM4
 */
#define	PACKET_TYPE0	0
#define	PACKET_TYPE1	1
#define	PACKET_TYPE2	2
#define	PACKET_TYPE3	3

#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
			 ((reg) & 0xFFFF) |			\
			 ((n) & 0x3FFF) << 16)
#define CP_PACKET2			0x80000000
#define		PACKET2_PAD_SHIFT		0
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)

#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
			 (((op) & 0xFF) << 8) |				\
			 ((n) & 0x3FFF) << 16)

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

/* Packet 3 types */
#define	PACKET3_NOP					0x10
#define	PACKET3_SET_BASE				0x11
#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
#define			CE_PARTITION_BASE		3
#define	PACKET3_CLEAR_STATE				0x12
#define	PACKET3_INDEX_BUFFER_SIZE			0x13
#define	PACKET3_DISPATCH_DIRECT				0x15
#define	PACKET3_DISPATCH_INDIRECT			0x16
#define	PACKET3_ATOMIC_GDS				0x1D
#define	PACKET3_ATOMIC_MEM				0x1E
#define	PACKET3_OCCLUSION_QUERY				0x1F
#define	PACKET3_SET_PREDICATION				0x20
#define	PACKET3_REG_RMW					0x21
#define	PACKET3_COND_EXEC				0x22
#define	PACKET3_PRED_EXEC				0x23
#define	PACKET3_DRAW_INDIRECT				0x24
#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
#define	PACKET3_INDEX_BASE				0x26
#define	PACKET3_DRAW_INDEX_2				0x27
#define	PACKET3_CONTEXT_CONTROL				0x28
#define	PACKET3_INDEX_TYPE				0x2A
#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
#define	PACKET3_DRAW_INDEX_AUTO				0x2D
#define	PACKET3_NUM_INSTANCES				0x2F
#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
#define	PACKET3_INDIRECT_BUFFER_CONST			0x33
#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
#define	PACKET3_DRAW_PREAMBLE				0x36
#define	PACKET3_WRITE_DATA				0x37
#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
		/* 0 - register
		 * 1 - memory (sync - via GRBM)
		 * 2 - gl2
		 * 3 - gds
		 * 4 - reserved
		 * 5 - memory (async - direct)
		 */
#define		WR_ONE_ADDR                             (1 << 16)
#define		WR_CONFIRM                              (1 << 20)
#define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
		/* 0 - LRU
		 * 1 - Stream
		 */
#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
		/* 0 - me
		 * 1 - pfp
		 * 2 - ce
		 */
#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
#define	PACKET3_MEM_SEMAPHORE				0x39
#              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
#              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
#              define PACKET3_SEM_CLIENT_CODE	    ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
#              define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
#              define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
#define	PACKET3_WAIT_REG_MEM				0x3C
#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
		/* 0 - always
		 * 1 - <
		 * 2 - <=
		 * 3 - ==
		 * 4 - !=
		 * 5 - >=
		 * 6 - >
		 */
#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
		/* 0 - reg
		 * 1 - mem
		 */
#define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
		/* 0 - wait_reg_mem
		 * 1 - wr_wait_wr_reg
		 */
#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
		/* 0 - me
		 * 1 - pfp
		 */
#define	PACKET3_INDIRECT_BUFFER				0x3F
#define		INDIRECT_BUFFER_TCL2_VOLATILE           (1 << 22)
#define		INDIRECT_BUFFER_VALID                   (1 << 23)
#define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
		/* 0 - LRU
		 * 1 - Stream
		 * 2 - Bypass
		 */
#define	PACKET3_COPY_DATA				0x40
#define	PACKET3_PFP_SYNC_ME				0x42
#define	PACKET3_SURFACE_SYNC				0x43
#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
#              define PACKET3_TCL1_VOL_ACTION_ENA  (1 << 15)
#              define PACKET3_TC_VOL_ACTION_ENA    (1 << 16) /* L2 */
#              define PACKET3_TC_WB_ACTION_ENA     (1 << 18) /* L2 */
#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
#              define PACKET3_TC_ACTION_ENA        (1 << 23) /* L2 */
#              define PACKET3_CB_ACTION_ENA        (1 << 25)
#              define PACKET3_DB_ACTION_ENA        (1 << 26)
#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
#              define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
#define	PACKET3_COND_WRITE				0x45
#define	PACKET3_EVENT_WRITE				0x46
#define		EVENT_TYPE(x)                           ((x) << 0)
#define		EVENT_INDEX(x)                          ((x) << 8)
		/* 0 - any non-TS event
		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
		 * 2 - SAMPLE_PIPELINESTAT
		 * 3 - SAMPLE_STREAMOUTSTAT*
		 * 4 - *S_PARTIAL_FLUSH
		 * 5 - EOP events
		 * 6 - EOS events
		 */
#define	PACKET3_EVENT_WRITE_EOP				0x47
#define		EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
#define		EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
#define		EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
#define		EOP_TCL1_ACTION_EN                      (1 << 16)
#define		EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
#define		EOP_TCL2_VOLATILE                       (1 << 24)
#define		EOP_CACHE_POLICY(x)                     ((x) << 25)
		/* 0 - LRU
		 * 1 - Stream
		 * 2 - Bypass
		 */
#define		DATA_SEL(x)                             ((x) << 29)
		/* 0 - discard
		 * 1 - send low 32bit data
		 * 2 - send 64bit data
		 * 3 - send 64bit GPU counter value
		 * 4 - send 64bit sys counter value
		 */
#define		INT_SEL(x)                              ((x) << 24)
		/* 0 - none
		 * 1 - interrupt only (DATA_SEL = 0)
		 * 2 - interrupt when data write is confirmed
		 */
#define		DST_SEL(x)                              ((x) << 16)
		/* 0 - MC
		 * 1 - TC/L2
		 */
#define	PACKET3_EVENT_WRITE_EOS				0x48
#define	PACKET3_RELEASE_MEM				0x49
#define	PACKET3_PREAMBLE_CNTL				0x4A
#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
#define	PACKET3_DMA_DATA				0x50
/* 1. header
 * 2. CONTROL
 * 3. SRC_ADDR_LO or DATA [31:0]
 * 4. SRC_ADDR_HI [31:0]
 * 5. DST_ADDR_LO [31:0]
 * 6. DST_ADDR_HI [7:0]
 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
 */
/* CONTROL */
#              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
		/* 0 - ME
		 * 1 - PFP
		 */
#              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
		/* 0 - LRU
		 * 1 - Stream
		 * 2 - Bypass
		 */
#              define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
#              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
		/* 0 - DST_ADDR using DAS
		 * 1 - GDS
		 * 3 - DST_ADDR using L2
		 */
#              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
		/* 0 - LRU
		 * 1 - Stream
		 * 2 - Bypass
		 */
#              define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
#              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
		/* 0 - SRC_ADDR using SAS
		 * 1 - GDS
		 * 2 - DATA
		 * 3 - SRC_ADDR using L2
		 */
#              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
/* COMMAND */
#              define PACKET3_DMA_DATA_DIS_WC      (1 << 21)
#              define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
		/* 0 - none
		 * 1 - 8 in 16
		 * 2 - 8 in 32
		 * 3 - 8 in 64
		 */
#              define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
		/* 0 - none
		 * 1 - 8 in 16
		 * 2 - 8 in 32
		 * 3 - 8 in 64
		 */
#              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
		/* 0 - memory
		 * 1 - register
		 */
#              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
		/* 0 - memory
		 * 1 - register
		 */
#              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
#              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
#              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
#define	PACKET3_AQUIRE_MEM				0x58
#define	PACKET3_REWIND					0x59
#define	PACKET3_LOAD_UCONFIG_REG			0x5E
#define	PACKET3_LOAD_SH_REG				0x5F
#define	PACKET3_LOAD_CONFIG_REG				0x60
#define	PACKET3_LOAD_CONTEXT_REG			0x61
#define	PACKET3_SET_CONFIG_REG				0x68
#define		PACKET3_SET_CONFIG_REG_START			0x00002000
#define		PACKET3_SET_CONFIG_REG_END			0x00002c00
#define	PACKET3_SET_CONTEXT_REG				0x69
#define		PACKET3_SET_CONTEXT_REG_START			0x0000a000
#define		PACKET3_SET_CONTEXT_REG_END			0x0000a400
#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
#define	PACKET3_SET_SH_REG				0x76
#define		PACKET3_SET_SH_REG_START			0x00002c00
#define		PACKET3_SET_SH_REG_END				0x00003000
#define	PACKET3_SET_SH_REG_OFFSET			0x77
#define	PACKET3_SET_QUEUE_REG				0x78
#define	PACKET3_SET_UCONFIG_REG				0x79
#define		PACKET3_SET_UCONFIG_REG_START			0x0000c000
#define		PACKET3_SET_UCONFIG_REG_END			0x0000c400
#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
#define	PACKET3_SCRATCH_RAM_READ			0x7E
#define	PACKET3_LOAD_CONST_RAM				0x80
#define	PACKET3_WRITE_CONST_RAM				0x81
#define	PACKET3_DUMP_CONST_RAM				0x83
#define	PACKET3_INCREMENT_CE_COUNTER			0x84
#define	PACKET3_INCREMENT_DE_COUNTER			0x85
#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
#define	PACKET3_SWITCH_BUFFER				0x8B

#define VCE_CMD_NO_OP		0x00000000
#define VCE_CMD_END		0x00000001
#define VCE_CMD_IB		0x00000002
#define VCE_CMD_FENCE		0x00000003
#define VCE_CMD_TRAP		0x00000004
#define VCE_CMD_IB_AUTO 	0x00000005
#define VCE_CMD_SEMAPHORE	0x00000006

#endif
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef VI_H
	24	#define VI_H
	25
	26	#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
	27	#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
	28	#define SDMA_MAX_INSTANCE 2
	29
	30	/* crtc instance offsets */
	31	#define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
	32	#define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
	33	#define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
	34	#define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
	35	#define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
	36	#define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
	37	#define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
	38
	39	/* dig instance offsets */
	40	#define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
	41	#define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
	42	#define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
	43	#define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
	44	#define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
	45	#define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
	46	#define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
	47	#define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
	48	#define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
	49
	50	/* audio endpt instance offsets */
	51	#define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
	52	#define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
	53	#define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
	54	#define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
	55	#define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
	56	#define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
	57	#define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8)
	58
	59	/* hpd instance offsets */
	60	#define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
	61	#define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
	62	#define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
	63	#define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
	64	#define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
65	#define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
66
67	#define AMDGPU_NUM_OF_VMIDS 8
68
69	#define RB_BITMAP_WIDTH_PER_SH 2
70
71	#define MC_SEQ_MISC0__GDDR5__SHIFT 0x1c
72	#define MC_SEQ_MISC0__GDDR5_MASK 0xf0000000
73	#define MC_SEQ_MISC0__GDDR5_VALUE 5
74
75	/*
76	* PM4
77	*/
78	#define PACKET_TYPE0 0
79	#define PACKET_TYPE1 1
80	#define PACKET_TYPE2 2
81	#define PACKET_TYPE3 3
82
83	#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
84	#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
85	#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
86	#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
87	#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) \| \
88	((reg) & 0xFFFF) \| \
89	((n) & 0x3FFF) << 16)
90	#define CP_PACKET2 0x80000000
91	#define PACKET2_PAD_SHIFT 0
92	#define PACKET2_PAD_MASK (0x3fffffff << 0)
93
94	#define PACKET2(v) (CP_PACKET2 \| REG_SET(PACKET2_PAD, (v)))
95
96	#define PACKET3(op, n) ((PACKET_TYPE3 << 30) \| \
97	(((op) & 0xFF) << 8) \| \
98	((n) & 0x3FFF) << 16)
99
100	#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) \| 1 << 1)
101
102	/* Packet 3 types */
103	#define PACKET3_NOP 0x10
104	#define PACKET3_SET_BASE 0x11
105	#define PACKET3_BASE_INDEX(x) ((x) << 0)
106	#define CE_PARTITION_BASE 3
107	#define PACKET3_CLEAR_STATE 0x12
108	#define PACKET3_INDEX_BUFFER_SIZE 0x13
109	#define PACKET3_DISPATCH_DIRECT 0x15
110	#define PACKET3_DISPATCH_INDIRECT 0x16
111	#define PACKET3_ATOMIC_GDS 0x1D
112	#define PACKET3_ATOMIC_MEM 0x1E
113	#define PACKET3_OCCLUSION_QUERY 0x1F
114	#define PACKET3_SET_PREDICATION 0x20
115	#define PACKET3_REG_RMW 0x21
116	#define PACKET3_COND_EXEC 0x22
117	#define PACKET3_PRED_EXEC 0x23
118	#define PACKET3_DRAW_INDIRECT 0x24
119	#define PACKET3_DRAW_INDEX_INDIRECT 0x25
120	#define PACKET3_INDEX_BASE 0x26
121	#define PACKET3_DRAW_INDEX_2 0x27
122	#define PACKET3_CONTEXT_CONTROL 0x28
123	#define PACKET3_INDEX_TYPE 0x2A
124	#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
125	#define PACKET3_DRAW_INDEX_AUTO 0x2D
126	#define PACKET3_NUM_INSTANCES 0x2F
127	#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
128	#define PACKET3_INDIRECT_BUFFER_CONST 0x33
129	#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
130	#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
131	#define PACKET3_DRAW_PREAMBLE 0x36
132	#define PACKET3_WRITE_DATA 0x37
133	#define WRITE_DATA_DST_SEL(x) ((x) << 8)
134	/* 0 - register
135	* 1 - memory (sync - via GRBM)
136	* 2 - gl2
137	* 3 - gds
138	* 4 - reserved
139	* 5 - memory (async - direct)
140	*/
141	#define WR_ONE_ADDR (1 << 16)
142	#define WR_CONFIRM (1 << 20)
143	#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
144	/* 0 - LRU
145	* 1 - Stream
146	*/
147	#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
148	/* 0 - me
149	* 1 - pfp
150	* 2 - ce
151	*/
152	#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
153	#define PACKET3_MEM_SEMAPHORE 0x39
154	# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
155	# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
156	# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
157	# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
158	# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
159	#define PACKET3_WAIT_REG_MEM 0x3C
160	#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
161	/* 0 - always
162	* 1 - <
163	* 2 - <=
164	* 3 - ==
165	* 4 - !=
166	* 5 - >=
167	* 6 - >
168	*/
169	#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
170	/* 0 - reg
171	* 1 - mem
172	*/
173	#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
174	/* 0 - wait_reg_mem
175	* 1 - wr_wait_wr_reg
176	*/
177	#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
178	/* 0 - me
179	* 1 - pfp
180	*/
181	#define PACKET3_INDIRECT_BUFFER 0x3F
182	#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
183	#define INDIRECT_BUFFER_VALID (1 << 23)
184	#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
185	/* 0 - LRU
186	* 1 - Stream
187	* 2 - Bypass
188	*/
189	#define PACKET3_COPY_DATA 0x40
190	#define PACKET3_PFP_SYNC_ME 0x42
191	#define PACKET3_SURFACE_SYNC 0x43
192	# define PACKET3_DEST_BASE_0_ENA (1 << 0)
193	# define PACKET3_DEST_BASE_1_ENA (1 << 1)
194	# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
195	# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
196	# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
197	# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
198	# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
199	# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
200	# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
201	# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
202	# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
203	# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
204	# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
205	# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
206	# define PACKET3_DEST_BASE_2_ENA (1 << 19)
207	# define PACKET3_DEST_BASE_3_ENA (1 << 21)
208	# define PACKET3_TCL1_ACTION_ENA (1 << 22)
209	# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
210	# define PACKET3_CB_ACTION_ENA (1 << 25)
211	# define PACKET3_DB_ACTION_ENA (1 << 26)
212	# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
213	# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
214	# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
215	#define PACKET3_COND_WRITE 0x45
216	#define PACKET3_EVENT_WRITE 0x46
217	#define EVENT_TYPE(x) ((x) << 0)
218	#define EVENT_INDEX(x) ((x) << 8)
219	/* 0 - any non-TS event
220	* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
221	* 2 - SAMPLE_PIPELINESTAT
222	* 3 - SAMPLE_STREAMOUTSTAT*
223	* 4 - *S_PARTIAL_FLUSH
224	* 5 - EOP events
225	* 6 - EOS events
226	*/
227	#define PACKET3_EVENT_WRITE_EOP 0x47
228	#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
229	#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
230	#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
231	#define EOP_TCL1_ACTION_EN (1 << 16)
232	#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
233	#define EOP_TCL2_VOLATILE (1 << 24)
234	#define EOP_CACHE_POLICY(x) ((x) << 25)
235	/* 0 - LRU
236	* 1 - Stream
237	* 2 - Bypass
238	*/
239	#define DATA_SEL(x) ((x) << 29)
240	/* 0 - discard
241	* 1 - send low 32bit data
242	* 2 - send 64bit data
243	* 3 - send 64bit GPU counter value
244	* 4 - send 64bit sys counter value
245	*/
246	#define INT_SEL(x) ((x) << 24)
247	/* 0 - none
248	* 1 - interrupt only (DATA_SEL = 0)
249	* 2 - interrupt when data write is confirmed
250	*/
251	#define DST_SEL(x) ((x) << 16)
252	/* 0 - MC
253	* 1 - TC/L2
254	*/
255	#define PACKET3_EVENT_WRITE_EOS 0x48
256	#define PACKET3_RELEASE_MEM 0x49
257	#define PACKET3_PREAMBLE_CNTL 0x4A
258	# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
259	# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
260	#define PACKET3_DMA_DATA 0x50
261	/* 1. header
262	* 2. CONTROL
263	* 3. SRC_ADDR_LO or DATA [31:0]
264	* 4. SRC_ADDR_HI [31:0]
265	* 5. DST_ADDR_LO [31:0]
266	* 6. DST_ADDR_HI [7:0]
267	* 7. COMMAND [30:21] \| BYTE_COUNT [20:0]
268	*/
269	/* CONTROL */
270	# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
271	/* 0 - ME
272	* 1 - PFP
273	*/
274	# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
275	/* 0 - LRU
276	* 1 - Stream
277	* 2 - Bypass
278	*/
279	# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
280	# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
281	/* 0 - DST_ADDR using DAS
282	* 1 - GDS
283	* 3 - DST_ADDR using L2
284	*/
285	# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
286	/* 0 - LRU
287	* 1 - Stream
288	* 2 - Bypass
289	*/
290	# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
291	# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
292	/* 0 - SRC_ADDR using SAS
293	* 1 - GDS
294	* 2 - DATA
295	* 3 - SRC_ADDR using L2
296	*/
297	# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
298	/* COMMAND */
299	# define PACKET3_DMA_DATA_DIS_WC (1 << 21)
300	# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
301	/* 0 - none
302	* 1 - 8 in 16
303	* 2 - 8 in 32
304	* 3 - 8 in 64
305	*/
306	# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
307	/* 0 - none
308	* 1 - 8 in 16
309	* 2 - 8 in 32
310	* 3 - 8 in 64
311	*/
312	# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
313	/* 0 - memory
314	* 1 - register
315	*/
316	# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
317	/* 0 - memory
318	* 1 - register
319	*/
320	# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
321	# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
322	# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
323	#define PACKET3_AQUIRE_MEM 0x58
324	#define PACKET3_REWIND 0x59
325	#define PACKET3_LOAD_UCONFIG_REG 0x5E
326	#define PACKET3_LOAD_SH_REG 0x5F
327	#define PACKET3_LOAD_CONFIG_REG 0x60
328	#define PACKET3_LOAD_CONTEXT_REG 0x61
329	#define PACKET3_SET_CONFIG_REG 0x68
330	#define PACKET3_SET_CONFIG_REG_START 0x00002000
331	#define PACKET3_SET_CONFIG_REG_END 0x00002c00
332	#define PACKET3_SET_CONTEXT_REG 0x69
333	#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
334	#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
335	#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
336	#define PACKET3_SET_SH_REG 0x76
337	#define PACKET3_SET_SH_REG_START 0x00002c00
338	#define PACKET3_SET_SH_REG_END 0x00003000
339	#define PACKET3_SET_SH_REG_OFFSET 0x77
340	#define PACKET3_SET_QUEUE_REG 0x78
341	#define PACKET3_SET_UCONFIG_REG 0x79
342	#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
343	#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
344	#define PACKET3_SCRATCH_RAM_WRITE 0x7D
345	#define PACKET3_SCRATCH_RAM_READ 0x7E
346	#define PACKET3_LOAD_CONST_RAM 0x80
347	#define PACKET3_WRITE_CONST_RAM 0x81
348	#define PACKET3_DUMP_CONST_RAM 0x83
349	#define PACKET3_INCREMENT_CE_COUNTER 0x84
350	#define PACKET3_INCREMENT_DE_COUNTER 0x85
351	#define PACKET3_WAIT_ON_CE_COUNTER 0x86
352	#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
353	#define PACKET3_SWITCH_BUFFER 0x8B
354
355	#define VCE_CMD_NO_OP 0x00000000
356	#define VCE_CMD_END 0x00000001
357	#define VCE_CMD_IB 0x00000002
358	#define VCE_CMD_FENCE 0x00000003
359	#define VCE_CMD_TRAP 0x00000004
360	#define VCE_CMD_IB_AUTO 0x00000005
361	#define VCE_CMD_SEMAPHORE 0x00000006
362
363	#endif