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1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Author: Huang Rui <ray.huang@amd.com> | |
23 | * | |
24 | */ | |
25 | #include <linux/module.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/fb.h> | |
28 | #include "linux/delay.h" | |
29 | #include "pp_acpi.h" | |
30 | #include "hwmgr.h" | |
31 | #include <atombios.h> | |
32 | #include "iceland_hwmgr.h" | |
33 | #include "pptable.h" | |
34 | #include "processpptables.h" | |
35 | #include "pp_debug.h" | |
36 | #include "ppsmc.h" | |
37 | #include "cgs_common.h" | |
38 | #include "pppcielanes.h" | |
39 | #include "iceland_dyn_defaults.h" | |
40 | #include "smumgr.h" | |
41 | #include "iceland_smumgr.h" | |
42 | #include "iceland_clockpowergating.h" | |
43 | #include "iceland_thermal.h" | |
44 | #include "iceland_powertune.h" | |
45 | ||
46 | #include "gmc/gmc_8_1_d.h" | |
47 | #include "gmc/gmc_8_1_sh_mask.h" | |
48 | ||
49 | #include "bif/bif_5_0_d.h" | |
50 | #include "bif/bif_5_0_sh_mask.h" | |
51 | ||
52 | #include "smu/smu_7_1_1_d.h" | |
53 | #include "smu/smu_7_1_1_sh_mask.h" | |
54 | ||
55 | #include "cgs_linux.h" | |
56 | #include "eventmgr.h" | |
57 | #include "amd_pcie_helpers.h" | |
58 | ||
59 | #define MC_CG_ARB_FREQ_F0 0x0a | |
60 | #define MC_CG_ARB_FREQ_F1 0x0b | |
61 | #define MC_CG_ARB_FREQ_F2 0x0c | |
62 | #define MC_CG_ARB_FREQ_F3 0x0d | |
63 | ||
64 | #define MC_CG_SEQ_DRAMCONF_S0 0x05 | |
65 | #define MC_CG_SEQ_DRAMCONF_S1 0x06 | |
66 | #define MC_CG_SEQ_YCLK_SUSPEND 0x04 | |
67 | #define MC_CG_SEQ_YCLK_RESUME 0x0a | |
68 | ||
69 | #define PCIE_BUS_CLK 10000 | |
70 | #define TCLK (PCIE_BUS_CLK / 10) | |
71 | ||
72 | #define SMC_RAM_END 0x40000 | |
73 | #define SMC_CG_IND_START 0xc0030000 | |
74 | #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/ | |
75 | ||
76 | #define VOLTAGE_SCALE 4 | |
77 | #define VOLTAGE_VID_OFFSET_SCALE1 625 | |
78 | #define VOLTAGE_VID_OFFSET_SCALE2 100 | |
79 | ||
80 | const uint32_t iceland_magic = (uint32_t)(PHM_VIslands_Magic); | |
81 | ||
82 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | |
83 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | |
84 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | |
85 | ||
86 | /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ | |
87 | enum DPM_EVENT_SRC { | |
88 | DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */ | |
89 | DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */ | |
90 | DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */ | |
91 | DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */ | |
92 | DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */ | |
93 | }; | |
94 | ||
95 | static int iceland_read_clock_registers(struct pp_hwmgr *hwmgr) | |
96 | { | |
97 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
98 | ||
99 | data->clock_registers.vCG_SPLL_FUNC_CNTL = | |
100 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); | |
101 | data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = | |
102 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); | |
103 | data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = | |
104 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); | |
105 | data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = | |
106 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); | |
107 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = | |
108 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); | |
109 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = | |
110 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); | |
111 | data->clock_registers.vDLL_CNTL = | |
112 | cgs_read_register(hwmgr->device, mmDLL_CNTL); | |
113 | data->clock_registers.vMCLK_PWRMGT_CNTL = | |
114 | cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); | |
115 | data->clock_registers.vMPLL_AD_FUNC_CNTL = | |
116 | cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); | |
117 | data->clock_registers.vMPLL_DQ_FUNC_CNTL = | |
118 | cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); | |
119 | data->clock_registers.vMPLL_FUNC_CNTL = | |
120 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); | |
121 | data->clock_registers.vMPLL_FUNC_CNTL_1 = | |
122 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); | |
123 | data->clock_registers.vMPLL_FUNC_CNTL_2 = | |
124 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); | |
125 | data->clock_registers.vMPLL_SS1 = | |
126 | cgs_read_register(hwmgr->device, mmMPLL_SS1); | |
127 | data->clock_registers.vMPLL_SS2 = | |
128 | cgs_read_register(hwmgr->device, mmMPLL_SS2); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | /** | |
134 | * Find out if memory is GDDR5. | |
135 | * | |
136 | * @param hwmgr the address of the powerplay hardware manager. | |
137 | * @return always 0 | |
138 | */ | |
139 | int iceland_get_memory_type(struct pp_hwmgr *hwmgr) | |
140 | { | |
141 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
142 | uint32_t temp; | |
143 | ||
144 | temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); | |
145 | ||
146 | data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE == | |
147 | ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> | |
148 | MC_SEQ_MISC0_GDDR5_SHIFT)); | |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | int iceland_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) | |
154 | { | |
155 | /* iceland does not have MM hardware blocks */ | |
156 | return 0; | |
157 | } | |
158 | ||
159 | /** | |
160 | * Enables Dynamic Power Management by SMC | |
161 | * | |
162 | * @param hwmgr the address of the powerplay hardware manager. | |
163 | * @return always 0 | |
164 | */ | |
165 | int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr) | |
166 | { | |
167 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | /** | |
173 | * Find the MC microcode version and store it in the HwMgr struct | |
174 | * | |
175 | * @param hwmgr the address of the powerplay hardware manager. | |
176 | * @return always 0 | |
177 | */ | |
178 | int iceland_get_mc_microcode_version(struct pp_hwmgr *hwmgr) | |
179 | { | |
180 | cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); | |
181 | ||
182 | hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
187 | static int iceland_init_sclk_threshold(struct pp_hwmgr *hwmgr) | |
188 | { | |
189 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
190 | ||
191 | data->low_sclk_interrupt_threshold = 0; | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | ||
197 | static int iceland_setup_asic_task(struct pp_hwmgr *hwmgr) | |
198 | { | |
199 | int tmp_result, result = 0; | |
200 | ||
201 | tmp_result = iceland_read_clock_registers(hwmgr); | |
202 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
203 | "Failed to read clock registers!", result = tmp_result); | |
204 | ||
205 | tmp_result = iceland_get_memory_type(hwmgr); | |
206 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
207 | "Failed to get memory type!", result = tmp_result); | |
208 | ||
209 | tmp_result = iceland_enable_acpi_power_management(hwmgr); | |
210 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
211 | "Failed to enable ACPI power management!", result = tmp_result); | |
212 | ||
213 | tmp_result = iceland_get_mc_microcode_version(hwmgr); | |
214 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
215 | "Failed to get MC microcode version!", result = tmp_result); | |
216 | ||
217 | tmp_result = iceland_init_sclk_threshold(hwmgr); | |
218 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
219 | "Failed to init sclk threshold!", result = tmp_result); | |
220 | ||
221 | return result; | |
222 | } | |
223 | ||
224 | static bool cf_iceland_voltage_control(struct pp_hwmgr *hwmgr) | |
225 | { | |
226 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
227 | ||
228 | return ICELAND_VOLTAGE_CONTROL_NONE != data->voltage_control; | |
229 | } | |
230 | ||
231 | /* | |
232 | * -------------- Voltage Tables ---------------------- | |
233 | * If the voltage table would be bigger than what will fit into the | |
234 | * state table on the SMC keep only the higher entries. | |
235 | */ | |
236 | ||
237 | static void iceland_trim_voltage_table_to_fit_state_table( | |
238 | struct pp_hwmgr *hwmgr, | |
239 | uint32_t max_voltage_steps, | |
240 | pp_atomctrl_voltage_table *voltage_table) | |
241 | { | |
242 | unsigned int i, diff; | |
243 | ||
244 | if (voltage_table->count <= max_voltage_steps) { | |
245 | return; | |
246 | } | |
247 | ||
248 | diff = voltage_table->count - max_voltage_steps; | |
249 | ||
250 | for (i = 0; i < max_voltage_steps; i++) { | |
251 | voltage_table->entries[i] = voltage_table->entries[i + diff]; | |
252 | } | |
253 | ||
254 | voltage_table->count = max_voltage_steps; | |
255 | ||
256 | return; | |
257 | } | |
258 | ||
259 | /** | |
260 | * Enable voltage control | |
261 | * | |
262 | * @param hwmgr the address of the powerplay hardware manager. | |
263 | * @return always 0 | |
264 | */ | |
265 | int iceland_enable_voltage_control(struct pp_hwmgr *hwmgr) | |
266 | { | |
267 | /* enable voltage control */ | |
268 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | static int iceland_get_svi2_voltage_table(struct pp_hwmgr *hwmgr, | |
274 | struct phm_clock_voltage_dependency_table *voltage_dependency_table, | |
275 | pp_atomctrl_voltage_table *voltage_table) | |
276 | { | |
277 | uint32_t i; | |
278 | ||
279 | PP_ASSERT_WITH_CODE((NULL != voltage_table), | |
280 | "Voltage Dependency Table empty.", return -EINVAL;); | |
281 | ||
282 | voltage_table->mask_low = 0; | |
283 | voltage_table->phase_delay = 0; | |
284 | voltage_table->count = voltage_dependency_table->count; | |
285 | ||
286 | for (i = 0; i < voltage_dependency_table->count; i++) { | |
287 | voltage_table->entries[i].value = | |
288 | voltage_dependency_table->entries[i].v; | |
289 | voltage_table->entries[i].smio_low = 0; | |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | /** | |
296 | * Create Voltage Tables. | |
297 | * | |
298 | * @param hwmgr the address of the powerplay hardware manager. | |
299 | * @return always 0 | |
300 | */ | |
301 | int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr) | |
302 | { | |
303 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
304 | int result; | |
305 | ||
306 | /* GPIO voltage */ | |
307 | if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { | |
308 | result = atomctrl_get_voltage_table_v3(hwmgr, | |
309 | VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT, | |
310 | &data->vddc_voltage_table); | |
311 | PP_ASSERT_WITH_CODE((0 == result), | |
312 | "Failed to retrieve VDDC table.", return result;); | |
313 | } else if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { | |
314 | /* SVI2 VDDC voltage */ | |
315 | result = iceland_get_svi2_voltage_table(hwmgr, | |
316 | hwmgr->dyn_state.vddc_dependency_on_mclk, | |
317 | &data->vddc_voltage_table); | |
318 | PP_ASSERT_WITH_CODE((0 == result), | |
319 | "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;); | |
320 | } | |
321 | ||
322 | PP_ASSERT_WITH_CODE( | |
323 | (data->vddc_voltage_table.count <= (SMU71_MAX_LEVELS_VDDC)), | |
324 | "Too many voltage values for VDDC. Trimming to fit state table.", | |
325 | iceland_trim_voltage_table_to_fit_state_table(hwmgr, | |
326 | SMU71_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)); | |
327 | ); | |
328 | ||
329 | /* GPIO */ | |
330 | if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { | |
331 | result = atomctrl_get_voltage_table_v3(hwmgr, | |
332 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table)); | |
333 | PP_ASSERT_WITH_CODE((0 == result), | |
334 | "Failed to retrieve VDDCI table.", return result;); | |
335 | } | |
336 | ||
337 | /* SVI2 VDDCI voltage */ | |
338 | if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { | |
339 | result = iceland_get_svi2_voltage_table(hwmgr, | |
340 | hwmgr->dyn_state.vddci_dependency_on_mclk, | |
341 | &data->vddci_voltage_table); | |
342 | PP_ASSERT_WITH_CODE((0 == result), | |
343 | "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;); | |
344 | } | |
345 | ||
346 | PP_ASSERT_WITH_CODE( | |
347 | (data->vddci_voltage_table.count <= (SMU71_MAX_LEVELS_VDDCI)), | |
348 | "Too many voltage values for VDDCI. Trimming to fit state table.", | |
349 | iceland_trim_voltage_table_to_fit_state_table(hwmgr, | |
350 | SMU71_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)); | |
351 | ); | |
352 | ||
353 | ||
354 | /* GPIO */ | |
355 | if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { | |
356 | result = atomctrl_get_voltage_table_v3(hwmgr, | |
357 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table)); | |
358 | PP_ASSERT_WITH_CODE((0 == result), | |
359 | "Failed to retrieve table.", return result;); | |
360 | } | |
361 | ||
362 | /* SVI2 voltage control */ | |
363 | if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { | |
364 | result = iceland_get_svi2_voltage_table(hwmgr, | |
365 | hwmgr->dyn_state.mvdd_dependency_on_mclk, | |
366 | &data->mvdd_voltage_table); | |
367 | PP_ASSERT_WITH_CODE((0 == result), | |
368 | "Failed to retrieve SVI2 MVDD table from dependancy table.", return result;); | |
369 | } | |
370 | ||
371 | PP_ASSERT_WITH_CODE( | |
372 | (data->mvdd_voltage_table.count <= (SMU71_MAX_LEVELS_MVDD)), | |
373 | "Too many voltage values for MVDD. Trimming to fit state table.", | |
374 | iceland_trim_voltage_table_to_fit_state_table(hwmgr, | |
375 | SMU71_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)); | |
376 | ); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | /*---------------------------MC----------------------------*/ | |
382 | ||
383 | uint8_t iceland_get_memory_module_index(struct pp_hwmgr *hwmgr) | |
384 | { | |
385 | return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); | |
386 | } | |
387 | ||
388 | bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) | |
389 | { | |
390 | bool result = true; | |
391 | ||
392 | switch (inReg) { | |
393 | case mmMC_SEQ_RAS_TIMING: | |
394 | *outReg = mmMC_SEQ_RAS_TIMING_LP; | |
395 | break; | |
396 | ||
397 | case mmMC_SEQ_DLL_STBY: | |
398 | *outReg = mmMC_SEQ_DLL_STBY_LP; | |
399 | break; | |
400 | ||
401 | case mmMC_SEQ_G5PDX_CMD0: | |
402 | *outReg = mmMC_SEQ_G5PDX_CMD0_LP; | |
403 | break; | |
404 | ||
405 | case mmMC_SEQ_G5PDX_CMD1: | |
406 | *outReg = mmMC_SEQ_G5PDX_CMD1_LP; | |
407 | break; | |
408 | ||
409 | case mmMC_SEQ_G5PDX_CTRL: | |
410 | *outReg = mmMC_SEQ_G5PDX_CTRL_LP; | |
411 | break; | |
412 | ||
413 | case mmMC_SEQ_CAS_TIMING: | |
414 | *outReg = mmMC_SEQ_CAS_TIMING_LP; | |
415 | break; | |
416 | ||
417 | case mmMC_SEQ_MISC_TIMING: | |
418 | *outReg = mmMC_SEQ_MISC_TIMING_LP; | |
419 | break; | |
420 | ||
421 | case mmMC_SEQ_MISC_TIMING2: | |
422 | *outReg = mmMC_SEQ_MISC_TIMING2_LP; | |
423 | break; | |
424 | ||
425 | case mmMC_SEQ_PMG_DVS_CMD: | |
426 | *outReg = mmMC_SEQ_PMG_DVS_CMD_LP; | |
427 | break; | |
428 | ||
429 | case mmMC_SEQ_PMG_DVS_CTL: | |
430 | *outReg = mmMC_SEQ_PMG_DVS_CTL_LP; | |
431 | break; | |
432 | ||
433 | case mmMC_SEQ_RD_CTL_D0: | |
434 | *outReg = mmMC_SEQ_RD_CTL_D0_LP; | |
435 | break; | |
436 | ||
437 | case mmMC_SEQ_RD_CTL_D1: | |
438 | *outReg = mmMC_SEQ_RD_CTL_D1_LP; | |
439 | break; | |
440 | ||
441 | case mmMC_SEQ_WR_CTL_D0: | |
442 | *outReg = mmMC_SEQ_WR_CTL_D0_LP; | |
443 | break; | |
444 | ||
445 | case mmMC_SEQ_WR_CTL_D1: | |
446 | *outReg = mmMC_SEQ_WR_CTL_D1_LP; | |
447 | break; | |
448 | ||
449 | case mmMC_PMG_CMD_EMRS: | |
450 | *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP; | |
451 | break; | |
452 | ||
453 | case mmMC_PMG_CMD_MRS: | |
454 | *outReg = mmMC_SEQ_PMG_CMD_MRS_LP; | |
455 | break; | |
456 | ||
457 | case mmMC_PMG_CMD_MRS1: | |
458 | *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP; | |
459 | break; | |
460 | ||
461 | case mmMC_SEQ_PMG_TIMING: | |
462 | *outReg = mmMC_SEQ_PMG_TIMING_LP; | |
463 | break; | |
464 | ||
465 | case mmMC_PMG_CMD_MRS2: | |
466 | *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP; | |
467 | break; | |
468 | ||
469 | case mmMC_SEQ_WR_CTL_2: | |
470 | *outReg = mmMC_SEQ_WR_CTL_2_LP; | |
471 | break; | |
472 | ||
473 | default: | |
474 | result = false; | |
475 | break; | |
476 | } | |
477 | ||
478 | return result; | |
479 | } | |
480 | ||
481 | int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table) | |
482 | { | |
483 | uint32_t i; | |
484 | uint16_t address; | |
485 | ||
486 | for (i = 0; i < table->last; i++) { | |
487 | table->mc_reg_address[i].s0 = | |
488 | iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) | |
489 | ? address : table->mc_reg_address[i].s1; | |
490 | } | |
491 | return 0; | |
492 | } | |
493 | ||
494 | int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_iceland_mc_reg_table *ni_table) | |
495 | { | |
496 | uint8_t i, j; | |
497 | ||
498 | PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
499 | "Invalid VramInfo table.", return -1); | |
500 | PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), | |
501 | "Invalid VramInfo table.", return -1); | |
502 | ||
503 | for (i = 0; i < table->last; i++) { | |
504 | ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; | |
505 | } | |
506 | ni_table->last = table->last; | |
507 | ||
508 | for (i = 0; i < table->num_entries; i++) { | |
509 | ni_table->mc_reg_table_entry[i].mclk_max = | |
510 | table->mc_reg_table_entry[i].mclk_max; | |
511 | for (j = 0; j < table->last; j++) { | |
512 | ni_table->mc_reg_table_entry[i].mc_data[j] = | |
513 | table->mc_reg_table_entry[i].mc_data[j]; | |
514 | } | |
515 | } | |
516 | ||
517 | ni_table->num_entries = table->num_entries; | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | /** | |
523 | * VBIOS omits some information to reduce size, we need to recover them here. | |
524 | * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. | |
525 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] | |
526 | * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0]. | |
527 | * 3. need to set these data for each clock range | |
528 | * | |
529 | * @param hwmgr the address of the powerplay hardware manager. | |
530 | * @param table the address of MCRegTable | |
531 | * @return always 0 | |
532 | */ | |
533 | static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_iceland_mc_reg_table *table) | |
534 | { | |
535 | uint8_t i, j, k; | |
536 | uint32_t temp_reg; | |
537 | const iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
538 | ||
539 | for (i = 0, j = table->last; i < table->last; i++) { | |
540 | PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
541 | "Invalid VramInfo table.", return -1); | |
542 | switch (table->mc_reg_address[i].s1) { | |
543 | /* | |
544 | * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write | |
545 | * to mmMC_PMG_CMD_EMRS/_LP[15:0]. Bit[15:0] MRS, need | |
546 | * to be update mmMC_PMG_CMD_MRS/_LP[15:0] | |
547 | */ | |
548 | case mmMC_SEQ_MISC1: | |
549 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); | |
550 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; | |
551 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; | |
552 | for (k = 0; k < table->num_entries; k++) { | |
553 | table->mc_reg_table_entry[k].mc_data[j] = | |
554 | ((temp_reg & 0xffff0000)) | | |
555 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); | |
556 | } | |
557 | j++; | |
558 | PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
559 | "Invalid VramInfo table.", return -1); | |
560 | ||
561 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); | |
562 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; | |
563 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; | |
564 | for (k = 0; k < table->num_entries; k++) { | |
565 | table->mc_reg_table_entry[k].mc_data[j] = | |
566 | (temp_reg & 0xffff0000) | | |
567 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
568 | ||
569 | if (!data->is_memory_GDDR5) { | |
570 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; | |
571 | } | |
572 | } | |
573 | j++; | |
574 | PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
575 | "Invalid VramInfo table.", return -1); | |
576 | ||
577 | if (!data->is_memory_GDDR5) { | |
578 | table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; | |
579 | table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; | |
580 | for (k = 0; k < table->num_entries; k++) { | |
581 | table->mc_reg_table_entry[k].mc_data[j] = | |
582 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; | |
583 | } | |
584 | j++; | |
585 | PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
586 | "Invalid VramInfo table.", return -1); | |
587 | } | |
588 | ||
589 | break; | |
590 | ||
591 | case mmMC_SEQ_RESERVE_M: | |
592 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); | |
593 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; | |
594 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; | |
595 | for (k = 0; k < table->num_entries; k++) { | |
596 | table->mc_reg_table_entry[k].mc_data[j] = | |
597 | (temp_reg & 0xffff0000) | | |
598 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
599 | } | |
600 | j++; | |
601 | PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
602 | "Invalid VramInfo table.", return -1); | |
603 | break; | |
604 | ||
605 | default: | |
606 | break; | |
607 | } | |
608 | ||
609 | } | |
610 | ||
611 | table->last = j; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | ||
617 | static int iceland_set_valid_flag(phw_iceland_mc_reg_table *table) | |
618 | { | |
619 | uint8_t i, j; | |
620 | for (i = 0; i < table->last; i++) { | |
621 | for (j = 1; j < table->num_entries; j++) { | |
622 | if (table->mc_reg_table_entry[j-1].mc_data[i] != | |
623 | table->mc_reg_table_entry[j].mc_data[i]) { | |
624 | table->validflag |= (1<<i); | |
625 | break; | |
626 | } | |
627 | } | |
628 | } | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) | |
634 | { | |
635 | int result; | |
636 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
637 | pp_atomctrl_mc_reg_table *table; | |
638 | phw_iceland_mc_reg_table *ni_table = &data->iceland_mc_reg_table; | |
639 | uint8_t module_index = iceland_get_memory_module_index(hwmgr); | |
640 | ||
641 | table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); | |
642 | ||
643 | if (NULL == table) | |
644 | return -ENOMEM; | |
645 | ||
646 | /* Program additional LP registers that are no longer programmed by VBIOS */ | |
647 | cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); | |
648 | cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); | |
649 | cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); | |
650 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); | |
651 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); | |
652 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); | |
653 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); | |
654 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); | |
655 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); | |
656 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); | |
657 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); | |
658 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); | |
659 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); | |
660 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); | |
661 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); | |
662 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); | |
663 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); | |
664 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); | |
665 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); | |
666 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); | |
667 | ||
668 | memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); | |
669 | ||
670 | result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); | |
671 | ||
672 | if (0 == result) | |
673 | result = iceland_copy_vbios_smc_reg_table(table, ni_table); | |
674 | ||
675 | if (0 == result) { | |
676 | iceland_set_s0_mc_reg_index(ni_table); | |
677 | result = iceland_set_mc_special_registers(hwmgr, ni_table); | |
678 | } | |
679 | ||
680 | if (0 == result) | |
681 | iceland_set_valid_flag(ni_table); | |
682 | ||
683 | kfree(table); | |
684 | return result; | |
685 | } | |
686 | ||
687 | /** | |
688 | * Programs static screed detection parameters | |
689 | * | |
690 | * @param hwmgr the address of the powerplay hardware manager. | |
691 | * @return always 0 | |
692 | */ | |
693 | int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) | |
694 | { | |
695 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
696 | ||
697 | /* Set static screen threshold unit*/ | |
698 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, | |
699 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, | |
700 | data->static_screen_threshold_unit); | |
701 | /* Set static screen threshold*/ | |
702 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, | |
703 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, | |
704 | data->static_screen_threshold); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /** | |
710 | * Setup display gap for glitch free memory clock switching. | |
711 | * | |
712 | * @param hwmgr the address of the powerplay hardware manager. | |
713 | * @return always 0 | |
714 | */ | |
715 | int iceland_enable_display_gap(struct pp_hwmgr *hwmgr) | |
716 | { | |
717 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, | |
718 | CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); | |
719 | ||
720 | display_gap = PHM_SET_FIELD(display_gap, | |
721 | CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE); | |
722 | ||
723 | display_gap = PHM_SET_FIELD(display_gap, | |
724 | CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); | |
725 | ||
726 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
727 | ixCG_DISPLAY_GAP_CNTL, display_gap); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
732 | /** | |
733 | * Programs activity state transition voting clients | |
734 | * | |
735 | * @param hwmgr the address of the powerplay hardware manager. | |
736 | * @return always 0 | |
737 | */ | |
738 | int iceland_program_voting_clients(struct pp_hwmgr *hwmgr) | |
739 | { | |
740 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
741 | ||
742 | /* Clear reset for voting clients before enabling DPM */ | |
743 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
744 | SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); | |
745 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
746 | SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); | |
747 | ||
748 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
749 | ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); | |
750 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
751 | ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); | |
752 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
753 | ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); | |
754 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
755 | ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); | |
756 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
757 | ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); | |
758 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
759 | ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); | |
760 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
761 | ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); | |
762 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
763 | ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | static int iceland_upload_firmware(struct pp_hwmgr *hwmgr) | |
769 | { | |
770 | int ret = 0; | |
771 | ||
772 | if (!iceland_is_smc_ram_running(hwmgr->smumgr)) | |
773 | ret = iceland_smu_upload_firmware_image(hwmgr->smumgr); | |
774 | ||
775 | return ret; | |
776 | } | |
777 | ||
778 | /** | |
779 | * Get the location of various tables inside the FW image. | |
780 | * | |
781 | * @param hwmgr the address of the powerplay hardware manager. | |
782 | * @return always 0 | |
783 | */ | |
784 | int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) | |
785 | { | |
786 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
787 | ||
788 | uint32_t tmp; | |
789 | int result; | |
790 | bool error = 0; | |
791 | ||
792 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
793 | SMU71_FIRMWARE_HEADER_LOCATION + | |
794 | offsetof(SMU71_Firmware_Header, DpmTable), | |
795 | &tmp, data->sram_end); | |
796 | ||
797 | if (0 == result) { | |
798 | data->dpm_table_start = tmp; | |
799 | } | |
800 | ||
801 | error |= (0 != result); | |
802 | ||
803 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
804 | SMU71_FIRMWARE_HEADER_LOCATION + | |
805 | offsetof(SMU71_Firmware_Header, SoftRegisters), | |
806 | &tmp, data->sram_end); | |
807 | ||
808 | if (0 == result) { | |
809 | data->soft_regs_start = tmp; | |
810 | } | |
811 | ||
812 | error |= (0 != result); | |
813 | ||
814 | ||
815 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
816 | SMU71_FIRMWARE_HEADER_LOCATION + | |
817 | offsetof(SMU71_Firmware_Header, mcRegisterTable), | |
818 | &tmp, data->sram_end); | |
819 | ||
820 | if (0 == result) { | |
821 | data->mc_reg_table_start = tmp; | |
822 | } | |
823 | ||
824 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
825 | SMU71_FIRMWARE_HEADER_LOCATION + | |
826 | offsetof(SMU71_Firmware_Header, FanTable), | |
827 | &tmp, data->sram_end); | |
828 | ||
829 | if (0 == result) { | |
830 | data->fan_table_start = tmp; | |
831 | } | |
832 | ||
833 | error |= (0 != result); | |
834 | ||
835 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
836 | SMU71_FIRMWARE_HEADER_LOCATION + | |
837 | offsetof(SMU71_Firmware_Header, mcArbDramTimingTable), | |
838 | &tmp, data->sram_end); | |
839 | ||
840 | if (0 == result) { | |
841 | data->arb_table_start = tmp; | |
842 | } | |
843 | ||
844 | error |= (0 != result); | |
845 | ||
846 | ||
847 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
848 | SMU71_FIRMWARE_HEADER_LOCATION + | |
849 | offsetof(SMU71_Firmware_Header, Version), | |
850 | &tmp, data->sram_end); | |
851 | ||
852 | if (0 == result) { | |
853 | hwmgr->microcode_version_info.SMC = tmp; | |
854 | } | |
855 | ||
856 | error |= (0 != result); | |
857 | ||
858 | result = iceland_read_smc_sram_dword(hwmgr->smumgr, | |
859 | SMU71_FIRMWARE_HEADER_LOCATION + | |
860 | offsetof(SMU71_Firmware_Header, UlvSettings), | |
861 | &tmp, data->sram_end); | |
862 | ||
863 | if (0 == result) { | |
864 | data->ulv_settings_start = tmp; | |
865 | } | |
866 | ||
867 | error |= (0 != result); | |
868 | ||
869 | return error ? 1 : 0; | |
870 | } | |
871 | ||
872 | /* | |
873 | * Copy one arb setting to another and then switch the active set. | |
874 | * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants. | |
875 | */ | |
876 | int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, | |
877 | uint32_t arbFreqSrc, uint32_t arbFreqDest) | |
878 | { | |
879 | uint32_t mc_arb_dram_timing; | |
880 | uint32_t mc_arb_dram_timing2; | |
881 | uint32_t burst_time; | |
882 | uint32_t mc_cg_config; | |
883 | ||
884 | switch (arbFreqSrc) { | |
885 | case MC_CG_ARB_FREQ_F0: | |
886 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); | |
887 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); | |
888 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); | |
889 | break; | |
890 | ||
891 | case MC_CG_ARB_FREQ_F1: | |
892 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); | |
893 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); | |
894 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); | |
895 | break; | |
896 | ||
897 | default: | |
898 | return -1; | |
899 | } | |
900 | ||
901 | switch (arbFreqDest) { | |
902 | case MC_CG_ARB_FREQ_F0: | |
903 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); | |
904 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); | |
905 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); | |
906 | break; | |
907 | ||
908 | case MC_CG_ARB_FREQ_F1: | |
909 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); | |
910 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); | |
911 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); | |
912 | break; | |
913 | ||
914 | default: | |
915 | return -1; | |
916 | } | |
917 | ||
918 | mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); | |
919 | mc_cg_config |= 0x0000000F; | |
920 | cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); | |
921 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest); | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | /** | |
927 | * Initial switch from ARB F0->F1 | |
928 | * | |
929 | * @param hwmgr the address of the powerplay hardware manager. | |
930 | * @return always 0 | |
931 | * This function is to be called from the SetPowerState table. | |
932 | */ | |
933 | int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) | |
934 | { | |
935 | return iceland_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); | |
936 | } | |
937 | ||
938 | /* ---------------------------------------- ULV related functions ----------------------------------------------------*/ | |
939 | ||
940 | ||
941 | static int iceland_reset_single_dpm_table( | |
942 | struct pp_hwmgr *hwmgr, | |
943 | struct iceland_single_dpm_table *dpm_table, | |
944 | uint32_t count) | |
945 | { | |
946 | uint32_t i; | |
947 | if (!(count <= MAX_REGULAR_DPM_NUMBER)) | |
948 | printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \ | |
949 | table entries to exceed max number! \n"); | |
950 | ||
951 | dpm_table->count = count; | |
952 | for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) { | |
953 | dpm_table->dpm_levels[i].enabled = 0; | |
954 | } | |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
959 | static void iceland_setup_pcie_table_entry( | |
960 | struct iceland_single_dpm_table *dpm_table, | |
961 | uint32_t index, uint32_t pcie_gen, | |
962 | uint32_t pcie_lanes) | |
963 | { | |
964 | dpm_table->dpm_levels[index].value = pcie_gen; | |
965 | dpm_table->dpm_levels[index].param1 = pcie_lanes; | |
966 | dpm_table->dpm_levels[index].enabled = 1; | |
967 | } | |
968 | ||
969 | /* | |
970 | * Set up the PCIe DPM table as follows: | |
971 | * | |
972 | * A = Performance State, Max, Gen Speed | |
973 | * C = Performance State, Min, Gen Speed | |
974 | * 1 = Performance State, Max, Lane # | |
975 | * 3 = Performance State, Min, Lane # | |
976 | * | |
977 | * B = Power Saving State, Max, Gen Speed | |
978 | * D = Power Saving State, Min, Gen Speed | |
979 | * 2 = Power Saving State, Max, Lane # | |
980 | * 4 = Power Saving State, Min, Lane # | |
981 | * | |
982 | * | |
983 | * DPM Index Gen Speed Lane # | |
984 | * 5 A 1 | |
985 | * 4 B 2 | |
986 | * 3 C 1 | |
987 | * 2 D 2 | |
988 | * 1 C 3 | |
989 | * 0 D 4 | |
990 | * | |
991 | */ | |
992 | static int iceland_setup_default_pcie_tables(struct pp_hwmgr *hwmgr) | |
993 | { | |
994 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
995 | ||
996 | PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || | |
997 | data->use_pcie_power_saving_levels), | |
998 | "No pcie performance levels!", return -EINVAL); | |
999 | ||
1000 | if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) { | |
1001 | data->pcie_gen_power_saving = data->pcie_gen_performance; | |
1002 | data->pcie_lane_power_saving = data->pcie_lane_performance; | |
1003 | } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) { | |
1004 | data->pcie_gen_performance = data->pcie_gen_power_saving; | |
1005 | data->pcie_lane_performance = data->pcie_lane_power_saving; | |
1006 | } | |
1007 | ||
1008 | iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU71_MAX_LEVELS_LINK); | |
1009 | ||
1010 | /* Hardcode Pcie Table */ | |
1011 | iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, | |
1012 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), | |
1013 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
1014 | iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, | |
1015 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), | |
1016 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
1017 | iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, | |
1018 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
1019 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
1020 | iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, | |
1021 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
1022 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
1023 | iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, | |
1024 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
1025 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
1026 | iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, | |
1027 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
1028 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
1029 | data->dpm_table.pcie_speed_table.count = 6; | |
1030 | ||
1031 | return 0; | |
1032 | ||
1033 | } | |
1034 | ||
1035 | ||
1036 | /* | |
1037 | * This function is to initalize all DPM state tables for SMU7 based on the dependency table. | |
1038 | * Dynamic state patching function will then trim these state tables to the allowed range based | |
1039 | * on the power policy or external client requests, such as UVD request, etc. | |
1040 | */ | |
1041 | static int iceland_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) | |
1042 | { | |
1043 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1044 | uint32_t i; | |
1045 | ||
1046 | struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table = | |
1047 | hwmgr->dyn_state.vddc_dependency_on_sclk; | |
1048 | struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table = | |
1049 | hwmgr->dyn_state.vddc_dependency_on_mclk; | |
1050 | struct phm_cac_leakage_table *std_voltage_table = | |
1051 | hwmgr->dyn_state.cac_leakage_table; | |
1052 | ||
1053 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, | |
1054 | "SCLK dependency table is missing. This table is mandatory", return -1); | |
1055 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, | |
1056 | "SCLK dependency table has to have is missing. This table is mandatory", return -1); | |
1057 | ||
1058 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, | |
1059 | "MCLK dependency table is missing. This table is mandatory", return -1); | |
1060 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, | |
1061 | "VMCLK dependency table has to have is missing. This table is mandatory", return -1); | |
1062 | ||
1063 | /* clear the state table to reset everything to default */ | |
1064 | memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); | |
1065 | iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU71_MAX_LEVELS_GRAPHICS); | |
1066 | iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU71_MAX_LEVELS_MEMORY); | |
1067 | iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.vddc_table, SMU71_MAX_LEVELS_VDDC); | |
1068 | iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.vdd_ci_table, SMU71_MAX_LEVELS_VDDCI); | |
1069 | iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.mvdd_table, SMU71_MAX_LEVELS_MVDD); | |
1070 | ||
1071 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, | |
1072 | "SCLK dependency table is missing. This table is mandatory", return -1); | |
1073 | /* Initialize Sclk DPM table based on allow Sclk values*/ | |
1074 | data->dpm_table.sclk_table.count = 0; | |
1075 | ||
1076 | for (i = 0; i < allowed_vdd_sclk_table->count; i++) { | |
1077 | if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != | |
1078 | allowed_vdd_sclk_table->entries[i].clk) { | |
1079 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = | |
1080 | allowed_vdd_sclk_table->entries[i].clk; | |
1081 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */ | |
1082 | data->dpm_table.sclk_table.count++; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, | |
1087 | "MCLK dependency table is missing. This table is mandatory", return -1); | |
1088 | /* Initialize Mclk DPM table based on allow Mclk values */ | |
1089 | data->dpm_table.mclk_table.count = 0; | |
1090 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { | |
1091 | if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != | |
1092 | allowed_vdd_mclk_table->entries[i].clk) { | |
1093 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = | |
1094 | allowed_vdd_mclk_table->entries[i].clk; | |
1095 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */ | |
1096 | data->dpm_table.mclk_table.count++; | |
1097 | } | |
1098 | } | |
1099 | ||
1100 | /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ | |
1101 | for (i = 0; i < allowed_vdd_sclk_table->count; i++) { | |
1102 | data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; | |
1103 | data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; | |
1104 | /* param1 is for corresponding std voltage */ | |
1105 | data->dpm_table.vddc_table.dpm_levels[i].enabled = 1; | |
1106 | } | |
1107 | ||
1108 | data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; | |
1109 | allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; | |
1110 | ||
1111 | if (NULL != allowed_vdd_mclk_table) { | |
1112 | /* Initialize Vddci DPM table based on allow Mclk values */ | |
1113 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { | |
1114 | data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; | |
1115 | data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1; | |
1116 | } | |
1117 | data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count; | |
1118 | } | |
1119 | ||
1120 | allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; | |
1121 | ||
1122 | if (NULL != allowed_vdd_mclk_table) { | |
1123 | /* | |
1124 | * Initialize MVDD DPM table based on allow Mclk | |
1125 | * values | |
1126 | */ | |
1127 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { | |
1128 | data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; | |
1129 | data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1; | |
1130 | } | |
1131 | data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; | |
1132 | } | |
1133 | ||
1134 | /* setup PCIE gen speed levels*/ | |
1135 | iceland_setup_default_pcie_tables(hwmgr); | |
1136 | ||
1137 | /* save a copy of the default DPM table*/ | |
1138 | memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct iceland_dpm_table)); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | /** | |
1144 | * @brief PhwIceland_GetVoltageOrder | |
1145 | * Returns index of requested voltage record in lookup(table) | |
1146 | * @param hwmgr - pointer to hardware manager | |
1147 | * @param lookutab - lookup list to search in | |
1148 | * @param voltage - voltage to look for | |
1149 | * @return 0 on success | |
1150 | */ | |
1151 | uint8_t iceland_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table, | |
1152 | uint16_t voltage) | |
1153 | { | |
1154 | uint8_t count = (uint8_t) (look_up_table->count); | |
1155 | uint8_t i; | |
1156 | ||
1157 | PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;); | |
1158 | PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;); | |
1159 | ||
1160 | for (i = 0; i < count; i++) { | |
1161 | /* find first voltage equal or bigger than requested */ | |
1162 | if (look_up_table->entries[i].us_vdd >= voltage) | |
1163 | return i; | |
1164 | } | |
1165 | ||
1166 | /* voltage is bigger than max voltage in the table */ | |
1167 | return i-1; | |
1168 | } | |
1169 | ||
1170 | ||
1171 | static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr, | |
1172 | pp_atomctrl_voltage_table_entry *tab, uint16_t *hi, | |
1173 | uint16_t *lo) | |
1174 | { | |
1175 | uint16_t v_index; | |
1176 | bool vol_found = false; | |
1177 | *hi = tab->value * VOLTAGE_SCALE; | |
1178 | *lo = tab->value * VOLTAGE_SCALE; | |
1179 | ||
1180 | /* SCLK/VDDC Dependency Table has to exist. */ | |
1181 | PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, | |
1182 | "The SCLK/VDDC Dependency Table does not exist.\n", | |
1183 | return -EINVAL); | |
1184 | ||
1185 | if (NULL == hwmgr->dyn_state.cac_leakage_table) { | |
1186 | pr_warning("CAC Leakage Table does not exist, using vddc.\n"); | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | /* | |
1191 | * Since voltage in the sclk/vddc dependency table is not | |
1192 | * necessarily in ascending order because of ELB voltage | |
1193 | * patching, loop through entire list to find exact voltage. | |
1194 | */ | |
1195 | for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { | |
1196 | if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { | |
1197 | vol_found = true; | |
1198 | if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { | |
1199 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; | |
1200 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); | |
1201 | } else { | |
1202 | pr_warning("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n"); | |
1203 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; | |
1204 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); | |
1205 | } | |
1206 | break; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | /* | |
1211 | * If voltage is not found in the first pass, loop again to | |
1212 | * find the best match, equal or higher value. | |
1213 | */ | |
1214 | if (!vol_found) { | |
1215 | for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { | |
1216 | if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { | |
1217 | vol_found = true; | |
1218 | if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { | |
1219 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; | |
1220 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; | |
1221 | } else { | |
1222 | pr_warning("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table."); | |
1223 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; | |
1224 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); | |
1225 | } | |
1226 | break; | |
1227 | } | |
1228 | } | |
1229 | ||
1230 | if (!vol_found) | |
1231 | pr_warning("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n"); | |
1232 | } | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr, | |
1238 | pp_atomctrl_voltage_table_entry *tab, | |
1239 | SMU71_Discrete_VoltageLevel *smc_voltage_tab) { | |
1240 | int result; | |
1241 | ||
1242 | ||
1243 | result = iceland_get_std_voltage_value_sidd(hwmgr, tab, | |
1244 | &smc_voltage_tab->StdVoltageHiSidd, | |
1245 | &smc_voltage_tab->StdVoltageLoSidd); | |
1246 | if (0 != result) { | |
1247 | smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE; | |
1248 | smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE; | |
1249 | } | |
1250 | ||
1251 | smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE); | |
1252 | CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd); | |
1253 | CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | /** | |
1259 | * Vddc table preparation for SMC. | |
1260 | * | |
1261 | * @param hwmgr the address of the hardware manager | |
1262 | * @param table the SMC DPM table structure to be populated | |
1263 | * @return always 0 | |
1264 | */ | |
1265 | static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, | |
1266 | SMU71_Discrete_DpmTable *table) | |
1267 | { | |
1268 | unsigned int count; | |
1269 | int result; | |
1270 | ||
1271 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1272 | ||
1273 | table->VddcLevelCount = data->vddc_voltage_table.count; | |
1274 | for (count = 0; count < table->VddcLevelCount; count++) { | |
1275 | result = iceland_populate_smc_voltage_table(hwmgr, | |
1276 | &data->vddc_voltage_table.entries[count], | |
1277 | &table->VddcLevel[count]); | |
1278 | PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); | |
1279 | ||
1280 | /* GPIO voltage control */ | |
1281 | if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) | |
1282 | table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low; | |
1283 | else if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) | |
1284 | table->VddcLevel[count].Smio = 0; | |
1285 | } | |
1286 | ||
1287 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | /** | |
1293 | * Vddci table preparation for SMC. | |
1294 | * | |
1295 | * @param *hwmgr The address of the hardware manager. | |
1296 | * @param *table The SMC DPM table structure to be populated. | |
1297 | * @return 0 | |
1298 | */ | |
1299 | static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, | |
1300 | SMU71_Discrete_DpmTable *table) | |
1301 | { | |
1302 | int result; | |
1303 | uint32_t count; | |
1304 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1305 | ||
1306 | table->VddciLevelCount = data->vddci_voltage_table.count; | |
1307 | for (count = 0; count < table->VddciLevelCount; count++) { | |
1308 | result = iceland_populate_smc_voltage_table(hwmgr, | |
1309 | &data->vddci_voltage_table.entries[count], | |
1310 | &table->VddciLevel[count]); | |
1311 | PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDCI voltage table", return -EINVAL); | |
1312 | ||
1313 | /* GPIO voltage control */ | |
1314 | if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) | |
1315 | table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low; | |
1316 | else | |
1317 | table->VddciLevel[count].Smio = 0; | |
1318 | } | |
1319 | ||
1320 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | /** | |
1326 | * Mvdd table preparation for SMC. | |
1327 | * | |
1328 | * @param *hwmgr The address of the hardware manager. | |
1329 | * @param *table The SMC DPM table structure to be populated. | |
1330 | * @return 0 | |
1331 | */ | |
1332 | static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, | |
1333 | SMU71_Discrete_DpmTable *table) | |
1334 | { | |
1335 | int result; | |
1336 | uint32_t count; | |
1337 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1338 | ||
1339 | table->MvddLevelCount = data->mvdd_voltage_table.count; | |
1340 | for (count = 0; count < table->MvddLevelCount; count++) { | |
1341 | result = iceland_populate_smc_voltage_table(hwmgr, | |
1342 | &data->mvdd_voltage_table.entries[count], | |
1343 | &table->MvddLevel[count]); | |
1344 | PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDCI voltage table", return -EINVAL); | |
1345 | ||
1346 | /* GPIO voltage control */ | |
1347 | if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) | |
1348 | table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low; | |
1349 | else | |
1350 | table->MvddLevel[count].Smio = 0; | |
1351 | } | |
1352 | ||
1353 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | /** | |
1359 | * Convert a voltage value in mv unit to VID number required by SMU firmware | |
1360 | */ | |
1361 | static uint8_t convert_to_vid(uint16_t vddc) | |
1362 | { | |
1363 | return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); | |
1364 | } | |
1365 | ||
1366 | int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) | |
1367 | { | |
1368 | int i; | |
1369 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
1370 | uint8_t * hi_vid = data->power_tune_table.BapmVddCVidHiSidd; | |
1371 | uint8_t * lo_vid = data->power_tune_table.BapmVddCVidLoSidd; | |
1372 | ||
1373 | PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, | |
1374 | "The CAC Leakage table does not exist!", return -EINVAL); | |
1375 | PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, | |
1376 | "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL); | |
1377 | PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, | |
1378 | "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL); | |
1379 | ||
1380 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) { | |
1381 | for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { | |
1382 | lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); | |
1383 | hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); | |
1384 | } | |
1385 | } else { | |
1386 | PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL); | |
1387 | } | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
1392 | int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) | |
1393 | { | |
1394 | int i; | |
1395 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
1396 | uint8_t *vid = data->power_tune_table.VddCVid; | |
1397 | ||
1398 | PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, | |
1399 | "There should never be more than 8 entries for VddcVid!!!", | |
1400 | return -EINVAL); | |
1401 | ||
1402 | for (i = 0; i < (int)data->vddc_voltage_table.count; i++) { | |
1403 | vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value); | |
1404 | } | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | /** | |
1410 | * Preparation of voltage tables for SMC. | |
1411 | * | |
1412 | * @param hwmgr the address of the hardware manager | |
1413 | * @param table the SMC DPM table structure to be populated | |
1414 | * @return always 0 | |
1415 | */ | |
1416 | ||
1417 | int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, | |
1418 | SMU71_Discrete_DpmTable *table) | |
1419 | { | |
1420 | int result; | |
1421 | ||
1422 | result = iceland_populate_smc_vddc_table(hwmgr, table); | |
1423 | PP_ASSERT_WITH_CODE(0 == result, | |
1424 | "can not populate VDDC voltage table to SMC", return -1); | |
1425 | ||
1426 | result = iceland_populate_smc_vdd_ci_table(hwmgr, table); | |
1427 | PP_ASSERT_WITH_CODE(0 == result, | |
1428 | "can not populate VDDCI voltage table to SMC", return -1); | |
1429 | ||
1430 | result = iceland_populate_smc_mvdd_table(hwmgr, table); | |
1431 | PP_ASSERT_WITH_CODE(0 == result, | |
1432 | "can not populate MVDD voltage table to SMC", return -1); | |
1433 | ||
1434 | return 0; | |
1435 | } | |
1436 | ||
1437 | ||
1438 | /** | |
1439 | * Re-generate the DPM level mask value | |
1440 | * @param hwmgr the address of the hardware manager | |
1441 | */ | |
1442 | static uint32_t iceland_get_dpm_level_enable_mask_value( | |
1443 | struct iceland_single_dpm_table * dpm_table) | |
1444 | { | |
1445 | uint32_t i; | |
1446 | uint32_t mask_value = 0; | |
1447 | ||
1448 | for (i = dpm_table->count; i > 0; i--) { | |
1449 | mask_value = mask_value << 1; | |
1450 | ||
1451 | if (dpm_table->dpm_levels[i-1].enabled) | |
1452 | mask_value |= 0x1; | |
1453 | else | |
1454 | mask_value &= 0xFFFFFFFE; | |
1455 | } | |
1456 | return mask_value; | |
1457 | } | |
1458 | ||
1459 | int iceland_populate_memory_timing_parameters( | |
1460 | struct pp_hwmgr *hwmgr, | |
1461 | uint32_t engine_clock, | |
1462 | uint32_t memory_clock, | |
1463 | struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs | |
1464 | ) | |
1465 | { | |
1466 | uint32_t dramTiming; | |
1467 | uint32_t dramTiming2; | |
1468 | uint32_t burstTime; | |
1469 | int result; | |
1470 | ||
1471 | result = atomctrl_set_engine_dram_timings_rv770(hwmgr, | |
1472 | engine_clock, memory_clock); | |
1473 | ||
1474 | PP_ASSERT_WITH_CODE(result == 0, | |
1475 | "Error calling VBIOS to set DRAM_TIMING.", return result); | |
1476 | ||
1477 | dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); | |
1478 | dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); | |
1479 | burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); | |
1480 | ||
1481 | arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); | |
1482 | arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); | |
1483 | arb_regs->McArbBurstTime = (uint8_t)burstTime; | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | /** | |
1489 | * Setup parameters for the MC ARB. | |
1490 | * | |
1491 | * @param hwmgr the address of the powerplay hardware manager. | |
1492 | * @return always 0 | |
1493 | * This function is to be called from the SetPowerState table. | |
1494 | */ | |
1495 | int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) | |
1496 | { | |
1497 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1498 | int result = 0; | |
1499 | SMU71_Discrete_MCArbDramTimingTable arb_regs; | |
1500 | uint32_t i, j; | |
1501 | ||
1502 | memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable)); | |
1503 | ||
1504 | for (i = 0; i < data->dpm_table.sclk_table.count; i++) { | |
1505 | for (j = 0; j < data->dpm_table.mclk_table.count; j++) { | |
1506 | result = iceland_populate_memory_timing_parameters | |
1507 | (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, | |
1508 | data->dpm_table.mclk_table.dpm_levels[j].value, | |
1509 | &arb_regs.entries[i][j]); | |
1510 | ||
1511 | if (0 != result) { | |
1512 | break; | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | if (0 == result) { | |
1518 | result = iceland_copy_bytes_to_smc( | |
1519 | hwmgr->smumgr, | |
1520 | data->arb_table_start, | |
1521 | (uint8_t *)&arb_regs, | |
1522 | sizeof(SMU71_Discrete_MCArbDramTimingTable), | |
1523 | data->sram_end | |
1524 | ); | |
1525 | } | |
1526 | ||
1527 | return result; | |
1528 | } | |
1529 | ||
1530 | static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table) | |
1531 | { | |
1532 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1533 | struct iceland_dpm_table *dpm_table = &data->dpm_table; | |
1534 | uint32_t i; | |
1535 | ||
1536 | /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ | |
1537 | for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { | |
1538 | table->LinkLevel[i].PcieGenSpeed = | |
1539 | (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; | |
1540 | table->LinkLevel[i].PcieLaneCount = | |
1541 | (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); | |
1542 | table->LinkLevel[i].EnabledForActivity = | |
1543 | 1; | |
1544 | table->LinkLevel[i].SPC = | |
1545 | (uint8_t)(data->pcie_spc_cap & 0xff); | |
1546 | table->LinkLevel[i].DownThreshold = | |
1547 | PP_HOST_TO_SMC_UL(5); | |
1548 | table->LinkLevel[i].UpThreshold = | |
1549 | PP_HOST_TO_SMC_UL(30); | |
1550 | } | |
1551 | ||
1552 | data->smc_state_table.LinkLevelCount = | |
1553 | (uint8_t)dpm_table->pcie_speed_table.count; | |
1554 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = | |
1555 | iceland_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, | |
1561 | SMU71_Discrete_DpmTable *table) | |
1562 | { | |
1563 | return 0; | |
1564 | } | |
1565 | ||
1566 | uint8_t iceland_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, | |
1567 | uint32_t voltage) | |
1568 | { | |
1569 | uint8_t count = (uint8_t) (voltage_table->count); | |
1570 | uint8_t i = 0; | |
1571 | ||
1572 | PP_ASSERT_WITH_CODE((NULL != voltage_table), | |
1573 | "Voltage Table empty.", return 0;); | |
1574 | PP_ASSERT_WITH_CODE((0 != count), | |
1575 | "Voltage Table empty.", return 0;); | |
1576 | ||
1577 | for (i = 0; i < count; i++) { | |
1578 | /* find first voltage bigger than requested */ | |
1579 | if (voltage_table->entries[i].value >= voltage) | |
1580 | return i; | |
1581 | } | |
1582 | ||
1583 | /* voltage is bigger than max voltage in the table */ | |
1584 | return i - 1; | |
1585 | } | |
1586 | ||
1587 | static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr, | |
1588 | SMU71_Discrete_DpmTable *table) | |
1589 | { | |
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr, | |
1594 | SMU71_Discrete_DpmTable *table) | |
1595 | { | |
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr, | |
1600 | SMU71_Discrete_DpmTable *table) | |
1601 | { | |
1602 | return 0; | |
1603 | } | |
1604 | ||
1605 | ||
1606 | static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr, | |
1607 | SMU71_Discrete_DpmTable *tab) | |
1608 | { | |
1609 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1610 | ||
1611 | if(ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) | |
1612 | tab->SVI2Enable |= VDDC_ON_SVI2; | |
1613 | ||
1614 | if(ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) | |
1615 | tab->SVI2Enable |= VDDCI_ON_SVI2; | |
1616 | else | |
1617 | tab->MergedVddci = 1; | |
1618 | ||
1619 | if(ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) | |
1620 | tab->SVI2Enable |= MVDD_ON_SVI2; | |
1621 | ||
1622 | PP_ASSERT_WITH_CODE( tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) && | |
1623 | (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL); | |
1624 | ||
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, | |
1629 | struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table, | |
1630 | uint32_t clock, uint32_t *vol) | |
1631 | { | |
1632 | uint32_t i = 0; | |
1633 | ||
1634 | /* clock - voltage dependency table is empty table */ | |
1635 | if (allowed_clock_voltage_table->count == 0) | |
1636 | return -EINVAL; | |
1637 | ||
1638 | for (i = 0; i < allowed_clock_voltage_table->count; i++) { | |
1639 | /* find first sclk bigger than request */ | |
1640 | if (allowed_clock_voltage_table->entries[i].clk >= clock) { | |
1641 | *vol = allowed_clock_voltage_table->entries[i].v; | |
1642 | return 0; | |
1643 | } | |
1644 | } | |
1645 | ||
1646 | /* sclk is bigger than max sclk in the dependence table */ | |
1647 | *vol = allowed_clock_voltage_table->entries[i - 1].v; | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
1652 | static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, | |
1653 | bool strobe_mode) | |
1654 | { | |
1655 | uint8_t mc_para_index; | |
1656 | ||
1657 | if (strobe_mode) { | |
1658 | if (memory_clock < 12500) { | |
1659 | mc_para_index = 0x00; | |
1660 | } else if (memory_clock > 47500) { | |
1661 | mc_para_index = 0x0f; | |
1662 | } else { | |
1663 | mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); | |
1664 | } | |
1665 | } else { | |
1666 | if (memory_clock < 65000) { | |
1667 | mc_para_index = 0x00; | |
1668 | } else if (memory_clock > 135000) { | |
1669 | mc_para_index = 0x0f; | |
1670 | } else { | |
1671 | mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); | |
1672 | } | |
1673 | } | |
1674 | ||
1675 | return mc_para_index; | |
1676 | } | |
1677 | ||
1678 | static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) | |
1679 | { | |
1680 | uint8_t mc_para_index; | |
1681 | ||
1682 | if (memory_clock < 10000) { | |
1683 | mc_para_index = 0; | |
1684 | } else if (memory_clock >= 80000) { | |
1685 | mc_para_index = 0x0f; | |
1686 | } else { | |
1687 | mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); | |
1688 | } | |
1689 | ||
1690 | return mc_para_index; | |
1691 | } | |
1692 | ||
1693 | static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, | |
1694 | uint32_t sclk, uint32_t *p_shed) | |
1695 | { | |
1696 | unsigned int i; | |
1697 | ||
1698 | /* use the minimum phase shedding */ | |
1699 | *p_shed = 1; | |
1700 | ||
1701 | /* | |
1702 | * PPGen ensures the phase shedding limits table is sorted | |
1703 | * from lowest voltage/sclk/mclk to highest voltage/sclk/mclk. | |
1704 | * VBIOS ensures the phase shedding masks table is sorted from | |
1705 | * least phases enabled (phase shedding on) to most phases | |
1706 | * enabled (phase shedding off). | |
1707 | */ | |
1708 | for (i = 0; i < pl->count; i++) { | |
1709 | if (sclk < pl->entries[i].Sclk) { | |
1710 | /* Enable phase shedding */ | |
1711 | *p_shed = i; | |
1712 | break; | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | return 0; | |
1717 | } | |
1718 | ||
1719 | static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, | |
1720 | uint32_t memory_clock, uint32_t *p_shed) | |
1721 | { | |
1722 | unsigned int i; | |
1723 | ||
1724 | /* use the minimum phase shedding */ | |
1725 | *p_shed = 1; | |
1726 | ||
1727 | /* | |
1728 | * PPGen ensures the phase shedding limits table is sorted | |
1729 | * from lowest voltage/sclk/mclk to highest voltage/sclk/mclk. | |
1730 | * VBIOS ensures the phase shedding masks table is sorted from | |
1731 | * least phases enabled (phase shedding on) to most phases | |
1732 | * enabled (phase shedding off). | |
1733 | */ | |
1734 | for (i = 0; i < pl->count; i++) { | |
1735 | if (memory_clock < pl->entries[i].Mclk) { | |
1736 | /* Enable phase shedding */ | |
1737 | *p_shed = i; | |
1738 | break; | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | return 0; | |
1743 | } | |
1744 | ||
1745 | /** | |
1746 | * Populates the SMC MCLK structure using the provided memory clock | |
1747 | * | |
1748 | * @param hwmgr the address of the hardware manager | |
1749 | * @param memory_clock the memory clock to use to populate the structure | |
1750 | * @param sclk the SMC SCLK structure to be populated | |
1751 | */ | |
1752 | static int iceland_calculate_mclk_params( | |
1753 | struct pp_hwmgr *hwmgr, | |
1754 | uint32_t memory_clock, | |
1755 | SMU71_Discrete_MemoryLevel *mclk, | |
1756 | bool strobe_mode, | |
1757 | bool dllStateOn | |
1758 | ) | |
1759 | { | |
1760 | const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1761 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; | |
1762 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; | |
1763 | uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; | |
1764 | uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; | |
1765 | uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; | |
1766 | uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; | |
1767 | uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; | |
1768 | uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; | |
1769 | uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; | |
1770 | ||
1771 | pp_atomctrl_memory_clock_param mpll_param; | |
1772 | int result; | |
1773 | ||
1774 | result = atomctrl_get_memory_pll_dividers_si(hwmgr, | |
1775 | memory_clock, &mpll_param, strobe_mode); | |
1776 | PP_ASSERT_WITH_CODE(0 == result, | |
1777 | "Error retrieving Memory Clock Parameters from VBIOS.", return result); | |
1778 | ||
1779 | /* MPLL_FUNC_CNTL setup*/ | |
1780 | mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); | |
1781 | ||
1782 | /* MPLL_FUNC_CNTL_1 setup*/ | |
1783 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1784 | MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); | |
1785 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1786 | MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); | |
1787 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1788 | MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); | |
1789 | ||
1790 | /* MPLL_AD_FUNC_CNTL setup*/ | |
1791 | mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, | |
1792 | MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); | |
1793 | ||
1794 | if (data->is_memory_GDDR5) { | |
1795 | /* MPLL_DQ_FUNC_CNTL setup*/ | |
1796 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, | |
1797 | MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); | |
1798 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, | |
1799 | MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); | |
1800 | } | |
1801 | ||
1802 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
1803 | PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { | |
1804 | /* | |
1805 | ************************************ | |
1806 | Fref = Reference Frequency | |
1807 | NF = Feedback divider ratio | |
1808 | NR = Reference divider ratio | |
1809 | Fnom = Nominal VCO output frequency = Fref * NF / NR | |
1810 | Fs = Spreading Rate | |
1811 | D = Percentage down-spread / 2 | |
1812 | Fint = Reference input frequency to PFD = Fref / NR | |
1813 | NS = Spreading rate divider ratio = int(Fint / (2 * Fs)) | |
1814 | CLKS = NS - 1 = ISS_STEP_NUM[11:0] | |
1815 | NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2) | |
1816 | CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] | |
1817 | ************************************* | |
1818 | */ | |
1819 | pp_atomctrl_internal_ss_info ss_info; | |
1820 | uint32_t freq_nom; | |
1821 | uint32_t tmp; | |
1822 | uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); | |
1823 | ||
1824 | /* for GDDR5 for all modes and DDR3 */ | |
1825 | if (1 == mpll_param.qdr) | |
1826 | freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); | |
1827 | else | |
1828 | freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); | |
1829 | ||
1830 | /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ | |
1831 | tmp = (freq_nom / reference_clock); | |
1832 | tmp = tmp * tmp; | |
1833 | ||
1834 | if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { | |
1835 | /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */ | |
1836 | /* ss.Info.speed_spectrum_rate -- in unit of khz */ | |
1837 | /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */ | |
1838 | /* = reference_clock * 5 / speed_spectrum_rate */ | |
1839 | uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; | |
1840 | ||
1841 | /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */ | |
1842 | /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */ | |
1843 | uint32_t clkv = | |
1844 | (uint32_t)((((131 * ss_info.speed_spectrum_percentage * | |
1845 | ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); | |
1846 | ||
1847 | mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); | |
1848 | mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); | |
1849 | } | |
1850 | } | |
1851 | ||
1852 | /* MCLK_PWRMGT_CNTL setup */ | |
1853 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1854 | MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); | |
1855 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1856 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); | |
1857 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1858 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); | |
1859 | ||
1860 | ||
1861 | /* Save the result data to outpupt memory level structure */ | |
1862 | mclk->MclkFrequency = memory_clock; | |
1863 | mclk->MpllFuncCntl = mpll_func_cntl; | |
1864 | mclk->MpllFuncCntl_1 = mpll_func_cntl_1; | |
1865 | mclk->MpllFuncCntl_2 = mpll_func_cntl_2; | |
1866 | mclk->MpllAdFuncCntl = mpll_ad_func_cntl; | |
1867 | mclk->MpllDqFuncCntl = mpll_dq_func_cntl; | |
1868 | mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; | |
1869 | mclk->DllCntl = dll_cntl; | |
1870 | mclk->MpllSs1 = mpll_ss1; | |
1871 | mclk->MpllSs2 = mpll_ss2; | |
1872 | ||
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | static int iceland_populate_single_memory_level( | |
1877 | struct pp_hwmgr *hwmgr, | |
1878 | uint32_t memory_clock, | |
1879 | SMU71_Discrete_MemoryLevel *memory_level | |
1880 | ) | |
1881 | { | |
1882 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
1883 | int result = 0; | |
1884 | bool dllStateOn; | |
1885 | struct cgs_display_info info = {0}; | |
1886 | ||
1887 | ||
1888 | if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) { | |
1889 | result = iceland_get_dependecy_volt_by_clk(hwmgr, | |
1890 | hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); | |
1891 | PP_ASSERT_WITH_CODE((0 == result), | |
1892 | "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); | |
1893 | } | |
1894 | ||
1895 | if (data->vdd_ci_control == ICELAND_VOLTAGE_CONTROL_NONE) { | |
1896 | memory_level->MinVddci = memory_level->MinVddc; | |
1897 | } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { | |
1898 | result = iceland_get_dependecy_volt_by_clk(hwmgr, | |
1899 | hwmgr->dyn_state.vddci_dependency_on_mclk, | |
1900 | memory_clock, | |
1901 | &memory_level->MinVddci); | |
1902 | PP_ASSERT_WITH_CODE((0 == result), | |
1903 | "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result); | |
1904 | } | |
1905 | ||
1906 | if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { | |
1907 | result = iceland_get_dependecy_volt_by_clk(hwmgr, | |
1908 | hwmgr->dyn_state.mvdd_dependency_on_mclk, memory_clock, &memory_level->MinMvdd); | |
1909 | PP_ASSERT_WITH_CODE((0 == result), | |
1910 | "can not find MinMVDD voltage value from memory MVDD voltage dependency table", return result); | |
1911 | } | |
1912 | ||
1913 | memory_level->MinVddcPhases = 1; | |
1914 | ||
1915 | if (data->vddc_phase_shed_control) { | |
1916 | iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, | |
1917 | memory_clock, &memory_level->MinVddcPhases); | |
1918 | } | |
1919 | ||
1920 | memory_level->EnabledForThrottle = 1; | |
1921 | memory_level->EnabledForActivity = 1; | |
1922 | memory_level->UpHyst = 0; | |
1923 | memory_level->DownHyst = 100; | |
1924 | memory_level->VoltageDownHyst = 0; | |
1925 | ||
1926 | /* Indicates maximum activity level for this performance level.*/ | |
1927 | memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target; | |
1928 | memory_level->StutterEnable = 0; | |
1929 | memory_level->StrobeEnable = 0; | |
1930 | memory_level->EdcReadEnable = 0; | |
1931 | memory_level->EdcWriteEnable = 0; | |
1932 | memory_level->RttEnable = 0; | |
1933 | ||
1934 | /* default set to low watermark. Highest level will be set to high later.*/ | |
1935 | memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
1936 | ||
1937 | cgs_get_active_displays_info(hwmgr->device, &info); | |
1938 | data->display_timing.num_existing_displays = info.display_count; | |
1939 | ||
1940 | //if ((data->mclk_stutter_mode_threshold != 0) && | |
1941 | // (memory_clock <= data->mclk_stutter_mode_threshold) && | |
1942 | // (data->is_uvd_enabled == 0) | |
1943 | // && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) | |
1944 | // && (data->display_timing.num_existing_displays <= 2) | |
1945 | // && (data->display_timing.num_existing_displays != 0)) | |
1946 | // memory_level->StutterEnable = 1; | |
1947 | ||
1948 | /* decide strobe mode*/ | |
1949 | memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) && | |
1950 | (memory_clock <= data->mclk_strobe_mode_threshold); | |
1951 | ||
1952 | /* decide EDC mode and memory clock ratio*/ | |
1953 | if (data->is_memory_GDDR5) { | |
1954 | memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock, | |
1955 | memory_level->StrobeEnable); | |
1956 | ||
1957 | if ((data->mclk_edc_enable_threshold != 0) && | |
1958 | (memory_clock > data->mclk_edc_enable_threshold)) { | |
1959 | memory_level->EdcReadEnable = 1; | |
1960 | } | |
1961 | ||
1962 | if ((data->mclk_edc_wr_enable_threshold != 0) && | |
1963 | (memory_clock > data->mclk_edc_wr_enable_threshold)) { | |
1964 | memory_level->EdcWriteEnable = 1; | |
1965 | } | |
1966 | ||
1967 | if (memory_level->StrobeEnable) { | |
1968 | if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >= | |
1969 | ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) { | |
1970 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; | |
1971 | } else { | |
1972 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; | |
1973 | } | |
1974 | ||
1975 | } else { | |
1976 | dllStateOn = data->dll_defaule_on; | |
1977 | } | |
1978 | } else { | |
1979 | memory_level->StrobeRatio = | |
1980 | iceland_get_ddr3_mclk_frequency_ratio(memory_clock); | |
1981 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; | |
1982 | } | |
1983 | ||
1984 | result = iceland_calculate_mclk_params(hwmgr, | |
1985 | memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn); | |
1986 | ||
1987 | if (0 == result) { | |
1988 | memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); | |
1989 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); | |
1990 | memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); | |
1991 | memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); | |
1992 | /* MCLK frequency in units of 10KHz*/ | |
1993 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); | |
1994 | /* Indicates maximum activity level for this performance level.*/ | |
1995 | CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); | |
1996 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); | |
1997 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); | |
1998 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); | |
1999 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); | |
2000 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); | |
2001 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); | |
2002 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); | |
2003 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); | |
2004 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); | |
2005 | } | |
2006 | ||
2007 | return result; | |
2008 | } | |
2009 | ||
2010 | /** | |
2011 | * Populates the SMC MVDD structure using the provided memory clock. | |
2012 | * | |
2013 | * @param hwmgr the address of the hardware manager | |
2014 | * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. | |
2015 | * @param voltage the SMC VOLTAGE structure to be populated | |
2016 | */ | |
2017 | int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMU71_Discrete_VoltageLevel *voltage) | |
2018 | { | |
2019 | const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2020 | uint32_t i = 0; | |
2021 | ||
2022 | if (ICELAND_VOLTAGE_CONTROL_NONE != data->mvdd_control) { | |
2023 | /* find mvdd value which clock is more than request */ | |
2024 | for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { | |
2025 | if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { | |
2026 | /* Always round to higher voltage. */ | |
2027 | voltage->Voltage = data->mvdd_voltage_table.entries[i].value; | |
2028 | break; | |
2029 | } | |
2030 | } | |
2031 | ||
2032 | PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, | |
2033 | "MVDD Voltage is outside the supported range.", return -1); | |
2034 | ||
2035 | } else { | |
2036 | return -1; | |
2037 | } | |
2038 | ||
2039 | return 0; | |
2040 | } | |
2041 | ||
2042 | ||
2043 | static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, | |
2044 | SMU71_Discrete_DpmTable *table) | |
2045 | { | |
2046 | int result = 0; | |
2047 | const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2048 | pp_atomctrl_clock_dividers_vi dividers; | |
2049 | SMU71_Discrete_VoltageLevel voltage_level; | |
2050 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; | |
2051 | uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; | |
2052 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; | |
2053 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; | |
2054 | ||
2055 | /* The ACPI state should not do DPM on DC (or ever).*/ | |
2056 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; | |
2057 | ||
2058 | if (data->acpi_vddc) | |
2059 | table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); | |
2060 | else | |
2061 | table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pp_table * VOLTAGE_SCALE); | |
2062 | ||
2063 | table->ACPILevel.MinVddcPhases = (data->vddc_phase_shed_control) ? 0 : 1; | |
2064 | ||
2065 | /* assign zero for now*/ | |
2066 | table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); | |
2067 | ||
2068 | /* get the engine clock dividers for this clock value*/ | |
2069 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, | |
2070 | table->ACPILevel.SclkFrequency, ÷rs); | |
2071 | ||
2072 | PP_ASSERT_WITH_CODE(result == 0, | |
2073 | "Error retrieving Engine Clock dividers from VBIOS.", return result); | |
2074 | ||
2075 | /* divider ID for required SCLK*/ | |
2076 | table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; | |
2077 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
2078 | table->ACPILevel.DeepSleepDivId = 0; | |
2079 | ||
2080 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2081 | CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); | |
2082 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2083 | CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); | |
2084 | spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, | |
2085 | CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); | |
2086 | ||
2087 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; | |
2088 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; | |
2089 | table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; | |
2090 | table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; | |
2091 | table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; | |
2092 | table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; | |
2093 | table->ACPILevel.CcPwrDynRm = 0; | |
2094 | table->ACPILevel.CcPwrDynRm1 = 0; | |
2095 | ||
2096 | ||
2097 | /* For various features to be enabled/disabled while this level is active.*/ | |
2098 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); | |
2099 | /* SCLK frequency in units of 10KHz*/ | |
2100 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); | |
2101 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); | |
2102 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); | |
2103 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); | |
2104 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); | |
2105 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); | |
2106 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); | |
2107 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); | |
2108 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); | |
2109 | ||
2110 | table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; | |
2111 | table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; | |
2112 | ||
2113 | /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/ | |
2114 | ||
2115 | if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level)) | |
2116 | table->MemoryACPILevel.MinMvdd = | |
2117 | PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); | |
2118 | else | |
2119 | table->MemoryACPILevel.MinMvdd = 0; | |
2120 | ||
2121 | /* Force reset on DLL*/ | |
2122 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2123 | MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); | |
2124 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2125 | MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); | |
2126 | ||
2127 | /* Disable DLL in ACPIState*/ | |
2128 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2129 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); | |
2130 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2131 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); | |
2132 | ||
2133 | /* Enable DLL bypass signal*/ | |
2134 | dll_cntl = PHM_SET_FIELD(dll_cntl, | |
2135 | DLL_CNTL, MRDCK0_BYPASS, 0); | |
2136 | dll_cntl = PHM_SET_FIELD(dll_cntl, | |
2137 | DLL_CNTL, MRDCK1_BYPASS, 0); | |
2138 | ||
2139 | table->MemoryACPILevel.DllCntl = | |
2140 | PP_HOST_TO_SMC_UL(dll_cntl); | |
2141 | table->MemoryACPILevel.MclkPwrmgtCntl = | |
2142 | PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); | |
2143 | table->MemoryACPILevel.MpllAdFuncCntl = | |
2144 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); | |
2145 | table->MemoryACPILevel.MpllDqFuncCntl = | |
2146 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); | |
2147 | table->MemoryACPILevel.MpllFuncCntl = | |
2148 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); | |
2149 | table->MemoryACPILevel.MpllFuncCntl_1 = | |
2150 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); | |
2151 | table->MemoryACPILevel.MpllFuncCntl_2 = | |
2152 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); | |
2153 | table->MemoryACPILevel.MpllSs1 = | |
2154 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); | |
2155 | table->MemoryACPILevel.MpllSs2 = | |
2156 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); | |
2157 | ||
2158 | table->MemoryACPILevel.EnabledForThrottle = 0; | |
2159 | table->MemoryACPILevel.EnabledForActivity = 0; | |
2160 | table->MemoryACPILevel.UpHyst = 0; | |
2161 | table->MemoryACPILevel.DownHyst = 100; | |
2162 | table->MemoryACPILevel.VoltageDownHyst = 0; | |
2163 | /* Indicates maximum activity level for this performance level.*/ | |
2164 | table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); | |
2165 | ||
2166 | table->MemoryACPILevel.StutterEnable = 0; | |
2167 | table->MemoryACPILevel.StrobeEnable = 0; | |
2168 | table->MemoryACPILevel.EdcReadEnable = 0; | |
2169 | table->MemoryACPILevel.EdcWriteEnable = 0; | |
2170 | table->MemoryACPILevel.RttEnable = 0; | |
2171 | ||
2172 | return result; | |
2173 | } | |
2174 | ||
2175 | static int iceland_find_boot_level(struct iceland_single_dpm_table *table, uint32_t value, uint32_t *boot_level) | |
2176 | { | |
2177 | int result = 0; | |
2178 | uint32_t i; | |
2179 | ||
2180 | for (i = 0; i < table->count; i++) { | |
2181 | if (value == table->dpm_levels[i].value) { | |
2182 | *boot_level = i; | |
2183 | result = 0; | |
2184 | } | |
2185 | } | |
2186 | return result; | |
2187 | } | |
2188 | ||
2189 | /** | |
2190 | * Calculates the SCLK dividers using the provided engine clock | |
2191 | * | |
2192 | * @param hwmgr the address of the hardware manager | |
2193 | * @param engine_clock the engine clock to use to populate the structure | |
2194 | * @param sclk the SMC SCLK structure to be populated | |
2195 | */ | |
2196 | int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, | |
2197 | uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) | |
2198 | { | |
2199 | const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2200 | pp_atomctrl_clock_dividers_vi dividers; | |
2201 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; | |
2202 | uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; | |
2203 | uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; | |
2204 | uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; | |
2205 | uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; | |
2206 | uint32_t reference_clock; | |
2207 | uint32_t reference_divider; | |
2208 | uint32_t fbdiv; | |
2209 | int result; | |
2210 | ||
2211 | /* get the engine clock dividers for this clock value*/ | |
2212 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); | |
2213 | ||
2214 | PP_ASSERT_WITH_CODE(result == 0, | |
2215 | "Error retrieving Engine Clock dividers from VBIOS.", return result); | |
2216 | ||
2217 | /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/ | |
2218 | reference_clock = atomctrl_get_reference_clock(hwmgr); | |
2219 | ||
2220 | reference_divider = 1 + dividers.uc_pll_ref_div; | |
2221 | ||
2222 | /* low 14 bits is fraction and high 12 bits is divider*/ | |
2223 | fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; | |
2224 | ||
2225 | /* SPLL_FUNC_CNTL setup*/ | |
2226 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2227 | CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); | |
2228 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2229 | CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); | |
2230 | ||
2231 | /* SPLL_FUNC_CNTL_3 setup*/ | |
2232 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, | |
2233 | CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); | |
2234 | ||
2235 | /* set to use fractional accumulation*/ | |
2236 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, | |
2237 | CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); | |
2238 | ||
2239 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2240 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { | |
2241 | pp_atomctrl_internal_ss_info ss_info; | |
2242 | ||
2243 | uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; | |
2244 | if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { | |
2245 | /* | |
2246 | * ss_info.speed_spectrum_percentage -- in unit of 0.01% | |
2247 | * ss_info.speed_spectrum_rate -- in unit of khz | |
2248 | */ | |
2249 | /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */ | |
2250 | uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); | |
2251 | ||
2252 | /* clkv = 2 * D * fbdiv / NS */ | |
2253 | uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); | |
2254 | ||
2255 | cg_spll_spread_spectrum = | |
2256 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS); | |
2257 | cg_spll_spread_spectrum = | |
2258 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); | |
2259 | cg_spll_spread_spectrum_2 = | |
2260 | PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV); | |
2261 | } | |
2262 | } | |
2263 | ||
2264 | sclk->SclkFrequency = engine_clock; | |
2265 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; | |
2266 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; | |
2267 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; | |
2268 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; | |
2269 | sclk->SclkDid = (uint8_t)dividers.pll_post_divider; | |
2270 | ||
2271 | return 0; | |
2272 | } | |
2273 | ||
2274 | static uint8_t iceland_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr, | |
2275 | uint32_t engine_clock, uint32_t min_engine_clock_in_sr) | |
2276 | { | |
2277 | uint32_t i, temp; | |
2278 | uint32_t min = (min_engine_clock_in_sr > ICELAND_MINIMUM_ENGINE_CLOCK) ? | |
2279 | min_engine_clock_in_sr : ICELAND_MINIMUM_ENGINE_CLOCK; | |
2280 | ||
2281 | PP_ASSERT_WITH_CODE((engine_clock >= min), | |
2282 | "Engine clock can't satisfy stutter requirement!", return 0); | |
2283 | ||
2284 | for (i = ICELAND_MAX_DEEPSLEEP_DIVIDER_ID;; i--) { | |
2285 | temp = engine_clock / (1 << i); | |
2286 | ||
2287 | if(temp >= min || i == 0) | |
2288 | break; | |
2289 | } | |
2290 | return (uint8_t)i; | |
2291 | } | |
2292 | ||
2293 | /** | |
2294 | * Populates single SMC SCLK structure using the provided engine clock | |
2295 | * | |
2296 | * @param hwmgr the address of the hardware manager | |
2297 | * @param engine_clock the engine clock to use to populate the structure | |
2298 | * @param sclk the SMC SCLK structure to be populated | |
2299 | */ | |
2300 | static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, | |
2301 | uint32_t engine_clock, uint16_t sclk_activity_level_threshold, | |
2302 | SMU71_Discrete_GraphicsLevel *graphic_level) | |
2303 | { | |
2304 | int result; | |
2305 | uint32_t threshold; | |
2306 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2307 | ||
2308 | result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); | |
2309 | ||
2310 | ||
2311 | /* populate graphics levels*/ | |
2312 | result = iceland_get_dependecy_volt_by_clk(hwmgr, | |
2313 | hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, &graphic_level->MinVddc); | |
2314 | PP_ASSERT_WITH_CODE((0 == result), | |
2315 | "can not find VDDC voltage value for VDDC engine clock dependency table", return result); | |
2316 | ||
2317 | /* SCLK frequency in units of 10KHz*/ | |
2318 | graphic_level->SclkFrequency = engine_clock; | |
2319 | ||
2320 | /* | |
2321 | * Minimum VDDC phases required to support this level, it | |
2322 | * should get from dependence table. | |
2323 | */ | |
2324 | graphic_level->MinVddcPhases = 1; | |
2325 | ||
2326 | if (data->vddc_phase_shed_control) { | |
2327 | iceland_populate_phase_value_based_on_sclk(hwmgr, | |
2328 | hwmgr->dyn_state.vddc_phase_shed_limits_table, | |
2329 | engine_clock, | |
2330 | &graphic_level->MinVddcPhases); | |
2331 | } | |
2332 | ||
2333 | /* Indicates maximum activity level for this performance level. 50% for now*/ | |
2334 | graphic_level->ActivityLevel = sclk_activity_level_threshold; | |
2335 | ||
2336 | graphic_level->CcPwrDynRm = 0; | |
2337 | graphic_level->CcPwrDynRm1 = 0; | |
2338 | /* this level can be used if activity is high enough.*/ | |
2339 | graphic_level->EnabledForActivity = 1; | |
2340 | /* this level can be used for throttling.*/ | |
2341 | graphic_level->EnabledForThrottle = 1; | |
2342 | graphic_level->UpHyst = 0; | |
2343 | graphic_level->DownHyst = 100; | |
2344 | graphic_level->VoltageDownHyst = 0; | |
2345 | graphic_level->PowerThrottle = 0; | |
2346 | ||
2347 | threshold = engine_clock * data->fast_watermark_threshold / 100; | |
2348 | ||
2349 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2350 | PHM_PlatformCaps_SclkDeepSleep)) { | |
2351 | graphic_level->DeepSleepDivId = | |
2352 | iceland_get_sleep_divider_id_from_clock(hwmgr, engine_clock, | |
2353 | data->display_timing.min_clock_insr); | |
2354 | } | |
2355 | ||
2356 | /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ | |
2357 | graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
2358 | ||
2359 | if (0 == result) { | |
2360 | graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE); | |
2361 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/ | |
2362 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases); | |
2363 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); | |
2364 | CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); | |
2365 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); | |
2366 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); | |
2367 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); | |
2368 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); | |
2369 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); | |
2370 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); | |
2371 | } | |
2372 | ||
2373 | return result; | |
2374 | } | |
2375 | ||
2376 | /** | |
2377 | * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states | |
2378 | * | |
2379 | * @param hwmgr the address of the hardware manager | |
2380 | */ | |
2381 | static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) | |
2382 | { | |
2383 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2384 | struct iceland_dpm_table *dpm_table = &data->dpm_table; | |
2385 | int result = 0; | |
2386 | uint32_t level_array_adress = data->dpm_table_start + | |
2387 | offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); | |
2388 | ||
2389 | uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) * SMU71_MAX_LEVELS_GRAPHICS; | |
2390 | SMU71_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; | |
2391 | uint32_t i; | |
2392 | uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0; | |
2393 | memset(levels, 0x00, level_array_size); | |
2394 | ||
2395 | for (i = 0; i < dpm_table->sclk_table.count; i++) { | |
2396 | result = iceland_populate_single_graphic_level(hwmgr, | |
2397 | dpm_table->sclk_table.dpm_levels[i].value, | |
2398 | (uint16_t)data->activity_target[i], | |
2399 | &(data->smc_state_table.GraphicsLevel[i])); | |
2400 | if (0 != result) | |
2401 | return result; | |
2402 | ||
2403 | /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ | |
2404 | if (i > 1) | |
2405 | data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; | |
2406 | } | |
2407 | ||
2408 | /* set highest level watermark to high */ | |
2409 | if (dpm_table->sclk_table.count > 1) | |
2410 | data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = | |
2411 | PPSMC_DISPLAY_WATERMARK_HIGH; | |
2412 | ||
2413 | data->smc_state_table.GraphicsDpmLevelCount = | |
2414 | (uint8_t)dpm_table->sclk_table.count; | |
2415 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = | |
2416 | iceland_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); | |
2417 | ||
2418 | while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
2419 | (1 << (highest_pcie_level_enabled + 1))) != 0) { | |
2420 | highest_pcie_level_enabled++; | |
2421 | } | |
2422 | ||
2423 | while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
2424 | (1 << lowest_pcie_level_enabled)) == 0) { | |
2425 | lowest_pcie_level_enabled++; | |
2426 | } | |
2427 | ||
2428 | while ((count < highest_pcie_level_enabled) && | |
2429 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
2430 | (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) { | |
2431 | count++; | |
2432 | } | |
2433 | ||
2434 | mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ? | |
2435 | (lowest_pcie_level_enabled + 1 + count) : highest_pcie_level_enabled; | |
2436 | ||
2437 | /* set pcieDpmLevel to highest_pcie_level_enabled*/ | |
2438 | for (i = 2; i < dpm_table->sclk_table.count; i++) { | |
2439 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; | |
2440 | } | |
2441 | ||
2442 | /* set pcieDpmLevel to lowest_pcie_level_enabled*/ | |
2443 | data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; | |
2444 | ||
2445 | /* set pcieDpmLevel to mid_pcie_level_enabled*/ | |
2446 | data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; | |
2447 | ||
2448 | for (i = 0; i < dpm_table->sclk_table.count; i++) | |
2449 | ||
2450 | /* level count will send to smc once at init smc table and never change*/ | |
2451 | result = iceland_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); | |
2452 | ||
2453 | if (0 != result) | |
2454 | return result; | |
2455 | ||
2456 | return 0; | |
2457 | } | |
2458 | ||
2459 | /** | |
2460 | * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states | |
2461 | * | |
2462 | * @param hwmgr the address of the hardware manager | |
2463 | */ | |
2464 | ||
2465 | static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) | |
2466 | { | |
2467 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2468 | struct iceland_dpm_table *dpm_table = &data->dpm_table; | |
2469 | int result; | |
2470 | /* populate MCLK dpm table to SMU7 */ | |
2471 | uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel); | |
2472 | uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY; | |
2473 | SMU71_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel; | |
2474 | uint32_t i; | |
2475 | ||
2476 | memset(levels, 0x00, level_array_size); | |
2477 | ||
2478 | for (i = 0; i < dpm_table->mclk_table.count; i++) { | |
2479 | PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), | |
2480 | "can not populate memory level as memory clock is zero", return -1); | |
2481 | result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, | |
2482 | &(data->smc_state_table.MemoryLevel[i])); | |
2483 | if (0 != result) { | |
2484 | return result; | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | /* Only enable level 0 for now.*/ | |
2489 | data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; | |
2490 | ||
2491 | /* | |
2492 | * in order to prevent MC activity from stutter mode to push DPM up. | |
2493 | * the UVD change complements this by putting the MCLK in a higher state | |
2494 | * by default such that we are not effected by up threshold or and MCLK DPM latency. | |
2495 | */ | |
2496 | data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; | |
2497 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel); | |
2498 | ||
2499 | data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; | |
2500 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); | |
2501 | /* set highest level watermark to high*/ | |
2502 | data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; | |
2503 | ||
2504 | /* level count will send to smc once at init smc table and never change*/ | |
2505 | result = iceland_copy_bytes_to_smc(hwmgr->smumgr, | |
2506 | level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); | |
2507 | ||
2508 | if (0 != result) { | |
2509 | return result; | |
2510 | } | |
2511 | ||
2512 | return 0; | |
2513 | } | |
2514 | ||
2515 | struct ICELAND_DLL_SPEED_SETTING | |
2516 | { | |
2517 | uint16_t Min; /* Minimum Data Rate*/ | |
2518 | uint16_t Max; /* Maximum Data Rate*/ | |
2519 | uint32_t dll_speed; /* The desired DLL_SPEED setting*/ | |
2520 | }; | |
2521 | ||
2522 | static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_Ulv *pstate) | |
2523 | { | |
2524 | int result = 0; | |
2525 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2526 | uint32_t voltage_response_time, ulv_voltage; | |
2527 | ||
2528 | pstate->CcPwrDynRm = 0; | |
2529 | pstate->CcPwrDynRm1 = 0; | |
2530 | ||
2531 | //backbiasResponseTime is use for ULV state voltage value. | |
2532 | result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage); | |
2533 | PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); | |
2534 | ||
2535 | if(!ulv_voltage) { | |
2536 | data->ulv.ulv_supported = false; | |
2537 | return 0; | |
2538 | } | |
2539 | ||
2540 | if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 != data->voltage_control) { | |
2541 | /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */ | |
2542 | if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) { | |
2543 | pstate->VddcOffset = 0; | |
2544 | } | |
2545 | else { | |
2546 | /* used in SMIO Mode. not implemented for now. this is backup only for CI. */ | |
2547 | pstate->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage); | |
2548 | } | |
2549 | } else { | |
2550 | /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */ | |
2551 | if(ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) { | |
2552 | pstate->VddcOffsetVid = 0; | |
2553 | } else { | |
2554 | /* used in SVI2 Mode */ | |
2555 | pstate->VddcOffsetVid = (uint8_t)((hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | /* used in SVI2 Mode to shed phase */ | |
2560 | pstate->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; | |
2561 | ||
2562 | if (0 == result) { | |
2563 | CONVERT_FROM_HOST_TO_SMC_UL(pstate->CcPwrDynRm); | |
2564 | CONVERT_FROM_HOST_TO_SMC_UL(pstate->CcPwrDynRm1); | |
2565 | CONVERT_FROM_HOST_TO_SMC_US(pstate->VddcOffset); | |
2566 | } | |
2567 | ||
2568 | return result; | |
2569 | } | |
2570 | ||
2571 | static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr, SMU71_Discrete_Ulv *ulv) | |
2572 | { | |
2573 | return iceland_populate_ulv_level(hwmgr, ulv); | |
2574 | } | |
2575 | ||
2576 | static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) | |
2577 | { | |
2578 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2579 | uint8_t count, level; | |
2580 | ||
2581 | count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); | |
2582 | ||
2583 | for (level = 0; level < count; level++) { | |
2584 | if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk | |
2585 | >= data->vbios_boot_state.sclk_bootup_value) { | |
2586 | data->smc_state_table.GraphicsBootLevel = level; | |
2587 | break; | |
2588 | } | |
2589 | } | |
2590 | ||
2591 | count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); | |
2592 | ||
2593 | for (level = 0; level < count; level++) { | |
2594 | if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk | |
2595 | >= data->vbios_boot_state.mclk_bootup_value) { | |
2596 | data->smc_state_table.MemoryBootLevel = level; | |
2597 | break; | |
2598 | } | |
2599 | } | |
2600 | ||
2601 | return 0; | |
2602 | } | |
2603 | ||
2604 | /** | |
2605 | * Initializes the SMC table and uploads it | |
2606 | * | |
2607 | * @param hwmgr the address of the powerplay hardware manager. | |
2608 | * @param pInput the pointer to input data (PowerState) | |
2609 | * @return always 0 | |
2610 | */ | |
2611 | int iceland_init_smc_table(struct pp_hwmgr *hwmgr) | |
2612 | { | |
2613 | int result; | |
2614 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2615 | SMU71_Discrete_DpmTable *table = &(data->smc_state_table); | |
2616 | const struct phw_iceland_ulv_parm *ulv = &(data->ulv); | |
2617 | ||
2618 | result = iceland_setup_default_dpm_tables(hwmgr); | |
2619 | PP_ASSERT_WITH_CODE(0 == result, | |
2620 | "Failed to setup default DPM tables!", return result;); | |
2621 | memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table)); | |
2622 | ||
2623 | if (ICELAND_VOLTAGE_CONTROL_NONE != data->voltage_control) { | |
2624 | iceland_populate_smc_voltage_tables(hwmgr, table); | |
2625 | } | |
2626 | ||
2627 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2628 | PHM_PlatformCaps_AutomaticDCTransition)) { | |
2629 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; | |
2630 | } | |
2631 | ||
2632 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2633 | PHM_PlatformCaps_StepVddc)) { | |
2634 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; | |
2635 | } | |
2636 | ||
2637 | if (data->is_memory_GDDR5) { | |
2638 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; | |
2639 | } | |
2640 | ||
2641 | if (ulv->ulv_supported) { | |
2642 | result = iceland_populate_ulv_state(hwmgr, &data->ulv_setting); | |
2643 | PP_ASSERT_WITH_CODE(0 == result, | |
2644 | "Failed to initialize ULV state!", return result;); | |
2645 | ||
2646 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2647 | ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter); | |
2648 | } | |
2649 | ||
2650 | result = iceland_populate_smc_link_level(hwmgr, table); | |
2651 | PP_ASSERT_WITH_CODE(0 == result, | |
2652 | "Failed to initialize Link Level!", return result;); | |
2653 | ||
2654 | result = iceland_populate_all_graphic_levels(hwmgr); | |
2655 | PP_ASSERT_WITH_CODE(0 == result, | |
2656 | "Failed to initialize Graphics Level!", return result;); | |
2657 | ||
2658 | result = iceland_populate_all_memory_levels(hwmgr); | |
2659 | PP_ASSERT_WITH_CODE(0 == result, | |
2660 | "Failed to initialize Memory Level!", return result;); | |
2661 | ||
2662 | result = iceland_populate_smc_acpi_level(hwmgr, table); | |
2663 | PP_ASSERT_WITH_CODE(0 == result, | |
2664 | "Failed to initialize ACPI Level!", return result;); | |
2665 | ||
2666 | result = iceland_populate_smc_vce_level(hwmgr, table); | |
2667 | PP_ASSERT_WITH_CODE(0 == result, | |
2668 | "Failed to initialize VCE Level!", return result;); | |
2669 | ||
2670 | result = iceland_populate_smc_acp_level(hwmgr, table); | |
2671 | PP_ASSERT_WITH_CODE(0 == result, | |
2672 | "Failed to initialize ACP Level!", return result;); | |
2673 | ||
2674 | result = iceland_populate_smc_samu_level(hwmgr, table); | |
2675 | PP_ASSERT_WITH_CODE(0 == result, | |
2676 | "Failed to initialize SAMU Level!", return result;); | |
2677 | ||
2678 | /* | |
2679 | * Since only the initial state is completely set up at this | |
2680 | * point (the other states are just copies of the boot state) | |
2681 | * we only need to populate the ARB settings for the initial | |
2682 | * state. | |
2683 | */ | |
2684 | result = iceland_program_memory_timing_parameters(hwmgr); | |
2685 | PP_ASSERT_WITH_CODE(0 == result, | |
2686 | "Failed to Write ARB settings for the initial state.", return result;); | |
2687 | ||
2688 | result = iceland_populate_smc_uvd_level(hwmgr, table); | |
2689 | PP_ASSERT_WITH_CODE(0 == result, | |
2690 | "Failed to initialize UVD Level!", return result;); | |
2691 | ||
2692 | table->GraphicsBootLevel = 0; | |
2693 | table->MemoryBootLevel = 0; | |
2694 | ||
2695 | /* find boot level from dpm table */ | |
2696 | result = iceland_find_boot_level(&(data->dpm_table.sclk_table), | |
2697 | data->vbios_boot_state.sclk_bootup_value, | |
2698 | (uint32_t *)&(data->smc_state_table.GraphicsBootLevel)); | |
2699 | ||
2700 | if (result) | |
2701 | pr_warning("VBIOS did not find boot engine clock value in dependency table.\n"); | |
2702 | ||
2703 | result = iceland_find_boot_level(&(data->dpm_table.mclk_table), | |
2704 | data->vbios_boot_state.mclk_bootup_value, | |
2705 | (uint32_t *)&(data->smc_state_table.MemoryBootLevel)); | |
2706 | ||
2707 | if (result) | |
2708 | pr_warning("VBIOS did not find boot memory clock value in dependency table.\n"); | |
2709 | ||
2710 | table->BootVddc = data->vbios_boot_state.vddc_bootup_value; | |
2711 | if (ICELAND_VOLTAGE_CONTROL_NONE == data->vdd_ci_control) { | |
2712 | table->BootVddci = table->BootVddc; | |
2713 | } | |
2714 | else { | |
2715 | table->BootVddci = data->vbios_boot_state.vddci_bootup_value; | |
2716 | } | |
2717 | table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; | |
2718 | ||
2719 | result = iceland_populate_smc_initial_state(hwmgr); | |
2720 | PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); | |
2721 | ||
2722 | result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr); | |
2723 | PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); | |
2724 | ||
2725 | table->GraphicsVoltageChangeEnable = 1; | |
2726 | table->GraphicsThermThrottleEnable = 1; | |
2727 | table->GraphicsInterval = 1; | |
2728 | table->VoltageInterval = 1; | |
2729 | table->ThermalInterval = 1; | |
2730 | table->TemperatureLimitHigh = | |
2731 | (data->thermal_temp_setting.temperature_high * | |
2732 | ICELAND_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
2733 | table->TemperatureLimitLow = | |
2734 | (data->thermal_temp_setting.temperature_low * | |
2735 | ICELAND_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
2736 | table->MemoryVoltageChangeEnable = 1; | |
2737 | table->MemoryInterval = 1; | |
2738 | table->VoltageResponseTime = 0; | |
2739 | table->PhaseResponseTime = 0; | |
2740 | table->MemoryThermThrottleEnable = 1; | |
2741 | table->PCIeBootLinkLevel = 0; | |
2742 | table->PCIeGenInterval = 1; | |
2743 | ||
2744 | result = iceland_populate_smc_svi2_config(hwmgr, table); | |
2745 | PP_ASSERT_WITH_CODE(0 == result, | |
2746 | "Failed to populate SVI2 setting!", return result); | |
2747 | ||
2748 | table->ThermGpio = 17; | |
2749 | table->SclkStepSize = 0x4000; | |
2750 | ||
2751 | CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); | |
2752 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid); | |
2753 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase); | |
2754 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid); | |
2755 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid); | |
2756 | CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); | |
2757 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); | |
2758 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); | |
2759 | CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); | |
2760 | CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); | |
2761 | ||
2762 | table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE); | |
2763 | table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE); | |
2764 | table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); | |
2765 | ||
2766 | /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ | |
2767 | result = iceland_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start + | |
2768 | offsetof(SMU71_Discrete_DpmTable, SystemFlags), | |
2769 | (uint8_t *)&(table->SystemFlags), | |
2770 | sizeof(SMU71_Discrete_DpmTable) - 3 * sizeof(SMU71_PIDController), | |
2771 | data->sram_end); | |
2772 | ||
2773 | PP_ASSERT_WITH_CODE(0 == result, | |
2774 | "Failed to upload dpm data to SMC memory!", return result); | |
2775 | ||
2776 | /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */ | |
2777 | result = iceland_copy_bytes_to_smc(hwmgr->smumgr, | |
2778 | data->ulv_settings_start, | |
2779 | (uint8_t *)&(data->ulv_setting), | |
2780 | sizeof(SMU71_Discrete_Ulv), | |
2781 | data->sram_end); | |
2782 | ||
2783 | #if 0 | |
2784 | /* Notify SMC to follow new GPIO scheme */ | |
2785 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2786 | PHM_PlatformCaps_AutomaticDCTransition)) { | |
2787 | if (0 == iceland_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_UseNewGPIOScheme)) | |
2788 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
2789 | PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); | |
2790 | } | |
2791 | #endif | |
2792 | ||
2793 | return result; | |
2794 | } | |
2795 | ||
2796 | int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCRegisters *mc_reg_table) | |
2797 | { | |
2798 | const struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
2799 | ||
2800 | uint32_t i, j; | |
2801 | ||
2802 | for (i = 0, j = 0; j < data->iceland_mc_reg_table.last; j++) { | |
2803 | if (data->iceland_mc_reg_table.validflag & 1<<j) { | |
2804 | PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE, | |
2805 | "Index of mc_reg_table->address[] array out of boundary", return -1); | |
2806 | mc_reg_table->address[i].s0 = | |
2807 | PP_HOST_TO_SMC_US(data->iceland_mc_reg_table.mc_reg_address[j].s0); | |
2808 | mc_reg_table->address[i].s1 = | |
2809 | PP_HOST_TO_SMC_US(data->iceland_mc_reg_table.mc_reg_address[j].s1); | |
2810 | i++; | |
2811 | } | |
2812 | } | |
2813 | ||
2814 | mc_reg_table->last = (uint8_t)i; | |
2815 | ||
2816 | return 0; | |
2817 | } | |
2818 | ||
2819 | /* convert register values from driver to SMC format */ | |
2820 | void iceland_convert_mc_registers( | |
2821 | const phw_iceland_mc_reg_entry * pEntry, | |
2822 | SMU71_Discrete_MCRegisterSet *pData, | |
2823 | uint32_t numEntries, uint32_t validflag) | |
2824 | { | |
2825 | uint32_t i, j; | |
2826 | ||
2827 | for (i = 0, j = 0; j < numEntries; j++) { | |
2828 | if (validflag & 1<<j) { | |
2829 | pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]); | |
2830 | i++; | |
2831 | } | |
2832 | } | |
2833 | } | |
2834 | ||
2835 | /* find the entry in the memory range table, then populate the value to SMC's iceland_mc_reg_table */ | |
2836 | int iceland_convert_mc_reg_table_entry_to_smc( | |
2837 | struct pp_hwmgr *hwmgr, | |
2838 | const uint32_t memory_clock, | |
2839 | SMU71_Discrete_MCRegisterSet *mc_reg_table_data | |
2840 | ) | |
2841 | { | |
2842 | const iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
2843 | uint32_t i = 0; | |
2844 | ||
2845 | for (i = 0; i < data->iceland_mc_reg_table.num_entries; i++) { | |
2846 | if (memory_clock <= | |
2847 | data->iceland_mc_reg_table.mc_reg_table_entry[i].mclk_max) { | |
2848 | break; | |
2849 | } | |
2850 | } | |
2851 | ||
2852 | if ((i == data->iceland_mc_reg_table.num_entries) && (i > 0)) | |
2853 | --i; | |
2854 | ||
2855 | iceland_convert_mc_registers(&data->iceland_mc_reg_table.mc_reg_table_entry[i], | |
2856 | mc_reg_table_data, data->iceland_mc_reg_table.last, data->iceland_mc_reg_table.validflag); | |
2857 | ||
2858 | return 0; | |
2859 | } | |
2860 | ||
2861 | int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, | |
2862 | SMU71_Discrete_MCRegisters *mc_reg_table) | |
2863 | { | |
2864 | int result = 0; | |
2865 | iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
2866 | int res; | |
2867 | uint32_t i; | |
2868 | ||
2869 | for (i = 0; i < data->dpm_table.mclk_table.count; i++) { | |
2870 | res = iceland_convert_mc_reg_table_entry_to_smc( | |
2871 | hwmgr, | |
2872 | data->dpm_table.mclk_table.dpm_levels[i].value, | |
2873 | &mc_reg_table->data[i] | |
2874 | ); | |
2875 | ||
2876 | if (0 != res) | |
2877 | result = res; | |
2878 | } | |
2879 | ||
2880 | return result; | |
2881 | } | |
2882 | ||
2883 | int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) | |
2884 | { | |
2885 | int result; | |
2886 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
2887 | ||
2888 | memset(&data->mc_reg_table, 0x00, sizeof(SMU71_Discrete_MCRegisters)); | |
2889 | result = iceland_populate_mc_reg_address(hwmgr, &(data->mc_reg_table)); | |
2890 | PP_ASSERT_WITH_CODE(0 == result, | |
2891 | "Failed to initialize MCRegTable for the MC register addresses!", return result;); | |
2892 | ||
2893 | result = iceland_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table); | |
2894 | PP_ASSERT_WITH_CODE(0 == result, | |
2895 | "Failed to initialize MCRegTable for driver state!", return result;); | |
2896 | ||
2897 | return iceland_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start, | |
2898 | (uint8_t *)&data->mc_reg_table, sizeof(SMU71_Discrete_MCRegisters), data->sram_end); | |
2899 | } | |
2900 | ||
2901 | int iceland_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) | |
2902 | { | |
2903 | PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; | |
2904 | ||
2905 | return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; | |
2906 | } | |
2907 | ||
2908 | int iceland_enable_sclk_control(struct pp_hwmgr *hwmgr) | |
2909 | { | |
2910 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); | |
2911 | ||
2912 | return 0; | |
2913 | } | |
2914 | ||
2915 | int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
2916 | { | |
2917 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2918 | ||
2919 | /* enable SCLK dpm */ | |
2920 | if (0 == data->sclk_dpm_key_disabled) { | |
2921 | PP_ASSERT_WITH_CODE( | |
2922 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
2923 | PPSMC_MSG_DPM_Enable)), | |
2924 | "Failed to enable SCLK DPM during DPM Start Function!", | |
2925 | return -1); | |
2926 | } | |
2927 | ||
2928 | /* enable MCLK dpm */ | |
2929 | if (0 == data->mclk_dpm_key_disabled) { | |
2930 | PP_ASSERT_WITH_CODE( | |
2931 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
2932 | PPSMC_MSG_MCLKDPM_Enable)), | |
2933 | "Failed to enable MCLK DPM during DPM Start Function!", | |
2934 | return -1); | |
2935 | ||
2936 | PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); | |
2937 | ||
2938 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2939 | ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */ | |
2940 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2941 | ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */ | |
2942 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2943 | ixLCAC_CPL_CNTL, 0x100005);/*Read */ | |
2944 | ||
2945 | udelay(10); | |
2946 | ||
2947 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2948 | ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */ | |
2949 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2950 | ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */ | |
2951 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2952 | ixLCAC_CPL_CNTL, 0x500005);/* write */ | |
2953 | ||
2954 | } | |
2955 | ||
2956 | return 0; | |
2957 | } | |
2958 | ||
2959 | int iceland_start_dpm(struct pp_hwmgr *hwmgr) | |
2960 | { | |
2961 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
2962 | ||
2963 | /* enable general power management */ | |
2964 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1); | |
2965 | /* enable sclk deep sleep */ | |
2966 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1); | |
2967 | ||
2968 | /* prepare for PCIE DPM */ | |
2969 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SOFT_REGISTERS_TABLE_12, VoltageChangeTimeout, 0x1000); | |
2970 | ||
2971 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); | |
2972 | ||
2973 | #if 0 | |
2974 | PP_ASSERT_WITH_CODE( | |
2975 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
2976 | PPSMC_MSG_Voltage_Cntl_Enable)), | |
2977 | "Failed to enable voltage DPM during DPM Start Function!", | |
2978 | return -1); | |
2979 | #endif | |
2980 | ||
2981 | if (0 != iceland_enable_sclk_mclk_dpm(hwmgr)) { | |
2982 | PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1); | |
2983 | } | |
2984 | ||
2985 | /* enable PCIE dpm */ | |
2986 | if (0 == data->pcie_dpm_key_disabled) { | |
2987 | PP_ASSERT_WITH_CODE( | |
2988 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
2989 | PPSMC_MSG_PCIeDPM_Enable)), | |
2990 | "Failed to enable pcie DPM during DPM Start Function!", | |
2991 | return -1 | |
2992 | ); | |
2993 | } | |
2994 | ||
2995 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2996 | PHM_PlatformCaps_Falcon_QuickTransition)) { | |
2997 | smum_send_msg_to_smc(hwmgr->smumgr, | |
2998 | PPSMC_MSG_EnableACDCGPIOInterrupt); | |
2999 | } | |
3000 | ||
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | static void iceland_set_dpm_event_sources(struct pp_hwmgr *hwmgr, | |
3005 | uint32_t sources) | |
3006 | { | |
3007 | bool protection; | |
3008 | enum DPM_EVENT_SRC src; | |
3009 | ||
3010 | switch (sources) { | |
3011 | default: | |
3012 | printk(KERN_ERR "Unknown throttling event sources."); | |
3013 | /* fall through */ | |
3014 | case 0: | |
3015 | protection = false; | |
3016 | /* src is unused */ | |
3017 | break; | |
3018 | case (1 << PHM_AutoThrottleSource_Thermal): | |
3019 | protection = true; | |
3020 | src = DPM_EVENT_SRC_DIGITAL; | |
3021 | break; | |
3022 | case (1 << PHM_AutoThrottleSource_External): | |
3023 | protection = true; | |
3024 | src = DPM_EVENT_SRC_EXTERNAL; | |
3025 | break; | |
3026 | case (1 << PHM_AutoThrottleSource_External) | | |
3027 | (1 << PHM_AutoThrottleSource_Thermal): | |
3028 | protection = true; | |
3029 | src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; | |
3030 | break; | |
3031 | } | |
3032 | /* Order matters - don't enable thermal protection for the wrong source. */ | |
3033 | if (protection) { | |
3034 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, | |
3035 | DPM_EVENT_SRC, src); | |
3036 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, | |
3037 | THERMAL_PROTECTION_DIS, | |
3038 | !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
3039 | PHM_PlatformCaps_ThermalController)); | |
3040 | } else | |
3041 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, | |
3042 | THERMAL_PROTECTION_DIS, 1); | |
3043 | } | |
3044 | ||
3045 | static int iceland_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, | |
3046 | PHM_AutoThrottleSource source) | |
3047 | { | |
3048 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
3049 | ||
3050 | if (!(data->active_auto_throttle_sources & (1 << source))) { | |
3051 | data->active_auto_throttle_sources |= 1 << source; | |
3052 | iceland_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); | |
3053 | } | |
3054 | return 0; | |
3055 | } | |
3056 | ||
3057 | static int iceland_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) | |
3058 | { | |
3059 | return iceland_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); | |
3060 | } | |
3061 | ||
3062 | static int iceland_tf_start_smc(struct pp_hwmgr *hwmgr) | |
3063 | { | |
3064 | int ret = 0; | |
3065 | ||
3066 | if (!iceland_is_smc_ram_running(hwmgr->smumgr)) | |
3067 | ret = iceland_smu_start_smc(hwmgr->smumgr); | |
3068 | ||
3069 | return ret; | |
3070 | } | |
3071 | ||
3072 | static int iceland_enable_dpm_tasks(struct pp_hwmgr *hwmgr) | |
3073 | { | |
3074 | int tmp_result, result = 0; | |
3075 | ||
3076 | if (cf_iceland_voltage_control(hwmgr)) { | |
3077 | tmp_result = iceland_enable_voltage_control(hwmgr); | |
3078 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3079 | "Failed to enable voltage control!", return tmp_result); | |
3080 | ||
3081 | tmp_result = iceland_construct_voltage_tables(hwmgr); | |
3082 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3083 | "Failed to contruct voltage tables!", return tmp_result); | |
3084 | } | |
3085 | ||
3086 | tmp_result = iceland_initialize_mc_reg_table(hwmgr); | |
3087 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3088 | "Failed to initialize MC reg table!", return tmp_result); | |
3089 | ||
3090 | tmp_result = iceland_program_static_screen_threshold_parameters(hwmgr); | |
3091 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3092 | "Failed to program static screen threshold parameters!", return tmp_result); | |
3093 | ||
3094 | tmp_result = iceland_enable_display_gap(hwmgr); | |
3095 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3096 | "Failed to enable display gap!", return tmp_result); | |
3097 | ||
3098 | tmp_result = iceland_program_voting_clients(hwmgr); | |
3099 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3100 | "Failed to program voting clients!", return tmp_result); | |
3101 | ||
3102 | tmp_result = iceland_upload_firmware(hwmgr); | |
3103 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3104 | "Failed to upload firmware header!", return tmp_result); | |
3105 | ||
3106 | tmp_result = iceland_process_firmware_header(hwmgr); | |
3107 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3108 | "Failed to process firmware header!", return tmp_result); | |
3109 | ||
3110 | tmp_result = iceland_initial_switch_from_arb_f0_to_f1(hwmgr); | |
3111 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3112 | "Failed to initialize switch from ArbF0 to F1!", return tmp_result); | |
3113 | ||
3114 | tmp_result = iceland_init_smc_table(hwmgr); | |
3115 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3116 | "Failed to initialize SMC table!", return tmp_result); | |
3117 | ||
3118 | tmp_result = iceland_populate_initial_mc_reg_table(hwmgr); | |
3119 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3120 | "Failed to populate initialize MC Reg table!", return tmp_result); | |
3121 | ||
3122 | tmp_result = iceland_populate_pm_fuses(hwmgr); | |
3123 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3124 | "Failed to populate PM fuses!", return tmp_result); | |
3125 | ||
3126 | /* start SMC */ | |
3127 | tmp_result = iceland_tf_start_smc(hwmgr); | |
3128 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3129 | "Failed to start SMC!", return tmp_result); | |
3130 | ||
3131 | /* enable SCLK control */ | |
3132 | tmp_result = iceland_enable_sclk_control(hwmgr); | |
3133 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3134 | "Failed to enable SCLK control!", return tmp_result); | |
3135 | ||
3136 | /* enable DPM */ | |
3137 | tmp_result = iceland_start_dpm(hwmgr); | |
3138 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3139 | "Failed to start DPM!", return tmp_result); | |
3140 | ||
3141 | tmp_result = iceland_enable_smc_cac(hwmgr); | |
3142 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3143 | "Failed to enable SMC CAC!", return tmp_result); | |
3144 | ||
3145 | tmp_result = iceland_enable_power_containment(hwmgr); | |
3146 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3147 | "Failed to enable power containment!", return tmp_result); | |
3148 | ||
3149 | tmp_result = iceland_power_control_set_level(hwmgr); | |
3150 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3151 | "Failed to power control set level!", result = tmp_result); | |
3152 | ||
3153 | tmp_result = iceland_enable_thermal_auto_throttle(hwmgr); | |
3154 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3155 | "Failed to enable thermal auto throttle!", result = tmp_result); | |
3156 | ||
3157 | return result; | |
3158 | } | |
3159 | ||
3160 | static int iceland_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) | |
3161 | { | |
3162 | return phm_hwmgr_backend_fini(hwmgr); | |
3163 | } | |
3164 | ||
3165 | static void iceland_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) | |
3166 | { | |
3167 | iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
3168 | struct phw_iceland_ulv_parm *ulv; | |
3169 | ||
3170 | ulv = &data->ulv; | |
3171 | ulv->ch_ulv_parameter = PPICELAND_CGULVPARAMETER_DFLT; | |
3172 | data->voting_rights_clients0 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT0; | |
3173 | data->voting_rights_clients1 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT1; | |
3174 | data->voting_rights_clients2 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT2; | |
3175 | data->voting_rights_clients3 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT3; | |
3176 | data->voting_rights_clients4 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT4; | |
3177 | data->voting_rights_clients5 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT5; | |
3178 | data->voting_rights_clients6 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT6; | |
3179 | data->voting_rights_clients7 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT7; | |
3180 | ||
3181 | data->static_screen_threshold_unit = PPICELAND_STATICSCREENTHRESHOLDUNIT_DFLT; | |
3182 | data->static_screen_threshold = PPICELAND_STATICSCREENTHRESHOLD_DFLT; | |
3183 | ||
3184 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3185 | PHM_PlatformCaps_ABM); | |
3186 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3187 | PHM_PlatformCaps_NonABMSupportInPPLib); | |
3188 | ||
3189 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3190 | PHM_PlatformCaps_DynamicACTiming); | |
3191 | ||
3192 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3193 | PHM_PlatformCaps_DisableMemoryTransition); | |
3194 | ||
3195 | iceland_initialize_power_tune_defaults(hwmgr); | |
3196 | ||
3197 | data->mclk_strobe_mode_threshold = 40000; | |
3198 | data->mclk_stutter_mode_threshold = 30000; | |
3199 | data->mclk_edc_enable_threshold = 40000; | |
3200 | data->mclk_edc_wr_enable_threshold = 40000; | |
3201 | ||
3202 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3203 | PHM_PlatformCaps_DisableMCLS); | |
3204 | ||
3205 | data->pcie_gen_performance.max = PP_PCIEGen1; | |
3206 | data->pcie_gen_performance.min = PP_PCIEGen3; | |
3207 | data->pcie_gen_power_saving.max = PP_PCIEGen1; | |
3208 | data->pcie_gen_power_saving.min = PP_PCIEGen3; | |
3209 | ||
3210 | data->pcie_lane_performance.max = 0; | |
3211 | data->pcie_lane_performance.min = 16; | |
3212 | data->pcie_lane_power_saving.max = 0; | |
3213 | data->pcie_lane_power_saving.min = 16; | |
3214 | ||
3215 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3216 | PHM_PlatformCaps_SclkThrottleLowNotification); | |
3217 | } | |
3218 | ||
3219 | static int iceland_get_evv_voltage(struct pp_hwmgr *hwmgr) | |
3220 | { | |
3221 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
3222 | uint16_t virtual_voltage_id; | |
3223 | uint16_t vddc = 0; | |
3224 | uint16_t i; | |
3225 | ||
3226 | /* the count indicates actual number of entries */ | |
3227 | data->vddc_leakage.count = 0; | |
3228 | data->vddci_leakage.count = 0; | |
3229 | ||
3230 | if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) { | |
3231 | pr_err("Iceland should always support EVV\n"); | |
3232 | return -EINVAL; | |
3233 | } | |
3234 | ||
3235 | /* retrieve voltage for leakage ID (0xff01 + i) */ | |
3236 | for (i = 0; i < ICELAND_MAX_LEAKAGE_COUNT; i++) { | |
3237 | virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; | |
3238 | ||
3239 | PP_ASSERT_WITH_CODE((0 == atomctrl_get_voltage_evv(hwmgr, virtual_voltage_id, &vddc)), | |
3240 | "Error retrieving EVV voltage value!\n", continue); | |
3241 | ||
3242 | if (vddc >= 2000) | |
3243 | pr_warning("Invalid VDDC value!\n"); | |
3244 | ||
3245 | if (vddc != 0 && vddc != virtual_voltage_id) { | |
3246 | data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; | |
3247 | data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; | |
3248 | data->vddc_leakage.count++; | |
3249 | } | |
3250 | } | |
3251 | ||
3252 | return 0; | |
3253 | } | |
3254 | ||
3255 | static void iceland_patch_with_vddc_leakage(struct pp_hwmgr *hwmgr, | |
3256 | uint32_t *vddc) | |
3257 | { | |
3258 | iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
3259 | uint32_t leakage_index; | |
3260 | struct phw_iceland_leakage_voltage *leakage_table = &data->vddc_leakage; | |
3261 | ||
3262 | /* search for leakage voltage ID 0xff01 ~ 0xff08 */ | |
3263 | for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { | |
3264 | /* | |
3265 | * If this voltage matches a leakage voltage ID, patch | |
3266 | * with actual leakage voltage. | |
3267 | */ | |
3268 | if (leakage_table->leakage_id[leakage_index] == *vddc) { | |
3269 | /* | |
3270 | * Need to make sure vddc is less than 2v or | |
3271 | * else, it could burn the ASIC. | |
3272 | */ | |
3273 | if (leakage_table->actual_voltage[leakage_index] >= 2000) | |
3274 | pr_warning("Invalid VDDC value!\n"); | |
3275 | *vddc = leakage_table->actual_voltage[leakage_index]; | |
3276 | /* we found leakage voltage */ | |
3277 | break; | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | if (*vddc >= ATOM_VIRTUAL_VOLTAGE_ID0) | |
3282 | pr_warning("Voltage value looks like a Leakage ID but it's not patched\n"); | |
3283 | } | |
3284 | ||
3285 | static void iceland_patch_with_vddci_leakage(struct pp_hwmgr *hwmgr, | |
3286 | uint32_t *vddci) | |
3287 | { | |
3288 | iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
3289 | uint32_t leakage_index; | |
3290 | struct phw_iceland_leakage_voltage *leakage_table = &data->vddci_leakage; | |
3291 | ||
3292 | /* search for leakage voltage ID 0xff01 ~ 0xff08 */ | |
3293 | for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { | |
3294 | /* | |
3295 | * If this voltage matches a leakage voltage ID, patch | |
3296 | * with actual leakage voltage. | |
3297 | */ | |
3298 | if (leakage_table->leakage_id[leakage_index] == *vddci) { | |
3299 | *vddci = leakage_table->actual_voltage[leakage_index]; | |
3300 | /* we found leakage voltage */ | |
3301 | break; | |
3302 | } | |
3303 | } | |
3304 | ||
3305 | if (*vddci >= ATOM_VIRTUAL_VOLTAGE_ID0) | |
3306 | pr_warning("Voltage value looks like a Leakage ID but it's not patched\n"); | |
3307 | } | |
3308 | ||
3309 | static int iceland_patch_vddc(struct pp_hwmgr *hwmgr, | |
3310 | struct phm_clock_voltage_dependency_table *tab) | |
3311 | { | |
3312 | uint16_t i; | |
3313 | ||
3314 | if (tab) | |
3315 | for (i = 0; i < tab->count; i++) | |
3316 | iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v); | |
3317 | ||
3318 | return 0; | |
3319 | } | |
3320 | ||
3321 | static int iceland_patch_vddci(struct pp_hwmgr *hwmgr, | |
3322 | struct phm_clock_voltage_dependency_table *tab) | |
3323 | { | |
3324 | uint16_t i; | |
3325 | ||
3326 | if (tab) | |
3327 | for (i = 0; i < tab->count; i++) | |
3328 | iceland_patch_with_vddci_leakage(hwmgr, &tab->entries[i].v); | |
3329 | ||
3330 | return 0; | |
3331 | } | |
3332 | ||
3333 | static int iceland_patch_vce_vddc(struct pp_hwmgr *hwmgr, | |
3334 | struct phm_vce_clock_voltage_dependency_table *tab) | |
3335 | { | |
3336 | uint16_t i; | |
3337 | ||
3338 | if (tab) | |
3339 | for (i = 0; i < tab->count; i++) | |
3340 | iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v); | |
3341 | ||
3342 | return 0; | |
3343 | } | |
3344 | ||
3345 | ||
3346 | static int iceland_patch_uvd_vddc(struct pp_hwmgr *hwmgr, | |
3347 | struct phm_uvd_clock_voltage_dependency_table *tab) | |
3348 | { | |
3349 | uint16_t i; | |
3350 | ||
3351 | if (tab) | |
3352 | for (i = 0; i < tab->count; i++) | |
3353 | iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v); | |
3354 | ||
3355 | return 0; | |
3356 | } | |
3357 | ||
3358 | static int iceland_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, | |
3359 | struct phm_phase_shedding_limits_table *tab) | |
3360 | { | |
3361 | uint16_t i; | |
3362 | ||
3363 | if (tab) | |
3364 | for (i = 0; i < tab->count; i++) | |
3365 | iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].Voltage); | |
3366 | ||
3367 | return 0; | |
3368 | } | |
3369 | ||
3370 | static int iceland_patch_samu_vddc(struct pp_hwmgr *hwmgr, | |
3371 | struct phm_samu_clock_voltage_dependency_table *tab) | |
3372 | { | |
3373 | uint16_t i; | |
3374 | ||
3375 | if (tab) | |
3376 | for (i = 0; i < tab->count; i++) | |
3377 | iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v); | |
3378 | ||
3379 | return 0; | |
3380 | } | |
3381 | ||
3382 | static int iceland_patch_acp_vddc(struct pp_hwmgr *hwmgr, | |
3383 | struct phm_acp_clock_voltage_dependency_table *tab) | |
3384 | { | |
3385 | uint16_t i; | |
3386 | ||
3387 | if (tab) | |
3388 | for (i = 0; i < tab->count; i++) | |
3389 | iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v); | |
3390 | ||
3391 | return 0; | |
3392 | } | |
3393 | ||
3394 | static int iceland_patch_limits_vddc(struct pp_hwmgr *hwmgr, | |
3395 | struct phm_clock_and_voltage_limits *tab) | |
3396 | { | |
3397 | if (tab) { | |
3398 | iceland_patch_with_vddc_leakage(hwmgr, (uint32_t *)&tab->vddc); | |
3399 | iceland_patch_with_vddci_leakage(hwmgr, (uint32_t *)&tab->vddci); | |
3400 | } | |
3401 | ||
3402 | return 0; | |
3403 | } | |
3404 | ||
3405 | static int iceland_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) | |
3406 | { | |
3407 | uint32_t i; | |
3408 | uint32_t vddc; | |
3409 | ||
3410 | if (tab) { | |
3411 | for (i = 0; i < tab->count; i++) { | |
3412 | vddc = (uint32_t)(tab->entries[i].Vddc); | |
3413 | iceland_patch_with_vddc_leakage(hwmgr, &vddc); | |
3414 | tab->entries[i].Vddc = (uint16_t)vddc; | |
3415 | } | |
3416 | } | |
3417 | ||
3418 | return 0; | |
3419 | } | |
3420 | ||
3421 | static int iceland_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) | |
3422 | { | |
3423 | int tmp; | |
3424 | ||
3425 | tmp = iceland_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); | |
3426 | if(tmp) | |
3427 | return -EINVAL; | |
3428 | ||
3429 | tmp = iceland_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); | |
3430 | if(tmp) | |
3431 | return -EINVAL; | |
3432 | ||
3433 | tmp = iceland_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); | |
3434 | if(tmp) | |
3435 | return -EINVAL; | |
3436 | ||
3437 | tmp = iceland_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); | |
3438 | if(tmp) | |
3439 | return -EINVAL; | |
3440 | ||
3441 | tmp = iceland_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); | |
3442 | if(tmp) | |
3443 | return -EINVAL; | |
3444 | ||
3445 | tmp = iceland_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); | |
3446 | if(tmp) | |
3447 | return -EINVAL; | |
3448 | ||
3449 | tmp = iceland_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); | |
3450 | if(tmp) | |
3451 | return -EINVAL; | |
3452 | ||
3453 | tmp = iceland_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); | |
3454 | if(tmp) | |
3455 | return -EINVAL; | |
3456 | ||
3457 | tmp = iceland_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); | |
3458 | if(tmp) | |
3459 | return -EINVAL; | |
3460 | ||
3461 | tmp = iceland_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); | |
3462 | if(tmp) | |
3463 | return -EINVAL; | |
3464 | ||
3465 | tmp = iceland_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); | |
3466 | if(tmp) | |
3467 | return -EINVAL; | |
3468 | ||
3469 | tmp = iceland_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); | |
3470 | if(tmp) | |
3471 | return -EINVAL; | |
3472 | ||
3473 | return 0; | |
3474 | } | |
3475 | ||
3476 | static int iceland_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr) | |
3477 | { | |
3478 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
3479 | ||
3480 | struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; | |
3481 | struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; | |
3482 | struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; | |
3483 | ||
3484 | PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, | |
3485 | "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL); | |
3486 | PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, | |
3487 | "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL); | |
3488 | ||
3489 | PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, | |
3490 | "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL); | |
3491 | PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, | |
3492 | "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL); | |
3493 | ||
3494 | data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vddc_table->entries[0].v; | |
3495 | data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; | |
3496 | ||
3497 | hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = | |
3498 | allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; | |
3499 | hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = | |
3500 | allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; | |
3501 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = | |
3502 | allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; | |
3503 | ||
3504 | if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) { | |
3505 | data->min_vddci_in_pp_table = (uint16_t)allowed_mclk_vddci_table->entries[0].v; | |
3506 | data->max_vddci_in_pp_table = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; | |
3507 | } | |
3508 | ||
3509 | if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1) | |
3510 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; | |
3511 | ||
3512 | return 0; | |
3513 | } | |
3514 | ||
3515 | static int iceland_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr) | |
3516 | { | |
3517 | uint32_t table_size; | |
3518 | struct phm_clock_voltage_dependency_table *table_clk_vlt; | |
3519 | ||
3520 | hwmgr->dyn_state.mclk_sclk_ratio = 4; | |
3521 | hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */ | |
3522 | hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */ | |
3523 | ||
3524 | /* initialize vddc_dep_on_dal_pwrl table */ | |
3525 | table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record); | |
3526 | table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL); | |
3527 | ||
3528 | if (NULL == table_clk_vlt) { | |
3529 | pr_err("[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n"); | |
3530 | return -ENOMEM; | |
3531 | } else { | |
3532 | table_clk_vlt->count = 4; | |
3533 | table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; | |
3534 | table_clk_vlt->entries[0].v = 0; | |
3535 | table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; | |
3536 | table_clk_vlt->entries[1].v = 720; | |
3537 | table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; | |
3538 | table_clk_vlt->entries[2].v = 810; | |
3539 | table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; | |
3540 | table_clk_vlt->entries[3].v = 900; | |
3541 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; | |
3542 | } | |
3543 | ||
3544 | return 0; | |
3545 | } | |
3546 | ||
3547 | /** | |
3548 | * Initializes the Volcanic Islands Hardware Manager | |
3549 | * | |
3550 | * @param hwmgr the address of the powerplay hardware manager. | |
3551 | * @return 1 if success; otherwise appropriate error code. | |
3552 | */ | |
3553 | static int iceland_hwmgr_backend_init(struct pp_hwmgr *hwmgr) | |
3554 | { | |
3555 | int result = 0; | |
3556 | SMU71_Discrete_DpmTable *table = NULL; | |
3557 | iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
3558 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; | |
3559 | bool stay_in_boot; | |
3560 | struct phw_iceland_ulv_parm *ulv; | |
3561 | struct cgs_system_info sys_info = {0}; | |
3562 | ||
3563 | PP_ASSERT_WITH_CODE((NULL != hwmgr), | |
3564 | "Invalid Parameter!", return -EINVAL;); | |
3565 | ||
3566 | data->dll_defaule_on = 0; | |
3567 | data->sram_end = SMC_RAM_END; | |
3568 | ||
3569 | data->activity_target[0] = PPICELAND_TARGETACTIVITY_DFLT; | |
3570 | data->activity_target[1] = PPICELAND_TARGETACTIVITY_DFLT; | |
3571 | data->activity_target[2] = PPICELAND_TARGETACTIVITY_DFLT; | |
3572 | data->activity_target[3] = PPICELAND_TARGETACTIVITY_DFLT; | |
3573 | data->activity_target[4] = PPICELAND_TARGETACTIVITY_DFLT; | |
3574 | data->activity_target[5] = PPICELAND_TARGETACTIVITY_DFLT; | |
3575 | data->activity_target[6] = PPICELAND_TARGETACTIVITY_DFLT; | |
3576 | data->activity_target[7] = PPICELAND_TARGETACTIVITY_DFLT; | |
3577 | ||
3578 | data->mclk_activity_target = PPICELAND_MCLK_TARGETACTIVITY_DFLT; | |
3579 | ||
3580 | data->sclk_dpm_key_disabled = 0; | |
3581 | data->mclk_dpm_key_disabled = 0; | |
3582 | data->pcie_dpm_key_disabled = 0; | |
3583 | data->pcc_monitor_enabled = 0; | |
3584 | ||
3585 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3586 | PHM_PlatformCaps_UnTabledHardwareInterface); | |
3587 | ||
3588 | data->gpio_debug = 0; | |
3589 | data->engine_clock_data = 0; | |
3590 | data->memory_clock_data = 0; | |
3591 | ||
3592 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3593 | PHM_PlatformCaps_SclkDeepSleep); | |
3594 | ||
3595 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3596 | PHM_PlatformCaps_SclkDeepSleepAboveLow); | |
3597 | ||
3598 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3599 | PHM_PlatformCaps_DynamicPatchPowerState); | |
3600 | ||
3601 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3602 | PHM_PlatformCaps_TablelessHardwareInterface); | |
3603 | ||
3604 | /* Initializes DPM default values. */ | |
3605 | iceland_initialize_dpm_defaults(hwmgr); | |
3606 | ||
3607 | /* Enable Platform EVV support. */ | |
3608 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3609 | PHM_PlatformCaps_EVV); | |
3610 | ||
3611 | /* Get leakage voltage based on leakage ID. */ | |
3612 | result = iceland_get_evv_voltage(hwmgr); | |
3613 | if (result) | |
3614 | goto failed; | |
3615 | ||
3616 | /** | |
3617 | * Patch our voltage dependency table with actual leakage | |
3618 | * voltage. We need to perform leakage translation before it's | |
3619 | * used by other functions such as | |
3620 | * iceland_set_hwmgr_variables_based_on_pptable. | |
3621 | */ | |
3622 | result = iceland_patch_dependency_tables_with_leakage(hwmgr); | |
3623 | if (result) | |
3624 | goto failed; | |
3625 | ||
3626 | /* Parse pptable data read from VBIOS. */ | |
3627 | result = iceland_set_private_var_based_on_pptale(hwmgr); | |
3628 | if (result) | |
3629 | goto failed; | |
3630 | ||
3631 | /* ULV support */ | |
3632 | ulv = &(data->ulv); | |
3633 | ulv->ulv_supported = 1; | |
3634 | ||
3635 | /* Initalize Dynamic State Adjustment Rule Settings*/ | |
3636 | result = iceland_initializa_dynamic_state_adjustment_rule_settings(hwmgr); | |
3637 | if (result) { | |
3638 | pr_err("[ powerplay ] iceland_initializa_dynamic_state_adjustment_rule_settings failed!\n"); | |
3639 | goto failed; | |
3640 | } | |
3641 | ||
3642 | data->voltage_control = ICELAND_VOLTAGE_CONTROL_NONE; | |
3643 | data->vdd_ci_control = ICELAND_VOLTAGE_CONTROL_NONE; | |
3644 | data->mvdd_control = ICELAND_VOLTAGE_CONTROL_NONE; | |
3645 | ||
3646 | /* | |
3647 | * Hardcode thermal temperature settings for now, these will | |
3648 | * be overwritten if a custom policy exists. | |
3649 | */ | |
3650 | data->thermal_temp_setting.temperature_low = 99500; | |
3651 | data->thermal_temp_setting.temperature_high = 100000; | |
3652 | data->thermal_temp_setting.temperature_shutdown = 104000; | |
3653 | data->uvd_enabled = false; | |
3654 | ||
3655 | table = &data->smc_state_table; | |
3656 | ||
3657 | if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, | |
3658 | &gpio_pin_assignment)) { | |
3659 | table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; | |
3660 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3661 | PHM_PlatformCaps_RegulatorHot); | |
3662 | } else { | |
3663 | table->VRHotGpio = ICELAND_UNUSED_GPIO_PIN; | |
3664 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3665 | PHM_PlatformCaps_RegulatorHot); | |
3666 | } | |
3667 | ||
3668 | if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, | |
3669 | &gpio_pin_assignment)) { | |
3670 | table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; | |
3671 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3672 | PHM_PlatformCaps_AutomaticDCTransition); | |
3673 | } else { | |
3674 | table->AcDcGpio = ICELAND_UNUSED_GPIO_PIN; | |
3675 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3676 | PHM_PlatformCaps_AutomaticDCTransition); | |
3677 | } | |
3678 | ||
3679 | /* | |
3680 | * If ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak. | |
3681 | * Current Control feature is enabled and we should program | |
3682 | * PCC HW register | |
3683 | */ | |
3684 | if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, | |
3685 | &gpio_pin_assignment)) { | |
3686 | uint32_t temp_reg = cgs_read_ind_register(hwmgr->device, | |
3687 | CGS_IND_REG__SMC, | |
3688 | ixCNB_PWRMGT_CNTL); | |
3689 | ||
3690 | switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { | |
3691 | case 0: | |
3692 | temp_reg = PHM_SET_FIELD(temp_reg, | |
3693 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); | |
3694 | break; | |
3695 | case 1: | |
3696 | temp_reg = PHM_SET_FIELD(temp_reg, | |
3697 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); | |
3698 | break; | |
3699 | case 2: | |
3700 | temp_reg = PHM_SET_FIELD(temp_reg, | |
3701 | CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); | |
3702 | break; | |
3703 | case 3: | |
3704 | temp_reg = PHM_SET_FIELD(temp_reg, | |
3705 | CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); | |
3706 | break; | |
3707 | case 4: | |
3708 | temp_reg = PHM_SET_FIELD(temp_reg, | |
3709 | CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); | |
3710 | break; | |
3711 | default: | |
3712 | pr_warning("[ powerplay ] Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!\n"); | |
3713 | break; | |
3714 | } | |
3715 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
3716 | ixCNB_PWRMGT_CNTL, temp_reg); | |
3717 | } | |
3718 | ||
3719 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3720 | PHM_PlatformCaps_EnableSMU7ThermalManagement); | |
3721 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3722 | PHM_PlatformCaps_SMU7); | |
3723 | ||
3724 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, | |
3725 | VOLTAGE_TYPE_VDDC, | |
3726 | VOLTAGE_OBJ_GPIO_LUT)) | |
3727 | data->voltage_control = ICELAND_VOLTAGE_CONTROL_BY_GPIO; | |
3728 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, | |
3729 | VOLTAGE_TYPE_VDDC, | |
3730 | VOLTAGE_OBJ_SVID2)) | |
3731 | data->voltage_control = ICELAND_VOLTAGE_CONTROL_BY_SVID2; | |
3732 | ||
3733 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
3734 | PHM_PlatformCaps_ControlVDDCI)) { | |
3735 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, | |
3736 | VOLTAGE_TYPE_VDDCI, | |
3737 | VOLTAGE_OBJ_GPIO_LUT)) | |
3738 | data->vdd_ci_control = ICELAND_VOLTAGE_CONTROL_BY_GPIO; | |
3739 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, | |
3740 | VOLTAGE_TYPE_VDDCI, | |
3741 | VOLTAGE_OBJ_SVID2)) | |
3742 | data->vdd_ci_control = ICELAND_VOLTAGE_CONTROL_BY_SVID2; | |
3743 | } | |
3744 | ||
3745 | if (data->vdd_ci_control == ICELAND_VOLTAGE_CONTROL_NONE) | |
3746 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3747 | PHM_PlatformCaps_ControlVDDCI); | |
3748 | ||
3749 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
3750 | PHM_PlatformCaps_EnableMVDDControl)) { | |
3751 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, | |
3752 | VOLTAGE_TYPE_MVDDC, | |
3753 | VOLTAGE_OBJ_GPIO_LUT)) | |
3754 | data->mvdd_control = ICELAND_VOLTAGE_CONTROL_BY_GPIO; | |
3755 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, | |
3756 | VOLTAGE_TYPE_MVDDC, | |
3757 | VOLTAGE_OBJ_SVID2)) | |
3758 | data->mvdd_control = ICELAND_VOLTAGE_CONTROL_BY_SVID2; | |
3759 | } | |
3760 | ||
3761 | if (data->mvdd_control == ICELAND_VOLTAGE_CONTROL_NONE) | |
3762 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3763 | PHM_PlatformCaps_EnableMVDDControl); | |
3764 | ||
3765 | data->vddc_phase_shed_control = false; | |
3766 | ||
3767 | stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
3768 | PHM_PlatformCaps_StayInBootState); | |
3769 | ||
3770 | /* iceland doesn't support UVD and VCE */ | |
3771 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3772 | PHM_PlatformCaps_UVDPowerGating); | |
3773 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3774 | PHM_PlatformCaps_VCEPowerGating); | |
3775 | ||
3776 | sys_info.size = sizeof(struct cgs_system_info); | |
3777 | sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; | |
3778 | result = cgs_query_system_info(hwmgr->device, &sys_info); | |
3779 | if (!result) { | |
3780 | if (sys_info.value & AMD_PG_SUPPORT_UVD) | |
3781 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3782 | PHM_PlatformCaps_UVDPowerGating); | |
3783 | if (sys_info.value & AMD_PG_SUPPORT_VCE) | |
3784 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3785 | PHM_PlatformCaps_VCEPowerGating); | |
3786 | ||
3787 | data->is_tlu_enabled = false; | |
3788 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = | |
3789 | ICELAND_MAX_HARDWARE_POWERLEVELS; | |
3790 | hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; | |
3791 | hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; | |
3792 | ||
3793 | sys_info.size = sizeof(struct cgs_system_info); | |
3794 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; | |
3795 | result = cgs_query_system_info(hwmgr->device, &sys_info); | |
3796 | if (result) | |
3797 | data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3798 | else | |
3799 | data->pcie_gen_cap = (uint32_t)sys_info.value; | |
3800 | if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) | |
3801 | data->pcie_spc_cap = 20; | |
3802 | sys_info.size = sizeof(struct cgs_system_info); | |
3803 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; | |
3804 | result = cgs_query_system_info(hwmgr->device, &sys_info); | |
3805 | if (result) | |
3806 | data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
3807 | else | |
3808 | data->pcie_lane_cap = (uint32_t)sys_info.value; | |
3809 | } else { | |
3810 | /* Ignore return value in here, we are cleaning up a mess. */ | |
3811 | iceland_hwmgr_backend_fini(hwmgr); | |
3812 | } | |
3813 | ||
3814 | return 0; | |
3815 | failed: | |
3816 | return result; | |
3817 | } | |
3818 | ||
3819 | static int iceland_get_num_of_entries(struct pp_hwmgr *hwmgr) | |
3820 | { | |
3821 | int result; | |
3822 | unsigned long ret = 0; | |
3823 | ||
3824 | result = pp_tables_get_num_of_entries(hwmgr, &ret); | |
3825 | ||
3826 | return result ? 0 : ret; | |
3827 | } | |
3828 | ||
3829 | static const unsigned long PhwIceland_Magic = (unsigned long)(PHM_VIslands_Magic); | |
3830 | ||
3831 | struct iceland_power_state *cast_phw_iceland_power_state( | |
3832 | struct pp_hw_power_state *hw_ps) | |
3833 | { | |
3834 | if (hw_ps == NULL) | |
3835 | return NULL; | |
3836 | ||
3837 | PP_ASSERT_WITH_CODE((PhwIceland_Magic == hw_ps->magic), | |
3838 | "Invalid Powerstate Type!", | |
3839 | return NULL); | |
3840 | ||
3841 | return (struct iceland_power_state *)hw_ps; | |
3842 | } | |
3843 | ||
3844 | static int iceland_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |
3845 | struct pp_power_state *prequest_ps, | |
3846 | const struct pp_power_state *pcurrent_ps) | |
3847 | { | |
3848 | struct iceland_power_state *iceland_ps = | |
3849 | cast_phw_iceland_power_state(&prequest_ps->hardware); | |
3850 | ||
3851 | uint32_t sclk; | |
3852 | uint32_t mclk; | |
3853 | struct PP_Clocks minimum_clocks = {0}; | |
3854 | bool disable_mclk_switching; | |
3855 | bool disable_mclk_switching_for_frame_lock; | |
3856 | struct cgs_display_info info = {0}; | |
3857 | const struct phm_clock_and_voltage_limits *max_limits; | |
3858 | uint32_t i; | |
3859 | iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
3860 | ||
3861 | int32_t count; | |
3862 | int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; | |
3863 | ||
3864 | data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); | |
3865 | ||
3866 | PP_ASSERT_WITH_CODE(iceland_ps->performance_level_count == 2, | |
3867 | "VI should always have 2 performance levels", | |
3868 | ); | |
3869 | ||
3870 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? | |
3871 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : | |
3872 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); | |
3873 | ||
3874 | if (PP_PowerSource_DC == hwmgr->power_source) { | |
3875 | for (i = 0; i < iceland_ps->performance_level_count; i++) { | |
3876 | if (iceland_ps->performance_levels[i].memory_clock > max_limits->mclk) | |
3877 | iceland_ps->performance_levels[i].memory_clock = max_limits->mclk; | |
3878 | if (iceland_ps->performance_levels[i].engine_clock > max_limits->sclk) | |
3879 | iceland_ps->performance_levels[i].engine_clock = max_limits->sclk; | |
3880 | } | |
3881 | } | |
3882 | ||
3883 | iceland_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk; | |
3884 | iceland_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk; | |
3885 | ||
3886 | cgs_get_active_displays_info(hwmgr->device, &info); | |
3887 | ||
3888 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { | |
3889 | ||
3890 | max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); | |
3891 | stable_pstate_sclk = (max_limits->sclk * 75) / 100; | |
3892 | ||
3893 | for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; count >= 0; count--) { | |
3894 | if (stable_pstate_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { | |
3895 | stable_pstate_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; | |
3896 | break; | |
3897 | } | |
3898 | } | |
3899 | ||
3900 | if (count < 0) | |
3901 | stable_pstate_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; | |
3902 | ||
3903 | stable_pstate_mclk = max_limits->mclk; | |
3904 | ||
3905 | minimum_clocks.engineClock = stable_pstate_sclk; | |
3906 | minimum_clocks.memoryClock = stable_pstate_mclk; | |
3907 | } | |
3908 | ||
3909 | if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) | |
3910 | minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; | |
3911 | ||
3912 | if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) | |
3913 | minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; | |
3914 | ||
3915 | iceland_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; | |
3916 | ||
3917 | if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { | |
3918 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock), | |
3919 | "Overdrive sclk exceeds limit", | |
3920 | hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock); | |
3921 | ||
3922 | if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) | |
3923 | iceland_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive; | |
3924 | } | |
3925 | ||
3926 | if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { | |
3927 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock), | |
3928 | "Overdrive mclk exceeds limit", | |
3929 | hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock); | |
3930 | ||
3931 | if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) | |
3932 | iceland_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive; | |
3933 | } | |
3934 | ||
3935 | disable_mclk_switching_for_frame_lock = phm_cap_enabled( | |
3936 | hwmgr->platform_descriptor.platformCaps, | |
3937 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); | |
3938 | ||
3939 | disable_mclk_switching = (1 < info.display_count) || | |
3940 | disable_mclk_switching_for_frame_lock; | |
3941 | ||
3942 | sclk = iceland_ps->performance_levels[0].engine_clock; | |
3943 | mclk = iceland_ps->performance_levels[0].memory_clock; | |
3944 | ||
3945 | if (disable_mclk_switching) | |
3946 | mclk = iceland_ps->performance_levels[iceland_ps->performance_level_count - 1].memory_clock; | |
3947 | ||
3948 | if (sclk < minimum_clocks.engineClock) | |
3949 | sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock; | |
3950 | ||
3951 | if (mclk < minimum_clocks.memoryClock) | |
3952 | mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock; | |
3953 | ||
3954 | iceland_ps->performance_levels[0].engine_clock = sclk; | |
3955 | iceland_ps->performance_levels[0].memory_clock = mclk; | |
3956 | ||
3957 | iceland_ps->performance_levels[1].engine_clock = | |
3958 | (iceland_ps->performance_levels[1].engine_clock >= iceland_ps->performance_levels[0].engine_clock) ? | |
3959 | iceland_ps->performance_levels[1].engine_clock : | |
3960 | iceland_ps->performance_levels[0].engine_clock; | |
3961 | ||
3962 | if (disable_mclk_switching) { | |
3963 | if (mclk < iceland_ps->performance_levels[1].memory_clock) | |
3964 | mclk = iceland_ps->performance_levels[1].memory_clock; | |
3965 | ||
3966 | iceland_ps->performance_levels[0].memory_clock = mclk; | |
3967 | iceland_ps->performance_levels[1].memory_clock = mclk; | |
3968 | } else { | |
3969 | if (iceland_ps->performance_levels[1].memory_clock < iceland_ps->performance_levels[0].memory_clock) | |
3970 | iceland_ps->performance_levels[1].memory_clock = iceland_ps->performance_levels[0].memory_clock; | |
3971 | } | |
3972 | ||
3973 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { | |
3974 | for (i=0; i < iceland_ps->performance_level_count; i++) { | |
3975 | iceland_ps->performance_levels[i].engine_clock = stable_pstate_sclk; | |
3976 | iceland_ps->performance_levels[i].memory_clock = stable_pstate_mclk; | |
3977 | iceland_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; | |
3978 | iceland_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; | |
3979 | } | |
3980 | } | |
3981 | ||
3982 | return 0; | |
3983 | } | |
3984 | ||
3985 | static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr) | |
3986 | { | |
3987 | /* | |
3988 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM | |
3989 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, | |
3990 | * whereas voltage control is a fundemental change that will not be disabled | |
3991 | */ | |
3992 | return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
3993 | FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0); | |
3994 | } | |
3995 | ||
3996 | /** | |
3997 | * force DPM power State | |
3998 | * | |
3999 | * @param hwmgr: the address of the powerplay hardware manager. | |
4000 | * @param n : DPM level | |
4001 | * @return The response that came from the SMC. | |
4002 | */ | |
4003 | int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) | |
4004 | { | |
4005 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4006 | ||
4007 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ | |
4008 | PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr), | |
4009 | "Trying to force SCLK when DPM is disabled", return -1;); | |
4010 | if (0 == data->sclk_dpm_key_disabled) | |
4011 | return (0 == smum_send_msg_to_smc_with_parameter( | |
4012 | hwmgr->smumgr, | |
4013 | PPSMC_MSG_DPM_ForceState, | |
4014 | n) ? 0 : 1); | |
4015 | ||
4016 | return 0; | |
4017 | } | |
4018 | ||
4019 | /** | |
4020 | * force DPM power State | |
4021 | * | |
4022 | * @param hwmgr: the address of the powerplay hardware manager. | |
4023 | * @param n : DPM level | |
4024 | * @return The response that came from the SMC. | |
4025 | */ | |
4026 | int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) | |
4027 | { | |
4028 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4029 | ||
4030 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ | |
4031 | PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr), | |
4032 | "Trying to Force MCLK when DPM is disabled", return -1;); | |
4033 | if (0 == data->mclk_dpm_key_disabled) | |
4034 | return (0 == smum_send_msg_to_smc_with_parameter( | |
4035 | hwmgr->smumgr, | |
4036 | PPSMC_MSG_MCLKDPM_ForceState, | |
4037 | n) ? 0 : 1); | |
4038 | ||
4039 | return 0; | |
4040 | } | |
4041 | ||
4042 | /** | |
4043 | * force DPM power State | |
4044 | * | |
4045 | * @param hwmgr: the address of the powerplay hardware manager. | |
4046 | * @param n : DPM level | |
4047 | * @return The response that came from the SMC. | |
4048 | */ | |
4049 | int iceland_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) | |
4050 | { | |
4051 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4052 | ||
4053 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
4054 | PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr), | |
4055 | "Trying to Force PCIE level when DPM is disabled", return -1;); | |
4056 | if (0 == data->pcie_dpm_key_disabled) | |
4057 | return (0 == smum_send_msg_to_smc_with_parameter( | |
4058 | hwmgr->smumgr, | |
4059 | PPSMC_MSG_PCIeDPM_ForceLevel, | |
4060 | n) ? 0 : 1); | |
4061 | ||
4062 | return 0; | |
4063 | } | |
4064 | ||
4065 | static int iceland_force_dpm_highest(struct pp_hwmgr *hwmgr) | |
4066 | { | |
4067 | uint32_t level, tmp; | |
4068 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4069 | ||
4070 | if (0 == data->sclk_dpm_key_disabled) { | |
4071 | /* SCLK */ | |
4072 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) { | |
4073 | level = 0; | |
4074 | tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; | |
4075 | while (tmp >>= 1) | |
4076 | level++ ; | |
4077 | ||
4078 | if (0 != level) { | |
4079 | PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state(hwmgr, level)), | |
4080 | "force highest sclk dpm state failed!", return -1); | |
4081 | PHM_WAIT_INDIRECT_FIELD(hwmgr->device, | |
4082 | SMC_IND, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX, level); | |
4083 | } | |
4084 | } | |
4085 | } | |
4086 | ||
4087 | if (0 == data->mclk_dpm_key_disabled) { | |
4088 | /* MCLK */ | |
4089 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { | |
4090 | level = 0; | |
4091 | tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; | |
4092 | while (tmp >>= 1) | |
4093 | level++ ; | |
4094 | ||
4095 | if (0 != level) { | |
4096 | PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state_mclk(hwmgr, level)), | |
4097 | "force highest mclk dpm state failed!", return -1); | |
4098 | PHM_WAIT_INDIRECT_FIELD(hwmgr->device, SMC_IND, | |
4099 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX, level); | |
4100 | } | |
4101 | } | |
4102 | } | |
4103 | ||
4104 | if (0 == data->pcie_dpm_key_disabled) { | |
4105 | /* PCIE */ | |
4106 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { | |
4107 | level = 0; | |
4108 | tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; | |
4109 | while (tmp >>= 1) | |
4110 | level++ ; | |
4111 | ||
4112 | if (0 != level) { | |
4113 | PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state_pcie(hwmgr, level)), | |
4114 | "force highest pcie dpm state failed!", return -1); | |
4115 | } | |
4116 | } | |
4117 | } | |
4118 | ||
4119 | return 0; | |
4120 | } | |
4121 | ||
4122 | static uint32_t iceland_get_lowest_enable_level(struct pp_hwmgr *hwmgr, | |
4123 | uint32_t level_mask) | |
4124 | { | |
4125 | uint32_t level = 0; | |
4126 | ||
4127 | while (0 == (level_mask & (1 << level))) | |
4128 | level++; | |
4129 | ||
4130 | return level; | |
4131 | } | |
4132 | ||
4133 | static int iceland_force_dpm_lowest(struct pp_hwmgr *hwmgr) | |
4134 | { | |
4135 | uint32_t level; | |
4136 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4137 | ||
4138 | /* for now force only sclk */ | |
4139 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { | |
4140 | level = iceland_get_lowest_enable_level(hwmgr, | |
4141 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); | |
4142 | ||
4143 | PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state(hwmgr, level)), | |
4144 | "force sclk dpm state failed!", return -1); | |
4145 | ||
4146 | PHM_WAIT_INDIRECT_FIELD(hwmgr->device, SMC_IND, | |
4147 | TARGET_AND_CURRENT_PROFILE_INDEX, | |
4148 | CURR_SCLK_INDEX, | |
4149 | level); | |
4150 | } | |
4151 | ||
4152 | return 0; | |
4153 | } | |
4154 | ||
4155 | int iceland_unforce_dpm_levels(struct pp_hwmgr *hwmgr) | |
4156 | { | |
4157 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4158 | ||
4159 | #if 0 | |
4160 | PP_ASSERT_WITH_CODE (0 == iceland_is_dpm_running(hwmgr), | |
4161 | "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.", | |
4162 | return -1); | |
4163 | #endif | |
4164 | ||
4165 | if (0 == data->sclk_dpm_key_disabled) { | |
4166 | PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( | |
4167 | hwmgr->smumgr, | |
4168 | PPSMC_MSG_NoForcedLevel)), | |
4169 | "unforce sclk dpm state failed!", | |
4170 | return -1); | |
4171 | } | |
4172 | ||
4173 | if (0 == data->pcie_dpm_key_disabled) { | |
4174 | PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( | |
4175 | hwmgr->smumgr, | |
4176 | PPSMC_MSG_MCLKDPM_NoForcedLevel)), | |
4177 | "unforce mclk dpm state failed!", | |
4178 | return -1); | |
4179 | } | |
4180 | ||
4181 | if (0 == data->pcie_dpm_key_disabled) { | |
4182 | PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( | |
4183 | hwmgr->smumgr, | |
4184 | PPSMC_MSG_PCIeDPM_UnForceLevel)), | |
4185 | "unforce pcie level failed!", | |
4186 | return -1); | |
4187 | } | |
4188 | ||
4189 | return 0; | |
4190 | } | |
4191 | ||
4192 | static int iceland_force_dpm_level(struct pp_hwmgr *hwmgr, | |
4193 | enum amd_dpm_forced_level level) | |
4194 | { | |
4195 | int ret = 0; | |
4196 | ||
4197 | switch (level) { | |
4198 | case AMD_DPM_FORCED_LEVEL_HIGH: | |
4199 | ret = iceland_force_dpm_highest(hwmgr); | |
4200 | if (ret) | |
4201 | return ret; | |
4202 | break; | |
4203 | case AMD_DPM_FORCED_LEVEL_LOW: | |
4204 | ret = iceland_force_dpm_lowest(hwmgr); | |
4205 | if (ret) | |
4206 | return ret; | |
4207 | break; | |
4208 | case AMD_DPM_FORCED_LEVEL_AUTO: | |
4209 | ret = iceland_unforce_dpm_levels(hwmgr); | |
4210 | if (ret) | |
4211 | return ret; | |
4212 | break; | |
4213 | default: | |
4214 | break; | |
4215 | } | |
4216 | ||
4217 | hwmgr->dpm_level = level; | |
4218 | return ret; | |
4219 | } | |
4220 | ||
4221 | const struct iceland_power_state *cast_const_phw_iceland_power_state( | |
4222 | const struct pp_hw_power_state *hw_ps) | |
4223 | { | |
4224 | if (hw_ps == NULL) | |
4225 | return NULL; | |
4226 | ||
4227 | PP_ASSERT_WITH_CODE((PhwIceland_Magic == hw_ps->magic), | |
4228 | "Invalid Powerstate Type!", | |
4229 | return NULL); | |
4230 | ||
4231 | return (const struct iceland_power_state *)hw_ps; | |
4232 | } | |
4233 | ||
4234 | static int iceland_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) | |
4235 | { | |
4236 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
4237 | const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state); | |
4238 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4239 | struct iceland_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table); | |
4240 | uint32_t sclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].engine_clock; | |
4241 | struct iceland_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table); | |
4242 | uint32_t mclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].memory_clock; | |
4243 | struct PP_Clocks min_clocks = {0}; | |
4244 | uint32_t i; | |
4245 | struct cgs_display_info info = {0}; | |
4246 | ||
4247 | data->need_update_smu7_dpm_table = 0; | |
4248 | ||
4249 | for (i = 0; i < psclk_table->count; i++) { | |
4250 | if (sclk == psclk_table->dpm_levels[i].value) | |
4251 | break; | |
4252 | } | |
4253 | ||
4254 | if (i >= psclk_table->count) | |
4255 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; | |
4256 | else { | |
4257 | /* | |
4258 | * TODO: Check SCLK in DAL's minimum clocks in case DeepSleep | |
4259 | * divider update is required. | |
4260 | */ | |
4261 | if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR) | |
4262 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; | |
4263 | } | |
4264 | ||
4265 | for (i = 0; i < pmclk_table->count; i++) { | |
4266 | if (mclk == pmclk_table->dpm_levels[i].value) | |
4267 | break; | |
4268 | } | |
4269 | ||
4270 | if (i >= pmclk_table->count) | |
4271 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; | |
4272 | ||
4273 | cgs_get_active_displays_info(hwmgr->device, &info); | |
4274 | ||
4275 | if (data->display_timing.num_existing_displays != info.display_count) | |
4276 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; | |
4277 | ||
4278 | return 0; | |
4279 | } | |
4280 | ||
4281 | static uint16_t iceland_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct iceland_power_state *hw_ps) | |
4282 | { | |
4283 | uint32_t i; | |
4284 | uint32_t pcie_speed, max_speed = 0; | |
4285 | ||
4286 | for (i = 0; i < hw_ps->performance_level_count; i++) { | |
4287 | pcie_speed = hw_ps->performance_levels[i].pcie_gen; | |
4288 | if (max_speed < pcie_speed) | |
4289 | max_speed = pcie_speed; | |
4290 | } | |
4291 | ||
4292 | return max_speed; | |
4293 | } | |
4294 | ||
4295 | static uint16_t iceland_get_current_pcie_speed(struct pp_hwmgr *hwmgr) | |
4296 | { | |
4297 | uint32_t speed_cntl = 0; | |
4298 | ||
4299 | speed_cntl = cgs_read_ind_register(hwmgr->device, | |
4300 | CGS_IND_REG__PCIE, | |
4301 | ixPCIE_LC_SPEED_CNTL); | |
4302 | return((uint16_t)PHM_GET_FIELD(speed_cntl, | |
4303 | PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); | |
4304 | } | |
4305 | ||
4306 | ||
4307 | static int iceland_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input) | |
4308 | { | |
4309 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
4310 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4311 | const struct iceland_power_state *iceland_nps = cast_const_phw_iceland_power_state(states->pnew_state); | |
4312 | const struct iceland_power_state *iceland_cps = cast_const_phw_iceland_power_state(states->pcurrent_state); | |
4313 | ||
4314 | uint16_t target_link_speed = iceland_get_maximum_link_speed(hwmgr, iceland_nps); | |
4315 | uint16_t current_link_speed; | |
4316 | ||
4317 | if (data->force_pcie_gen == PP_PCIEGenInvalid) | |
4318 | current_link_speed = iceland_get_maximum_link_speed(hwmgr, iceland_cps); | |
4319 | else | |
4320 | current_link_speed = data->force_pcie_gen; | |
4321 | ||
4322 | data->force_pcie_gen = PP_PCIEGenInvalid; | |
4323 | data->pspp_notify_required = false; | |
4324 | if (target_link_speed > current_link_speed) { | |
4325 | switch(target_link_speed) { | |
4326 | case PP_PCIEGen3: | |
4327 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) | |
4328 | break; | |
4329 | data->force_pcie_gen = PP_PCIEGen2; | |
4330 | if (current_link_speed == PP_PCIEGen2) | |
4331 | break; | |
4332 | case PP_PCIEGen2: | |
4333 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) | |
4334 | break; | |
4335 | default: | |
4336 | data->force_pcie_gen = iceland_get_current_pcie_speed(hwmgr); | |
4337 | break; | |
4338 | } | |
4339 | } else { | |
4340 | if (target_link_speed < current_link_speed) | |
4341 | data->pspp_notify_required = true; | |
4342 | } | |
4343 | ||
4344 | return 0; | |
4345 | } | |
4346 | ||
4347 | static int iceland_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
4348 | { | |
4349 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4350 | ||
4351 | if (0 == data->need_update_smu7_dpm_table) | |
4352 | return 0; | |
4353 | ||
4354 | if ((0 == data->sclk_dpm_key_disabled) && | |
4355 | (data->need_update_smu7_dpm_table & | |
4356 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { | |
4357 | PP_ASSERT_WITH_CODE( | |
4358 | 0 == iceland_is_dpm_running(hwmgr), | |
4359 | "Trying to freeze SCLK DPM when DPM is disabled", | |
4360 | ); | |
4361 | PP_ASSERT_WITH_CODE( | |
4362 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
4363 | PPSMC_MSG_SCLKDPM_FreezeLevel), | |
4364 | "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", | |
4365 | return -1); | |
4366 | } | |
4367 | ||
4368 | if ((0 == data->mclk_dpm_key_disabled) && | |
4369 | (data->need_update_smu7_dpm_table & | |
4370 | DPMTABLE_OD_UPDATE_MCLK)) { | |
4371 | PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr), | |
4372 | "Trying to freeze MCLK DPM when DPM is disabled", | |
4373 | ); | |
4374 | PP_ASSERT_WITH_CODE( | |
4375 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
4376 | PPSMC_MSG_MCLKDPM_FreezeLevel), | |
4377 | "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", | |
4378 | return -1); | |
4379 | } | |
4380 | ||
4381 | return 0; | |
4382 | } | |
4383 | ||
4384 | static int iceland_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input) | |
4385 | { | |
4386 | int result = 0; | |
4387 | ||
4388 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
4389 | const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state); | |
4390 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4391 | uint32_t sclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].engine_clock; | |
4392 | uint32_t mclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].memory_clock; | |
4393 | struct iceland_dpm_table *pdpm_table = &data->dpm_table; | |
4394 | ||
4395 | struct iceland_dpm_table *pgolden_dpm_table = &data->golden_dpm_table; | |
4396 | uint32_t dpm_count, clock_percent; | |
4397 | uint32_t i; | |
4398 | ||
4399 | if (0 == data->need_update_smu7_dpm_table) | |
4400 | return 0; | |
4401 | ||
4402 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { | |
4403 | pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk; | |
4404 | ||
4405 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || | |
4406 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { | |
4407 | /* | |
4408 | * Need to do calculation based on the golden DPM table | |
4409 | * as the Heatmap GPU Clock axis is also based on the default values | |
4410 | */ | |
4411 | PP_ASSERT_WITH_CODE( | |
4412 | (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0), | |
4413 | "Divide by 0!", | |
4414 | return -1); | |
4415 | dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2; | |
4416 | for (i = dpm_count; i > 1; i--) { | |
4417 | if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) { | |
4418 | clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) / | |
4419 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; | |
4420 | ||
4421 | pdpm_table->sclk_table.dpm_levels[i].value = | |
4422 | pgolden_dpm_table->sclk_table.dpm_levels[i].value + | |
4423 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; | |
4424 | ||
4425 | } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) { | |
4426 | clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) / | |
4427 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; | |
4428 | ||
4429 | pdpm_table->sclk_table.dpm_levels[i].value = | |
4430 | pgolden_dpm_table->sclk_table.dpm_levels[i].value - | |
4431 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; | |
4432 | } else | |
4433 | pdpm_table->sclk_table.dpm_levels[i].value = | |
4434 | pgolden_dpm_table->sclk_table.dpm_levels[i].value; | |
4435 | } | |
4436 | } | |
4437 | } | |
4438 | ||
4439 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { | |
4440 | pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk; | |
4441 | ||
4442 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || | |
4443 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { | |
4444 | ||
4445 | PP_ASSERT_WITH_CODE( | |
4446 | (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0), | |
4447 | "Divide by 0!", | |
4448 | return -1); | |
4449 | dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2; | |
4450 | for (i = dpm_count; i > 1; i--) { | |
4451 | if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) { | |
4452 | clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) / | |
4453 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; | |
4454 | ||
4455 | pdpm_table->mclk_table.dpm_levels[i].value = | |
4456 | pgolden_dpm_table->mclk_table.dpm_levels[i].value + | |
4457 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; | |
4458 | ||
4459 | } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) { | |
4460 | clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) / | |
4461 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; | |
4462 | ||
4463 | pdpm_table->mclk_table.dpm_levels[i].value = | |
4464 | pgolden_dpm_table->mclk_table.dpm_levels[i].value - | |
4465 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; | |
4466 | } else | |
4467 | pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value; | |
4468 | } | |
4469 | } | |
4470 | } | |
4471 | ||
4472 | ||
4473 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { | |
4474 | result = iceland_populate_all_graphic_levels(hwmgr); | |
4475 | PP_ASSERT_WITH_CODE((0 == result), | |
4476 | "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", | |
4477 | return result); | |
4478 | } | |
4479 | ||
4480 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { | |
4481 | /*populate MCLK dpm table to SMU7 */ | |
4482 | result = iceland_populate_all_memory_levels(hwmgr); | |
4483 | PP_ASSERT_WITH_CODE((0 == result), | |
4484 | "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", | |
4485 | return result); | |
4486 | } | |
4487 | ||
4488 | return result; | |
4489 | } | |
4490 | ||
4491 | static int iceland_trim_single_dpm_states(struct pp_hwmgr *hwmgr, | |
4492 | struct iceland_single_dpm_table *pdpm_table, | |
4493 | uint32_t low_limit, uint32_t high_limit) | |
4494 | { | |
4495 | uint32_t i; | |
4496 | ||
4497 | for (i = 0; i < pdpm_table->count; i++) { | |
4498 | if ((pdpm_table->dpm_levels[i].value < low_limit) || | |
4499 | (pdpm_table->dpm_levels[i].value > high_limit)) | |
4500 | pdpm_table->dpm_levels[i].enabled = false; | |
4501 | else | |
4502 | pdpm_table->dpm_levels[i].enabled = true; | |
4503 | } | |
4504 | return 0; | |
4505 | } | |
4506 | ||
4507 | static int iceland_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct iceland_power_state *hw_state) | |
4508 | { | |
4509 | int result = 0; | |
4510 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4511 | uint32_t high_limit_count; | |
4512 | ||
4513 | PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1), | |
4514 | "power state did not have any performance level", | |
4515 | return -1); | |
4516 | ||
4517 | high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1; | |
4518 | ||
4519 | iceland_trim_single_dpm_states(hwmgr, &(data->dpm_table.sclk_table), | |
4520 | hw_state->performance_levels[0].engine_clock, | |
4521 | hw_state->performance_levels[high_limit_count].engine_clock); | |
4522 | ||
4523 | iceland_trim_single_dpm_states(hwmgr, &(data->dpm_table.mclk_table), | |
4524 | hw_state->performance_levels[0].memory_clock, | |
4525 | hw_state->performance_levels[high_limit_count].memory_clock); | |
4526 | ||
4527 | return result; | |
4528 | } | |
4529 | ||
4530 | static int iceland_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input) | |
4531 | { | |
4532 | int result; | |
4533 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
4534 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4535 | const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state); | |
4536 | ||
4537 | result = iceland_trim_dpm_states(hwmgr, iceland_ps); | |
4538 | if (0 != result) | |
4539 | return result; | |
4540 | ||
4541 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); | |
4542 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); | |
4543 | data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask; | |
4544 | if (data->uvd_enabled && (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)) | |
4545 | data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; | |
4546 | ||
4547 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); | |
4548 | ||
4549 | return 0; | |
4550 | } | |
4551 | ||
4552 | static int iceland_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) | |
4553 | { | |
4554 | return 0; | |
4555 | } | |
4556 | ||
4557 | int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) | |
4558 | { | |
4559 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4560 | ||
4561 | int result = 0; | |
4562 | uint32_t low_sclk_interrupt_threshold = 0; | |
4563 | ||
4564 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
4565 | PHM_PlatformCaps_SclkThrottleLowNotification) | |
4566 | && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) { | |
4567 | data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold; | |
4568 | low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold; | |
4569 | ||
4570 | CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); | |
4571 | ||
4572 | result = iceland_copy_bytes_to_smc( | |
4573 | hwmgr->smumgr, | |
4574 | data->dpm_table_start + offsetof(SMU71_Discrete_DpmTable, | |
4575 | LowSclkInterruptThreshold), | |
4576 | (uint8_t *)&low_sclk_interrupt_threshold, | |
4577 | sizeof(uint32_t), | |
4578 | data->sram_end | |
4579 | ); | |
4580 | } | |
4581 | ||
4582 | return result; | |
4583 | } | |
4584 | ||
4585 | static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) | |
4586 | { | |
4587 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4588 | ||
4589 | uint32_t address; | |
4590 | int32_t result; | |
4591 | ||
4592 | if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) | |
4593 | return 0; | |
4594 | ||
4595 | ||
4596 | memset(&data->mc_reg_table, 0, sizeof(SMU71_Discrete_MCRegisters)); | |
4597 | ||
4598 | result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table)); | |
4599 | ||
4600 | if(result != 0) | |
4601 | return result; | |
4602 | ||
4603 | ||
4604 | address = data->mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); | |
4605 | ||
4606 | return iceland_copy_bytes_to_smc(hwmgr->smumgr, address, | |
4607 | (uint8_t *)&data->mc_reg_table.data[0], | |
4608 | sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, | |
4609 | data->sram_end); | |
4610 | } | |
4611 | ||
4612 | static int iceland_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr) | |
4613 | { | |
4614 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4615 | ||
4616 | if (data->need_update_smu7_dpm_table & | |
4617 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) | |
4618 | return iceland_program_memory_timing_parameters(hwmgr); | |
4619 | ||
4620 | return 0; | |
4621 | } | |
4622 | ||
4623 | static int iceland_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
4624 | { | |
4625 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4626 | ||
4627 | if (0 == data->need_update_smu7_dpm_table) | |
4628 | return 0; | |
4629 | ||
4630 | if ((0 == data->sclk_dpm_key_disabled) && | |
4631 | (data->need_update_smu7_dpm_table & | |
4632 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { | |
4633 | ||
4634 | PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr), | |
4635 | "Trying to Unfreeze SCLK DPM when DPM is disabled", | |
4636 | ); | |
4637 | PP_ASSERT_WITH_CODE( | |
4638 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
4639 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), | |
4640 | "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", | |
4641 | return -1); | |
4642 | } | |
4643 | ||
4644 | if ((0 == data->mclk_dpm_key_disabled) && | |
4645 | (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { | |
4646 | ||
4647 | PP_ASSERT_WITH_CODE( | |
4648 | 0 == iceland_is_dpm_running(hwmgr), | |
4649 | "Trying to Unfreeze MCLK DPM when DPM is disabled", | |
4650 | ); | |
4651 | PP_ASSERT_WITH_CODE( | |
4652 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
4653 | PPSMC_MSG_MCLKDPM_UnfreezeLevel), | |
4654 | "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", | |
4655 | return -1); | |
4656 | } | |
4657 | ||
4658 | data->need_update_smu7_dpm_table = 0; | |
4659 | ||
4660 | return 0; | |
4661 | } | |
4662 | ||
4663 | static int iceland_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input) | |
4664 | { | |
4665 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
4666 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4667 | const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state); | |
4668 | uint16_t target_link_speed = iceland_get_maximum_link_speed(hwmgr, iceland_ps); | |
4669 | uint8_t request; | |
4670 | ||
4671 | if (data->pspp_notify_required || | |
4672 | data->pcie_performance_request) { | |
4673 | if (target_link_speed == PP_PCIEGen3) | |
4674 | request = PCIE_PERF_REQ_GEN3; | |
4675 | else if (target_link_speed == PP_PCIEGen2) | |
4676 | request = PCIE_PERF_REQ_GEN2; | |
4677 | else | |
4678 | request = PCIE_PERF_REQ_GEN1; | |
4679 | ||
4680 | if(request == PCIE_PERF_REQ_GEN1 && iceland_get_current_pcie_speed(hwmgr) > 0) { | |
4681 | data->pcie_performance_request = false; | |
4682 | return 0; | |
4683 | } | |
4684 | ||
4685 | if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) { | |
4686 | if (PP_PCIEGen2 == target_link_speed) | |
4687 | printk("PSPP request to switch to Gen2 from Gen3 Failed!"); | |
4688 | else | |
4689 | printk("PSPP request to switch to Gen1 from Gen2 Failed!"); | |
4690 | } | |
4691 | } | |
4692 | ||
4693 | data->pcie_performance_request = false; | |
4694 | return 0; | |
4695 | } | |
4696 | ||
4697 | int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) | |
4698 | { | |
4699 | PPSMC_Result result; | |
4700 | iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); | |
4701 | ||
4702 | if (0 == data->sclk_dpm_key_disabled) { | |
4703 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
4704 | if (0 != iceland_is_dpm_running(hwmgr)) | |
4705 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Sclk Mask when DPM is disabled \n"); | |
4706 | ||
4707 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { | |
4708 | result = smum_send_msg_to_smc_with_parameter( | |
4709 | hwmgr->smumgr, | |
4710 | (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask, | |
4711 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); | |
4712 | PP_ASSERT_WITH_CODE((0 == result), | |
4713 | "Set Sclk Dpm enable Mask failed", return -1); | |
4714 | } | |
4715 | } | |
4716 | ||
4717 | if (0 == data->mclk_dpm_key_disabled) { | |
4718 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
4719 | if (0 != iceland_is_dpm_running(hwmgr)) | |
4720 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mclk Mask when DPM is disabled \n"); | |
4721 | ||
4722 | if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) { | |
4723 | result = smum_send_msg_to_smc_with_parameter( | |
4724 | hwmgr->smumgr, | |
4725 | (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask, | |
4726 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); | |
4727 | PP_ASSERT_WITH_CODE((0 == result), | |
4728 | "Set Mclk Dpm enable Mask failed", return -1); | |
4729 | } | |
4730 | } | |
4731 | ||
4732 | return 0; | |
4733 | } | |
4734 | ||
4735 | static int iceland_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) | |
4736 | { | |
4737 | int tmp_result, result = 0; | |
4738 | ||
4739 | tmp_result = iceland_find_dpm_states_clocks_in_dpm_table(hwmgr, input); | |
4740 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result); | |
4741 | ||
4742 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { | |
4743 | tmp_result = iceland_request_link_speed_change_before_state_change(hwmgr, input); | |
4744 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result); | |
4745 | } | |
4746 | ||
4747 | tmp_result = iceland_freeze_sclk_mclk_dpm(hwmgr); | |
4748 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result); | |
4749 | ||
4750 | tmp_result = iceland_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); | |
4751 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result); | |
4752 | ||
4753 | tmp_result = iceland_generate_dpm_level_enable_mask(hwmgr, input); | |
4754 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result); | |
4755 | ||
4756 | tmp_result = iceland_update_vce_dpm(hwmgr, input); | |
4757 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result); | |
4758 | ||
4759 | tmp_result = iceland_update_sclk_threshold(hwmgr); | |
4760 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result); | |
4761 | ||
4762 | tmp_result = iceland_update_and_upload_mc_reg_table(hwmgr); | |
4763 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result); | |
4764 | ||
4765 | tmp_result = iceland_program_memory_timing_parameters_conditionally(hwmgr); | |
4766 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result); | |
4767 | ||
4768 | tmp_result = iceland_unfreeze_sclk_mclk_dpm(hwmgr); | |
4769 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result); | |
4770 | ||
4771 | tmp_result = iceland_upload_dpm_level_enable_mask(hwmgr); | |
4772 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result); | |
4773 | ||
4774 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { | |
4775 | tmp_result = iceland_notify_link_speed_change_after_state_change(hwmgr, input); | |
4776 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result); | |
4777 | } | |
4778 | ||
4779 | return result; | |
4780 | } | |
4781 | ||
4782 | static int iceland_get_power_state_size(struct pp_hwmgr *hwmgr) | |
4783 | { | |
4784 | return sizeof(struct iceland_power_state); | |
4785 | } | |
4786 | ||
4787 | static int iceland_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) | |
4788 | { | |
4789 | struct pp_power_state *ps; | |
4790 | struct iceland_power_state *iceland_ps; | |
4791 | ||
4792 | if (hwmgr == NULL) | |
4793 | return -EINVAL; | |
4794 | ||
4795 | ps = hwmgr->request_ps; | |
4796 | ||
4797 | if (ps == NULL) | |
4798 | return -EINVAL; | |
4799 | ||
4800 | iceland_ps = cast_phw_iceland_power_state(&ps->hardware); | |
4801 | ||
4802 | if (low) | |
4803 | return iceland_ps->performance_levels[0].memory_clock; | |
4804 | else | |
4805 | return iceland_ps->performance_levels[iceland_ps->performance_level_count-1].memory_clock; | |
4806 | } | |
4807 | ||
4808 | static int iceland_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) | |
4809 | { | |
4810 | struct pp_power_state *ps; | |
4811 | struct iceland_power_state *iceland_ps; | |
4812 | ||
4813 | if (hwmgr == NULL) | |
4814 | return -EINVAL; | |
4815 | ||
4816 | ps = hwmgr->request_ps; | |
4817 | ||
4818 | if (ps == NULL) | |
4819 | return -EINVAL; | |
4820 | ||
4821 | iceland_ps = cast_phw_iceland_power_state(&ps->hardware); | |
4822 | ||
4823 | if (low) | |
4824 | return iceland_ps->performance_levels[0].engine_clock; | |
4825 | else | |
4826 | return iceland_ps->performance_levels[iceland_ps->performance_level_count-1].engine_clock; | |
4827 | } | |
4828 | ||
4829 | static int iceland_get_current_pcie_lane_number( | |
4830 | struct pp_hwmgr *hwmgr) | |
4831 | { | |
4832 | uint32_t link_width; | |
4833 | ||
4834 | link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, | |
4835 | CGS_IND_REG__PCIE, | |
4836 | PCIE_LC_LINK_WIDTH_CNTL, | |
4837 | LC_LINK_WIDTH_RD); | |
4838 | ||
4839 | PP_ASSERT_WITH_CODE((7 >= link_width), | |
4840 | "Invalid PCIe lane width!", return 0); | |
4841 | ||
4842 | return decode_pcie_lane_width(link_width); | |
4843 | } | |
4844 | ||
4845 | static int iceland_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, | |
4846 | struct pp_hw_power_state *hw_ps) | |
4847 | { | |
4848 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4849 | struct iceland_power_state *ps = (struct iceland_power_state *)hw_ps; | |
4850 | ATOM_FIRMWARE_INFO_V2_2 *fw_info; | |
4851 | uint16_t size; | |
4852 | uint8_t frev, crev; | |
4853 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
4854 | ||
4855 | /* First retrieve the Boot clocks and VDDC from the firmware info table. | |
4856 | * We assume here that fw_info is unchanged if this call fails. | |
4857 | */ | |
4858 | fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( | |
4859 | hwmgr->device, index, | |
4860 | &size, &frev, &crev); | |
4861 | if (!fw_info) | |
4862 | /* During a test, there is no firmware info table. */ | |
4863 | return 0; | |
4864 | ||
4865 | /* Patch the state. */ | |
4866 | data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock); | |
4867 | data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock); | |
4868 | data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage); | |
4869 | data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage); | |
4870 | data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage); | |
4871 | data->vbios_boot_state.pcie_gen_bootup_value = iceland_get_current_pcie_speed(hwmgr); | |
4872 | data->vbios_boot_state.pcie_lane_bootup_value = | |
4873 | (uint16_t)iceland_get_current_pcie_lane_number(hwmgr); | |
4874 | ||
4875 | /* set boot power state */ | |
4876 | ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; | |
4877 | ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; | |
4878 | ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; | |
4879 | ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; | |
4880 | ||
4881 | return 0; | |
4882 | } | |
4883 | ||
4884 | static int iceland_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, | |
4885 | struct pp_hw_power_state *power_state, | |
4886 | unsigned int index, const void *clock_info) | |
4887 | { | |
4888 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4889 | struct iceland_power_state *iceland_power_state = cast_phw_iceland_power_state(power_state); | |
4890 | const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info; | |
4891 | struct iceland_performance_level *performance_level; | |
4892 | uint32_t engine_clock, memory_clock; | |
4893 | uint16_t pcie_gen_from_bios; | |
4894 | ||
4895 | engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow; | |
4896 | memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow; | |
4897 | ||
4898 | if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) | |
4899 | data->highest_mclk = memory_clock; | |
4900 | ||
4901 | performance_level = &(iceland_power_state->performance_levels | |
4902 | [iceland_power_state->performance_level_count++]); | |
4903 | ||
4904 | PP_ASSERT_WITH_CODE( | |
4905 | (iceland_power_state->performance_level_count < SMU71_MAX_LEVELS_GRAPHICS), | |
4906 | "Performance levels exceeds SMC limit!", | |
4907 | return -1); | |
4908 | ||
4909 | PP_ASSERT_WITH_CODE( | |
4910 | (iceland_power_state->performance_level_count <= | |
4911 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), | |
4912 | "Performance levels exceeds Driver limit!", | |
4913 | return -1); | |
4914 | ||
4915 | /* Performance levels are arranged from low to high. */ | |
4916 | performance_level->memory_clock = memory_clock; | |
4917 | performance_level->engine_clock = engine_clock; | |
4918 | ||
4919 | pcie_gen_from_bios = visland_clk_info->ucPCIEGen; | |
4920 | ||
4921 | performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios); | |
4922 | performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane); | |
4923 | ||
4924 | return 0; | |
4925 | } | |
4926 | ||
4927 | static int iceland_get_pp_table_entry(struct pp_hwmgr *hwmgr, | |
4928 | unsigned long entry_index, struct pp_power_state *state) | |
4929 | { | |
4930 | int result; | |
4931 | struct iceland_power_state *ps; | |
4932 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
4933 | struct phm_clock_voltage_dependency_table *dep_mclk_table = | |
4934 | hwmgr->dyn_state.vddci_dependency_on_mclk; | |
4935 | ||
4936 | memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state)); | |
4937 | ||
4938 | state->hardware.magic = PHM_VIslands_Magic; | |
4939 | ||
4940 | ps = (struct iceland_power_state *)(&state->hardware); | |
4941 | ||
4942 | result = pp_tables_get_entry(hwmgr, entry_index, state, | |
4943 | iceland_get_pp_table_entry_callback_func); | |
4944 | ||
4945 | /* | |
4946 | * This is the earliest time we have all the dependency table | |
4947 | * and the VBIOS boot state as | |
4948 | * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot | |
4949 | * state if there is only one VDDCI/MCLK level, check if it's | |
4950 | * the same as VBIOS boot state | |
4951 | */ | |
4952 | if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { | |
4953 | if (dep_mclk_table->entries[0].clk != | |
4954 | data->vbios_boot_state.mclk_bootup_value) | |
4955 | printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " | |
4956 | "does not match VBIOS boot MCLK level"); | |
4957 | if (dep_mclk_table->entries[0].v != | |
4958 | data->vbios_boot_state.vddci_bootup_value) | |
4959 | printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " | |
4960 | "does not match VBIOS boot VDDCI level"); | |
4961 | } | |
4962 | ||
4963 | /* set DC compatible flag if this state supports DC */ | |
4964 | if (!state->validation.disallowOnDC) | |
4965 | ps->dc_compatible = true; | |
4966 | ||
4967 | if (state->classification.flags & PP_StateClassificationFlag_ACPI) | |
4968 | data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; | |
4969 | else if (0 != (state->classification.flags & PP_StateClassificationFlag_Boot)) { | |
4970 | if (data->bacos.best_match == 0xffff) { | |
4971 | /* For C.I. use boot state as base BACO state */ | |
4972 | data->bacos.best_match = PP_StateClassificationFlag_Boot; | |
4973 | data->bacos.performance_level = ps->performance_levels[0]; | |
4974 | } | |
4975 | } | |
4976 | ||
4977 | ||
4978 | ps->uvd_clocks.VCLK = state->uvd_clocks.VCLK; | |
4979 | ps->uvd_clocks.DCLK = state->uvd_clocks.DCLK; | |
4980 | ||
4981 | if (!result) { | |
4982 | uint32_t i; | |
4983 | ||
4984 | switch (state->classification.ui_label) { | |
4985 | case PP_StateUILabel_Performance: | |
4986 | data->use_pcie_performance_levels = true; | |
4987 | ||
4988 | for (i = 0; i < ps->performance_level_count; i++) { | |
4989 | if (data->pcie_gen_performance.max < | |
4990 | ps->performance_levels[i].pcie_gen) | |
4991 | data->pcie_gen_performance.max = | |
4992 | ps->performance_levels[i].pcie_gen; | |
4993 | ||
4994 | if (data->pcie_gen_performance.min > | |
4995 | ps->performance_levels[i].pcie_gen) | |
4996 | data->pcie_gen_performance.min = | |
4997 | ps->performance_levels[i].pcie_gen; | |
4998 | ||
4999 | if (data->pcie_lane_performance.max < | |
5000 | ps->performance_levels[i].pcie_lane) | |
5001 | data->pcie_lane_performance.max = | |
5002 | ps->performance_levels[i].pcie_lane; | |
5003 | ||
5004 | if (data->pcie_lane_performance.min > | |
5005 | ps->performance_levels[i].pcie_lane) | |
5006 | data->pcie_lane_performance.min = | |
5007 | ps->performance_levels[i].pcie_lane; | |
5008 | } | |
5009 | break; | |
5010 | case PP_StateUILabel_Battery: | |
5011 | data->use_pcie_power_saving_levels = true; | |
5012 | ||
5013 | for (i = 0; i < ps->performance_level_count; i++) { | |
5014 | if (data->pcie_gen_power_saving.max < | |
5015 | ps->performance_levels[i].pcie_gen) | |
5016 | data->pcie_gen_power_saving.max = | |
5017 | ps->performance_levels[i].pcie_gen; | |
5018 | ||
5019 | if (data->pcie_gen_power_saving.min > | |
5020 | ps->performance_levels[i].pcie_gen) | |
5021 | data->pcie_gen_power_saving.min = | |
5022 | ps->performance_levels[i].pcie_gen; | |
5023 | ||
5024 | if (data->pcie_lane_power_saving.max < | |
5025 | ps->performance_levels[i].pcie_lane) | |
5026 | data->pcie_lane_power_saving.max = | |
5027 | ps->performance_levels[i].pcie_lane; | |
5028 | ||
5029 | if (data->pcie_lane_power_saving.min > | |
5030 | ps->performance_levels[i].pcie_lane) | |
5031 | data->pcie_lane_power_saving.min = | |
5032 | ps->performance_levels[i].pcie_lane; | |
5033 | } | |
5034 | break; | |
5035 | default: | |
5036 | break; | |
5037 | } | |
5038 | } | |
5039 | return 0; | |
5040 | } | |
5041 | ||
5042 | static void | |
5043 | iceland_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) | |
5044 | { | |
5045 | uint32_t sclk, mclk, activity_percent; | |
5046 | uint32_t offset; | |
5047 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5048 | ||
5049 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency)); | |
5050 | ||
5051 | sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
5052 | ||
5053 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency)); | |
5054 | ||
5055 | mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
5056 | seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100); | |
5057 | ||
5058 | offset = data->soft_regs_start + offsetof(SMU71_SoftRegisters, AverageGraphicsActivity); | |
5059 | activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); | |
5060 | activity_percent += 0x80; | |
5061 | activity_percent >>= 8; | |
5062 | ||
5063 | seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent); | |
5064 | ||
5065 | seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en"); | |
5066 | ||
5067 | seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); | |
5068 | } | |
5069 | ||
5070 | int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) | |
5071 | { | |
5072 | uint32_t num_active_displays = 0; | |
5073 | struct cgs_display_info info = {0}; | |
5074 | info.mode_info = NULL; | |
5075 | ||
5076 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5077 | ||
5078 | num_active_displays = info.display_count; | |
5079 | ||
5080 | if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ | |
5081 | iceland_notify_smc_display_change(hwmgr, false); | |
5082 | else | |
5083 | iceland_notify_smc_display_change(hwmgr, true); | |
5084 | ||
5085 | return 0; | |
5086 | } | |
5087 | ||
5088 | /** | |
5089 | * Programs the display gap | |
5090 | * | |
5091 | * @param hwmgr the address of the powerplay hardware manager. | |
5092 | * @return always OK | |
5093 | */ | |
5094 | int iceland_program_display_gap(struct pp_hwmgr *hwmgr) | |
5095 | { | |
5096 | uint32_t num_active_displays = 0; | |
5097 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); | |
5098 | uint32_t display_gap2; | |
5099 | uint32_t pre_vbi_time_in_us; | |
5100 | uint32_t frame_time_in_us; | |
5101 | uint32_t ref_clock; | |
5102 | uint32_t refresh_rate = 0; | |
5103 | struct cgs_display_info info = {0}; | |
5104 | struct cgs_mode_info mode_info; | |
5105 | ||
5106 | info.mode_info = &mode_info; | |
5107 | ||
5108 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5109 | num_active_displays = info.display_count; | |
5110 | ||
5111 | display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); | |
5112 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); | |
5113 | ||
5114 | ref_clock = mode_info.ref_clock; | |
5115 | refresh_rate = mode_info.refresh_rate; | |
5116 | ||
5117 | if(0 == refresh_rate) | |
5118 | refresh_rate = 60; | |
5119 | ||
5120 | frame_time_in_us = 1000000 / refresh_rate; | |
5121 | ||
5122 | pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; | |
5123 | display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); | |
5124 | ||
5125 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); | |
5126 | ||
5127 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SOFT_REGISTERS_TABLE_4, PreVBlankGap, 0x64); | |
5128 | ||
5129 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SOFT_REGISTERS_TABLE_5, VBlankTimeout, (frame_time_in_us - pre_vbi_time_in_us)); | |
5130 | ||
5131 | if (num_active_displays == 1) | |
5132 | iceland_notify_smc_display_change(hwmgr, true); | |
5133 | ||
5134 | return 0; | |
5135 | } | |
5136 | ||
5137 | int iceland_display_configuration_changed_task(struct pp_hwmgr *hwmgr) | |
5138 | { | |
5139 | iceland_program_display_gap(hwmgr); | |
5140 | ||
5141 | return 0; | |
5142 | } | |
5143 | ||
5144 | /** | |
5145 | * Set maximum target operating fan output PWM | |
5146 | * | |
5147 | * @param pHwMgr: the address of the powerplay hardware manager. | |
5148 | * @param usMaxFanPwm: max operating fan PWM in percents | |
5149 | * @return The response that came from the SMC. | |
5150 | */ | |
5151 | static int iceland_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) | |
5152 | { | |
5153 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; | |
5154 | ||
5155 | if (phm_is_hw_access_blocked(hwmgr)) | |
5156 | return 0; | |
5157 | ||
5158 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1); | |
5159 | } | |
5160 | ||
5161 | /** | |
5162 | * Set maximum target operating fan output RPM | |
5163 | * | |
5164 | * @param pHwMgr: the address of the powerplay hardware manager. | |
5165 | * @param usMaxFanRpm: max operating fan RPM value. | |
5166 | * @return The response that came from the SMC. | |
5167 | */ | |
5168 | static int iceland_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) | |
5169 | { | |
5170 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm; | |
5171 | ||
5172 | if (phm_is_hw_access_blocked(hwmgr)) | |
5173 | return 0; | |
5174 | ||
5175 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1); | |
5176 | } | |
5177 | ||
5178 | static int iceland_dpm_set_interrupt_state(void *private_data, | |
5179 | unsigned src_id, unsigned type, | |
5180 | int enabled) | |
5181 | { | |
5182 | uint32_t cg_thermal_int; | |
5183 | struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr; | |
5184 | ||
5185 | if (hwmgr == NULL) | |
5186 | return -EINVAL; | |
5187 | ||
5188 | switch (type) { | |
5189 | case AMD_THERMAL_IRQ_LOW_TO_HIGH: | |
5190 | if (enabled) { | |
5191 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5192 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; | |
5193 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5194 | } else { | |
5195 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5196 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; | |
5197 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5198 | } | |
5199 | break; | |
5200 | ||
5201 | case AMD_THERMAL_IRQ_HIGH_TO_LOW: | |
5202 | if (enabled) { | |
5203 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5204 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; | |
5205 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5206 | } else { | |
5207 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5208 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; | |
5209 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5210 | } | |
5211 | break; | |
5212 | default: | |
5213 | break; | |
5214 | } | |
5215 | return 0; | |
5216 | } | |
5217 | ||
5218 | static int iceland_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, | |
5219 | const void *thermal_interrupt_info) | |
5220 | { | |
5221 | int result; | |
5222 | const struct pp_interrupt_registration_info *info = | |
5223 | (const struct pp_interrupt_registration_info *)thermal_interrupt_info; | |
5224 | ||
5225 | if (info == NULL) | |
5226 | return -EINVAL; | |
5227 | ||
5228 | result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST, | |
5229 | iceland_dpm_set_interrupt_state, | |
5230 | info->call_back, info->context); | |
5231 | ||
5232 | if (result) | |
5233 | return -EINVAL; | |
5234 | ||
5235 | result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST, | |
5236 | iceland_dpm_set_interrupt_state, | |
5237 | info->call_back, info->context); | |
5238 | ||
5239 | if (result) | |
5240 | return -EINVAL; | |
5241 | ||
5242 | return 0; | |
5243 | } | |
5244 | ||
5245 | ||
5246 | static bool iceland_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) | |
5247 | { | |
5248 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5249 | bool is_update_required = false; | |
5250 | struct cgs_display_info info = {0,0,NULL}; | |
5251 | ||
5252 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5253 | ||
5254 | if (data->display_timing.num_existing_displays != info.display_count) | |
5255 | is_update_required = true; | |
5256 | /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL | |
5257 | if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { | |
5258 | cgs_get_min_clock_settings(hwmgr->device, &min_clocks); | |
5259 | if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) | |
5260 | is_update_required = true; | |
5261 | */ | |
5262 | return is_update_required; | |
5263 | } | |
5264 | ||
5265 | ||
5266 | static inline bool iceland_are_power_levels_equal(const struct iceland_performance_level *pl1, | |
5267 | const struct iceland_performance_level *pl2) | |
5268 | { | |
5269 | return ((pl1->memory_clock == pl2->memory_clock) && | |
5270 | (pl1->engine_clock == pl2->engine_clock) && | |
5271 | (pl1->pcie_gen == pl2->pcie_gen) && | |
5272 | (pl1->pcie_lane == pl2->pcie_lane)); | |
5273 | } | |
5274 | ||
5275 | int iceland_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, | |
5276 | const struct pp_hw_power_state *pstate2, bool *equal) | |
5277 | { | |
5278 | const struct iceland_power_state *psa = cast_const_phw_iceland_power_state(pstate1); | |
5279 | const struct iceland_power_state *psb = cast_const_phw_iceland_power_state(pstate2); | |
5280 | int i; | |
5281 | ||
5282 | if (equal == NULL || psa == NULL || psb == NULL) | |
5283 | return -EINVAL; | |
5284 | ||
5285 | /* If the two states don't even have the same number of performance levels they cannot be the same state. */ | |
5286 | if (psa->performance_level_count != psb->performance_level_count) { | |
5287 | *equal = false; | |
5288 | return 0; | |
5289 | } | |
5290 | ||
5291 | for (i = 0; i < psa->performance_level_count; i++) { | |
5292 | if (!iceland_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { | |
5293 | /* If we have found even one performance level pair that is different the states are different. */ | |
5294 | *equal = false; | |
5295 | return 0; | |
5296 | } | |
5297 | } | |
5298 | ||
5299 | /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ | |
5300 | *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK)); | |
5301 | *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK)); | |
5302 | *equal &= (psa->sclk_threshold == psb->sclk_threshold); | |
5303 | *equal &= (psa->acp_clk == psb->acp_clk); | |
5304 | ||
5305 | return 0; | |
5306 | } | |
5307 | ||
5308 | static int iceland_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) | |
5309 | { | |
5310 | if (mode) { | |
5311 | /* stop auto-manage */ | |
5312 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
5313 | PHM_PlatformCaps_MicrocodeFanControl)) | |
5314 | iceland_fan_ctrl_stop_smc_fan_control(hwmgr); | |
5315 | iceland_fan_ctrl_set_static_mode(hwmgr, mode); | |
5316 | } else | |
5317 | /* restart auto-manage */ | |
5318 | iceland_fan_ctrl_reset_fan_speed_to_default(hwmgr); | |
5319 | ||
5320 | return 0; | |
5321 | } | |
5322 | ||
5323 | static int iceland_get_fan_control_mode(struct pp_hwmgr *hwmgr) | |
5324 | { | |
5325 | if (hwmgr->fan_ctrl_is_in_default_mode) | |
5326 | return hwmgr->fan_ctrl_default_mode; | |
5327 | else | |
5328 | return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
5329 | CG_FDO_CTRL2, FDO_PWM_MODE); | |
5330 | } | |
5331 | ||
5332 | static int iceland_force_clock_level(struct pp_hwmgr *hwmgr, | |
5333 | enum pp_clock_type type, uint32_t mask) | |
5334 | { | |
5335 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5336 | ||
5337 | if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) | |
5338 | return -EINVAL; | |
5339 | ||
5340 | switch (type) { | |
5341 | case PP_SCLK: | |
5342 | if (!data->sclk_dpm_key_disabled) | |
5343 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
5344 | PPSMC_MSG_SCLKDPM_SetEnabledMask, | |
5345 | data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); | |
5346 | break; | |
5347 | case PP_MCLK: | |
5348 | if (!data->mclk_dpm_key_disabled) | |
5349 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
5350 | PPSMC_MSG_MCLKDPM_SetEnabledMask, | |
5351 | data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); | |
5352 | break; | |
5353 | case PP_PCIE: | |
5354 | { | |
5355 | uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; | |
5356 | uint32_t level = 0; | |
5357 | ||
5358 | while (tmp >>= 1) | |
5359 | level++; | |
5360 | ||
5361 | if (!data->pcie_dpm_key_disabled) | |
5362 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
5363 | PPSMC_MSG_PCIeDPM_ForceLevel, | |
5364 | level); | |
5365 | break; | |
5366 | } | |
5367 | default: | |
5368 | break; | |
5369 | } | |
5370 | ||
5371 | return 0; | |
5372 | } | |
5373 | ||
5374 | static int iceland_print_clock_levels(struct pp_hwmgr *hwmgr, | |
5375 | enum pp_clock_type type, char *buf) | |
5376 | { | |
5377 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5378 | struct iceland_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); | |
5379 | struct iceland_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); | |
5380 | struct iceland_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); | |
5381 | int i, now, size = 0; | |
5382 | uint32_t clock, pcie_speed; | |
5383 | ||
5384 | switch (type) { | |
5385 | case PP_SCLK: | |
5386 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); | |
5387 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
5388 | ||
5389 | for (i = 0; i < sclk_table->count; i++) { | |
5390 | if (clock > sclk_table->dpm_levels[i].value) | |
5391 | continue; | |
5392 | break; | |
5393 | } | |
5394 | now = i; | |
5395 | ||
5396 | for (i = 0; i < sclk_table->count; i++) | |
5397 | size += sprintf(buf + size, "%d: %uMhz %s\n", | |
5398 | i, sclk_table->dpm_levels[i].value / 100, | |
5399 | (i == now) ? "*" : ""); | |
5400 | break; | |
5401 | case PP_MCLK: | |
5402 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); | |
5403 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
5404 | ||
5405 | for (i = 0; i < mclk_table->count; i++) { | |
5406 | if (clock > mclk_table->dpm_levels[i].value) | |
5407 | continue; | |
5408 | break; | |
5409 | } | |
5410 | now = i; | |
5411 | ||
5412 | for (i = 0; i < mclk_table->count; i++) | |
5413 | size += sprintf(buf + size, "%d: %uMhz %s\n", | |
5414 | i, mclk_table->dpm_levels[i].value / 100, | |
5415 | (i == now) ? "*" : ""); | |
5416 | break; | |
5417 | case PP_PCIE: | |
5418 | pcie_speed = iceland_get_current_pcie_speed(hwmgr); | |
5419 | for (i = 0; i < pcie_table->count; i++) { | |
5420 | if (pcie_speed != pcie_table->dpm_levels[i].value) | |
5421 | continue; | |
5422 | break; | |
5423 | } | |
5424 | now = i; | |
5425 | ||
5426 | for (i = 0; i < pcie_table->count; i++) | |
5427 | size += sprintf(buf + size, "%d: %s %s\n", i, | |
5428 | (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : | |
5429 | (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : | |
5430 | (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", | |
5431 | (i == now) ? "*" : ""); | |
5432 | break; | |
5433 | default: | |
5434 | break; | |
5435 | } | |
5436 | return size; | |
5437 | } | |
5438 | ||
5439 | static int iceland_get_sclk_od(struct pp_hwmgr *hwmgr) | |
5440 | { | |
5441 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5442 | struct iceland_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); | |
5443 | struct iceland_single_dpm_table *golden_sclk_table = | |
5444 | &(data->golden_dpm_table.sclk_table); | |
5445 | int value; | |
5446 | ||
5447 | value = (sclk_table->dpm_levels[sclk_table->count - 1].value - | |
5448 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * | |
5449 | 100 / | |
5450 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; | |
5451 | ||
5452 | return value; | |
5453 | } | |
5454 | ||
5455 | static int iceland_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) | |
5456 | { | |
5457 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5458 | struct iceland_single_dpm_table *golden_sclk_table = | |
5459 | &(data->golden_dpm_table.sclk_table); | |
5460 | struct pp_power_state *ps; | |
5461 | struct iceland_power_state *iceland_ps; | |
5462 | ||
5463 | if (value > 20) | |
5464 | value = 20; | |
5465 | ||
5466 | ps = hwmgr->request_ps; | |
5467 | ||
5468 | if (ps == NULL) | |
5469 | return -EINVAL; | |
5470 | ||
5471 | iceland_ps = cast_phw_iceland_power_state(&ps->hardware); | |
5472 | ||
5473 | iceland_ps->performance_levels[iceland_ps->performance_level_count - 1].engine_clock = | |
5474 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * | |
5475 | value / 100 + | |
5476 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; | |
5477 | ||
5478 | return 0; | |
5479 | } | |
5480 | ||
5481 | static int iceland_get_mclk_od(struct pp_hwmgr *hwmgr) | |
5482 | { | |
5483 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5484 | struct iceland_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); | |
5485 | struct iceland_single_dpm_table *golden_mclk_table = | |
5486 | &(data->golden_dpm_table.mclk_table); | |
5487 | int value; | |
5488 | ||
5489 | value = (mclk_table->dpm_levels[mclk_table->count - 1].value - | |
5490 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * | |
5491 | 100 / | |
5492 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; | |
5493 | ||
5494 | return value; | |
5495 | } | |
5496 | ||
5497 | uint32_t iceland_get_xclk(struct pp_hwmgr *hwmgr) | |
5498 | { | |
5499 | uint32_t reference_clock; | |
5500 | uint32_t tc; | |
5501 | uint32_t divide; | |
5502 | ||
5503 | ATOM_FIRMWARE_INFO *fw_info; | |
5504 | uint16_t size; | |
5505 | uint8_t frev, crev; | |
5506 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
5507 | ||
5508 | tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); | |
5509 | ||
5510 | if (tc) | |
5511 | return TCLK; | |
5512 | ||
5513 | fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index, | |
5514 | &size, &frev, &crev); | |
5515 | ||
5516 | if (!fw_info) | |
5517 | return 0; | |
5518 | ||
5519 | reference_clock = le16_to_cpu(fw_info->usReferenceClock); | |
5520 | ||
5521 | divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); | |
5522 | ||
5523 | if (0 != divide) | |
5524 | return reference_clock / 4; | |
5525 | ||
5526 | return reference_clock; | |
5527 | } | |
5528 | ||
5529 | static int iceland_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) | |
5530 | { | |
5531 | struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); | |
5532 | struct iceland_single_dpm_table *golden_mclk_table = | |
5533 | &(data->golden_dpm_table.mclk_table); | |
5534 | struct pp_power_state *ps; | |
5535 | struct iceland_power_state *iceland_ps; | |
5536 | ||
5537 | if (value > 20) | |
5538 | value = 20; | |
5539 | ||
5540 | ps = hwmgr->request_ps; | |
5541 | ||
5542 | if (ps == NULL) | |
5543 | return -EINVAL; | |
5544 | ||
5545 | iceland_ps = cast_phw_iceland_power_state(&ps->hardware); | |
5546 | ||
5547 | iceland_ps->performance_levels[iceland_ps->performance_level_count - 1].memory_clock = | |
5548 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * | |
5549 | value / 100 + | |
5550 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; | |
5551 | ||
5552 | return 0; | |
5553 | } | |
5554 | ||
5555 | static const struct pp_hwmgr_func iceland_hwmgr_funcs = { | |
5556 | .backend_init = &iceland_hwmgr_backend_init, | |
5557 | .backend_fini = &iceland_hwmgr_backend_fini, | |
5558 | .asic_setup = &iceland_setup_asic_task, | |
5559 | .dynamic_state_management_enable = &iceland_enable_dpm_tasks, | |
5560 | .apply_state_adjust_rules = iceland_apply_state_adjust_rules, | |
5561 | .force_dpm_level = &iceland_force_dpm_level, | |
5562 | .power_state_set = iceland_set_power_state_tasks, | |
5563 | .get_power_state_size = iceland_get_power_state_size, | |
5564 | .get_mclk = iceland_dpm_get_mclk, | |
5565 | .get_sclk = iceland_dpm_get_sclk, | |
5566 | .patch_boot_state = iceland_dpm_patch_boot_state, | |
5567 | .get_pp_table_entry = iceland_get_pp_table_entry, | |
5568 | .get_num_of_pp_table_entries = iceland_get_num_of_entries, | |
5569 | .print_current_perforce_level = iceland_print_current_perforce_level, | |
5570 | .powerdown_uvd = iceland_phm_powerdown_uvd, | |
5571 | .powergate_uvd = iceland_phm_powergate_uvd, | |
5572 | .powergate_vce = iceland_phm_powergate_vce, | |
5573 | .disable_clock_power_gating = iceland_phm_disable_clock_power_gating, | |
5574 | .update_clock_gatings = iceland_phm_update_clock_gatings, | |
5575 | .notify_smc_display_config_after_ps_adjustment = iceland_notify_smc_display_config_after_ps_adjustment, | |
5576 | .display_config_changed = iceland_display_configuration_changed_task, | |
5577 | .set_max_fan_pwm_output = iceland_set_max_fan_pwm_output, | |
5578 | .set_max_fan_rpm_output = iceland_set_max_fan_rpm_output, | |
5579 | .get_temperature = iceland_thermal_get_temperature, | |
5580 | .stop_thermal_controller = iceland_thermal_stop_thermal_controller, | |
5581 | .get_fan_speed_info = iceland_fan_ctrl_get_fan_speed_info, | |
5582 | .get_fan_speed_percent = iceland_fan_ctrl_get_fan_speed_percent, | |
5583 | .set_fan_speed_percent = iceland_fan_ctrl_set_fan_speed_percent, | |
5584 | .reset_fan_speed_to_default = iceland_fan_ctrl_reset_fan_speed_to_default, | |
5585 | .get_fan_speed_rpm = iceland_fan_ctrl_get_fan_speed_rpm, | |
5586 | .set_fan_speed_rpm = iceland_fan_ctrl_set_fan_speed_rpm, | |
5587 | .uninitialize_thermal_controller = iceland_thermal_ctrl_uninitialize_thermal_controller, | |
5588 | .register_internal_thermal_interrupt = iceland_register_internal_thermal_interrupt, | |
5589 | .check_smc_update_required_for_display_configuration = iceland_check_smc_update_required_for_display_configuration, | |
5590 | .check_states_equal = iceland_check_states_equal, | |
5591 | .set_fan_control_mode = iceland_set_fan_control_mode, | |
5592 | .get_fan_control_mode = iceland_get_fan_control_mode, | |
5593 | .force_clock_level = iceland_force_clock_level, | |
5594 | .print_clock_levels = iceland_print_clock_levels, | |
5595 | .get_sclk_od = iceland_get_sclk_od, | |
5596 | .set_sclk_od = iceland_set_sclk_od, | |
5597 | .get_mclk_od = iceland_get_mclk_od, | |
5598 | .set_mclk_od = iceland_set_mclk_od, | |
5599 | }; | |
5600 | ||
5601 | int iceland_hwmgr_init(struct pp_hwmgr *hwmgr) | |
5602 | { | |
5603 | iceland_hwmgr *data; | |
5604 | ||
5605 | data = kzalloc (sizeof(iceland_hwmgr), GFP_KERNEL); | |
5606 | if (data == NULL) | |
5607 | return -ENOMEM; | |
5608 | memset(data, 0x00, sizeof(iceland_hwmgr)); | |
5609 | ||
5610 | hwmgr->backend = data; | |
5611 | hwmgr->hwmgr_func = &iceland_hwmgr_funcs; | |
5612 | hwmgr->pptable_func = &pptable_funcs; | |
5613 | ||
5614 | /* thermal */ | |
5615 | pp_iceland_thermal_initialize(hwmgr); | |
5616 | return 0; | |
5617 | } |