[deliverable/linux.git] / drivers / gpu / drm / arm / hdlcd_drv.c

/*
 * Copyright (C) 2013-2015 ARM Limited
 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 *
 *  ARM HDLCD Driver
 */

#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/list.h>
#include <linux/of_graph.h>
#include <linux/of_reserved_mem.h>
#include <linux/pm_runtime.h>

#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_of.h>

#include "hdlcd_drv.h"
#include "hdlcd_regs.h"

static int hdlcd_load(struct drm_device *drm, unsigned long flags)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	struct platform_device *pdev = to_platform_device(drm->dev);
	struct resource *res;
	u32 version;
	int ret;

	hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
	if (IS_ERR(hdlcd->clk))
		return PTR_ERR(hdlcd->clk);

#ifdef CONFIG_DEBUG_FS
	atomic_set(&hdlcd->buffer_underrun_count, 0);
	atomic_set(&hdlcd->bus_error_count, 0);
	atomic_set(&hdlcd->vsync_count, 0);
	atomic_set(&hdlcd->dma_end_count, 0);
#endif

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
	if (IS_ERR(hdlcd->mmio)) {
		DRM_ERROR("failed to map control registers area\n");
		ret = PTR_ERR(hdlcd->mmio);
		hdlcd->mmio = NULL;
		return ret;
	}

	version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
	if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
		DRM_ERROR("unknown product id: 0x%x\n", version);
		return -EINVAL;
	}
	DRM_INFO("found ARM HDLCD version r%dp%d\n",
		(version & HDLCD_VERSION_MAJOR_MASK) >> 8,
		version & HDLCD_VERSION_MINOR_MASK);

	/* Get the optional framebuffer memory resource */
	ret = of_reserved_mem_device_init(drm->dev);
	if (ret && ret != -ENODEV)
		return ret;

	ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
	if (ret)
		goto setup_fail;

	ret = hdlcd_setup_crtc(drm);
	if (ret < 0) {
		DRM_ERROR("failed to create crtc\n");
		goto setup_fail;
	}

	ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
	if (ret < 0) {
		DRM_ERROR("failed to install IRQ handler\n");
		goto irq_fail;
	}

	return 0;

irq_fail:
	drm_crtc_cleanup(&hdlcd->crtc);
setup_fail:
	of_reserved_mem_device_release(drm->dev);

	return ret;
}

static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;

	drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
}

static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
	.fb_create = drm_fb_cma_create,
	.output_poll_changed = hdlcd_fb_output_poll_changed,
	.atomic_check = drm_atomic_helper_check,
	.atomic_commit = drm_atomic_helper_commit,
};

static void hdlcd_setup_mode_config(struct drm_device *drm)
{
	drm_mode_config_init(drm);
	drm->mode_config.min_width = 0;
	drm->mode_config.min_height = 0;
	drm->mode_config.max_width = HDLCD_MAX_XRES;
	drm->mode_config.max_height = HDLCD_MAX_YRES;
	drm->mode_config.funcs = &hdlcd_mode_config_funcs;
}

static void hdlcd_lastclose(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;

	drm_fbdev_cma_restore_mode(hdlcd->fbdev);
}

static irqreturn_t hdlcd_irq(int irq, void *arg)
{
	struct drm_device *drm = arg;
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	unsigned long irq_status;

	irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);

#ifdef CONFIG_DEBUG_FS
	if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
		atomic_inc(&hdlcd->buffer_underrun_count);

	if (irq_status & HDLCD_INTERRUPT_DMA_END)
		atomic_inc(&hdlcd->dma_end_count);

	if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
		atomic_inc(&hdlcd->bus_error_count);

	if (irq_status & HDLCD_INTERRUPT_VSYNC)
		atomic_inc(&hdlcd->vsync_count);

#endif
	if (irq_status & HDLCD_INTERRUPT_VSYNC)
		drm_crtc_handle_vblank(&hdlcd->crtc);

	/* acknowledge interrupt(s) */
	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);

	return IRQ_HANDLED;
}

static void hdlcd_irq_preinstall(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	/* Ensure interrupts are disabled */
	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
}

static int hdlcd_irq_postinstall(struct drm_device *drm)
{
#ifdef CONFIG_DEBUG_FS
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	/* enable debug interrupts */
	irq_mask |= HDLCD_DEBUG_INT_MASK;

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
#endif
	return 0;
}

static void hdlcd_irq_uninstall(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	/* disable all the interrupts that we might have enabled */
	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

#ifdef CONFIG_DEBUG_FS
	/* disable debug interrupts */
	irq_mask &= ~HDLCD_DEBUG_INT_MASK;
#endif

	/* disable vsync interrupts */
	irq_mask &= ~HDLCD_INTERRUPT_VSYNC;

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
}

static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);

	return 0;
}

static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
}

#ifdef CONFIG_DEBUG_FS
static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *drm = node->minor->dev;
	struct hdlcd_drm_private *hdlcd = drm->dev_private;

	seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
	seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
	seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
	seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
	return 0;
}

static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *drm = node->minor->dev;
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	unsigned long clkrate = clk_get_rate(hdlcd->clk);
	unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;

	seq_printf(m, "hw  : %lu\n", clkrate);
	seq_printf(m, "mode: %lu\n", mode_clock);
	return 0;
}

static struct drm_info_list hdlcd_debugfs_list[] = {
	{ "interrupt_count", hdlcd_show_underrun_count, 0 },
	{ "clocks", hdlcd_show_pxlclock, 0 },
	{ "fb", drm_fb_cma_debugfs_show, 0 },
};

static int hdlcd_debugfs_init(struct drm_minor *minor)
{
	return drm_debugfs_create_files(hdlcd_debugfs_list,
		ARRAY_SIZE(hdlcd_debugfs_list),	minor->debugfs_root, minor);
}

static void hdlcd_debugfs_cleanup(struct drm_minor *minor)
{
	drm_debugfs_remove_files(hdlcd_debugfs_list,
		ARRAY_SIZE(hdlcd_debugfs_list), minor);
}
#endif

static const struct file_operations fops = {
	.owner		= THIS_MODULE,
	.open		= drm_open,
	.release	= drm_release,
	.unlocked_ioctl	= drm_ioctl,
#ifdef CONFIG_COMPAT
	.compat_ioctl	= drm_compat_ioctl,
#endif
	.poll		= drm_poll,
	.read		= drm_read,
	.llseek		= noop_llseek,
	.mmap		= drm_gem_cma_mmap,
};

static struct drm_driver hdlcd_driver = {
	.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
			   DRIVER_MODESET | DRIVER_PRIME |
			   DRIVER_ATOMIC,
	.lastclose = hdlcd_lastclose,
	.irq_handler = hdlcd_irq,
	.irq_preinstall = hdlcd_irq_preinstall,
	.irq_postinstall = hdlcd_irq_postinstall,
	.irq_uninstall = hdlcd_irq_uninstall,
	.get_vblank_counter = drm_vblank_no_hw_counter,
	.enable_vblank = hdlcd_enable_vblank,
	.disable_vblank = hdlcd_disable_vblank,
	.gem_free_object_unlocked = drm_gem_cma_free_object,
	.gem_vm_ops = &drm_gem_cma_vm_ops,
	.dumb_create = drm_gem_cma_dumb_create,
	.dumb_map_offset = drm_gem_cma_dumb_map_offset,
	.dumb_destroy = drm_gem_dumb_destroy,
	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = drm_gem_prime_export,
	.gem_prime_import = drm_gem_prime_import,
	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	.gem_prime_vmap = drm_gem_cma_prime_vmap,
	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
	.gem_prime_mmap = drm_gem_cma_prime_mmap,
#ifdef CONFIG_DEBUG_FS
	.debugfs_init = hdlcd_debugfs_init,
	.debugfs_cleanup = hdlcd_debugfs_cleanup,
#endif
	.fops = &fops,
	.name = "hdlcd",
	.desc = "ARM HDLCD Controller DRM",
	.date = "20151021",
	.major = 1,
	.minor = 0,
};

static int hdlcd_drm_bind(struct device *dev)
{
	struct drm_device *drm;
	struct hdlcd_drm_private *hdlcd;
	int ret;

	hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
	if (!hdlcd)
		return -ENOMEM;

	drm = drm_dev_alloc(&hdlcd_driver, dev);
	if (!drm)
		return -ENOMEM;

	drm->dev_private = hdlcd;
	dev_set_drvdata(dev, drm);

	hdlcd_setup_mode_config(drm);
	ret = hdlcd_load(drm, 0);
	if (ret)
		goto err_free;

	ret = drm_dev_register(drm, 0);
	if (ret)
		goto err_unload;

	ret = component_bind_all(dev, drm);
	if (ret) {
		DRM_ERROR("Failed to bind all components\n");
		goto err_unregister;
	}

	ret = pm_runtime_set_active(dev);
	if (ret)
		goto err_pm_active;

	pm_runtime_enable(dev);

	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
	if (ret < 0) {
		DRM_ERROR("failed to initialise vblank\n");
		goto err_vblank;
	}

	drm_mode_config_reset(drm);
	drm_kms_helper_poll_init(drm);

	hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
					  drm->mode_config.num_connector);

	if (IS_ERR(hdlcd->fbdev)) {
		ret = PTR_ERR(hdlcd->fbdev);
		hdlcd->fbdev = NULL;
		goto err_fbdev;
	}

	return 0;

err_fbdev:
	drm_kms_helper_poll_fini(drm);
	drm_mode_config_cleanup(drm);
	drm_vblank_cleanup(drm);
err_vblank:
	pm_runtime_disable(drm->dev);
err_pm_active:
	component_unbind_all(dev, drm);
err_unregister:
	drm_dev_unregister(drm);
err_unload:
	drm_irq_uninstall(drm);
	of_reserved_mem_device_release(drm->dev);
err_free:
	dev_set_drvdata(dev, NULL);
	drm_dev_unref(drm);

	return ret;
}

static void hdlcd_drm_unbind(struct device *dev)
{
	struct drm_device *drm = dev_get_drvdata(dev);
	struct hdlcd_drm_private *hdlcd = drm->dev_private;

	if (hdlcd->fbdev) {
		drm_fbdev_cma_fini(hdlcd->fbdev);
		hdlcd->fbdev = NULL;
	}
	drm_kms_helper_poll_fini(drm);
	component_unbind_all(dev, drm);
	drm_vblank_cleanup(drm);
	pm_runtime_get_sync(drm->dev);
	drm_irq_uninstall(drm);
	pm_runtime_put_sync(drm->dev);
	pm_runtime_disable(drm->dev);
	of_reserved_mem_device_release(drm->dev);
	drm_mode_config_cleanup(drm);
	drm_dev_unregister(drm);
	drm_dev_unref(drm);
	drm->dev_private = NULL;
	dev_set_drvdata(dev, NULL);
}

static const struct component_master_ops hdlcd_master_ops = {
	.bind		= hdlcd_drm_bind,
	.unbind		= hdlcd_drm_unbind,
};

static int compare_dev(struct device *dev, void *data)
{
	return dev->of_node == data;
}

static int hdlcd_probe(struct platform_device *pdev)
{
	struct device_node *port, *ep;
	struct component_match *match = NULL;

	if (!pdev->dev.of_node)
		return -ENODEV;

	/* there is only one output port inside each device, find it */
	ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
	if (!ep)
		return -ENODEV;

	if (!of_device_is_available(ep)) {
		of_node_put(ep);
		return -ENODEV;
	}

	/* add the remote encoder port as component */
	port = of_graph_get_remote_port_parent(ep);
	of_node_put(ep);
	if (!port || !of_device_is_available(port)) {
		of_node_put(port);
		return -EAGAIN;
	}

	component_match_add(&pdev->dev, &match, compare_dev, port);

	return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
					       match);
}

static int hdlcd_remove(struct platform_device *pdev)
{
	component_master_del(&pdev->dev, &hdlcd_master_ops);
	return 0;
}

static const struct of_device_id  hdlcd_of_match[] = {
	{ .compatible	= "arm,hdlcd" },
	{},
};
MODULE_DEVICE_TABLE(of, hdlcd_of_match);

static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
{
	struct drm_device *drm = dev_get_drvdata(dev);
	struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;

	if (!hdlcd)
		return 0;

	drm_kms_helper_poll_disable(drm);

	hdlcd->state = drm_atomic_helper_suspend(drm);
	if (IS_ERR(hdlcd->state)) {
		drm_kms_helper_poll_enable(drm);
		return PTR_ERR(hdlcd->state);
	}

	return 0;
}

static int __maybe_unused hdlcd_pm_resume(struct device *dev)
{
	struct drm_device *drm = dev_get_drvdata(dev);
	struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;

	if (!hdlcd)
		return 0;

	drm_atomic_helper_resume(drm, hdlcd->state);
	drm_kms_helper_poll_enable(drm);
	pm_runtime_set_active(dev);

	return 0;
}

static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);

static struct platform_driver hdlcd_platform_driver = {
	.probe		= hdlcd_probe,
	.remove		= hdlcd_remove,
	.driver	= {
		.name = "hdlcd",
		.pm = &hdlcd_pm_ops,
		.of_match_table	= hdlcd_of_match,
	},
};

module_platform_driver(hdlcd_platform_driver);

MODULE_AUTHOR("Liviu Dudau");
MODULE_DESCRIPTION("ARM HDLCD DRM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8e22d792 LD	1	/*
	2	* Copyright (C) 2013-2015 ARM Limited
	3	* Author: Liviu Dudau <Liviu.Dudau@arm.com>
	4	*
	5	* This file is subject to the terms and conditions of the GNU General Public
	6	* License. See the file COPYING in the main directory of this archive
	7	* for more details.
	8	*
	9	* ARM HDLCD Driver
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/clk.h>
	15	#include <linux/component.h>
	16	#include <linux/list.h>
	17	#include <linux/of_graph.h>
	18	#include <linux/of_reserved_mem.h>
	19	#include <linux/pm_runtime.h>
	20
	21	#include <drm/drmP.h>
	22	#include <drm/drm_atomic_helper.h>
	23	#include <drm/drm_crtc.h>
	24	#include <drm/drm_crtc_helper.h>
	25	#include <drm/drm_fb_helper.h>
	26	#include <drm/drm_fb_cma_helper.h>
	27	#include <drm/drm_gem_cma_helper.h>
	28	#include <drm/drm_of.h>
	29
	30	#include "hdlcd_drv.h"
	31	#include "hdlcd_regs.h"
	32
	33	static int hdlcd_load(struct drm_device *drm, unsigned long flags)
	34	{
	35	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	36	struct platform_device *pdev = to_platform_device(drm->dev);
	37	struct resource *res;
	38	u32 version;
	39	int ret;
	40
	41	hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
	42	if (IS_ERR(hdlcd->clk))
	43	return PTR_ERR(hdlcd->clk);
	44
	45	#ifdef CONFIG_DEBUG_FS
	46	atomic_set(&hdlcd->buffer_underrun_count, 0);
	47	atomic_set(&hdlcd->bus_error_count, 0);
	48	atomic_set(&hdlcd->vsync_count, 0);
	49	atomic_set(&hdlcd->dma_end_count, 0);
	50	#endif
	51
8e22d792 LD	52	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	53	hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
	54	if (IS_ERR(hdlcd->mmio)) {
	55	DRM_ERROR("failed to map control registers area\n");
69c2565a	56	ret = PTR_ERR(hdlcd->mmio);
8e22d792	57	hdlcd->mmio = NULL;
69c2565a	58	return ret;
8e22d792 LD	59	}
	60
	61	version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
	62	if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
	63	DRM_ERROR("unknown product id: 0x%x\n", version);
61a6dcd7	64	return -EINVAL;
8e22d792 LD	65	}
	66	DRM_INFO("found ARM HDLCD version r%dp%d\n",
	67	(version & HDLCD_VERSION_MAJOR_MASK) >> 8,
	68	version & HDLCD_VERSION_MINOR_MASK);
	69
	70	/* Get the optional framebuffer memory resource */
	71	ret = of_reserved_mem_device_init(drm->dev);
	72	if (ret && ret != -ENODEV)
61a6dcd7	73	return ret;
8e22d792 LD	74
	75	ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
	76	if (ret)
	77	goto setup_fail;
	78
	79	ret = hdlcd_setup_crtc(drm);
	80	if (ret < 0) {
	81	DRM_ERROR("failed to create crtc\n");
	82	goto setup_fail;
	83	}
	84
8e22d792	85	ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
8e22d792 LD	86	if (ret < 0) {
	87	DRM_ERROR("failed to install IRQ handler\n");
	88	goto irq_fail;
	89	}
	90
	91	return 0;
	92
	93	irq_fail:
	94	drm_crtc_cleanup(&hdlcd->crtc);
	95	setup_fail:
	96	of_reserved_mem_device_release(drm->dev);
8e22d792 LD	97
	98	return ret;
	99	}
	100
	101	static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
	102	{
	103	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	104
536cea60	105	drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
8e22d792 LD	106	}
8e22d792 LD	107
8e22d792 LD	108	static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
	109	.fb_create = drm_fb_cma_create,
	110	.output_poll_changed = hdlcd_fb_output_poll_changed,
	111	.atomic_check = drm_atomic_helper_check,
2bd6cc8c	112	.atomic_commit = drm_atomic_helper_commit,
8e22d792 LD	113	};
	114
	115	static void hdlcd_setup_mode_config(struct drm_device *drm)
	116	{
	117	drm_mode_config_init(drm);
	118	drm->mode_config.min_width = 0;
	119	drm->mode_config.min_height = 0;
	120	drm->mode_config.max_width = HDLCD_MAX_XRES;
	121	drm->mode_config.max_height = HDLCD_MAX_YRES;
	122	drm->mode_config.funcs = &hdlcd_mode_config_funcs;
	123	}
	124
	125	static void hdlcd_lastclose(struct drm_device *drm)
	126	{
	127	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	128
	129	drm_fbdev_cma_restore_mode(hdlcd->fbdev);
	130	}
	131
	132	static irqreturn_t hdlcd_irq(int irq, void *arg)
	133	{
	134	struct drm_device *drm = arg;
	135	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	136	unsigned long irq_status;
	137
	138	irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
	139
	140	#ifdef CONFIG_DEBUG_FS
	141	if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
	142	atomic_inc(&hdlcd->buffer_underrun_count);
	143
	144	if (irq_status & HDLCD_INTERRUPT_DMA_END)
	145	atomic_inc(&hdlcd->dma_end_count);
	146
	147	if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
	148	atomic_inc(&hdlcd->bus_error_count);
	149
	150	if (irq_status & HDLCD_INTERRUPT_VSYNC)
	151	atomic_inc(&hdlcd->vsync_count);
	152
	153	#endif
38c8c22c	154	if (irq_status & HDLCD_INTERRUPT_VSYNC)
8e22d792 LD	155	drm_crtc_handle_vblank(&hdlcd->crtc);
8e22d792 LD	156
8e22d792 LD	157	/* acknowledge interrupt(s) */
	158	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
	159
	160	return IRQ_HANDLED;
	161	}
	162
	163	static void hdlcd_irq_preinstall(struct drm_device *drm)
	164	{
	165	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	166	/* Ensure interrupts are disabled */
	167	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
	168	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
	169	}
	170
	171	static int hdlcd_irq_postinstall(struct drm_device *drm)
	172	{
	173	#ifdef CONFIG_DEBUG_FS
	174	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	175	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	176
	177	/* enable debug interrupts */
	178	irq_mask \|= HDLCD_DEBUG_INT_MASK;
	179
	180	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
	181	#endif
	182	return 0;
	183	}
	184
	185	static void hdlcd_irq_uninstall(struct drm_device *drm)
	186	{
	187	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	188	/* disable all the interrupts that we might have enabled */
	189	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	190
	191	#ifdef CONFIG_DEBUG_FS
	192	/* disable debug interrupts */
	193	irq_mask &= ~HDLCD_DEBUG_INT_MASK;
	194	#endif
	195
	196	/* disable vsync interrupts */
	197	irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
	198
	199	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
	200	}
	201
	202	static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc)
	203	{
	204	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	205	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	206
	207	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask \| HDLCD_INTERRUPT_VSYNC);
	208
	209	return 0;
	210	}
	211
	212	static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc)
	213	{
	214	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	215	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	216
	217	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
	218	}
	219
	220	#ifdef CONFIG_DEBUG_FS
221	static int hdlcd_show_underrun_count(struct seq_file m, void arg)
222	{
223	struct drm_info_node node = (struct drm_info_node )m->private;
224	struct drm_device *drm = node->minor->dev;
225	struct hdlcd_drm_private *hdlcd = drm->dev_private;
226
227	seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
228	seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
229	seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
230	seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
231	return 0;
232	}
233
234	static int hdlcd_show_pxlclock(struct seq_file m, void arg)
235	{
236	struct drm_info_node node = (struct drm_info_node )m->private;
237	struct drm_device *drm = node->minor->dev;
238	struct hdlcd_drm_private *hdlcd = drm->dev_private;
239	unsigned long clkrate = clk_get_rate(hdlcd->clk);
240	unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
241
242	seq_printf(m, "hw : %lu\n", clkrate);
243	seq_printf(m, "mode: %lu\n", mode_clock);
244	return 0;
245	}
246
247	static struct drm_info_list hdlcd_debugfs_list[] = {
248	{ "interrupt_count", hdlcd_show_underrun_count, 0 },
249	{ "clocks", hdlcd_show_pxlclock, 0 },
f6c68b4b	250	{ "fb", drm_fb_cma_debugfs_show, 0 },
8e22d792 LD	251	};
	252
	253	static int hdlcd_debugfs_init(struct drm_minor *minor)
	254	{
	255	return drm_debugfs_create_files(hdlcd_debugfs_list,
	256	ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
	257	}
	258
	259	static void hdlcd_debugfs_cleanup(struct drm_minor *minor)
	260	{
	261	drm_debugfs_remove_files(hdlcd_debugfs_list,
	262	ARRAY_SIZE(hdlcd_debugfs_list), minor);
	263	}
	264	#endif
	265
	266	static const struct file_operations fops = {
	267	.owner = THIS_MODULE,
	268	.open = drm_open,
	269	.release = drm_release,
	270	.unlocked_ioctl = drm_ioctl,
	271	#ifdef CONFIG_COMPAT
	272	.compat_ioctl = drm_compat_ioctl,
	273	#endif
	274	.poll = drm_poll,
	275	.read = drm_read,
	276	.llseek = noop_llseek,
	277	.mmap = drm_gem_cma_mmap,
	278	};
	279
	280	static struct drm_driver hdlcd_driver = {
	281	.driver_features = DRIVER_HAVE_IRQ \| DRIVER_GEM \|
	282	DRIVER_MODESET \| DRIVER_PRIME \|
	283	DRIVER_ATOMIC,
	284	.lastclose = hdlcd_lastclose,
	285	.irq_handler = hdlcd_irq,
	286	.irq_preinstall = hdlcd_irq_preinstall,
	287	.irq_postinstall = hdlcd_irq_postinstall,
	288	.irq_uninstall = hdlcd_irq_uninstall,
	289	.get_vblank_counter = drm_vblank_no_hw_counter,
	290	.enable_vblank = hdlcd_enable_vblank,
	291	.disable_vblank = hdlcd_disable_vblank,
6d910bfa	292	.gem_free_object_unlocked = drm_gem_cma_free_object,
8e22d792 LD	293	.gem_vm_ops = &drm_gem_cma_vm_ops,
	294	.dumb_create = drm_gem_cma_dumb_create,
	295	.dumb_map_offset = drm_gem_cma_dumb_map_offset,
	296	.dumb_destroy = drm_gem_dumb_destroy,
	297	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	298	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	299	.gem_prime_export = drm_gem_prime_export,
	300	.gem_prime_import = drm_gem_prime_import,
	301	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
	302	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
	303	.gem_prime_vmap = drm_gem_cma_prime_vmap,
	304	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
	305	.gem_prime_mmap = drm_gem_cma_prime_mmap,
	306	#ifdef CONFIG_DEBUG_FS
	307	.debugfs_init = hdlcd_debugfs_init,
	308	.debugfs_cleanup = hdlcd_debugfs_cleanup,
	309	#endif
	310	.fops = &fops,
	311	.name = "hdlcd",
	312	.desc = "ARM HDLCD Controller DRM",
	313	.date = "20151021",
	314	.major = 1,
	315	.minor = 0,
	316	};
	317
	318	static int hdlcd_drm_bind(struct device *dev)
	319	{
	320	struct drm_device *drm;
	321	struct hdlcd_drm_private *hdlcd;
	322	int ret;
	323
	324	hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
	325	if (!hdlcd)
	326	return -ENOMEM;
	327
	328	drm = drm_dev_alloc(&hdlcd_driver, dev);
	329	if (!drm)
	330	return -ENOMEM;
	331
	332	drm->dev_private = hdlcd;
a95acec1 LD	333	dev_set_drvdata(dev, drm);
a95acec1 LD	334
8e22d792 LD	335	hdlcd_setup_mode_config(drm);
	336	ret = hdlcd_load(drm, 0);
	337	if (ret)
	338	goto err_free;
	339
	340	ret = drm_dev_register(drm, 0);
	341	if (ret)
	342	goto err_unload;
	343
8e22d792 LD	344	ret = component_bind_all(dev, drm);
	345	if (ret) {
	346	DRM_ERROR("Failed to bind all components\n");
	347	goto err_unregister;
	348	}
	349
a95acec1 LD	350	ret = pm_runtime_set_active(dev);
	351	if (ret)
	352	goto err_pm_active;
	353
	354	pm_runtime_enable(dev);
	355
8e22d792 LD	356	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
	357	if (ret < 0) {
	358	DRM_ERROR("failed to initialise vblank\n");
	359	goto err_vblank;
	360	}
8e22d792 LD	361
	362	drm_mode_config_reset(drm);
	363	drm_kms_helper_poll_init(drm);
	364
	365	hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
	366	drm->mode_config.num_connector);
	367
	368	if (IS_ERR(hdlcd->fbdev)) {
	369	ret = PTR_ERR(hdlcd->fbdev);
	370	hdlcd->fbdev = NULL;
	371	goto err_fbdev;
	372	}
	373
	374	return 0;
	375
	376	err_fbdev:
	377	drm_kms_helper_poll_fini(drm);
	378	drm_mode_config_cleanup(drm);
	379	drm_vblank_cleanup(drm);
	380	err_vblank:
a95acec1 LD	381	pm_runtime_disable(drm->dev);
a95acec1 LD	382	err_pm_active:
8e22d792 LD	383	component_unbind_all(dev, drm);
	384	err_unregister:
	385	drm_dev_unregister(drm);
	386	err_unload:
8e22d792	387	drm_irq_uninstall(drm);
8e22d792	388	of_reserved_mem_device_release(drm->dev);
8e22d792	389	err_free:
a95acec1	390	dev_set_drvdata(dev, NULL);
8e22d792 LD	391	drm_dev_unref(drm);
	392
	393	return ret;
	394	}
	395
	396	static void hdlcd_drm_unbind(struct device *dev)
	397	{
	398	struct drm_device *drm = dev_get_drvdata(dev);
	399	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	400
	401	if (hdlcd->fbdev) {
	402	drm_fbdev_cma_fini(hdlcd->fbdev);
	403	hdlcd->fbdev = NULL;
	404	}
	405	drm_kms_helper_poll_fini(drm);
	406	component_unbind_all(dev, drm);
	407	drm_vblank_cleanup(drm);
	408	pm_runtime_get_sync(drm->dev);
	409	drm_irq_uninstall(drm);
	410	pm_runtime_put_sync(drm->dev);
	411	pm_runtime_disable(drm->dev);
	412	of_reserved_mem_device_release(drm->dev);
8e22d792 LD	413	drm_mode_config_cleanup(drm);
	414	drm_dev_unregister(drm);
	415	drm_dev_unref(drm);
	416	drm->dev_private = NULL;
	417	dev_set_drvdata(dev, NULL);
	418	}
	419
	420	static const struct component_master_ops hdlcd_master_ops = {
	421	.bind = hdlcd_drm_bind,
	422	.unbind = hdlcd_drm_unbind,
	423	};
	424
	425	static int compare_dev(struct device dev, void data)
	426	{
	427	return dev->of_node == data;
	428	}
	429
	430	static int hdlcd_probe(struct platform_device *pdev)
	431	{
	432	struct device_node port, ep;
	433	struct component_match *match = NULL;
	434
	435	if (!pdev->dev.of_node)
	436	return -ENODEV;
	437
	438	/* there is only one output port inside each device, find it */
	439	ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
	440	if (!ep)
	441	return -ENODEV;
	442
	443	if (!of_device_is_available(ep)) {
	444	of_node_put(ep);
	445	return -ENODEV;
	446	}
	447
	448	/* add the remote encoder port as component */
	449	port = of_graph_get_remote_port_parent(ep);
	450	of_node_put(ep);
	451	if (!port \|\| !of_device_is_available(port)) {
	452	of_node_put(port);
	453	return -EAGAIN;
	454	}
	455
	456	component_match_add(&pdev->dev, &match, compare_dev, port);
	457
	458	return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
	459	match);
	460	}
	461
	462	static int hdlcd_remove(struct platform_device *pdev)
	463	{
	464	component_master_del(&pdev->dev, &hdlcd_master_ops);
	465	return 0;
	466	}
	467
	468	static const struct of_device_id hdlcd_of_match[] = {
	469	{ .compatible = "arm,hdlcd" },
	470	{},
	471	};
	472	MODULE_DEVICE_TABLE(of, hdlcd_of_match);
	473
	474	static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
	475	{
	476	struct drm_device *drm = dev_get_drvdata(dev);
a95acec1	477	struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
8e22d792	478
a95acec1	479	if (!hdlcd)
8e22d792 LD	480	return 0;
8e22d792 LD	481
a95acec1 LD	482	drm_kms_helper_poll_disable(drm);
	483
	484	hdlcd->state = drm_atomic_helper_suspend(drm);
	485	if (IS_ERR(hdlcd->state)) {
	486	drm_kms_helper_poll_enable(drm);
	487	return PTR_ERR(hdlcd->state);
	488	}
	489
8e22d792 LD	490	return 0;
	491	}
	492
	493	static int __maybe_unused hdlcd_pm_resume(struct device *dev)
	494	{
	495	struct drm_device *drm = dev_get_drvdata(dev);
a95acec1	496	struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
8e22d792	497
a95acec1	498	if (!hdlcd)
8e22d792 LD	499	return 0;
8e22d792 LD	500
a95acec1 LD	501	drm_atomic_helper_resume(drm, hdlcd->state);
	502	drm_kms_helper_poll_enable(drm);
	503	pm_runtime_set_active(dev);
	504
8e22d792 LD	505	return 0;
	506	}
	507
	508	static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
	509
	510	static struct platform_driver hdlcd_platform_driver = {
	511	.probe = hdlcd_probe,
	512	.remove = hdlcd_remove,
	513	.driver = {
	514	.name = "hdlcd",
	515	.pm = &hdlcd_pm_ops,
	516	.of_match_table = hdlcd_of_match,
	517	},
	518	};
	519
	520	module_platform_driver(hdlcd_platform_driver);
	521
	522	MODULE_AUTHOR("Liviu Dudau");
	523	MODULE_DESCRIPTION("ARM HDLCD DRM driver");
	524	MODULE_LICENSE("GPL v2");