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drm: bridge: analogix/dp: rename register constants
[deliverable/linux.git] / drivers / gpu / drm / bridge / analogix / analogix_dp_core.c
CommitLineData
3424e3a4
YY		 1/*
2* Analogix DP (Display Port) core interface driver.
3*
4* Copyright (C) 2012 Samsung Electronics Co., Ltd.
5* Author: Jingoo Han <jg1.han@samsung.com>
6*
7* This program is free software; you can redistribute it and/or modify it
8* under the terms of the GNU General Public License as published by the
9* Free Software Foundation; either version 2 of the License, or (at your
10* option) any later version.
11*/
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/interrupt.h>
19#include <linux/of.h>
20#include <linux/of_gpio.h>
21#include <linux/gpio.h>
22#include <linux/component.h>
23#include <linux/phy/phy.h>
24
25#include <drm/drmP.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_crtc.h>
28#include <drm/drm_crtc_helper.h>
29#include <drm/drm_panel.h>
30
31#include <drm/bridge/analogix_dp.h>
32
33#include "analogix_dp_core.h"
34
35#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
36
37struct bridge_init {
38 struct i2c_client *client;
39 struct device_node *node;
40};
41
42static void analogix_dp_init_dp(struct analogix_dp_device *dp)
43{
44 analogix_dp_reset(dp);
45
46 analogix_dp_swreset(dp);
47
48 analogix_dp_init_analog_param(dp);
49 analogix_dp_init_interrupt(dp);
50
51 /* SW defined function Normal operation */
52 analogix_dp_enable_sw_function(dp);
53
54 analogix_dp_config_interrupt(dp);
55 analogix_dp_init_analog_func(dp);
56
57 analogix_dp_init_hpd(dp);
58 analogix_dp_init_aux(dp);
59}
60
61static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
62{
63 int timeout_loop = 0;
64
65 while (analogix_dp_get_plug_in_status(dp) != 0) {
66 timeout_loop++;
67 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
68 dev_err(dp->dev, "failed to get hpd plug status\n");
69 return -ETIMEDOUT;
70 }
71 usleep_range(10, 11);
72 }
73
74 return 0;
75}
76
77static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
78{
79 int i;
80 unsigned char sum = 0;
81
82 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
83 sum = sum + edid_data[i];
84
85 return sum;
86}
87
88static int analogix_dp_read_edid(struct analogix_dp_device *dp)
89{
90 unsigned char edid[EDID_BLOCK_LENGTH * 2];
91 unsigned int extend_block = 0;
92 unsigned char sum;
93 unsigned char test_vector;
94 int retval;
95
96 /*
97 * EDID device address is 0x50.
98 * However, if necessary, you must have set upper address
99 * into E-EDID in I2C device, 0x30.
100 */
101
102 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
103 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
104 EDID_EXTENSION_FLAG,
105 &extend_block);
106 if (retval)
107 return retval;
108
109 if (extend_block > 0) {
110 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
111
112 /* Read EDID data */
113 retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
114 EDID_HEADER_PATTERN,
115 EDID_BLOCK_LENGTH,
116 &edid[EDID_HEADER_PATTERN]);
117 if (retval != 0) {
118 dev_err(dp->dev, "EDID Read failed!\n");
119 return -EIO;
120 }
121 sum = analogix_dp_calc_edid_check_sum(edid);
122 if (sum != 0) {
123 dev_err(dp->dev, "EDID bad checksum!\n");
124 return -EIO;
125 }
126
127 /* Read additional EDID data */
128 retval = analogix_dp_read_bytes_from_i2c(dp,
129 I2C_EDID_DEVICE_ADDR,
130 EDID_BLOCK_LENGTH,
131 EDID_BLOCK_LENGTH,
132 &edid[EDID_BLOCK_LENGTH]);
133 if (retval != 0) {
134 dev_err(dp->dev, "EDID Read failed!\n");
135 return -EIO;
136 }
137 sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
138 if (sum != 0) {
139 dev_err(dp->dev, "EDID bad checksum!\n");
140 return -EIO;
141 }
142
143 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
144 &test_vector);
145 if (test_vector & DP_TEST_LINK_EDID_READ) {
146 analogix_dp_write_byte_to_dpcd(dp,
147 DP_TEST_EDID_CHECKSUM,
148 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
149 analogix_dp_write_byte_to_dpcd(dp,
150 DP_TEST_RESPONSE,
151 DP_TEST_EDID_CHECKSUM_WRITE);
152 }
153 } else {
154 dev_info(dp->dev, "EDID data does not include any extensions.\n");
155
156 /* Read EDID data */
157 retval = analogix_dp_read_bytes_from_i2c(dp,
158 I2C_EDID_DEVICE_ADDR,
159 EDID_HEADER_PATTERN,
160 EDID_BLOCK_LENGTH,
161 &edid[EDID_HEADER_PATTERN]);
162 if (retval != 0) {
163 dev_err(dp->dev, "EDID Read failed!\n");
164 return -EIO;
165 }
166 sum = analogix_dp_calc_edid_check_sum(edid);
167 if (sum != 0) {
168 dev_err(dp->dev, "EDID bad checksum!\n");
169 return -EIO;
170 }
171
172 analogix_dp_read_byte_from_dpcd(dp,
173 DP_TEST_REQUEST,
174 &test_vector);
175 if (test_vector & DP_TEST_LINK_EDID_READ) {
176 analogix_dp_write_byte_to_dpcd(dp,
177 DP_TEST_EDID_CHECKSUM,
178 edid[EDID_CHECKSUM]);
179 analogix_dp_write_byte_to_dpcd(dp,
180 DP_TEST_RESPONSE,
181 DP_TEST_EDID_CHECKSUM_WRITE);
182 }
183 }
184
185 dev_dbg(dp->dev, "EDID Read success!\n");
186 return 0;
187}
188
189static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
190{
191 u8 buf[12];
192 int i;
193 int retval;
194
195 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
196 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
197 12, buf);
198 if (retval)
199 return retval;
200
201 /* Read EDID */
202 for (i = 0; i < 3; i++) {
203 retval = analogix_dp_read_edid(dp);
204 if (!retval)
205 break;
206 }
207
208 return retval;
209}
210
211static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
212 bool enable)
213{
214 u8 data;
215
216 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
217
218 if (enable)
219 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
220 DP_LANE_COUNT_ENHANCED_FRAME_EN |
221 DPCD_LANE_COUNT_SET(data));
222 else
223 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
224 DPCD_LANE_COUNT_SET(data));
225}
226
227static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
228{
229 u8 data;
230 int retval;
231
232 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
233 retval = DPCD_ENHANCED_FRAME_CAP(data);
234
235 return retval;
236}
237
238static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
239{
240 u8 data;
241
242 data = analogix_dp_is_enhanced_mode_available(dp);
243 analogix_dp_enable_rx_to_enhanced_mode(dp, data);
244 analogix_dp_enable_enhanced_mode(dp, data);
245}
246
247static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
248{
249 analogix_dp_set_training_pattern(dp, DP_NONE);
250
251 analogix_dp_write_byte_to_dpcd(dp,
252 DP_TRAINING_PATTERN_SET,
253 DP_TRAINING_PATTERN_DISABLE);
254}
255
256static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
257 int pre_emphasis, int lane)
258{
259 switch (lane) {
260 case 0:
261 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
262 break;
263 case 1:
264 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
265 break;
266
267 case 2:
268 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
269 break;
270
271 case 3:
272 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
273 break;
274 }
275}
276
277static int analogix_dp_link_start(struct analogix_dp_device *dp)
278{
279 u8 buf[4];
280 int lane, lane_count, pll_tries, retval;
281
282 lane_count = dp->link_train.lane_count;
283
284 dp->link_train.lt_state = CLOCK_RECOVERY;
285 dp->link_train.eq_loop = 0;
286
287 for (lane = 0; lane < lane_count; lane++)
288 dp->link_train.cr_loop[lane] = 0;
289
290 /* Set link rate and count as you want to establish*/
291 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
292 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
293
294 /* Setup RX configuration */
295 buf[0] = dp->link_train.link_rate;
296 buf[1] = dp->link_train.lane_count;
297 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
298 2, buf);
299 if (retval)
300 return retval;
301
302 /* Set TX pre-emphasis to minimum */
303 for (lane = 0; lane < lane_count; lane++)
304 analogix_dp_set_lane_lane_pre_emphasis(dp,
305 PRE_EMPHASIS_LEVEL_0, lane);
306
307 /* Wait for PLL lock */
308 pll_tries = 0;
309 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
310 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
311 dev_err(dp->dev, "Wait for PLL lock timed out\n");
312 return -ETIMEDOUT;
313 }
314
315 pll_tries++;
316 usleep_range(90, 120);
317 }
318
319 /* Set training pattern 1 */
320 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
321
322 /* Set RX training pattern */
323 retval = analogix_dp_write_byte_to_dpcd(dp,
324 DP_TRAINING_PATTERN_SET,
325 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
326 if (retval)
327 return retval;
328
329 for (lane = 0; lane < lane_count; lane++)
330 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
331 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
332
333 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
334 lane_count, buf);
335
336 return retval;
337}
338
339static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
340{
341 int shift = (lane & 1) * 4;
342 u8 link_value = link_status[lane>>1];
343
344 return (link_value >> shift) & 0xf;
345}
346
347static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
348{
349 int lane;
350 u8 lane_status;
351
352 for (lane = 0; lane < lane_count; lane++) {
353 lane_status = analogix_dp_get_lane_status(link_status, lane);
354 if ((lane_status & DP_LANE_CR_DONE) == 0)
355 return -EINVAL;
356 }
357 return 0;
358}
359
360static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
361 int lane_count)
362{
363 int lane;
364 u8 lane_status;
365
366 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
367 return -EINVAL;
368
369 for (lane = 0; lane < lane_count; lane++) {
370 lane_status = analogix_dp_get_lane_status(link_status, lane);
371 lane_status &= DP_CHANNEL_EQ_BITS;
372 if (lane_status != DP_CHANNEL_EQ_BITS)
373 return -EINVAL;
374 }
375
376 return 0;
377}
378
379static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
380 int lane)
381{
382 int shift = (lane & 1) * 4;
383 u8 link_value = adjust_request[lane>>1];
384
385 return (link_value >> shift) & 0x3;
386}
387
388static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
389 u8 adjust_request[2],
390 int lane)
391{
392 int shift = (lane & 1) * 4;
393 u8 link_value = adjust_request[lane>>1];
394
395 return ((link_value >> shift) & 0xc) >> 2;
396}
397
398static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
399 u8 training_lane_set, int lane)
400{
401 switch (lane) {
402 case 0:
403 analogix_dp_set_lane0_link_training(dp, training_lane_set);
404 break;
405 case 1:
406 analogix_dp_set_lane1_link_training(dp, training_lane_set);
407 break;
408
409 case 2:
410 analogix_dp_set_lane2_link_training(dp, training_lane_set);
411 break;
412
413 case 3:
414 analogix_dp_set_lane3_link_training(dp, training_lane_set);
415 break;
416 }
417}
418
419static unsigned int analogix_dp_get_lane_link_training(
420 struct analogix_dp_device *dp,
421 int lane)
422{
423 u32 reg;
424
425 switch (lane) {
426 case 0:
427 reg = analogix_dp_get_lane0_link_training(dp);
428 break;
429 case 1:
430 reg = analogix_dp_get_lane1_link_training(dp);
431 break;
432 case 2:
433 reg = analogix_dp_get_lane2_link_training(dp);
434 break;
435 case 3:
436 reg = analogix_dp_get_lane3_link_training(dp);
437 break;
438 default:
439 WARN_ON(1);
440 return 0;
441 }
442
443 return reg;
444}
445
446static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
447{
448 analogix_dp_training_pattern_dis(dp);
449 analogix_dp_set_enhanced_mode(dp);
450
451 dp->link_train.lt_state = FAILED;
452}
453
454static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
455 u8 adjust_request[2])
456{
457 int lane, lane_count;
458 u8 voltage_swing, pre_emphasis, training_lane;
459
460 lane_count = dp->link_train.lane_count;
461 for (lane = 0; lane < lane_count; lane++) {
462 voltage_swing = analogix_dp_get_adjust_request_voltage(
463 adjust_request, lane);
464 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
465 adjust_request, lane);
466 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
467 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
468
469 if (voltage_swing == VOLTAGE_LEVEL_3)
470 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
471 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
472 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
473
474 dp->link_train.training_lane[lane] = training_lane;
475 }
476}
477
478static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
479{
480 int lane, lane_count, retval;
481 u8 voltage_swing, pre_emphasis, training_lane;
482 u8 link_status[2], adjust_request[2];
483
484 usleep_range(100, 101);
485
486 lane_count = dp->link_train.lane_count;
487
488 retval = analogix_dp_read_bytes_from_dpcd(dp,
489 DP_LANE0_1_STATUS, 2, link_status);
490 if (retval)
491 return retval;
492
493 retval = analogix_dp_read_bytes_from_dpcd(dp,
494 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
495 if (retval)
496 return retval;
497
498 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
499 /* set training pattern 2 for EQ */
500 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
501
502 retval = analogix_dp_write_byte_to_dpcd(dp,
503 DP_TRAINING_PATTERN_SET,
504 DP_LINK_SCRAMBLING_DISABLE |
505 DP_TRAINING_PATTERN_2);
506 if (retval)
507 return retval;
508
509 dev_info(dp->dev, "Link Training Clock Recovery success\n");
510 dp->link_train.lt_state = EQUALIZER_TRAINING;
511 } else {
512 for (lane = 0; lane < lane_count; lane++) {
513 training_lane = analogix_dp_get_lane_link_training(
514 dp, lane);
515 voltage_swing = analogix_dp_get_adjust_request_voltage(
516 adjust_request, lane);
517 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
518 adjust_request, lane);
519
520 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
521 voltage_swing &&
522 DPCD_PRE_EMPHASIS_GET(training_lane) ==
523 pre_emphasis)
524 dp->link_train.cr_loop[lane]++;
525
526 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
527 voltage_swing == VOLTAGE_LEVEL_3 ||
528 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
529 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
530 dp->link_train.cr_loop[lane],
531 voltage_swing, pre_emphasis);
532 analogix_dp_reduce_link_rate(dp);
533 return -EIO;
534 }
535 }
536 }
537
538 analogix_dp_get_adjust_training_lane(dp, adjust_request);
539
540 for (lane = 0; lane < lane_count; lane++)
541 analogix_dp_set_lane_link_training(dp,
542 dp->link_train.training_lane[lane], lane);
543
544 retval = analogix_dp_write_bytes_to_dpcd(dp,
545 DP_TRAINING_LANE0_SET, lane_count,
546 dp->link_train.training_lane);
547 if (retval)
548 return retval;
549
550 return retval;
551}
552
553static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
554{
555 int lane, lane_count, retval;
556 u32 reg;
557 u8 link_align, link_status[2], adjust_request[2];
558
559 usleep_range(400, 401);
560
561 lane_count = dp->link_train.lane_count;
562
563 retval = analogix_dp_read_bytes_from_dpcd(dp,
564 DP_LANE0_1_STATUS, 2, link_status);
565 if (retval)
566 return retval;
567
568 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
569 analogix_dp_reduce_link_rate(dp);
570 return -EIO;
571 }
572
573 retval = analogix_dp_read_bytes_from_dpcd(dp,
574 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
575 if (retval)
576 return retval;
577
578 retval = analogix_dp_read_byte_from_dpcd(dp,
579 DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
580 if (retval)
581 return retval;
582
583 analogix_dp_get_adjust_training_lane(dp, adjust_request);
584
585 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
586 /* traing pattern Set to Normal */
587 analogix_dp_training_pattern_dis(dp);
588
589 dev_info(dp->dev, "Link Training success!\n");
590
591 analogix_dp_get_link_bandwidth(dp, &reg);
592 dp->link_train.link_rate = reg;
593 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
594 dp->link_train.link_rate);
595
596 analogix_dp_get_lane_count(dp, &reg);
597 dp->link_train.lane_count = reg;
598 dev_dbg(dp->dev, "final lane count = %.2x\n",
599 dp->link_train.lane_count);
600
601 /* set enhanced mode if available */
602 analogix_dp_set_enhanced_mode(dp);
603 dp->link_train.lt_state = FINISHED;
604
605 return 0;
606 }
607
608 /* not all locked */
609 dp->link_train.eq_loop++;
610
611 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
612 dev_err(dp->dev, "EQ Max loop\n");
613 analogix_dp_reduce_link_rate(dp);
614 return -EIO;
615 }
616
617 for (lane = 0; lane < lane_count; lane++)
618 analogix_dp_set_lane_link_training(dp,
619 dp->link_train.training_lane[lane], lane);
620
621 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
622 lane_count, dp->link_train.training_lane);
623
624 return retval;
625}
626
627static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
628 u8 *bandwidth)
629{
630 u8 data;
631
632 /*
633 * For DP rev.1.1, Maximum link rate of Main Link lanes
634 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
635 */
636 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
637 *bandwidth = data;
638}
639
640static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
641 u8 *lane_count)
642{
643 u8 data;
644
645 /*
646 * For DP rev.1.1, Maximum number of Main Link lanes
647 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
648 */
649 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
650 *lane_count = DPCD_MAX_LANE_COUNT(data);
651}
652
653static void analogix_dp_init_training(struct analogix_dp_device *dp,
654 enum link_lane_count_type max_lane,
655 enum link_rate_type max_rate)
656{
657 /*
658 * MACRO_RST must be applied after the PLL_LOCK to avoid
659 * the DP inter pair skew issue for at least 10 us
660 */
661 analogix_dp_reset_macro(dp);
662
663 /* Initialize by reading RX's DPCD */
664 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
665 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
666
667 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
668 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
669 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
670 dp->link_train.link_rate);
671 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
672 }
673
674 if (dp->link_train.lane_count == 0) {
675 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
676 dp->link_train.lane_count);
677 dp->link_train.lane_count = (u8)LANE_COUNT1;
678 }
679
680 /* Setup TX lane count & rate */
681 if (dp->link_train.lane_count > max_lane)
682 dp->link_train.lane_count = max_lane;
683 if (dp->link_train.link_rate > max_rate)
684 dp->link_train.link_rate = max_rate;
685
686 /* All DP analog module power up */
687 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
688}
689
690static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
691{
692 int retval = 0, training_finished = 0;
693
694 dp->link_train.lt_state = START;
695
696 /* Process here */
697 while (!retval && !training_finished) {
698 switch (dp->link_train.lt_state) {
699 case START:
700 retval = analogix_dp_link_start(dp);
701 if (retval)
702 dev_err(dp->dev, "LT link start failed!\n");
703 break;
704 case CLOCK_RECOVERY:
705 retval = analogix_dp_process_clock_recovery(dp);
706 if (retval)
707 dev_err(dp->dev, "LT CR failed!\n");
708 break;
709 case EQUALIZER_TRAINING:
710 retval = analogix_dp_process_equalizer_training(dp);
711 if (retval)
712 dev_err(dp->dev, "LT EQ failed!\n");
713 break;
714 case FINISHED:
715 training_finished = 1;
716 break;
717 case FAILED:
718 return -EREMOTEIO;
719 }
720 }
721 if (retval)
722 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
723
724 return retval;
725}
726
727static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
728 u32 count,
729 u32 bwtype)
730{
731 int i;
732 int retval;
733
734 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
735 analogix_dp_init_training(dp, count, bwtype);
736 retval = analogix_dp_sw_link_training(dp);
737 if (retval == 0)
738 break;
739
740 usleep_range(100, 110);
741 }
742
743 return retval;
744}
745
746static int analogix_dp_config_video(struct analogix_dp_device *dp)
747{
748 int retval = 0;
749 int timeout_loop = 0;
750 int done_count = 0;
751
752 analogix_dp_config_video_slave_mode(dp);
753
754 analogix_dp_set_video_color_format(dp);
755
756 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
757 dev_err(dp->dev, "PLL is not locked yet.\n");
758 return -EINVAL;
759 }
760
761 for (;;) {
762 timeout_loop++;
763 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
764 break;
765 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
766 dev_err(dp->dev, "Timeout of video streamclk ok\n");
767 return -ETIMEDOUT;
768 }
769
770 usleep_range(1, 2);
771 }
772
773 /* Set to use the register calculated M/N video */
774 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
775
776 /* For video bist, Video timing must be generated by register */
777 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
778
779 /* Disable video mute */
780 analogix_dp_enable_video_mute(dp, 0);
781
782 /* Configure video slave mode */
783 analogix_dp_enable_video_master(dp, 0);
784
785 timeout_loop = 0;
786
787 for (;;) {
788 timeout_loop++;
789 if (analogix_dp_is_video_stream_on(dp) == 0) {
790 done_count++;
791 if (done_count > 10)
792 break;
793 } else if (done_count) {
794 done_count = 0;
795 }
796 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
797 dev_err(dp->dev, "Timeout of video streamclk ok\n");
798 return -ETIMEDOUT;
799 }
800
801 usleep_range(1000, 1001);
802 }
803
804 if (retval != 0)
805 dev_err(dp->dev, "Video stream is not detected!\n");
806
807 return retval;
808}
809
810static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
811{
812 u8 data;
813
814 if (enable) {
815 analogix_dp_enable_scrambling(dp);
816
817 analogix_dp_read_byte_from_dpcd(dp,
818 DP_TRAINING_PATTERN_SET,
819 &data);
820 analogix_dp_write_byte_to_dpcd(dp,
821 DP_TRAINING_PATTERN_SET,
822 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
823 } else {
824 analogix_dp_disable_scrambling(dp);
825
826 analogix_dp_read_byte_from_dpcd(dp,
827 DP_TRAINING_PATTERN_SET,
828 &data);
829 analogix_dp_write_byte_to_dpcd(dp,
830 DP_TRAINING_PATTERN_SET,
831 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
832 }
833}
834
835static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
836{
837 struct analogix_dp_device *dp = arg;
838
839 enum dp_irq_type irq_type;
840
841 irq_type = analogix_dp_get_irq_type(dp);
842 switch (irq_type) {
843 case DP_IRQ_TYPE_HP_CABLE_IN:
844 dev_dbg(dp->dev, "Received irq - cable in\n");
845 schedule_work(&dp->hotplug_work);
846 analogix_dp_clear_hotplug_interrupts(dp);
847 break;
848 case DP_IRQ_TYPE_HP_CABLE_OUT:
849 dev_dbg(dp->dev, "Received irq - cable out\n");
850 analogix_dp_clear_hotplug_interrupts(dp);
851 break;
852 case DP_IRQ_TYPE_HP_CHANGE:
853 /*
854 * We get these change notifications once in a while, but there
855 * is nothing we can do with them. Just ignore it for now and
856 * only handle cable changes.
857 */
858 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
859 analogix_dp_clear_hotplug_interrupts(dp);
860 break;
861 default:
862 dev_err(dp->dev, "Received irq - unknown type!\n");
863 break;
864 }
865 return IRQ_HANDLED;
866}
867
868static void analogix_dp_hotplug(struct work_struct *work)
869{
870 struct analogix_dp_device *dp;
871
872 dp = container_of(work, struct analogix_dp_device, hotplug_work);
873
874 if (dp->drm_dev)
875 drm_helper_hpd_irq_event(dp->drm_dev);
876}
877
878static void analogix_dp_commit(struct analogix_dp_device *dp)
879{
880 int ret;
881
882 /* Keep the panel disabled while we configure video */
883 if (dp->plat_data->panel) {
884 if (drm_panel_disable(dp->plat_data->panel))
885 DRM_ERROR("failed to disable the panel\n");
886 }
887
888 ret = analogix_dp_detect_hpd(dp);
889 if (ret) {
890 /* Cable has been disconnected, we're done */
891 return;
892 }
893
894 ret = analogix_dp_handle_edid(dp);
895 if (ret) {
896 dev_err(dp->dev, "unable to handle edid\n");
897 return;
898 }
899
900 ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
901 dp->video_info->link_rate);
902 if (ret) {
903 dev_err(dp->dev, "unable to do link train\n");
904 return;
905 }
906
907 analogix_dp_enable_scramble(dp, 1);
908 analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
909 analogix_dp_enable_enhanced_mode(dp, 1);
910
911 analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
912 analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
913
914 analogix_dp_init_video(dp);
915 ret = analogix_dp_config_video(dp);
916 if (ret)
917 dev_err(dp->dev, "unable to config video\n");
918
919 /* Safe to enable the panel now */
920 if (dp->plat_data->panel) {
921 if (drm_panel_enable(dp->plat_data->panel))
922 DRM_ERROR("failed to enable the panel\n");
923 }
924
925 /* Enable video */
926 analogix_dp_start_video(dp);
927}
928
929int analogix_dp_get_modes(struct drm_connector *connector)
930{
931 struct analogix_dp_device *dp = to_dp(connector);
932 int num_modes = 0;
933
934 if (dp->plat_data->panel)
935 num_modes += drm_panel_get_modes(dp->plat_data->panel);
936
937 if (dp->plat_data->get_modes)
938 num_modes += dp->plat_data->get_modes(dp->plat_data);
939
940 return num_modes;
941}
942
943static struct drm_encoder *
944analogix_dp_best_encoder(struct drm_connector *connector)
945{
946 struct analogix_dp_device *dp = to_dp(connector);
947
948 return dp->encoder;
949}
950
951static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
952 .get_modes = analogix_dp_get_modes,
953 .best_encoder = analogix_dp_best_encoder,
954};
955
956enum drm_connector_status
957analogix_dp_detect(struct drm_connector *connector, bool force)
958{
959 return connector_status_connected;
960}
961
962static void analogix_dp_connector_destroy(struct drm_connector *connector)
963{
964 drm_connector_unregister(connector);
965 drm_connector_cleanup(connector);
966}
967
968static const struct drm_connector_funcs analogix_dp_connector_funcs = {
969 .dpms = drm_atomic_helper_connector_dpms,
970 .fill_modes = drm_helper_probe_single_connector_modes,
971 .detect = analogix_dp_detect,
972 .destroy = analogix_dp_connector_destroy,
973 .reset = drm_atomic_helper_connector_reset,
974 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
975 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
976};
977
978static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
979{
980 struct analogix_dp_device *dp = bridge->driver_private;
981 struct drm_encoder *encoder = dp->encoder;
982 struct drm_connector *connector = &dp->connector;
983 int ret;
984
985 if (!bridge->encoder) {
986 DRM_ERROR("Parent encoder object not found");
987 return -ENODEV;
988 }
989
990 connector->polled = DRM_CONNECTOR_POLL_HPD;
991
992 ret = drm_connector_init(dp->drm_dev, connector,
993 &analogix_dp_connector_funcs,
994 DRM_MODE_CONNECTOR_eDP);
995 if (ret) {
996 DRM_ERROR("Failed to initialize connector with drm\n");
997 return ret;
998 }
999
1000 drm_connector_helper_add(connector,
1001 &analogix_dp_connector_helper_funcs);
1002 drm_mode_connector_attach_encoder(connector, encoder);
1003
1004 /*
1005 * NOTE: the connector registration is implemented in analogix
1006 * platform driver, that to say connector would be exist after
1007 * plat_data->attch return, that's why we record the connector
1008 * point after plat attached.
1009 */
1010 if (dp->plat_data->attach) {
1011 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1012 if (ret) {
1013 DRM_ERROR("Failed at platform attch func\n");
1014 return ret;
1015 }
1016 }
1017
1018 if (dp->plat_data->panel) {
1019 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1020 if (ret) {
1021 DRM_ERROR("Failed to attach panel\n");
1022 return ret;
1023 }
1024 }
1025
1026 return 0;
1027}
1028
1029static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1030{
1031 struct analogix_dp_device *dp = bridge->driver_private;
1032
1033 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1034 return;
1035
1036 pm_runtime_get_sync(dp->dev);
1037
1038 if (dp->plat_data->panel) {
1039 if (drm_panel_prepare(dp->plat_data->panel)) {
1040 DRM_ERROR("failed to setup the panel\n");
1041 return;
1042 }
1043 }
1044
1045 if (dp->plat_data->power_on)
1046 dp->plat_data->power_on(dp->plat_data);
1047
1048 phy_power_on(dp->phy);
1049 analogix_dp_init_dp(dp);
1050 enable_irq(dp->irq);
1051 analogix_dp_commit(dp);
1052
1053 dp->dpms_mode = DRM_MODE_DPMS_ON;
1054}
1055
1056static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1057{
1058 struct analogix_dp_device *dp = bridge->driver_private;
1059
1060 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1061 return;
1062
1063 if (dp->plat_data->panel) {
1064 if (drm_panel_disable(dp->plat_data->panel)) {
1065 DRM_ERROR("failed to disable the panel\n");
1066 return;
1067 }
1068 }
1069
1070 disable_irq(dp->irq);
1071 flush_work(&dp->hotplug_work);
1072 phy_power_off(dp->phy);
1073
1074 if (dp->plat_data->power_off)
1075 dp->plat_data->power_off(dp->plat_data);
1076
1077 if (dp->plat_data->panel) {
1078 if (drm_panel_unprepare(dp->plat_data->panel))
1079 DRM_ERROR("failed to turnoff the panel\n");
1080 }
1081
1082 pm_runtime_put_sync(dp->dev);
1083
1084 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1085}
1086
1087static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1088{
1089 /* do nothing */
1090}
1091
1092static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1093 .enable = analogix_dp_bridge_enable,
1094 .disable = analogix_dp_bridge_disable,
1095 .pre_enable = analogix_dp_bridge_nop,
1096 .post_disable = analogix_dp_bridge_nop,
1097 .attach = analogix_dp_bridge_attach,
1098};
1099
1100static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1101 struct analogix_dp_device *dp)
1102{
1103 struct drm_bridge *bridge;
1104 int ret;
1105
1106 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1107 if (!bridge) {
1108 DRM_ERROR("failed to allocate for drm bridge\n");
1109 return -ENOMEM;
1110 }
1111
1112 dp->bridge = bridge;
1113
1114 dp->encoder->bridge = bridge;
1115 bridge->driver_private = dp;
1116 bridge->encoder = dp->encoder;
1117 bridge->funcs = &analogix_dp_bridge_funcs;
1118
1119 ret = drm_bridge_attach(drm_dev, bridge);
1120 if (ret) {
1121 DRM_ERROR("failed to attach drm bridge\n");
1122 return -EINVAL;
1123 }
1124
1125 return 0;
1126}
1127
1128static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
1129{
1130 struct device_node *dp_node = dev->of_node;
1131 struct video_info *dp_video_config;
1132
1133 dp_video_config = devm_kzalloc(dev,
1134 sizeof(*dp_video_config), GFP_KERNEL);
1135 if (!dp_video_config)
1136 return ERR_PTR(-ENOMEM);
1137
1138 dp_video_config->h_sync_polarity =
1139 of_property_read_bool(dp_node, "hsync-active-high");
1140
1141 dp_video_config->v_sync_polarity =
1142 of_property_read_bool(dp_node, "vsync-active-high");
1143
1144 dp_video_config->interlaced =
1145 of_property_read_bool(dp_node, "interlaced");
1146
1147 if (of_property_read_u32(dp_node, "samsung,color-space",
1148 &dp_video_config->color_space)) {
1149 dev_err(dev, "failed to get color-space\n");
1150 return ERR_PTR(-EINVAL);
1151 }
1152
1153 if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1154 &dp_video_config->dynamic_range)) {
1155 dev_err(dev, "failed to get dynamic-range\n");
1156 return ERR_PTR(-EINVAL);
1157 }
1158
1159 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1160 &dp_video_config->ycbcr_coeff)) {
1161 dev_err(dev, "failed to get ycbcr-coeff\n");
1162 return ERR_PTR(-EINVAL);
1163 }
1164
1165 if (of_property_read_u32(dp_node, "samsung,color-depth",
1166 &dp_video_config->color_depth)) {
1167 dev_err(dev, "failed to get color-depth\n");
1168 return ERR_PTR(-EINVAL);
1169 }
1170
1171 if (of_property_read_u32(dp_node, "samsung,link-rate",
1172 &dp_video_config->link_rate)) {
1173 dev_err(dev, "failed to get link-rate\n");
1174 return ERR_PTR(-EINVAL);
1175 }
1176
1177 if (of_property_read_u32(dp_node, "samsung,lane-count",
1178 &dp_video_config->lane_count)) {
1179 dev_err(dev, "failed to get lane-count\n");
1180 return ERR_PTR(-EINVAL);
1181 }
1182
1183 return dp_video_config;
1184}
1185
1186int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1187 struct analogix_dp_plat_data *plat_data)
1188{
1189 struct platform_device *pdev = to_platform_device(dev);
1190 struct analogix_dp_device *dp;
1191 struct resource *res;
1192 unsigned int irq_flags;
1193 int ret;
1194
1195 if (!plat_data) {
1196 dev_err(dev, "Invalided input plat_data\n");
1197 return -EINVAL;
1198 }
1199
1200 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1201 if (!dp)
1202 return -ENOMEM;
1203
1204 dev_set_drvdata(dev, dp);
1205
1206 dp->dev = &pdev->dev;
1207 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1208
1209 /*
1210 * platform dp driver need containor_of the plat_data to get
1211 * the driver private data, so we need to store the point of
1212 * plat_data, not the context of plat_data.
1213 */
1214 dp->plat_data = plat_data;
1215
1216 dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
1217 if (IS_ERR(dp->video_info))
1218 return PTR_ERR(dp->video_info);
1219
1220 dp->phy = devm_phy_get(dp->dev, "dp");
1221 if (IS_ERR(dp->phy)) {
1222 dev_err(dp->dev, "no DP phy configured\n");
1223 ret = PTR_ERR(dp->phy);
1224 if (ret) {
1225 /*
1226 * phy itself is not enabled, so we can move forward
1227 * assigning NULL to phy pointer.
1228 */
1229 if (ret == -ENOSYS || ret == -ENODEV)
1230 dp->phy = NULL;
1231 else
1232 return ret;
1233 }
1234 }
1235
1236 dp->clock = devm_clk_get(&pdev->dev, "dp");
1237 if (IS_ERR(dp->clock)) {
1238 dev_err(&pdev->dev, "failed to get clock\n");
1239 return PTR_ERR(dp->clock);
1240 }
1241
1242 clk_prepare_enable(dp->clock);
1243
1244 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1245
1246 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1247 if (IS_ERR(dp->reg_base))
1248 return PTR_ERR(dp->reg_base);
1249
1250 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1251 if (!gpio_is_valid(dp->hpd_gpio))
1252 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1253 "samsung,hpd-gpio", 0);
1254
1255 if (gpio_is_valid(dp->hpd_gpio)) {
1256 /*
1257 * Set up the hotplug GPIO from the device tree as an interrupt.
1258 * Simply specifying a different interrupt in the device tree
1259 * doesn't work since we handle hotplug rather differently when
1260 * using a GPIO. We also need the actual GPIO specifier so
1261 * that we can get the current state of the GPIO.
1262 */
1263 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1264 "hpd_gpio");
1265 if (ret) {
1266 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1267 return ret;
1268 }
1269 dp->irq = gpio_to_irq(dp->hpd_gpio);
1270 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1271 } else {
1272 dp->hpd_gpio = -ENODEV;
1273 dp->irq = platform_get_irq(pdev, 0);
1274 irq_flags = 0;
1275 }
1276
1277 if (dp->irq == -ENXIO) {
1278 dev_err(&pdev->dev, "failed to get irq\n");
1279 return -ENODEV;
1280 }
1281
1282 INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
1283
1284 pm_runtime_enable(dev);
1285
1286 ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
1287 irq_flags, "analogix-dp", dp);
1288 if (ret) {
1289 dev_err(&pdev->dev, "failed to request irq\n");
1290 goto err_disable_pm_runtime;
1291 }
1292 disable_irq(dp->irq);
1293
1294 dp->drm_dev = drm_dev;
1295 dp->encoder = dp->plat_data->encoder;
1296
1297 ret = analogix_dp_create_bridge(drm_dev, dp);
1298 if (ret) {
1299 DRM_ERROR("failed to create bridge (%d)\n", ret);
1300 drm_encoder_cleanup(dp->encoder);
1301 goto err_disable_pm_runtime;
1302 }
1303
1304 return 0;
1305
1306err_disable_pm_runtime:
1307 pm_runtime_disable(dev);
1308
1309 return ret;
1310}
1311EXPORT_SYMBOL_GPL(analogix_dp_bind);
1312
1313void analogix_dp_unbind(struct device *dev, struct device *master,
1314 void *data)
1315{
1316 struct analogix_dp_device *dp = dev_get_drvdata(dev);
1317
1318 analogix_dp_bridge_disable(dp->bridge);
1319 pm_runtime_disable(dev);
1320}
1321EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1322
1323#ifdef CONFIG_PM
1324int analogix_dp_suspend(struct device *dev)
1325{
1326 struct analogix_dp_device *dp = dev_get_drvdata(dev);
1327
1328 clk_disable_unprepare(dp->clock);
1329 return 0;
1330}
1331EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1332
1333int analogix_dp_resume(struct device *dev)
1334{
1335 struct analogix_dp_device *dp = dev_get_drvdata(dev);
1336 int ret;
1337
1338 ret = clk_prepare_enable(dp->clock);
1339 if (ret < 0) {
1340 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1341 return ret;
1342 }
1343
1344 return 0;
1345}
1346EXPORT_SYMBOL_GPL(analogix_dp_resume);
1347#endif
1348
1349MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1350MODULE_DESCRIPTION("Analogix DP Core Driver");
1351MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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