Commit | Line | Data |
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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2009 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/delay.h> | |
a4fc5ed6 KP |
26 | #include <linux/init.h> |
27 | #include <linux/errno.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/i2c.h> | |
760285e7 DH |
30 | #include <drm/drm_dp_helper.h> |
31 | #include <drm/drmP.h> | |
a4fc5ed6 | 32 | |
e15c8f4b DV |
33 | #include "drm_crtc_helper_internal.h" |
34 | ||
28164fda DV |
35 | /** |
36 | * DOC: dp helpers | |
37 | * | |
38 | * These functions contain some common logic and helpers at various abstraction | |
39 | * levels to deal with Display Port sink devices and related things like DP aux | |
40 | * channel transfers, EDID reading over DP aux channels, decoding certain DPCD | |
41 | * blocks, ... | |
42 | */ | |
43 | ||
1ffdff13 | 44 | /* Helpers for DP link training */ |
0aec2881 | 45 | static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) |
1ffdff13 DV |
46 | { |
47 | return link_status[r - DP_LANE0_1_STATUS]; | |
48 | } | |
49 | ||
0aec2881 | 50 | static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 DV |
51 | int lane) |
52 | { | |
53 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
54 | int s = (lane & 1) * 4; | |
55 | u8 l = dp_link_status(link_status, i); | |
56 | return (l >> s) & 0xf; | |
57 | } | |
58 | ||
0aec2881 | 59 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 DV |
60 | int lane_count) |
61 | { | |
62 | u8 lane_align; | |
63 | u8 lane_status; | |
64 | int lane; | |
65 | ||
66 | lane_align = dp_link_status(link_status, | |
67 | DP_LANE_ALIGN_STATUS_UPDATED); | |
68 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
69 | return false; | |
70 | for (lane = 0; lane < lane_count; lane++) { | |
71 | lane_status = dp_get_lane_status(link_status, lane); | |
72 | if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) | |
73 | return false; | |
74 | } | |
75 | return true; | |
76 | } | |
77 | EXPORT_SYMBOL(drm_dp_channel_eq_ok); | |
78 | ||
0aec2881 | 79 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 DV |
80 | int lane_count) |
81 | { | |
82 | int lane; | |
83 | u8 lane_status; | |
84 | ||
85 | for (lane = 0; lane < lane_count; lane++) { | |
86 | lane_status = dp_get_lane_status(link_status, lane); | |
87 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
88 | return false; | |
89 | } | |
90 | return true; | |
91 | } | |
92 | EXPORT_SYMBOL(drm_dp_clock_recovery_ok); | |
0f037bde | 93 | |
0aec2881 | 94 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde DV |
95 | int lane) |
96 | { | |
97 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
98 | int s = ((lane & 1) ? | |
99 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
100 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
101 | u8 l = dp_link_status(link_status, i); | |
102 | ||
103 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
104 | } | |
105 | EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); | |
106 | ||
0aec2881 | 107 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde DV |
108 | int lane) |
109 | { | |
110 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
111 | int s = ((lane & 1) ? | |
112 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
113 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
114 | u8 l = dp_link_status(link_status, i); | |
115 | ||
116 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
117 | } | |
118 | EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); | |
119 | ||
0aec2881 | 120 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
1a644cd4 DV |
121 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
122 | udelay(100); | |
123 | else | |
124 | mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); | |
125 | } | |
126 | EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); | |
127 | ||
0aec2881 | 128 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
1a644cd4 DV |
129 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
130 | udelay(400); | |
131 | else | |
132 | mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); | |
133 | } | |
134 | EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); | |
3b5c662e DV |
135 | |
136 | u8 drm_dp_link_rate_to_bw_code(int link_rate) | |
137 | { | |
138 | switch (link_rate) { | |
139 | case 162000: | |
140 | default: | |
141 | return DP_LINK_BW_1_62; | |
142 | case 270000: | |
143 | return DP_LINK_BW_2_7; | |
144 | case 540000: | |
145 | return DP_LINK_BW_5_4; | |
146 | } | |
147 | } | |
148 | EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); | |
149 | ||
150 | int drm_dp_bw_code_to_link_rate(u8 link_bw) | |
151 | { | |
152 | switch (link_bw) { | |
153 | case DP_LINK_BW_1_62: | |
154 | default: | |
155 | return 162000; | |
156 | case DP_LINK_BW_2_7: | |
157 | return 270000; | |
158 | case DP_LINK_BW_5_4: | |
159 | return 540000; | |
160 | } | |
161 | } | |
162 | EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); | |
c197db75 | 163 | |
79a2b161 VS |
164 | #define AUX_RETRY_INTERVAL 500 /* us */ |
165 | ||
c197db75 TR |
166 | /** |
167 | * DOC: dp helpers | |
168 | * | |
169 | * The DisplayPort AUX channel is an abstraction to allow generic, driver- | |
170 | * independent access to AUX functionality. Drivers can take advantage of | |
171 | * this by filling in the fields of the drm_dp_aux structure. | |
172 | * | |
173 | * Transactions are described using a hardware-independent drm_dp_aux_msg | |
174 | * structure, which is passed into a driver's .transfer() implementation. | |
175 | * Both native and I2C-over-AUX transactions are supported. | |
c197db75 TR |
176 | */ |
177 | ||
178 | static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, | |
179 | unsigned int offset, void *buffer, size_t size) | |
180 | { | |
181 | struct drm_dp_aux_msg msg; | |
82922da3 L |
182 | unsigned int retry, native_reply; |
183 | int err = 0, ret = 0; | |
c197db75 TR |
184 | |
185 | memset(&msg, 0, sizeof(msg)); | |
186 | msg.address = offset; | |
187 | msg.request = request; | |
188 | msg.buffer = buffer; | |
189 | msg.size = size; | |
190 | ||
7779c5e2 RC |
191 | mutex_lock(&aux->hw_mutex); |
192 | ||
c197db75 TR |
193 | /* |
194 | * The specification doesn't give any recommendation on how often to | |
19a93f04 DA |
195 | * retry native transactions. We used to retry 7 times like for |
196 | * aux i2c transactions but real world devices this wasn't | |
197 | * sufficient, bump to 32 which makes Dell 4k monitors happier. | |
c197db75 | 198 | */ |
19a93f04 | 199 | for (retry = 0; retry < 32; retry++) { |
82922da3 | 200 | if (ret != 0 && ret != -ETIMEDOUT) { |
e1083ff3 L |
201 | usleep_range(AUX_RETRY_INTERVAL, |
202 | AUX_RETRY_INTERVAL + 100); | |
203 | } | |
4f71d0cb | 204 | |
82922da3 | 205 | ret = aux->transfer(aux, &msg); |
c197db75 | 206 | |
a1f5524a | 207 | if (ret >= 0) { |
82922da3 L |
208 | native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; |
209 | if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { | |
210 | if (ret == size) | |
211 | goto unlock; | |
c197db75 | 212 | |
82922da3 L |
213 | ret = -EPROTO; |
214 | } else | |
215 | ret = -EIO; | |
c197db75 | 216 | } |
82922da3 L |
217 | |
218 | /* | |
219 | * We want the error we return to be the error we received on | |
220 | * the first transaction, since we may get a different error the | |
221 | * next time we retry | |
222 | */ | |
223 | if (!err) | |
224 | err = ret; | |
c197db75 TR |
225 | } |
226 | ||
29f21e04 | 227 | DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err); |
82922da3 | 228 | ret = err; |
7779c5e2 RC |
229 | |
230 | unlock: | |
231 | mutex_unlock(&aux->hw_mutex); | |
82922da3 | 232 | return ret; |
c197db75 TR |
233 | } |
234 | ||
235 | /** | |
236 | * drm_dp_dpcd_read() - read a series of bytes from the DPCD | |
237 | * @aux: DisplayPort AUX channel | |
238 | * @offset: address of the (first) register to read | |
239 | * @buffer: buffer to store the register values | |
240 | * @size: number of bytes in @buffer | |
241 | * | |
242 | * Returns the number of bytes transferred on success, or a negative error | |
243 | * code on failure. -EIO is returned if the request was NAKed by the sink or | |
244 | * if the retry count was exceeded. If not all bytes were transferred, this | |
245 | * function returns -EPROTO. Errors from the underlying AUX channel transfer | |
246 | * function, with the exception of -EBUSY (which causes the transaction to | |
247 | * be retried), are propagated to the caller. | |
248 | */ | |
249 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, | |
250 | void *buffer, size_t size) | |
251 | { | |
f808f633 L |
252 | int ret; |
253 | ||
254 | /* | |
255 | * HP ZR24w corrupts the first DPCD access after entering power save | |
256 | * mode. Eg. on a read, the entire buffer will be filled with the same | |
257 | * byte. Do a throw away read to avoid corrupting anything we care | |
258 | * about. Afterwards things will work correctly until the monitor | |
259 | * gets woken up and subsequently re-enters power save mode. | |
260 | * | |
261 | * The user pressing any button on the monitor is enough to wake it | |
262 | * up, so there is no particularly good place to do the workaround. | |
263 | * We just have to do it before any DPCD access and hope that the | |
264 | * monitor doesn't power down exactly after the throw away read. | |
265 | */ | |
266 | ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer, | |
267 | 1); | |
268 | if (ret != 1) | |
269 | return ret; | |
270 | ||
c197db75 TR |
271 | return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer, |
272 | size); | |
273 | } | |
274 | EXPORT_SYMBOL(drm_dp_dpcd_read); | |
275 | ||
276 | /** | |
277 | * drm_dp_dpcd_write() - write a series of bytes to the DPCD | |
278 | * @aux: DisplayPort AUX channel | |
279 | * @offset: address of the (first) register to write | |
280 | * @buffer: buffer containing the values to write | |
281 | * @size: number of bytes in @buffer | |
282 | * | |
283 | * Returns the number of bytes transferred on success, or a negative error | |
284 | * code on failure. -EIO is returned if the request was NAKed by the sink or | |
285 | * if the retry count was exceeded. If not all bytes were transferred, this | |
286 | * function returns -EPROTO. Errors from the underlying AUX channel transfer | |
287 | * function, with the exception of -EBUSY (which causes the transaction to | |
288 | * be retried), are propagated to the caller. | |
289 | */ | |
290 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, | |
291 | void *buffer, size_t size) | |
292 | { | |
293 | return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, | |
294 | size); | |
295 | } | |
296 | EXPORT_SYMBOL(drm_dp_dpcd_write); | |
8d4adc6a TR |
297 | |
298 | /** | |
299 | * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) | |
300 | * @aux: DisplayPort AUX channel | |
301 | * @status: buffer to store the link status in (must be at least 6 bytes) | |
302 | * | |
303 | * Returns the number of bytes transferred on success or a negative error | |
304 | * code on failure. | |
305 | */ | |
306 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, | |
307 | u8 status[DP_LINK_STATUS_SIZE]) | |
308 | { | |
309 | return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, | |
310 | DP_LINK_STATUS_SIZE); | |
311 | } | |
312 | EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); | |
516c0f7c TR |
313 | |
314 | /** | |
315 | * drm_dp_link_probe() - probe a DisplayPort link for capabilities | |
316 | * @aux: DisplayPort AUX channel | |
317 | * @link: pointer to structure in which to return link capabilities | |
318 | * | |
319 | * The structure filled in by this function can usually be passed directly | |
320 | * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and | |
321 | * configure the link based on the link's capabilities. | |
322 | * | |
323 | * Returns 0 on success or a negative error code on failure. | |
324 | */ | |
325 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
326 | { | |
327 | u8 values[3]; | |
328 | int err; | |
329 | ||
330 | memset(link, 0, sizeof(*link)); | |
331 | ||
332 | err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); | |
333 | if (err < 0) | |
334 | return err; | |
335 | ||
336 | link->revision = values[0]; | |
337 | link->rate = drm_dp_bw_code_to_link_rate(values[1]); | |
338 | link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; | |
339 | ||
340 | if (values[2] & DP_ENHANCED_FRAME_CAP) | |
341 | link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; | |
342 | ||
343 | return 0; | |
344 | } | |
345 | EXPORT_SYMBOL(drm_dp_link_probe); | |
346 | ||
347 | /** | |
348 | * drm_dp_link_power_up() - power up a DisplayPort link | |
349 | * @aux: DisplayPort AUX channel | |
350 | * @link: pointer to a structure containing the link configuration | |
351 | * | |
352 | * Returns 0 on success or a negative error code on failure. | |
353 | */ | |
354 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
355 | { | |
356 | u8 value; | |
357 | int err; | |
358 | ||
359 | /* DP_SET_POWER register is only available on DPCD v1.1 and later */ | |
360 | if (link->revision < 0x11) | |
361 | return 0; | |
362 | ||
363 | err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); | |
364 | if (err < 0) | |
365 | return err; | |
366 | ||
367 | value &= ~DP_SET_POWER_MASK; | |
368 | value |= DP_SET_POWER_D0; | |
369 | ||
370 | err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); | |
371 | if (err < 0) | |
372 | return err; | |
373 | ||
374 | /* | |
375 | * According to the DP 1.1 specification, a "Sink Device must exit the | |
376 | * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink | |
377 | * Control Field" (register 0x600). | |
378 | */ | |
379 | usleep_range(1000, 2000); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | EXPORT_SYMBOL(drm_dp_link_power_up); | |
384 | ||
d816f077 RC |
385 | /** |
386 | * drm_dp_link_power_down() - power down a DisplayPort link | |
387 | * @aux: DisplayPort AUX channel | |
388 | * @link: pointer to a structure containing the link configuration | |
389 | * | |
390 | * Returns 0 on success or a negative error code on failure. | |
391 | */ | |
392 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
393 | { | |
394 | u8 value; | |
395 | int err; | |
396 | ||
397 | /* DP_SET_POWER register is only available on DPCD v1.1 and later */ | |
398 | if (link->revision < 0x11) | |
399 | return 0; | |
400 | ||
401 | err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); | |
402 | if (err < 0) | |
403 | return err; | |
404 | ||
405 | value &= ~DP_SET_POWER_MASK; | |
406 | value |= DP_SET_POWER_D3; | |
407 | ||
408 | err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); | |
409 | if (err < 0) | |
410 | return err; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | EXPORT_SYMBOL(drm_dp_link_power_down); | |
415 | ||
516c0f7c TR |
416 | /** |
417 | * drm_dp_link_configure() - configure a DisplayPort link | |
418 | * @aux: DisplayPort AUX channel | |
419 | * @link: pointer to a structure containing the link configuration | |
420 | * | |
421 | * Returns 0 on success or a negative error code on failure. | |
422 | */ | |
423 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
424 | { | |
425 | u8 values[2]; | |
426 | int err; | |
427 | ||
428 | values[0] = drm_dp_link_rate_to_bw_code(link->rate); | |
429 | values[1] = link->num_lanes; | |
430 | ||
431 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) | |
432 | values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
433 | ||
434 | err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); | |
435 | if (err < 0) | |
436 | return err; | |
437 | ||
438 | return 0; | |
439 | } | |
440 | EXPORT_SYMBOL(drm_dp_link_configure); | |
88759686 TR |
441 | |
442 | /* | |
443 | * I2C-over-AUX implementation | |
444 | */ | |
445 | ||
446 | static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) | |
447 | { | |
448 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
449 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
450 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | | |
451 | I2C_FUNC_10BIT_ADDR; | |
452 | } | |
453 | ||
68ec2a2a VS |
454 | static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) |
455 | { | |
456 | /* | |
457 | * In case of i2c defer or short i2c ack reply to a write, | |
458 | * we need to switch to WRITE_STATUS_UPDATE to drain the | |
459 | * rest of the message | |
460 | */ | |
461 | if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { | |
462 | msg->request &= DP_AUX_I2C_MOT; | |
463 | msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; | |
464 | } | |
465 | } | |
466 | ||
4efa83c8 VS |
467 | #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ |
468 | #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ | |
469 | #define AUX_STOP_LEN 4 | |
470 | #define AUX_CMD_LEN 4 | |
471 | #define AUX_ADDRESS_LEN 20 | |
472 | #define AUX_REPLY_PAD_LEN 4 | |
473 | #define AUX_LENGTH_LEN 8 | |
474 | ||
475 | /* | |
476 | * Calculate the duration of the AUX request/reply in usec. Gives the | |
477 | * "best" case estimate, ie. successful while as short as possible. | |
478 | */ | |
479 | static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) | |
480 | { | |
481 | int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + | |
482 | AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; | |
483 | ||
484 | if ((msg->request & DP_AUX_I2C_READ) == 0) | |
485 | len += msg->size * 8; | |
486 | ||
487 | return len; | |
488 | } | |
489 | ||
490 | static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) | |
491 | { | |
492 | int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + | |
493 | AUX_CMD_LEN + AUX_REPLY_PAD_LEN; | |
494 | ||
495 | /* | |
496 | * For read we expect what was asked. For writes there will | |
497 | * be 0 or 1 data bytes. Assume 0 for the "best" case. | |
498 | */ | |
499 | if (msg->request & DP_AUX_I2C_READ) | |
500 | len += msg->size * 8; | |
501 | ||
502 | return len; | |
503 | } | |
504 | ||
505 | #define I2C_START_LEN 1 | |
506 | #define I2C_STOP_LEN 1 | |
507 | #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ | |
508 | #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ | |
509 | ||
510 | /* | |
511 | * Calculate the length of the i2c transfer in usec, assuming | |
512 | * the i2c bus speed is as specified. Gives the the "worst" | |
513 | * case estimate, ie. successful while as long as possible. | |
514 | * Doesn't account the the "MOT" bit, and instead assumes each | |
515 | * message includes a START, ADDRESS and STOP. Neither does it | |
516 | * account for additional random variables such as clock stretching. | |
517 | */ | |
518 | static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, | |
519 | int i2c_speed_khz) | |
520 | { | |
521 | /* AUX bitrate is 1MHz, i2c bitrate as specified */ | |
522 | return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + | |
523 | msg->size * I2C_DATA_LEN + | |
524 | I2C_STOP_LEN) * 1000, i2c_speed_khz); | |
525 | } | |
526 | ||
527 | /* | |
528 | * Deterine how many retries should be attempted to successfully transfer | |
529 | * the specified message, based on the estimated durations of the | |
530 | * i2c and AUX transfers. | |
531 | */ | |
532 | static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, | |
533 | int i2c_speed_khz) | |
534 | { | |
535 | int aux_time_us = drm_dp_aux_req_duration(msg) + | |
536 | drm_dp_aux_reply_duration(msg); | |
537 | int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); | |
538 | ||
539 | return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); | |
540 | } | |
541 | ||
f36203be VS |
542 | /* |
543 | * FIXME currently assumes 10 kHz as some real world devices seem | |
544 | * to require it. We should query/set the speed via DPCD if supported. | |
545 | */ | |
546 | static int dp_aux_i2c_speed_khz __read_mostly = 10; | |
547 | module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); | |
548 | MODULE_PARM_DESC(dp_aux_i2c_speed_khz, | |
549 | "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); | |
550 | ||
88759686 TR |
551 | /* |
552 | * Transfer a single I2C-over-AUX message and handle various error conditions, | |
732d50b4 AD |
553 | * retrying the transaction as appropriate. It is assumed that the |
554 | * aux->transfer function does not modify anything in the msg other than the | |
555 | * reply field. | |
1d002fa7 SF |
556 | * |
557 | * Returns bytes transferred on success, or a negative error code on failure. | |
88759686 TR |
558 | */ |
559 | static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
560 | { | |
396aa445 | 561 | unsigned int retry, defer_i2c; |
1d002fa7 | 562 | int ret; |
88759686 TR |
563 | /* |
564 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device | |
565 | * is required to retry at least seven times upon receiving AUX_DEFER | |
566 | * before giving up the AUX transaction. | |
4efa83c8 VS |
567 | * |
568 | * We also try to account for the i2c bus speed. | |
88759686 | 569 | */ |
f36203be | 570 | int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); |
4efa83c8 VS |
571 | |
572 | for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { | |
1d002fa7 | 573 | ret = aux->transfer(aux, msg); |
1d002fa7 SF |
574 | if (ret < 0) { |
575 | if (ret == -EBUSY) | |
88759686 TR |
576 | continue; |
577 | ||
9622c38f L |
578 | /* |
579 | * While timeouts can be errors, they're usually normal | |
580 | * behavior (for instance, when a driver tries to | |
581 | * communicate with a non-existant DisplayPort device). | |
582 | * Avoid spamming the kernel log with timeout errors. | |
583 | */ | |
584 | if (ret == -ETIMEDOUT) | |
585 | DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n"); | |
586 | else | |
587 | DRM_DEBUG_KMS("transaction failed: %d\n", ret); | |
588 | ||
1d002fa7 | 589 | return ret; |
88759686 TR |
590 | } |
591 | ||
88759686 TR |
592 | |
593 | switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { | |
594 | case DP_AUX_NATIVE_REPLY_ACK: | |
595 | /* | |
596 | * For I2C-over-AUX transactions this isn't enough, we | |
597 | * need to check for the I2C ACK reply. | |
598 | */ | |
599 | break; | |
600 | ||
601 | case DP_AUX_NATIVE_REPLY_NACK: | |
fb8c5e49 | 602 | DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size); |
88759686 TR |
603 | return -EREMOTEIO; |
604 | ||
605 | case DP_AUX_NATIVE_REPLY_DEFER: | |
747552b9 | 606 | DRM_DEBUG_KMS("native defer\n"); |
88759686 TR |
607 | /* |
608 | * We could check for I2C bit rate capabilities and if | |
609 | * available adjust this interval. We could also be | |
610 | * more careful with DP-to-legacy adapters where a | |
611 | * long legacy cable may force very low I2C bit rates. | |
612 | * | |
613 | * For now just defer for long enough to hopefully be | |
614 | * safe for all use-cases. | |
615 | */ | |
79a2b161 | 616 | usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); |
88759686 TR |
617 | continue; |
618 | ||
619 | default: | |
620 | DRM_ERROR("invalid native reply %#04x\n", msg->reply); | |
621 | return -EREMOTEIO; | |
622 | } | |
623 | ||
624 | switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { | |
625 | case DP_AUX_I2C_REPLY_ACK: | |
626 | /* | |
627 | * Both native ACK and I2C ACK replies received. We | |
628 | * can assume the transfer was successful. | |
629 | */ | |
68ec2a2a VS |
630 | if (ret != msg->size) |
631 | drm_dp_i2c_msg_write_status_update(msg); | |
1d002fa7 | 632 | return ret; |
88759686 TR |
633 | |
634 | case DP_AUX_I2C_REPLY_NACK: | |
fb8c5e49 | 635 | DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu\n", ret, msg->size); |
e9cf6194 | 636 | aux->i2c_nack_count++; |
88759686 TR |
637 | return -EREMOTEIO; |
638 | ||
639 | case DP_AUX_I2C_REPLY_DEFER: | |
640 | DRM_DEBUG_KMS("I2C defer\n"); | |
396aa445 TP |
641 | /* DP Compliance Test 4.2.2.5 Requirement: |
642 | * Must have at least 7 retries for I2C defers on the | |
643 | * transaction to pass this test | |
644 | */ | |
e9cf6194 | 645 | aux->i2c_defer_count++; |
396aa445 TP |
646 | if (defer_i2c < 7) |
647 | defer_i2c++; | |
79a2b161 | 648 | usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); |
68ec2a2a | 649 | drm_dp_i2c_msg_write_status_update(msg); |
646db260 | 650 | |
88759686 TR |
651 | continue; |
652 | ||
653 | default: | |
654 | DRM_ERROR("invalid I2C reply %#04x\n", msg->reply); | |
655 | return -EREMOTEIO; | |
656 | } | |
657 | } | |
658 | ||
743b1e32 | 659 | DRM_DEBUG_KMS("too many retries, giving up\n"); |
88759686 TR |
660 | return -EREMOTEIO; |
661 | } | |
662 | ||
68ec2a2a VS |
663 | static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, |
664 | const struct i2c_msg *i2c_msg) | |
665 | { | |
666 | msg->request = (i2c_msg->flags & I2C_M_RD) ? | |
667 | DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; | |
668 | msg->request |= DP_AUX_I2C_MOT; | |
669 | } | |
670 | ||
1d002fa7 SF |
671 | /* |
672 | * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. | |
673 | * | |
674 | * Returns an error code on failure, or a recommended transfer size on success. | |
675 | */ | |
676 | static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) | |
677 | { | |
678 | int err, ret = orig_msg->size; | |
679 | struct drm_dp_aux_msg msg = *orig_msg; | |
680 | ||
681 | while (msg.size > 0) { | |
682 | err = drm_dp_i2c_do_msg(aux, &msg); | |
683 | if (err <= 0) | |
684 | return err == 0 ? -EPROTO : err; | |
685 | ||
686 | if (err < msg.size && err < ret) { | |
687 | DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n", | |
688 | msg.size, err); | |
689 | ret = err; | |
690 | } | |
691 | ||
692 | msg.size -= err; | |
693 | msg.buffer += err; | |
694 | } | |
695 | ||
696 | return ret; | |
697 | } | |
698 | ||
699 | /* | |
700 | * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX | |
701 | * packets to be as large as possible. If not, the I2C transactions never | |
702 | * succeed. Hence the default is maximum. | |
703 | */ | |
704 | static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; | |
705 | module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); | |
706 | MODULE_PARM_DESC(dp_aux_i2c_transfer_size, | |
707 | "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); | |
708 | ||
88759686 TR |
709 | static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, |
710 | int num) | |
711 | { | |
712 | struct drm_dp_aux *aux = adapter->algo_data; | |
713 | unsigned int i, j; | |
1d002fa7 | 714 | unsigned transfer_size; |
ccdb516e AD |
715 | struct drm_dp_aux_msg msg; |
716 | int err = 0; | |
88759686 | 717 | |
1d002fa7 SF |
718 | dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); |
719 | ||
ccdb516e | 720 | memset(&msg, 0, sizeof(msg)); |
88759686 | 721 | |
ccdb516e AD |
722 | for (i = 0; i < num; i++) { |
723 | msg.address = msgs[i].addr; | |
68ec2a2a | 724 | drm_dp_i2c_msg_set_request(&msg, &msgs[i]); |
ccdb516e AD |
725 | /* Send a bare address packet to start the transaction. |
726 | * Zero sized messages specify an address only (bare | |
727 | * address) transaction. | |
728 | */ | |
729 | msg.buffer = NULL; | |
730 | msg.size = 0; | |
731 | err = drm_dp_i2c_do_msg(aux, &msg); | |
68ec2a2a VS |
732 | |
733 | /* | |
734 | * Reset msg.request in case in case it got | |
735 | * changed into a WRITE_STATUS_UPDATE. | |
736 | */ | |
737 | drm_dp_i2c_msg_set_request(&msg, &msgs[i]); | |
738 | ||
ccdb516e AD |
739 | if (err < 0) |
740 | break; | |
1d002fa7 SF |
741 | /* We want each transaction to be as large as possible, but |
742 | * we'll go to smaller sizes if the hardware gives us a | |
743 | * short reply. | |
88759686 | 744 | */ |
1d002fa7 SF |
745 | transfer_size = dp_aux_i2c_transfer_size; |
746 | for (j = 0; j < msgs[i].len; j += msg.size) { | |
88759686 | 747 | msg.buffer = msgs[i].buf + j; |
1d002fa7 | 748 | msg.size = min(transfer_size, msgs[i].len - j); |
88759686 | 749 | |
1d002fa7 | 750 | err = drm_dp_i2c_drain_msg(aux, &msg); |
68ec2a2a VS |
751 | |
752 | /* | |
753 | * Reset msg.request in case in case it got | |
754 | * changed into a WRITE_STATUS_UPDATE. | |
755 | */ | |
756 | drm_dp_i2c_msg_set_request(&msg, &msgs[i]); | |
757 | ||
88759686 | 758 | if (err < 0) |
ccdb516e | 759 | break; |
1d002fa7 | 760 | transfer_size = err; |
88759686 | 761 | } |
ccdb516e AD |
762 | if (err < 0) |
763 | break; | |
88759686 | 764 | } |
ccdb516e AD |
765 | if (err >= 0) |
766 | err = num; | |
767 | /* Send a bare address packet to close out the transaction. | |
768 | * Zero sized messages specify an address only (bare | |
769 | * address) transaction. | |
770 | */ | |
771 | msg.request &= ~DP_AUX_I2C_MOT; | |
772 | msg.buffer = NULL; | |
773 | msg.size = 0; | |
774 | (void)drm_dp_i2c_do_msg(aux, &msg); | |
88759686 | 775 | |
ccdb516e | 776 | return err; |
88759686 TR |
777 | } |
778 | ||
779 | static const struct i2c_algorithm drm_dp_i2c_algo = { | |
780 | .functionality = drm_dp_i2c_functionality, | |
781 | .master_xfer = drm_dp_i2c_xfer, | |
782 | }; | |
783 | ||
0c2f6f1a CW |
784 | static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) |
785 | { | |
786 | return container_of(i2c, struct drm_dp_aux, ddc); | |
787 | } | |
788 | ||
789 | static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) | |
790 | { | |
791 | mutex_lock(&i2c_to_aux(i2c)->hw_mutex); | |
792 | } | |
793 | ||
794 | static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) | |
795 | { | |
796 | return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); | |
797 | } | |
798 | ||
799 | static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) | |
800 | { | |
801 | mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); | |
802 | } | |
803 | ||
d1ed7985 PR |
804 | static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { |
805 | .lock_bus = lock_bus, | |
806 | .trylock_bus = trylock_bus, | |
807 | .unlock_bus = unlock_bus, | |
808 | }; | |
809 | ||
88759686 | 810 | /** |
acd8f414 | 811 | * drm_dp_aux_init() - minimally initialise an aux channel |
88759686 TR |
812 | * @aux: DisplayPort AUX channel |
813 | * | |
acd8f414 CW |
814 | * If you need to use the drm_dp_aux's i2c adapter prior to registering it |
815 | * with the outside world, call drm_dp_aux_init() first. You must still | |
816 | * call drm_dp_aux_register() once the connector has been registered to | |
817 | * allow userspace access to the auxiliary DP channel. | |
88759686 | 818 | */ |
acd8f414 | 819 | void drm_dp_aux_init(struct drm_dp_aux *aux) |
88759686 | 820 | { |
4f71d0cb DA |
821 | mutex_init(&aux->hw_mutex); |
822 | ||
88759686 TR |
823 | aux->ddc.algo = &drm_dp_i2c_algo; |
824 | aux->ddc.algo_data = aux; | |
825 | aux->ddc.retries = 3; | |
826 | ||
d1ed7985 | 827 | aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; |
acd8f414 CW |
828 | } |
829 | EXPORT_SYMBOL(drm_dp_aux_init); | |
830 | ||
831 | /** | |
832 | * drm_dp_aux_register() - initialise and register aux channel | |
833 | * @aux: DisplayPort AUX channel | |
834 | * | |
835 | * Automatically calls drm_dp_aux_init() if this hasn't been done yet. | |
836 | * | |
837 | * Returns 0 on success or a negative error code on failure. | |
838 | */ | |
839 | int drm_dp_aux_register(struct drm_dp_aux *aux) | |
840 | { | |
841 | int ret; | |
842 | ||
843 | if (!aux->ddc.algo) | |
844 | drm_dp_aux_init(aux); | |
0c2f6f1a | 845 | |
88759686 TR |
846 | aux->ddc.class = I2C_CLASS_DDC; |
847 | aux->ddc.owner = THIS_MODULE; | |
848 | aux->ddc.dev.parent = aux->dev; | |
849 | aux->ddc.dev.of_node = aux->dev->of_node; | |
850 | ||
9dc40560 JN |
851 | strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), |
852 | sizeof(aux->ddc.name)); | |
88759686 | 853 | |
e94cb37b RA |
854 | ret = drm_dp_aux_register_devnode(aux); |
855 | if (ret) | |
856 | return ret; | |
857 | ||
858 | ret = i2c_add_adapter(&aux->ddc); | |
859 | if (ret) { | |
860 | drm_dp_aux_unregister_devnode(aux); | |
861 | return ret; | |
862 | } | |
863 | ||
864 | return 0; | |
88759686 | 865 | } |
4f71d0cb | 866 | EXPORT_SYMBOL(drm_dp_aux_register); |
88759686 TR |
867 | |
868 | /** | |
4f71d0cb | 869 | * drm_dp_aux_unregister() - unregister an AUX adapter |
88759686 TR |
870 | * @aux: DisplayPort AUX channel |
871 | */ | |
4f71d0cb | 872 | void drm_dp_aux_unregister(struct drm_dp_aux *aux) |
88759686 | 873 | { |
e94cb37b | 874 | drm_dp_aux_unregister_devnode(aux); |
88759686 TR |
875 | i2c_del_adapter(&aux->ddc); |
876 | } | |
4f71d0cb | 877 | EXPORT_SYMBOL(drm_dp_aux_unregister); |
6608804b VS |
878 | |
879 | #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) | |
880 | ||
881 | /** | |
882 | * drm_dp_psr_setup_time() - PSR setup in time usec | |
883 | * @psr_cap: PSR capabilities from DPCD | |
884 | * | |
885 | * Returns: | |
886 | * PSR setup time for the panel in microseconds, negative | |
887 | * error code on failure. | |
888 | */ | |
889 | int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) | |
890 | { | |
891 | static const u16 psr_setup_time_us[] = { | |
892 | PSR_SETUP_TIME(330), | |
893 | PSR_SETUP_TIME(275), | |
894 | PSR_SETUP_TIME(165), | |
895 | PSR_SETUP_TIME(110), | |
896 | PSR_SETUP_TIME(55), | |
897 | PSR_SETUP_TIME(0), | |
898 | }; | |
899 | int i; | |
900 | ||
901 | i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; | |
902 | if (i >= ARRAY_SIZE(psr_setup_time_us)) | |
903 | return -EINVAL; | |
904 | ||
905 | return psr_setup_time_us[i]; | |
906 | } | |
907 | EXPORT_SYMBOL(drm_dp_psr_setup_time); | |
908 | ||
909 | #undef PSR_SETUP_TIME |