projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: remove dev_priv->pc8.enabled
[deliverable/linux.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
760285e7
DH		 35#include <drm/drmP.h>
36#include <drm/drm_edid.h>
f453ba04 37
13931579
AJ		 38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 41
d1ff6409
AJ		 42#define EDID_EST_TIMINGS 16
43#define EDID_STD_TIMINGS 8
44#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 45
46/*
47 * EDID blocks out in the wild have a variety of bugs, try to collect
48 * them here (note that userspace may work around broken monitors first,
49 * but fixes should make their way here so that the kernel "just works"
50 * on as many displays as possible).
51 */
52
53/* First detailed mode wrong, use largest 60Hz mode */
54#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
55/* Reported 135MHz pixel clock is too high, needs adjustment */
56#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
57/* Prefer the largest mode at 75 Hz */
58#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
59/* Detail timing is in cm not mm */
60#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
61/* Detailed timing descriptors have bogus size values, so just take the
62 * maximum size and use that.
63 */
64#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
65/* Monitor forgot to set the first detailed is preferred bit. */
66#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
67/* use +hsync +vsync for detailed mode */
68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 69/* Force reduced-blanking timings for detailed modes */
70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 71/* Force 8bpc */
72#define EDID_QUIRK_FORCE_8BPC (1 << 8)
3c537889 73
13931579
AJ		 74struct detailed_mode_closure {
75 struct drm_connector *connector;
76 struct edid *edid;
77 bool preferred;
78 u32 quirks;
79 int modes;
80};
f453ba04 81
5c61259e
ZY		 82#define LEVEL_DMT 0
83#define LEVEL_GTF 1
7a374350
AJ		 84#define LEVEL_GTF2 2
85#define LEVEL_CVT 3
5c61259e 86
f453ba04 87static struct edid_quirk {
c51a3fd6 88 char vendor[4];
f453ba04
DA		 89 int product_id;
90 u32 quirks;
91} edid_quirk_list[] = {
92 /* Acer AL1706 */
93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
94 /* Acer F51 */
95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
96 /* Unknown Acer */
97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
98
99 /* Belinea 10 15 55 */
100 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
101 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
102
103 /* Envision Peripherals, Inc. EN-7100e */
104 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 105 /* Envision EN2028 */
106 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 107
108 /* Funai Electronics PM36B */
109 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
110 EDID_QUIRK_DETAILED_IN_CM },
111
112 /* LG Philips LCD LP154W01-A5 */
113 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
114 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
115
116 /* Philips 107p5 CRT */
117 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
118
119 /* Proview AY765C */
120 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
121
122 /* Samsung SyncMaster 205BW. Note: irony */
123 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
124 /* Samsung SyncMaster 22[5-6]BW */
125 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
126 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc
AJ		 127
128 /* ViewSonic VA2026w */
129 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 130
131 /* Medion MD 30217 PG */
132 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 133
134 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
135 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
f453ba04
DA		 136};
137
a6b21831
TR		 138/*
139 * Autogenerated from the DMT spec.
140 * This table is copied from xfree86/modes/xf86EdidModes.c.
141 */
142static const struct drm_display_mode drm_dmt_modes[] = {
143 /* 640x350@85Hz */
144 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
145 736, 832, 0, 350, 382, 385, 445, 0,
146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
147 /* 640x400@85Hz */
148 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
149 736, 832, 0, 400, 401, 404, 445, 0,
150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
151 /* 720x400@85Hz */
152 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
153 828, 936, 0, 400, 401, 404, 446, 0,
154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
155 /* 640x480@60Hz */
156 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
157 752, 800, 0, 480, 489, 492, 525, 0,
158 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
159 /* 640x480@72Hz */
160 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
161 704, 832, 0, 480, 489, 492, 520, 0,
162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
163 /* 640x480@75Hz */
164 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
165 720, 840, 0, 480, 481, 484, 500, 0,
166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
167 /* 640x480@85Hz */
168 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
169 752, 832, 0, 480, 481, 484, 509, 0,
170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
171 /* 800x600@56Hz */
172 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
173 896, 1024, 0, 600, 601, 603, 625, 0,
174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
175 /* 800x600@60Hz */
176 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
177 968, 1056, 0, 600, 601, 605, 628, 0,
178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
179 /* 800x600@72Hz */
180 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
181 976, 1040, 0, 600, 637, 643, 666, 0,
182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
183 /* 800x600@75Hz */
184 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
185 896, 1056, 0, 600, 601, 604, 625, 0,
186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
187 /* 800x600@85Hz */
188 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
189 896, 1048, 0, 600, 601, 604, 631, 0,
190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
191 /* 800x600@120Hz RB */
192 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
193 880, 960, 0, 600, 603, 607, 636, 0,
194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
195 /* 848x480@60Hz */
196 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
197 976, 1088, 0, 480, 486, 494, 517, 0,
198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
199 /* 1024x768@43Hz, interlace */
200 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
201 1208, 1264, 0, 768, 768, 772, 817, 0,
202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
203 DRM_MODE_FLAG_INTERLACE) },
204 /* 1024x768@60Hz */
205 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
206 1184, 1344, 0, 768, 771, 777, 806, 0,
207 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
208 /* 1024x768@70Hz */
209 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
210 1184, 1328, 0, 768, 771, 777, 806, 0,
211 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
212 /* 1024x768@75Hz */
213 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
214 1136, 1312, 0, 768, 769, 772, 800, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
216 /* 1024x768@85Hz */
217 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
218 1168, 1376, 0, 768, 769, 772, 808, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
220 /* 1024x768@120Hz RB */
221 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
222 1104, 1184, 0, 768, 771, 775, 813, 0,
223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
224 /* 1152x864@75Hz */
225 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
226 1344, 1600, 0, 864, 865, 868, 900, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
228 /* 1280x768@60Hz RB */
229 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
230 1360, 1440, 0, 768, 771, 778, 790, 0,
231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
232 /* 1280x768@60Hz */
233 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
234 1472, 1664, 0, 768, 771, 778, 798, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 1280x768@75Hz */
237 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
238 1488, 1696, 0, 768, 771, 778, 805, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 1280x768@85Hz */
241 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
242 1496, 1712, 0, 768, 771, 778, 809, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
244 /* 1280x768@120Hz RB */
245 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
246 1360, 1440, 0, 768, 771, 778, 813, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 1280x800@60Hz RB */
249 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
250 1360, 1440, 0, 800, 803, 809, 823, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 1280x800@60Hz */
253 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
254 1480, 1680, 0, 800, 803, 809, 831, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 1280x800@75Hz */
257 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
258 1488, 1696, 0, 800, 803, 809, 838, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 1280x800@85Hz */
261 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
262 1496, 1712, 0, 800, 803, 809, 843, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 1280x800@120Hz RB */
265 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
266 1360, 1440, 0, 800, 803, 809, 847, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 1280x960@60Hz */
269 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
270 1488, 1800, 0, 960, 961, 964, 1000, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 1280x960@85Hz */
273 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
274 1504, 1728, 0, 960, 961, 964, 1011, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 1280x960@120Hz RB */
277 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
278 1360, 1440, 0, 960, 963, 967, 1017, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 1280x1024@60Hz */
281 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
282 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 1280x1024@75Hz */
285 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
286 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 1280x1024@85Hz */
289 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
290 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 1280x1024@120Hz RB */
293 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
294 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296 /* 1360x768@60Hz */
297 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
298 1536, 1792, 0, 768, 771, 777, 795, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 1360x768@120Hz RB */
301 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
302 1440, 1520, 0, 768, 771, 776, 813, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
304 /* 1400x1050@60Hz RB */
305 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
306 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 1400x1050@60Hz */
309 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
310 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 1400x1050@75Hz */
313 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
314 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
316 /* 1400x1050@85Hz */
317 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
318 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 1400x1050@120Hz RB */
321 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
322 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
324 /* 1440x900@60Hz RB */
325 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
326 1520, 1600, 0, 900, 903, 909, 926, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 1440x900@60Hz */
329 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
330 1672, 1904, 0, 900, 903, 909, 934, 0,
331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 1440x900@75Hz */
333 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
334 1688, 1936, 0, 900, 903, 909, 942, 0,
335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 1440x900@85Hz */
337 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
338 1696, 1952, 0, 900, 903, 909, 948, 0,
339 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
340 /* 1440x900@120Hz RB */
341 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
342 1520, 1600, 0, 900, 903, 909, 953, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
344 /* 1600x1200@60Hz */
345 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
346 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 1600x1200@65Hz */
349 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
350 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 1600x1200@70Hz */
353 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
354 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
356 /* 1600x1200@75Hz */
357 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
358 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
360 /* 1600x1200@85Hz */
361 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
362 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 1600x1200@120Hz RB */
365 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
366 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
368 /* 1680x1050@60Hz RB */
369 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
370 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
372 /* 1680x1050@60Hz */
373 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
374 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
376 /* 1680x1050@75Hz */
377 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
378 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 1680x1050@85Hz */
381 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
382 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 1680x1050@120Hz RB */
385 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
386 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 1792x1344@60Hz */
389 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
390 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 1792x1344@75Hz */
393 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
394 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 1792x1344@120Hz RB */
397 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
398 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
400 /* 1856x1392@60Hz */
401 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
402 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
404 /* 1856x1392@75Hz */
405 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
406 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 1856x1392@120Hz RB */
409 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
410 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
412 /* 1920x1200@60Hz RB */
413 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
414 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
416 /* 1920x1200@60Hz */
417 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
418 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 1920x1200@75Hz */
421 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
422 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
424 /* 1920x1200@85Hz */
425 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
426 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 1920x1200@120Hz RB */
429 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
430 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
432 /* 1920x1440@60Hz */
433 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
434 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 1920x1440@75Hz */
437 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
438 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
440 /* 1920x1440@120Hz RB */
441 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
442 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 2560x1600@60Hz RB */
445 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
446 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 2560x1600@60Hz */
449 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
450 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 2560x1600@75HZ */
453 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
454 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 2560x1600@85HZ */
457 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
458 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
460 /* 2560x1600@120Hz RB */
461 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
462 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
464};
465
e7bfa5c4
VS		 466/*
467 * These more or less come from the DMT spec. The 720x400 modes are
468 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
469 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
470 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
471 * mode.
472 *
473 * The DMT modes have been fact-checked; the rest are mild guesses.
474 */
a6b21831
TR		 475static const struct drm_display_mode edid_est_modes[] = {
476 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
477 968, 1056, 0, 600, 601, 605, 628, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
479 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
480 896, 1024, 0, 600, 601, 603, 625, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
482 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
483 720, 840, 0, 480, 481, 484, 500, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
485 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
486 704, 832, 0, 480, 489, 491, 520, 0,
487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
488 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
489 768, 864, 0, 480, 483, 486, 525, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
492 752, 800, 0, 480, 490, 492, 525, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
494 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
495 846, 900, 0, 400, 421, 423, 449, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
497 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
498 846, 900, 0, 400, 412, 414, 449, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
500 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
501 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
503 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
504 1136, 1312, 0, 768, 769, 772, 800, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
506 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
507 1184, 1328, 0, 768, 771, 777, 806, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
509 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
510 1184, 1344, 0, 768, 771, 777, 806, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
512 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
513 1208, 1264, 0, 768, 768, 776, 817, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
515 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
516 928, 1152, 0, 624, 625, 628, 667, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
518 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
519 896, 1056, 0, 600, 601, 604, 625, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
521 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
522 976, 1040, 0, 600, 637, 643, 666, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
524 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
525 1344, 1600, 0, 864, 865, 868, 900, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
527};
528
529struct minimode {
530 short w;
531 short h;
532 short r;
533 short rb;
534};
535
536static const struct minimode est3_modes[] = {
537 /* byte 6 */
538 { 640, 350, 85, 0 },
539 { 640, 400, 85, 0 },
540 { 720, 400, 85, 0 },
541 { 640, 480, 85, 0 },
542 { 848, 480, 60, 0 },
543 { 800, 600, 85, 0 },
544 { 1024, 768, 85, 0 },
545 { 1152, 864, 75, 0 },
546 /* byte 7 */
547 { 1280, 768, 60, 1 },
548 { 1280, 768, 60, 0 },
549 { 1280, 768, 75, 0 },
550 { 1280, 768, 85, 0 },
551 { 1280, 960, 60, 0 },
552 { 1280, 960, 85, 0 },
553 { 1280, 1024, 60, 0 },
554 { 1280, 1024, 85, 0 },
555 /* byte 8 */
556 { 1360, 768, 60, 0 },
557 { 1440, 900, 60, 1 },
558 { 1440, 900, 60, 0 },
559 { 1440, 900, 75, 0 },
560 { 1440, 900, 85, 0 },
561 { 1400, 1050, 60, 1 },
562 { 1400, 1050, 60, 0 },
563 { 1400, 1050, 75, 0 },
564 /* byte 9 */
565 { 1400, 1050, 85, 0 },
566 { 1680, 1050, 60, 1 },
567 { 1680, 1050, 60, 0 },
568 { 1680, 1050, 75, 0 },
569 { 1680, 1050, 85, 0 },
570 { 1600, 1200, 60, 0 },
571 { 1600, 1200, 65, 0 },
572 { 1600, 1200, 70, 0 },
573 /* byte 10 */
574 { 1600, 1200, 75, 0 },
575 { 1600, 1200, 85, 0 },
576 { 1792, 1344, 60, 0 },
c068b32a 577 { 1792, 1344, 75, 0 },
a6b21831
TR		 578 { 1856, 1392, 60, 0 },
579 { 1856, 1392, 75, 0 },
580 { 1920, 1200, 60, 1 },
581 { 1920, 1200, 60, 0 },
582 /* byte 11 */
583 { 1920, 1200, 75, 0 },
584 { 1920, 1200, 85, 0 },
585 { 1920, 1440, 60, 0 },
586 { 1920, 1440, 75, 0 },
587};
588
589static const struct minimode extra_modes[] = {
590 { 1024, 576, 60, 0 },
591 { 1366, 768, 60, 0 },
592 { 1600, 900, 60, 0 },
593 { 1680, 945, 60, 0 },
594 { 1920, 1080, 60, 0 },
595 { 2048, 1152, 60, 0 },
596 { 2048, 1536, 60, 0 },
597};
598
599/*
600 * Probably taken from CEA-861 spec.
601 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
602 */
603static const struct drm_display_mode edid_cea_modes[] = {
604 /* 1 - 640x480@60Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 608 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 609 /* 2 - 720x480@60Hz */
610 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
611 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 613 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 614 /* 3 - 720x480@60Hz */
615 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
616 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 618 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 619 /* 4 - 1280x720@60Hz */
620 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
621 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 623 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 624 /* 5 - 1920x1080i@60Hz */
625 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
626 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 628 DRM_MODE_FLAG_INTERLACE),
985e5dc2 629 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 630 /* 6 - 1440x480i@60Hz */
631 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
632 1602, 1716, 0, 480, 488, 494, 525, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 634 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 636 /* 7 - 1440x480i@60Hz */
637 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
638 1602, 1716, 0, 480, 488, 494, 525, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 640 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 641 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 642 /* 8 - 1440x240@60Hz */
643 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
644 1602, 1716, 0, 240, 244, 247, 262, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 646 DRM_MODE_FLAG_DBLCLK),
985e5dc2 647 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 648 /* 9 - 1440x240@60Hz */
649 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
650 1602, 1716, 0, 240, 244, 247, 262, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 652 DRM_MODE_FLAG_DBLCLK),
985e5dc2 653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 654 /* 10 - 2880x480i@60Hz */
655 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
656 3204, 3432, 0, 480, 488, 494, 525, 0,
657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 658 DRM_MODE_FLAG_INTERLACE),
985e5dc2 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 660 /* 11 - 2880x480i@60Hz */
661 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
662 3204, 3432, 0, 480, 488, 494, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 664 DRM_MODE_FLAG_INTERLACE),
985e5dc2 665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 666 /* 12 - 2880x240@60Hz */
667 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
668 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 671 /* 13 - 2880x240@60Hz */
672 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
673 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 675 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 676 /* 14 - 1440x480@60Hz */
677 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
678 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 681 /* 15 - 1440x480@60Hz */
682 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
683 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 686 /* 16 - 1920x1080@60Hz */
687 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
688 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 691 /* 17 - 720x576@50Hz */
692 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
693 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 695 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 696 /* 18 - 720x576@50Hz */
697 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
698 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 700 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 701 /* 19 - 1280x720@50Hz */
702 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
703 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 705 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 706 /* 20 - 1920x1080i@50Hz */
707 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
708 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 710 DRM_MODE_FLAG_INTERLACE),
985e5dc2 711 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 712 /* 21 - 1440x576i@50Hz */
713 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
714 1590, 1728, 0, 576, 580, 586, 625, 0,
715 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 716 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 717 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 718 /* 22 - 1440x576i@50Hz */
719 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
720 1590, 1728, 0, 576, 580, 586, 625, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 722 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 723 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 724 /* 23 - 1440x288@50Hz */
725 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
726 1590, 1728, 0, 288, 290, 293, 312, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 728 DRM_MODE_FLAG_DBLCLK),
985e5dc2 729 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 730 /* 24 - 1440x288@50Hz */
731 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
732 1590, 1728, 0, 288, 290, 293, 312, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 734 DRM_MODE_FLAG_DBLCLK),
985e5dc2 735 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 736 /* 25 - 2880x576i@50Hz */
737 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
738 3180, 3456, 0, 576, 580, 586, 625, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 740 DRM_MODE_FLAG_INTERLACE),
985e5dc2 741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 742 /* 26 - 2880x576i@50Hz */
743 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
744 3180, 3456, 0, 576, 580, 586, 625, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 746 DRM_MODE_FLAG_INTERLACE),
985e5dc2 747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 748 /* 27 - 2880x288@50Hz */
749 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
750 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 753 /* 28 - 2880x288@50Hz */
754 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
755 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 757 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 758 /* 29 - 1440x576@50Hz */
759 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
760 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 763 /* 30 - 1440x576@50Hz */
764 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
765 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 768 /* 31 - 1920x1080@50Hz */
769 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
770 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 773 /* 32 - 1920x1080@24Hz */
774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
775 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 777 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 778 /* 33 - 1920x1080@25Hz */
779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
780 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 782 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 783 /* 34 - 1920x1080@30Hz */
784 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
785 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 787 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 788 /* 35 - 2880x480@60Hz */
789 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
790 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 793 /* 36 - 2880x480@60Hz */
794 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
795 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 798 /* 37 - 2880x576@50Hz */
799 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
800 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 803 /* 38 - 2880x576@50Hz */
804 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
805 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 808 /* 39 - 1920x1080i@50Hz */
809 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
810 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 812 DRM_MODE_FLAG_INTERLACE),
985e5dc2 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 814 /* 40 - 1920x1080i@100Hz */
815 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
816 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 818 DRM_MODE_FLAG_INTERLACE),
985e5dc2 819 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 820 /* 41 - 1280x720@100Hz */
821 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
822 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 824 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 825 /* 42 - 720x576@100Hz */
826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
827 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 829 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 830 /* 43 - 720x576@100Hz */
831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
832 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 834 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 835 /* 44 - 1440x576i@100Hz */
836 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
837 1590, 1728, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 839 DRM_MODE_FLAG_DBLCLK),
985e5dc2 840 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 841 /* 45 - 1440x576i@100Hz */
842 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
843 1590, 1728, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 845 DRM_MODE_FLAG_DBLCLK),
985e5dc2 846 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 847 /* 46 - 1920x1080i@120Hz */
848 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
849 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 851 DRM_MODE_FLAG_INTERLACE),
985e5dc2 852 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 853 /* 47 - 1280x720@120Hz */
854 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
855 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 857 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 858 /* 48 - 720x480@120Hz */
859 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
860 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 862 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 863 /* 49 - 720x480@120Hz */
864 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
865 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 867 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 868 /* 50 - 1440x480i@120Hz */
869 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
870 1602, 1716, 0, 480, 488, 494, 525, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 872 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 873 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 874 /* 51 - 1440x480i@120Hz */
875 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
876 1602, 1716, 0, 480, 488, 494, 525, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 878 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 879 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 880 /* 52 - 720x576@200Hz */
881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
882 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 884 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 885 /* 53 - 720x576@200Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 889 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 890 /* 54 - 1440x576i@200Hz */
891 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
892 1590, 1728, 0, 576, 580, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 894 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 895 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 896 /* 55 - 1440x576i@200Hz */
897 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
898 1590, 1728, 0, 576, 580, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 901 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 902 /* 56 - 720x480@240Hz */
903 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
904 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 906 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 907 /* 57 - 720x480@240Hz */
908 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
909 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 911 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 912 /* 58 - 1440x480i@240 */
913 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
914 1602, 1716, 0, 480, 488, 494, 525, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 916 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 917 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 918 /* 59 - 1440x480i@240 */
919 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
920 1602, 1716, 0, 480, 488, 494, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 923 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 924 /* 60 - 1280x720@24Hz */
925 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
926 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 928 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 929 /* 61 - 1280x720@25Hz */
930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
931 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 933 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 934 /* 62 - 1280x720@30Hz */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
936 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 938 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 939 /* 63 - 1920x1080@120Hz */
940 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
941 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 943 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 944 /* 64 - 1920x1080@100Hz */
945 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
946 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
ee7925bb 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 949};
950
7ebe1963
LD		 951/*
952 * HDMI 1.4 4k modes.
953 */
954static const struct drm_display_mode edid_4k_modes[] = {
955 /* 1 - 3840x2160@30Hz */
956 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
957 3840, 4016, 4104, 4400, 0,
958 2160, 2168, 2178, 2250, 0,
959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
960 .vrefresh = 30, },
961 /* 2 - 3840x2160@25Hz */
962 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
963 3840, 4896, 4984, 5280, 0,
964 2160, 2168, 2178, 2250, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
966 .vrefresh = 25, },
967 /* 3 - 3840x2160@24Hz */
968 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
969 3840, 5116, 5204, 5500, 0,
970 2160, 2168, 2178, 2250, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .vrefresh = 24, },
973 /* 4 - 4096x2160@24Hz (SMPTE) */
974 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
975 4096, 5116, 5204, 5500, 0,
976 2160, 2168, 2178, 2250, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 24, },
979};
980
61e57a8d 981/*** DDC fetch and block validation ***/
f453ba04 982
083ae056
AJ		 983static const u8 edid_header[] = {
984 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
985};
f453ba04 986
051963d4
TR		 987 /*
988 * Sanity check the header of the base EDID block. Return 8 if the header
989 * is perfect, down to 0 if it's totally wrong.
990 */
991int drm_edid_header_is_valid(const u8 *raw_edid)
992{
993 int i, score = 0;
994
995 for (i = 0; i < sizeof(edid_header); i++)
996 if (raw_edid[i] == edid_header[i])
997 score++;
998
999 return score;
1000}
1001EXPORT_SYMBOL(drm_edid_header_is_valid);
1002
47819ba2
AJ		 1003static int edid_fixup __read_mostly = 6;
1004module_param_named(edid_fixup, edid_fixup, int, 0400);
1005MODULE_PARM_DESC(edid_fixup,
1006 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1007
61e57a8d
AJ		 1008/*
1009 * Sanity check the EDID block (base or extension). Return 0 if the block
1010 * doesn't check out, or 1 if it's valid.
f453ba04 1011 */
0b2443ed 1012bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
f453ba04 1013{
61e57a8d 1014 int i;
f453ba04 1015 u8 csum = 0;
61e57a8d 1016 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1017
fe2ef780
SWK		 1018 if (WARN_ON(!raw_edid))
1019 return false;
1020
47819ba2
AJ		 1021 if (edid_fixup > 8 || edid_fixup < 0)
1022 edid_fixup = 6;
1023
f89ec8a4 1024 if (block == 0) {
051963d4 1025 int score = drm_edid_header_is_valid(raw_edid);
61e57a8d 1026 if (score == 8) ;
47819ba2 1027 else if (score >= edid_fixup) {
61e57a8d
AJ		 1028 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1029 memcpy(raw_edid, edid_header, sizeof(edid_header));
1030 } else {
1031 goto bad;
1032 }
1033 }
f453ba04
DA		 1034
1035 for (i = 0; i < EDID_LENGTH; i++)
1036 csum += raw_edid[i];
1037 if (csum) {
0b2443ed
JG		 1038 if (print_bad_edid) {
1039 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1040 }
4a638b4e
AJ		 1041
1042 /* allow CEA to slide through, switches mangle this */
1043 if (raw_edid[0] != 0x02)
1044 goto bad;
f453ba04
DA		 1045 }
1046
61e57a8d
AJ		 1047 /* per-block-type checks */
1048 switch (raw_edid[0]) {
1049 case 0: /* base */
1050 if (edid->version != 1) {
1051 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1052 goto bad;
1053 }
862b89c0 1054
61e57a8d
AJ		 1055 if (edid->revision > 4)
1056 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1057 break;
862b89c0 1058
61e57a8d
AJ		 1059 default:
1060 break;
1061 }
47ee4ccf 1062
fe2ef780 1063 return true;
f453ba04
DA		 1064
1065bad:
fe2ef780 1066 if (print_bad_edid) {
f49dadb8 1067 printk(KERN_ERR "Raw EDID:\n");
0aff47f2
TV		 1068 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1069 raw_edid, EDID_LENGTH, false);
f453ba04 1070 }
fe2ef780 1071 return false;
f453ba04 1072}
da0df92b 1073EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1074
1075/**
1076 * drm_edid_is_valid - sanity check EDID data
1077 * @edid: EDID data
1078 *
1079 * Sanity-check an entire EDID record (including extensions)
1080 */
1081bool drm_edid_is_valid(struct edid *edid)
1082{
1083 int i;
1084 u8 *raw = (u8 *)edid;
1085
1086 if (!edid)
1087 return false;
1088
1089 for (i = 0; i <= edid->extensions; i++)
0b2443ed 1090 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true))
61e57a8d
AJ		 1091 return false;
1092
1093 return true;
1094}
3c537889 1095EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1096
61e57a8d
AJ		 1097#define DDC_SEGMENT_ADDR 0x30
1098/**
1099 * Get EDID information via I2C.
1100 *
fc66811c
DV		 1101 * @adapter : i2c device adaptor
1102 * @buf: EDID data buffer to be filled
1103 * @block: 128 byte EDID block to start fetching from
1104 * @len: EDID data buffer length to fetch
1105 *
1106 * Returns:
1107 *
1108 * 0 on success or -1 on failure.
61e57a8d
AJ		 1109 *
1110 * Try to fetch EDID information by calling i2c driver function.
1111 */
1112static int
1113drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
1114 int block, int len)
1115{
1116 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1117 unsigned char segment = block >> 1;
1118 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1119 int ret, retries = 5;
1120
1121 /* The core i2c driver will automatically retry the transfer if the
1122 * adapter reports EAGAIN. However, we find that bit-banging transfers
1123 * are susceptible to errors under a heavily loaded machine and
1124 * generate spurious NAKs and timeouts. Retrying the transfer
1125 * of the individual block a few times seems to overcome this.
1126 */
1127 do {
1128 struct i2c_msg msgs[] = {
1129 {
cd004b3f
S		 1130 .addr = DDC_SEGMENT_ADDR,
1131 .flags = 0,
1132 .len = 1,
1133 .buf = &segment,
1134 }, {
4819d2e4
CW		 1135 .addr = DDC_ADDR,
1136 .flags = 0,
1137 .len = 1,
1138 .buf = &start,
1139 }, {
1140 .addr = DDC_ADDR,
1141 .flags = I2C_M_RD,
1142 .len = len,
1143 .buf = buf,
1144 }
1145 };
cd004b3f
S		 1146
1147 /*
1148 * Avoid sending the segment addr to not upset non-compliant ddc
1149 * monitors.
1150 */
1151 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1152
9292f37e
ED		 1153 if (ret == -ENXIO) {
1154 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1155 adapter->name);
1156 break;
1157 }
cd004b3f 1158 } while (ret != xfers && --retries);
4819d2e4 1159
cd004b3f 1160 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1161}
1162
4a9a8b71
DA		 1163static bool drm_edid_is_zero(u8 *in_edid, int length)
1164{
6311803b
AM		 1165 if (memchr_inv(in_edid, 0, length))
1166 return false;
4a9a8b71 1167
4a9a8b71
DA		 1168 return true;
1169}
1170
61e57a8d
AJ		 1171static u8 *
1172drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1173{
0ea75e23 1174 int i, j = 0, valid_extensions = 0;
61e57a8d 1175 u8 *block, *new;
0b2443ed 1176 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
61e57a8d
AJ		 1177
1178 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1179 return NULL;
1180
1181 /* base block fetch */
1182 for (i = 0; i < 4; i++) {
1183 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
1184 goto out;
0b2443ed 1185 if (drm_edid_block_valid(block, 0, print_bad_edid))
61e57a8d 1186 break;
4a9a8b71
DA		 1187 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1188 connector->null_edid_counter++;
1189 goto carp;
1190 }
61e57a8d
AJ		 1191 }
1192 if (i == 4)
1193 goto carp;
1194
1195 /* if there's no extensions, we're done */
1196 if (block[0x7e] == 0)
1197 return block;
1198
1199 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1200 if (!new)
1201 goto out;
1202 block = new;
1203
1204 for (j = 1; j <= block[0x7e]; j++) {
1205 for (i = 0; i < 4; i++) {
0ea75e23
ST		 1206 if (drm_do_probe_ddc_edid(adapter,
1207 block + (valid_extensions + 1) * EDID_LENGTH,
1208 j, EDID_LENGTH))
61e57a8d 1209 goto out;
0b2443ed 1210 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) {
0ea75e23 1211 valid_extensions++;
61e57a8d 1212 break;
0ea75e23 1213 }
61e57a8d 1214 }
f934ec8c
ML		 1215
1216 if (i == 4 && print_bad_edid) {
0ea75e23
ST		 1217 dev_warn(connector->dev->dev,
1218 "%s: Ignoring invalid EDID block %d.\n",
1219 drm_get_connector_name(connector), j);
f934ec8c
ML		 1220
1221 connector->bad_edid_counter++;
1222 }
0ea75e23
ST		 1223 }
1224
1225 if (valid_extensions != block[0x7e]) {
1226 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1227 block[0x7e] = valid_extensions;
1228 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1229 if (!new)
1230 goto out;
1231 block = new;
61e57a8d
AJ		 1232 }
1233
1234 return block;
1235
1236carp:
0b2443ed
JG		 1237 if (print_bad_edid) {
1238 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1239 drm_get_connector_name(connector), j);
1240 }
1241 connector->bad_edid_counter++;
61e57a8d
AJ		 1242
1243out:
1244 kfree(block);
1245 return NULL;
1246}
1247
1248/**
1249 * Probe DDC presence.
fc66811c
DV		 1250 * @adapter: i2c adapter to probe
1251 *
1252 * Returns:
61e57a8d 1253 *
fc66811c 1254 * 1 on success
61e57a8d 1255 */
fbff4690 1256bool
61e57a8d
AJ		 1257drm_probe_ddc(struct i2c_adapter *adapter)
1258{
1259 unsigned char out;
1260
1261 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1262}
fbff4690 1263EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1264
1265/**
1266 * drm_get_edid - get EDID data, if available
1267 * @connector: connector we're probing
1268 * @adapter: i2c adapter to use for DDC
1269 *
1270 * Poke the given i2c channel to grab EDID data if possible. If found,
1271 * attach it to the connector.
1272 *
1273 * Return edid data or NULL if we couldn't find any.
1274 */
1275struct edid *drm_get_edid(struct drm_connector *connector,
1276 struct i2c_adapter *adapter)
1277{
1278 struct edid *edid = NULL;
1279
1280 if (drm_probe_ddc(adapter))
1281 edid = (struct edid *)drm_do_get_edid(connector, adapter);
1282
61e57a8d 1283 return edid;
61e57a8d
AJ		 1284}
1285EXPORT_SYMBOL(drm_get_edid);
1286
51f8da59
JN		 1287/**
1288 * drm_edid_duplicate - duplicate an EDID and the extensions
1289 * @edid: EDID to duplicate
1290 *
1291 * Return duplicate edid or NULL on allocation failure.
1292 */
1293struct edid *drm_edid_duplicate(const struct edid *edid)
1294{
1295 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1296}
1297EXPORT_SYMBOL(drm_edid_duplicate);
1298
61e57a8d
AJ		 1299/*** EDID parsing ***/
1300
f453ba04
DA		 1301/**
1302 * edid_vendor - match a string against EDID's obfuscated vendor field
1303 * @edid: EDID to match
1304 * @vendor: vendor string
1305 *
1306 * Returns true if @vendor is in @edid, false otherwise
1307 */
1308static bool edid_vendor(struct edid *edid, char *vendor)
1309{
1310 char edid_vendor[3];
1311
1312 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1313 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1314 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1315 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1316
1317 return !strncmp(edid_vendor, vendor, 3);
1318}
1319
1320/**
1321 * edid_get_quirks - return quirk flags for a given EDID
1322 * @edid: EDID to process
1323 *
1324 * This tells subsequent routines what fixes they need to apply.
1325 */
1326static u32 edid_get_quirks(struct edid *edid)
1327{
1328 struct edid_quirk *quirk;
1329 int i;
1330
1331 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1332 quirk = &edid_quirk_list[i];
1333
1334 if (edid_vendor(edid, quirk->vendor) &&
1335 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1336 return quirk->quirks;
1337 }
1338
1339 return 0;
1340}
1341
1342#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1343#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1344
f453ba04
DA		 1345/**
1346 * edid_fixup_preferred - set preferred modes based on quirk list
1347 * @connector: has mode list to fix up
1348 * @quirks: quirks list
1349 *
1350 * Walk the mode list for @connector, clearing the preferred status
1351 * on existing modes and setting it anew for the right mode ala @quirks.
1352 */
1353static void edid_fixup_preferred(struct drm_connector *connector,
1354 u32 quirks)
1355{
1356 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1357 int target_refresh = 0;
339d202c 1358 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1359
1360 if (list_empty(&connector->probed_modes))
1361 return;
1362
1363 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1364 target_refresh = 60;
1365 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1366 target_refresh = 75;
1367
1368 preferred_mode = list_first_entry(&connector->probed_modes,
1369 struct drm_display_mode, head);
1370
1371 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1372 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1373
1374 if (cur_mode == preferred_mode)
1375 continue;
1376
1377 /* Largest mode is preferred */
1378 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1379 preferred_mode = cur_mode;
1380
339d202c
AD		 1381 cur_vrefresh = cur_mode->vrefresh ?
1382 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1383 preferred_vrefresh = preferred_mode->vrefresh ?
1384 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1385 /* At a given size, try to get closest to target refresh */
1386 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1387 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1388 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1389 preferred_mode = cur_mode;
1390 }
1391 }
1392
1393 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1394}
1395
f6e252ba
AJ		 1396static bool
1397mode_is_rb(const struct drm_display_mode *mode)
1398{
1399 return (mode->htotal - mode->hdisplay == 160) &&
1400 (mode->hsync_end - mode->hdisplay == 80) &&
1401 (mode->hsync_end - mode->hsync_start == 32) &&
1402 (mode->vsync_start - mode->vdisplay == 3);
1403}
1404
33c7531d
AJ		 1405/*
1406 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1407 * @dev: Device to duplicate against
1408 * @hsize: Mode width
1409 * @vsize: Mode height
1410 * @fresh: Mode refresh rate
f6e252ba 1411 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1412 *
1413 * Walk the DMT mode list looking for a match for the given parameters.
1414 * Return a newly allocated copy of the mode, or NULL if not found.
1415 */
1d42bbc8 1416struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1417 int hsize, int vsize, int fresh,
1418 bool rb)
559ee21d 1419{
07a5e632 1420 int i;
559ee21d 1421
a6b21831 1422 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1423 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1424 if (hsize != ptr->hdisplay)
1425 continue;
1426 if (vsize != ptr->vdisplay)
1427 continue;
1428 if (fresh != drm_mode_vrefresh(ptr))
1429 continue;
f6e252ba
AJ		 1430 if (rb != mode_is_rb(ptr))
1431 continue;
f8b46a05
AJ		 1432
1433 return drm_mode_duplicate(dev, ptr);
559ee21d 1434 }
f8b46a05
AJ		 1435
1436 return NULL;
559ee21d 1437}
1d42bbc8 1438EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1439
d1ff6409
AJ		 1440typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1441
4d76a221
AJ		 1442static void
1443cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1444{
1445 int i, n = 0;
4966b2a9 1446 u8 d = ext[0x02];
4d76a221
AJ		 1447 u8 *det_base = ext + d;
1448
4966b2a9 1449 n = (127 - d) / 18;
4d76a221
AJ		 1450 for (i = 0; i < n; i++)
1451 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1452}
1453
cbba98f8
AJ		 1454static void
1455vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1456{
1457 unsigned int i, n = min((int)ext[0x02], 6);
1458 u8 *det_base = ext + 5;
1459
1460 if (ext[0x01] != 1)
1461 return; /* unknown version */
1462
1463 for (i = 0; i < n; i++)
1464 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1465}
1466
d1ff6409
AJ		 1467static void
1468drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1469{
1470 int i;
1471 struct edid *edid = (struct edid *)raw_edid;
1472
1473 if (edid == NULL)
1474 return;
1475
1476 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1477 cb(&(edid->detailed_timings[i]), closure);
1478
4d76a221
AJ		 1479 for (i = 1; i <= raw_edid[0x7e]; i++) {
1480 u8 *ext = raw_edid + (i * EDID_LENGTH);
1481 switch (*ext) {
1482 case CEA_EXT:
1483 cea_for_each_detailed_block(ext, cb, closure);
1484 break;
cbba98f8
AJ		 1485 case VTB_EXT:
1486 vtb_for_each_detailed_block(ext, cb, closure);
1487 break;
4d76a221
AJ		 1488 default:
1489 break;
1490 }
1491 }
d1ff6409
AJ		 1492}
1493
1494static void
1495is_rb(struct detailed_timing *t, void *data)
1496{
1497 u8 *r = (u8 *)t;
1498 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1499 if (r[15] & 0x10)
1500 *(bool *)data = true;
1501}
1502
1503/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1504static bool
1505drm_monitor_supports_rb(struct edid *edid)
1506{
1507 if (edid->revision >= 4) {
b196a498 1508 bool ret = false;
d1ff6409
AJ		 1509 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1510 return ret;
1511 }
1512
1513 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1514}
1515
7a374350
AJ		 1516static void
1517find_gtf2(struct detailed_timing *t, void *data)
1518{
1519 u8 *r = (u8 *)t;
1520 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1521 *(u8 **)data = r;
1522}
1523
1524/* Secondary GTF curve kicks in above some break frequency */
1525static int
1526drm_gtf2_hbreak(struct edid *edid)
1527{
1528 u8 *r = NULL;
1529 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1530 return r ? (r[12] * 2) : 0;
1531}
1532
1533static int
1534drm_gtf2_2c(struct edid *edid)
1535{
1536 u8 *r = NULL;
1537 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1538 return r ? r[13] : 0;
1539}
1540
1541static int
1542drm_gtf2_m(struct edid *edid)
1543{
1544 u8 *r = NULL;
1545 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1546 return r ? (r[15] << 8) + r[14] : 0;
1547}
1548
1549static int
1550drm_gtf2_k(struct edid *edid)
1551{
1552 u8 *r = NULL;
1553 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1554 return r ? r[16] : 0;
1555}
1556
1557static int
1558drm_gtf2_2j(struct edid *edid)
1559{
1560 u8 *r = NULL;
1561 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1562 return r ? r[17] : 0;
1563}
1564
1565/**
1566 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1567 * @edid: EDID block to scan
1568 */
1569static int standard_timing_level(struct edid *edid)
1570{
1571 if (edid->revision >= 2) {
1572 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1573 return LEVEL_CVT;
1574 if (drm_gtf2_hbreak(edid))
1575 return LEVEL_GTF2;
1576 return LEVEL_GTF;
1577 }
1578 return LEVEL_DMT;
1579}
1580
23425cae
AJ		 1581/*
1582 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1583 * monitors fill with ascii space (0x20) instead.
1584 */
1585static int
1586bad_std_timing(u8 a, u8 b)
1587{
1588 return (a == 0x00 && b == 0x00) ||
1589 (a == 0x01 && b == 0x01) ||
1590 (a == 0x20 && b == 0x20);
1591}
1592
f453ba04
DA		 1593/**
1594 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 1595 * @connector: connector of for the EDID block
1596 * @edid: EDID block to scan
f453ba04 1597 * @t: standard timing params
fc66811c 1598 * @revision: standard timing level
f453ba04
DA		 1599 *
1600 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 1601 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 1602 */
7ca6adb3 1603static struct drm_display_mode *
7a374350
AJ		 1604drm_mode_std(struct drm_connector *connector, struct edid *edid,
1605 struct std_timing *t, int revision)
f453ba04 1606{
7ca6adb3
AJ		 1607 struct drm_device *dev = connector->dev;
1608 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 1609 int hsize, vsize;
1610 int vrefresh_rate;
0454beab
MD		 1611 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1612 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 1613 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1614 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 1615 int timing_level = standard_timing_level(edid);
5c61259e 1616
23425cae
AJ		 1617 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1618 return NULL;
1619
5c61259e
ZY		 1620 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1621 hsize = t->hsize * 8 + 248;
1622 /* vrefresh_rate = vfreq + 60 */
1623 vrefresh_rate = vfreq + 60;
1624 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ		 1625 if (aspect_ratio == 0) {
1626 if (revision < 3)
1627 vsize = hsize;
1628 else
1629 vsize = (hsize * 10) / 16;
1630 } else if (aspect_ratio == 1)
f453ba04 1631 vsize = (hsize * 3) / 4;
0454beab 1632 else if (aspect_ratio == 2)
f453ba04
DA		 1633 vsize = (hsize * 4) / 5;
1634 else
1635 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 1636
1637 /* HDTV hack, part 1 */
1638 if (vrefresh_rate == 60 &&
1639 ((hsize == 1360 && vsize == 765) ||
1640 (hsize == 1368 && vsize == 769))) {
1641 hsize = 1366;
1642 vsize = 768;
1643 }
1644
7ca6adb3
AJ		 1645 /*
1646 * If this connector already has a mode for this size and refresh
1647 * rate (because it came from detailed or CVT info), use that
1648 * instead. This way we don't have to guess at interlace or
1649 * reduced blanking.
1650 */
522032da 1651 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 1652 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1653 drm_mode_vrefresh(m) == vrefresh_rate)
1654 return NULL;
1655
a0910c8e
AJ		 1656 /* HDTV hack, part 2 */
1657 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1658 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 1659 false);
559ee21d 1660 mode->hdisplay = 1366;
a4967de6
AJ		 1661 mode->hsync_start = mode->hsync_start - 1;
1662 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 1663 return mode;
1664 }
a0910c8e 1665
559ee21d 1666 /* check whether it can be found in default mode table */
f6e252ba
AJ		 1667 if (drm_monitor_supports_rb(edid)) {
1668 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1669 true);
1670 if (mode)
1671 return mode;
1672 }
1673 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 1674 if (mode)
1675 return mode;
1676
f6e252ba 1677 /* okay, generate it */
5c61259e
ZY		 1678 switch (timing_level) {
1679 case LEVEL_DMT:
5c61259e
ZY		 1680 break;
1681 case LEVEL_GTF:
1682 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1683 break;
7a374350
AJ		 1684 case LEVEL_GTF2:
1685 /*
1686 * This is potentially wrong if there's ever a monitor with
1687 * more than one ranges section, each claiming a different
1688 * secondary GTF curve. Please don't do that.
1689 */
1690 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 1691 if (!mode)
1692 return NULL;
7a374350 1693 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 1694 drm_mode_destroy(dev, mode);
7a374350
AJ		 1695 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1696 vrefresh_rate, 0, 0,
1697 drm_gtf2_m(edid),
1698 drm_gtf2_2c(edid),
1699 drm_gtf2_k(edid),
1700 drm_gtf2_2j(edid));
1701 }
1702 break;
5c61259e 1703 case LEVEL_CVT:
d50ba256
DA		 1704 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1705 false);
5c61259e
ZY		 1706 break;
1707 }
f453ba04
DA		 1708 return mode;
1709}
1710
b58db2c6
AJ		 1711/*
1712 * EDID is delightfully ambiguous about how interlaced modes are to be
1713 * encoded. Our internal representation is of frame height, but some
1714 * HDTV detailed timings are encoded as field height.
1715 *
1716 * The format list here is from CEA, in frame size. Technically we
1717 * should be checking refresh rate too. Whatever.
1718 */
1719static void
1720drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1721 struct detailed_pixel_timing *pt)
1722{
1723 int i;
1724 static const struct {
1725 int w, h;
1726 } cea_interlaced[] = {
1727 { 1920, 1080 },
1728 { 720, 480 },
1729 { 1440, 480 },
1730 { 2880, 480 },
1731 { 720, 576 },
1732 { 1440, 576 },
1733 { 2880, 576 },
1734 };
b58db2c6
AJ		 1735
1736 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1737 return;
1738
3c581411 1739 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 1740 if ((mode->hdisplay == cea_interlaced[i].w) &&
1741 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1742 mode->vdisplay *= 2;
1743 mode->vsync_start *= 2;
1744 mode->vsync_end *= 2;
1745 mode->vtotal *= 2;
1746 mode->vtotal |= 1;
1747 }
1748 }
1749
1750 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1751}
1752
f453ba04
DA		 1753/**
1754 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1755 * @dev: DRM device (needed to create new mode)
1756 * @edid: EDID block
1757 * @timing: EDID detailed timing info
1758 * @quirks: quirks to apply
1759 *
1760 * An EDID detailed timing block contains enough info for us to create and
1761 * return a new struct drm_display_mode.
1762 */
1763static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1764 struct edid *edid,
1765 struct detailed_timing *timing,
1766 u32 quirks)
1767{
1768 struct drm_display_mode *mode;
1769 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 1770 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1771 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1772 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1773 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 1774 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1775 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 1776 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 1777 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 1778
fc438966 1779 /* ignore tiny modes */
0454beab 1780 if (hactive < 64 || vactive < 64)
fc438966
AJ		 1781 return NULL;
1782
0454beab 1783 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 1784 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 1785 return NULL;
1786 }
0454beab 1787 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 1788 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 1789 }
1790
fcb45611
ZY		 1791 /* it is incorrect if hsync/vsync width is zero */
1792 if (!hsync_pulse_width || !vsync_pulse_width) {
1793 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1794 "Wrong Hsync/Vsync pulse width\n");
1795 return NULL;
1796 }
bc42aabc
AJ		 1797
1798 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1799 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1800 if (!mode)
1801 return NULL;
1802
1803 goto set_size;
1804 }
1805
f453ba04
DA		 1806 mode = drm_mode_create(dev);
1807 if (!mode)
1808 return NULL;
1809
f453ba04 1810 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1811 timing->pixel_clock = cpu_to_le16(1088);
1812
1813 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1814
1815 mode->hdisplay = hactive;
1816 mode->hsync_start = mode->hdisplay + hsync_offset;
1817 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1818 mode->htotal = mode->hdisplay + hblank;
1819
1820 mode->vdisplay = vactive;
1821 mode->vsync_start = mode->vdisplay + vsync_offset;
1822 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1823 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1824
7064fef5
JB		 1825 /* Some EDIDs have bogus h/vtotal values */
1826 if (mode->hsync_end > mode->htotal)
1827 mode->htotal = mode->hsync_end + 1;
1828 if (mode->vsync_end > mode->vtotal)
1829 mode->vtotal = mode->vsync_end + 1;
1830
b58db2c6 1831 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 1832
1833 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1834 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1835 }
1836
0454beab
MD		 1837 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1838 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1839 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1840 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1841
bc42aabc 1842set_size:
e14cbee4
MD		 1843 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1844 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1845
1846 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1847 mode->width_mm *= 10;
1848 mode->height_mm *= 10;
1849 }
1850
1851 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1852 mode->width_mm = edid->width_cm * 10;
1853 mode->height_mm = edid->height_cm * 10;
1854 }
1855
bc42aabc 1856 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 1857 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 1858 drm_mode_set_name(mode);
1859
f453ba04
DA		 1860 return mode;
1861}
1862
b17e52ef 1863static bool
b1f559ec
CW		 1864mode_in_hsync_range(const struct drm_display_mode *mode,
1865 struct edid *edid, u8 *t)
b17e52ef
AJ		 1866{
1867 int hsync, hmin, hmax;
1868
1869 hmin = t[7];
1870 if (edid->revision >= 4)
1871 hmin += ((t[4] & 0x04) ? 255 : 0);
1872 hmax = t[8];
1873 if (edid->revision >= 4)
1874 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1875 hsync = drm_mode_hsync(mode);
07a5e632 1876
b17e52ef
AJ		 1877 return (hsync <= hmax && hsync >= hmin);
1878}
1879
1880static bool
b1f559ec
CW		 1881mode_in_vsync_range(const struct drm_display_mode *mode,
1882 struct edid *edid, u8 *t)
b17e52ef
AJ		 1883{
1884 int vsync, vmin, vmax;
1885
1886 vmin = t[5];
1887 if (edid->revision >= 4)
1888 vmin += ((t[4] & 0x01) ? 255 : 0);
1889 vmax = t[6];
1890 if (edid->revision >= 4)
1891 vmax += ((t[4] & 0x02) ? 255 : 0);
1892 vsync = drm_mode_vrefresh(mode);
1893
1894 return (vsync <= vmax && vsync >= vmin);
1895}
1896
1897static u32
1898range_pixel_clock(struct edid *edid, u8 *t)
1899{
1900 /* unspecified */
1901 if (t[9] == 0 || t[9] == 255)
1902 return 0;
1903
1904 /* 1.4 with CVT support gives us real precision, yay */
1905 if (edid->revision >= 4 && t[10] == 0x04)
1906 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1907
1908 /* 1.3 is pathetic, so fuzz up a bit */
1909 return t[9] * 10000 + 5001;
1910}
1911
b17e52ef 1912static bool
b1f559ec 1913mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 1914 struct detailed_timing *timing)
1915{
1916 u32 max_clock;
1917 u8 *t = (u8 *)timing;
1918
1919 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1920 return false;
1921
b17e52ef 1922 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1923 return false;
1924
b17e52ef 1925 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1926 if (mode->clock > max_clock)
1927 return false;
b17e52ef
AJ		 1928
1929 /* 1.4 max horizontal check */
1930 if (edid->revision >= 4 && t[10] == 0x04)
1931 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1932 return false;
1933
1934 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1935 return false;
07a5e632
AJ		 1936
1937 return true;
1938}
1939
7b668ebe
TI		 1940static bool valid_inferred_mode(const struct drm_connector *connector,
1941 const struct drm_display_mode *mode)
1942{
1943 struct drm_display_mode *m;
1944 bool ok = false;
1945
1946 list_for_each_entry(m, &connector->probed_modes, head) {
1947 if (mode->hdisplay == m->hdisplay &&
1948 mode->vdisplay == m->vdisplay &&
1949 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
1950 return false; /* duplicated */
1951 if (mode->hdisplay <= m->hdisplay &&
1952 mode->vdisplay <= m->vdisplay)
1953 ok = true;
1954 }
1955 return ok;
1956}
1957
b17e52ef 1958static int
cd4cd3de 1959drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 1960 struct detailed_timing *timing)
07a5e632
AJ		 1961{
1962 int i, modes = 0;
1963 struct drm_display_mode *newmode;
1964 struct drm_device *dev = connector->dev;
1965
a6b21831 1966 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 1967 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
1968 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 1969 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1970 if (newmode) {
1971 drm_mode_probed_add(connector, newmode);
1972 modes++;
1973 }
1974 }
1975 }
1976
1977 return modes;
1978}
1979
c09dedb7
TI		 1980/* fix up 1366x768 mode from 1368x768;
1981 * GFT/CVT can't express 1366 width which isn't dividable by 8
1982 */
1983static void fixup_mode_1366x768(struct drm_display_mode *mode)
1984{
1985 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
1986 mode->hdisplay = 1366;
1987 mode->hsync_start--;
1988 mode->hsync_end--;
1989 drm_mode_set_name(mode);
1990 }
1991}
1992
b309bd37
AJ		 1993static int
1994drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1995 struct detailed_timing *timing)
1996{
1997 int i, modes = 0;
1998 struct drm_display_mode *newmode;
1999 struct drm_device *dev = connector->dev;
2000
a6b21831 2001 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2002 const struct minimode *m = &extra_modes[i];
2003 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2004 if (!newmode)
2005 return modes;
b309bd37 2006
c09dedb7 2007 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2008 if (!mode_in_range(newmode, edid, timing) ||
2009 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2010 drm_mode_destroy(dev, newmode);
2011 continue;
2012 }
2013
2014 drm_mode_probed_add(connector, newmode);
2015 modes++;
2016 }
2017
2018 return modes;
2019}
2020
2021static int
2022drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2023 struct detailed_timing *timing)
2024{
2025 int i, modes = 0;
2026 struct drm_display_mode *newmode;
2027 struct drm_device *dev = connector->dev;
2028 bool rb = drm_monitor_supports_rb(edid);
2029
a6b21831 2030 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2031 const struct minimode *m = &extra_modes[i];
2032 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2033 if (!newmode)
2034 return modes;
b309bd37 2035
c09dedb7 2036 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2037 if (!mode_in_range(newmode, edid, timing) ||
2038 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2039 drm_mode_destroy(dev, newmode);
2040 continue;
2041 }
2042
2043 drm_mode_probed_add(connector, newmode);
2044 modes++;
2045 }
2046
2047 return modes;
2048}
2049
13931579
AJ		 2050static void
2051do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2052{
13931579
AJ		 2053 struct detailed_mode_closure *closure = c;
2054 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2055 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2056
cb21aafe
AJ		 2057 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2058 return;
2059
2060 closure->modes += drm_dmt_modes_for_range(closure->connector,
2061 closure->edid,
2062 timing);
b309bd37
AJ		 2063
2064 if (!version_greater(closure->edid, 1, 1))
2065 return; /* GTF not defined yet */
2066
2067 switch (range->flags) {
2068 case 0x02: /* secondary gtf, XXX could do more */
2069 case 0x00: /* default gtf */
2070 closure->modes += drm_gtf_modes_for_range(closure->connector,
2071 closure->edid,
2072 timing);
2073 break;
2074 case 0x04: /* cvt, only in 1.4+ */
2075 if (!version_greater(closure->edid, 1, 3))
2076 break;
2077
2078 closure->modes += drm_cvt_modes_for_range(closure->connector,
2079 closure->edid,
2080 timing);
2081 break;
2082 case 0x01: /* just the ranges, no formula */
2083 default:
2084 break;
2085 }
13931579 2086}
69da3015 2087
13931579
AJ		 2088static int
2089add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2090{
2091 struct detailed_mode_closure closure = {
2092 connector, edid, 0, 0, 0
2093 };
9340d8cf 2094
13931579
AJ		 2095 if (version_greater(edid, 1, 0))
2096 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2097 &closure);
9340d8cf 2098
13931579 2099 return closure.modes;
9340d8cf
AJ		 2100}
2101
2255be14
AJ		 2102static int
2103drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2104{
2105 int i, j, m, modes = 0;
2106 struct drm_display_mode *mode;
2107 u8 *est = ((u8 *)timing) + 5;
2108
2109 for (i = 0; i < 6; i++) {
891a7469 2110 for (j = 7; j >= 0; j--) {
2255be14 2111 m = (i * 8) + (7 - j);
3c581411 2112 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2113 break;
2114 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2115 mode = drm_mode_find_dmt(connector->dev,
2116 est3_modes[m].w,
2117 est3_modes[m].h,
f6e252ba
AJ		 2118 est3_modes[m].r,
2119 est3_modes[m].rb);
2255be14
AJ		 2120 if (mode) {
2121 drm_mode_probed_add(connector, mode);
2122 modes++;
2123 }
2124 }
2125 }
2126 }
2127
2128 return modes;
2129}
2130
13931579
AJ		 2131static void
2132do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2133{
13931579 2134 struct detailed_mode_closure *closure = c;
9cf00977 2135 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2136
13931579
AJ		 2137 if (data->type == EDID_DETAIL_EST_TIMINGS)
2138 closure->modes += drm_est3_modes(closure->connector, timing);
2139}
9cf00977 2140
13931579
AJ		 2141/**
2142 * add_established_modes - get est. modes from EDID and add them
fc66811c 2143 * @connector: connector of for the EDID block
13931579
AJ		 2144 * @edid: EDID block to scan
2145 *
2146 * Each EDID block contains a bitmap of the supported "established modes" list
2147 * (defined above). Tease them out and add them to the global modes list.
2148 */
2149static int
2150add_established_modes(struct drm_connector *connector, struct edid *edid)
2151{
2152 struct drm_device *dev = connector->dev;
2153 unsigned long est_bits = edid->established_timings.t1 |
2154 (edid->established_timings.t2 << 8) |
2155 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2156 int i, modes = 0;
2157 struct detailed_mode_closure closure = {
2158 connector, edid, 0, 0, 0
2159 };
9cf00977 2160
13931579
AJ		 2161 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2162 if (est_bits & (1<<i)) {
2163 struct drm_display_mode *newmode;
2164 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2165 if (newmode) {
2166 drm_mode_probed_add(connector, newmode);
2167 modes++;
2168 }
2169 }
9cf00977
AJ		 2170 }
2171
13931579
AJ		 2172 if (version_greater(edid, 1, 0))
2173 drm_for_each_detailed_block((u8 *)edid,
2174 do_established_modes, &closure);
2175
2176 return modes + closure.modes;
2177}
2178
2179static void
2180do_standard_modes(struct detailed_timing *timing, void *c)
2181{
2182 struct detailed_mode_closure *closure = c;
2183 struct detailed_non_pixel *data = &timing->data.other_data;
2184 struct drm_connector *connector = closure->connector;
2185 struct edid *edid = closure->edid;
2186
2187 if (data->type == EDID_DETAIL_STD_MODES) {
2188 int i;
9cf00977
AJ		 2189 for (i = 0; i < 6; i++) {
2190 struct std_timing *std;
2191 struct drm_display_mode *newmode;
2192
2193 std = &data->data.timings[i];
7a374350
AJ		 2194 newmode = drm_mode_std(connector, edid, std,
2195 edid->revision);
9cf00977
AJ		 2196 if (newmode) {
2197 drm_mode_probed_add(connector, newmode);
13931579 2198 closure->modes++;
9cf00977
AJ		 2199 }
2200 }
9cf00977 2201 }
9cf00977
AJ		 2202}
2203
f453ba04 2204/**
13931579 2205 * add_standard_modes - get std. modes from EDID and add them
fc66811c 2206 * @connector: connector of for the EDID block
f453ba04 2207 * @edid: EDID block to scan
f453ba04 2208 *
13931579
AJ		 2209 * Standard modes can be calculated using the appropriate standard (DMT,
2210 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2211 */
13931579
AJ		 2212static int
2213add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2214{
9cf00977 2215 int i, modes = 0;
13931579
AJ		 2216 struct detailed_mode_closure closure = {
2217 connector, edid, 0, 0, 0
2218 };
2219
2220 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2221 struct drm_display_mode *newmode;
2222
2223 newmode = drm_mode_std(connector, edid,
2224 &edid->standard_timings[i],
2225 edid->revision);
2226 if (newmode) {
2227 drm_mode_probed_add(connector, newmode);
2228 modes++;
2229 }
2230 }
2231
2232 if (version_greater(edid, 1, 0))
2233 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2234 &closure);
2235
2236 /* XXX should also look for standard codes in VTB blocks */
2237
2238 return modes + closure.modes;
2239}
f453ba04 2240
13931579
AJ		 2241static int drm_cvt_modes(struct drm_connector *connector,
2242 struct detailed_timing *timing)
2243{
2244 int i, j, modes = 0;
2245 struct drm_display_mode *newmode;
2246 struct drm_device *dev = connector->dev;
2247 struct cvt_timing *cvt;
2248 const int rates[] = { 60, 85, 75, 60, 50 };
2249 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2250
13931579
AJ		 2251 for (i = 0; i < 4; i++) {
2252 int uninitialized_var(width), height;
2253 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2254
13931579 2255 if (!memcmp(cvt->code, empty, 3))
9cf00977 2256 continue;
f453ba04 2257
13931579
AJ		 2258 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2259 switch (cvt->code[1] & 0x0c) {
2260 case 0x00:
2261 width = height * 4 / 3;
2262 break;
2263 case 0x04:
2264 width = height * 16 / 9;
2265 break;
2266 case 0x08:
2267 width = height * 16 / 10;
2268 break;
2269 case 0x0c:
2270 width = height * 15 / 9;
2271 break;
2272 }
2273
2274 for (j = 1; j < 5; j++) {
2275 if (cvt->code[2] & (1 << j)) {
2276 newmode = drm_cvt_mode(dev, width, height,
2277 rates[j], j == 0,
2278 false, false);
2279 if (newmode) {
2280 drm_mode_probed_add(connector, newmode);
2281 modes++;
2282 }
2283 }
2284 }
f453ba04
DA		 2285 }
2286
2287 return modes;
2288}
9cf00977 2289
13931579
AJ		 2290static void
2291do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2292{
13931579
AJ		 2293 struct detailed_mode_closure *closure = c;
2294 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2295
13931579
AJ		 2296 if (data->type == EDID_DETAIL_CVT_3BYTE)
2297 closure->modes += drm_cvt_modes(closure->connector, timing);
2298}
882f0219 2299
13931579
AJ		 2300static int
2301add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2302{
2303 struct detailed_mode_closure closure = {
2304 connector, edid, 0, 0, 0
2305 };
882f0219 2306
13931579
AJ		 2307 if (version_greater(edid, 1, 2))
2308 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2309
13931579 2310 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2311
13931579
AJ		 2312 return closure.modes;
2313}
2314
2315static void
2316do_detailed_mode(struct detailed_timing *timing, void *c)
2317{
2318 struct detailed_mode_closure *closure = c;
2319 struct drm_display_mode *newmode;
2320
2321 if (timing->pixel_clock) {
2322 newmode = drm_mode_detailed(closure->connector->dev,
2323 closure->edid, timing,
2324 closure->quirks);
2325 if (!newmode)
2326 return;
2327
2328 if (closure->preferred)
2329 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2330
2331 drm_mode_probed_add(closure->connector, newmode);
2332 closure->modes++;
2333 closure->preferred = 0;
882f0219 2334 }
13931579 2335}
882f0219 2336
13931579
AJ		 2337/*
2338 * add_detailed_modes - Add modes from detailed timings
2339 * @connector: attached connector
2340 * @edid: EDID block to scan
2341 * @quirks: quirks to apply
2342 */
2343static int
2344add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2345 u32 quirks)
2346{
2347 struct detailed_mode_closure closure = {
2348 connector,
2349 edid,
2350 1,
2351 quirks,
2352 0
2353 };
2354
2355 if (closure.preferred && !version_greater(edid, 1, 3))
2356 closure.preferred =
2357 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2358
2359 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2360
2361 return closure.modes;
882f0219 2362}
f453ba04 2363
8fe9790d 2364#define AUDIO_BLOCK 0x01
54ac76f8 2365#define VIDEO_BLOCK 0x02
f23c20c8 2366#define VENDOR_BLOCK 0x03
76adaa34 2367#define SPEAKER_BLOCK 0x04
b1edd6a6 2368#define VIDEO_CAPABILITY_BLOCK 0x07
8fe9790d 2369#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2370#define EDID_CEA_YCRCB444 (1 << 5)
2371#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2372#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2373
d4e4a31d 2374/*
8fe9790d 2375 * Search EDID for CEA extension block.
f23c20c8 2376 */
d4e4a31d 2377static u8 *drm_find_cea_extension(struct edid *edid)
f23c20c8 2378{
8fe9790d
ZW		 2379 u8 *edid_ext = NULL;
2380 int i;
f23c20c8
ML		 2381
2382 /* No EDID or EDID extensions */
2383 if (edid == NULL || edid->extensions == 0)
8fe9790d 2384 return NULL;
f23c20c8 2385
f23c20c8 2386 /* Find CEA extension */
7466f4cc 2387 for (i = 0; i < edid->extensions; i++) {
8fe9790d
ZW		 2388 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2389 if (edid_ext[0] == CEA_EXT)
f23c20c8
ML		 2390 break;
2391 }
2392
7466f4cc 2393 if (i == edid->extensions)
8fe9790d
ZW		 2394 return NULL;
2395
2396 return edid_ext;
2397}
2398
e6e79209
VS		 2399/*
2400 * Calculate the alternate clock for the CEA mode
2401 * (60Hz vs. 59.94Hz etc.)
2402 */
2403static unsigned int
2404cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2405{
2406 unsigned int clock = cea_mode->clock;
2407
2408 if (cea_mode->vrefresh % 6 != 0)
2409 return clock;
2410
2411 /*
2412 * edid_cea_modes contains the 59.94Hz
2413 * variant for 240 and 480 line modes,
2414 * and the 60Hz variant otherwise.
2415 */
2416 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2417 clock = clock * 1001 / 1000;
2418 else
2419 clock = DIV_ROUND_UP(clock * 1000, 1001);
2420
2421 return clock;
2422}
2423
18316c8c
TR		 2424/**
2425 * drm_match_cea_mode - look for a CEA mode matching given mode
2426 * @to_match: display mode
2427 *
2428 * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2429 * mode.
a4799037 2430 */
18316c8c 2431u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2432{
a4799037
SM		 2433 u8 mode;
2434
a90b590e
VS		 2435 if (!to_match->clock)
2436 return 0;
2437
a6b21831 2438 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
a90b590e
VS		 2439 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
2440 unsigned int clock1, clock2;
2441
a90b590e 2442 /* Check both 60Hz and 59.94Hz */
e6e79209
VS		 2443 clock1 = cea_mode->clock;
2444 clock2 = cea_mode_alternate_clock(cea_mode);
a4799037 2445
a90b590e
VS		 2446 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2447 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2448 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
a4799037
SM		 2449 return mode + 1;
2450 }
2451 return 0;
2452}
2453EXPORT_SYMBOL(drm_match_cea_mode);
2454
3f2f6533
LD		 2455/*
2456 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2457 * specific block).
2458 *
2459 * It's almost like cea_mode_alternate_clock(), we just need to add an
2460 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2461 * one.
2462 */
2463static unsigned int
2464hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2465{
2466 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2467 return hdmi_mode->clock;
2468
2469 return cea_mode_alternate_clock(hdmi_mode);
2470}
2471
2472/*
2473 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2474 * @to_match: display mode
2475 *
2476 * An HDMI mode is one defined in the HDMI vendor specific block.
2477 *
2478 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2479 */
2480static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2481{
2482 u8 mode;
2483
2484 if (!to_match->clock)
2485 return 0;
2486
2487 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
2488 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
2489 unsigned int clock1, clock2;
2490
2491 /* Make sure to also match alternate clocks */
2492 clock1 = hdmi_mode->clock;
2493 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2494
2495 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2496 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2497 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3f2f6533
LD		 2498 return mode + 1;
2499 }
2500 return 0;
2501}
2502
e6e79209
VS		 2503static int
2504add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2505{
2506 struct drm_device *dev = connector->dev;
2507 struct drm_display_mode *mode, *tmp;
2508 LIST_HEAD(list);
2509 int modes = 0;
2510
2511 /* Don't add CEA modes if the CEA extension block is missing */
2512 if (!drm_find_cea_extension(edid))
2513 return 0;
2514
2515 /*
2516 * Go through all probed modes and create a new mode
2517 * with the alternate clock for certain CEA modes.
2518 */
2519 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 2520 const struct drm_display_mode *cea_mode = NULL;
e6e79209 2521 struct drm_display_mode *newmode;
3f2f6533 2522 u8 mode_idx = drm_match_cea_mode(mode) - 1;
e6e79209
VS		 2523 unsigned int clock1, clock2;
2524
3f2f6533
LD		 2525 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
2526 cea_mode = &edid_cea_modes[mode_idx];
2527 clock2 = cea_mode_alternate_clock(cea_mode);
2528 } else {
2529 mode_idx = drm_match_hdmi_mode(mode) - 1;
2530 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
2531 cea_mode = &edid_4k_modes[mode_idx];
2532 clock2 = hdmi_mode_alternate_clock(cea_mode);
2533 }
2534 }
e6e79209 2535
3f2f6533
LD		 2536 if (!cea_mode)
2537 continue;
e6e79209
VS		 2538
2539 clock1 = cea_mode->clock;
e6e79209
VS		 2540
2541 if (clock1 == clock2)
2542 continue;
2543
2544 if (mode->clock != clock1 && mode->clock != clock2)
2545 continue;
2546
2547 newmode = drm_mode_duplicate(dev, cea_mode);
2548 if (!newmode)
2549 continue;
2550
27130212
DL		 2551 /* Carry over the stereo flags */
2552 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2553
e6e79209
VS		 2554 /*
2555 * The current mode could be either variant. Make
2556 * sure to pick the "other" clock for the new mode.
2557 */
2558 if (mode->clock != clock1)
2559 newmode->clock = clock1;
2560 else
2561 newmode->clock = clock2;
2562
2563 list_add_tail(&newmode->head, &list);
2564 }
2565
2566 list_for_each_entry_safe(mode, tmp, &list, head) {
2567 list_del(&mode->head);
2568 drm_mode_probed_add(connector, mode);
2569 modes++;
2570 }
2571
2572 return modes;
2573}
a4799037 2574
aff04ace
TW		 2575static struct drm_display_mode *
2576drm_display_mode_from_vic_index(struct drm_connector *connector,
2577 const u8 *video_db, u8 video_len,
2578 u8 video_index)
54ac76f8
CS		 2579{
2580 struct drm_device *dev = connector->dev;
aff04ace 2581 struct drm_display_mode *newmode;
13ac3f55 2582 u8 cea_mode;
54ac76f8 2583
aff04ace
TW		 2584 if (video_db == NULL || video_index >= video_len)
2585 return NULL;
2586
2587 /* CEA modes are numbered 1..127 */
2588 cea_mode = (video_db[video_index] & 127) - 1;
2589 if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
2590 return NULL;
2591
2592 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
409bbf1e
DL		 2593 if (!newmode)
2594 return NULL;
2595
aff04ace
TW		 2596 newmode->vrefresh = 0;
2597
2598 return newmode;
2599}
2600
2601static int
2602do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2603{
2604 int i, modes = 0;
2605
2606 for (i = 0; i < len; i++) {
2607 struct drm_display_mode *mode;
2608 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2609 if (mode) {
2610 drm_mode_probed_add(connector, mode);
2611 modes++;
54ac76f8
CS		 2612 }
2613 }
2614
2615 return modes;
2616}
2617
c858cfca
DL		 2618struct stereo_mandatory_mode {
2619 int width, height, vrefresh;
2620 unsigned int flags;
2621};
2622
2623static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 2624 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2625 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 2626 { 1920, 1080, 50,
2627 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2628 { 1920, 1080, 60,
2629 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 2630 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2631 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2632 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2633 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 2634};
2635
2636static bool
2637stereo_match_mandatory(const struct drm_display_mode *mode,
2638 const struct stereo_mandatory_mode *stereo_mode)
2639{
2640 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2641
2642 return mode->hdisplay == stereo_mode->width &&
2643 mode->vdisplay == stereo_mode->height &&
2644 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2645 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2646}
2647
c858cfca
DL		 2648static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2649{
2650 struct drm_device *dev = connector->dev;
2651 const struct drm_display_mode *mode;
2652 struct list_head stereo_modes;
f7e121b7 2653 int modes = 0, i;
c858cfca
DL		 2654
2655 INIT_LIST_HEAD(&stereo_modes);
2656
2657 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 2658 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2659 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 2660 struct drm_display_mode *new_mode;
2661
f7e121b7
DL		 2662 if (!stereo_match_mandatory(mode,
2663 &stereo_mandatory_modes[i]))
2664 continue;
c858cfca 2665
f7e121b7 2666 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 2667 new_mode = drm_mode_duplicate(dev, mode);
2668 if (!new_mode)
2669 continue;
2670
f7e121b7 2671 new_mode->flags |= mandatory->flags;
c858cfca
DL		 2672 list_add_tail(&new_mode->head, &stereo_modes);
2673 modes++;
f7e121b7 2674 }
c858cfca
DL		 2675 }
2676
2677 list_splice_tail(&stereo_modes, &connector->probed_modes);
2678
2679 return modes;
2680}
2681
1deee8d7
DL		 2682static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2683{
2684 struct drm_device *dev = connector->dev;
2685 struct drm_display_mode *newmode;
2686
2687 vic--; /* VICs start at 1 */
2688 if (vic >= ARRAY_SIZE(edid_4k_modes)) {
2689 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2690 return 0;
2691 }
2692
2693 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2694 if (!newmode)
2695 return 0;
2696
2697 drm_mode_probed_add(connector, newmode);
2698
2699 return 1;
2700}
2701
fbf46025
TW		 2702static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2703 const u8 *video_db, u8 video_len, u8 video_index)
2704{
fbf46025
TW		 2705 struct drm_display_mode *newmode;
2706 int modes = 0;
fbf46025
TW		 2707
2708 if (structure & (1 << 0)) {
aff04ace
TW		 2709 newmode = drm_display_mode_from_vic_index(connector, video_db,
2710 video_len,
2711 video_index);
fbf46025
TW		 2712 if (newmode) {
2713 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2714 drm_mode_probed_add(connector, newmode);
2715 modes++;
2716 }
2717 }
2718 if (structure & (1 << 6)) {
aff04ace
TW		 2719 newmode = drm_display_mode_from_vic_index(connector, video_db,
2720 video_len,
2721 video_index);
fbf46025
TW		 2722 if (newmode) {
2723 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2724 drm_mode_probed_add(connector, newmode);
2725 modes++;
2726 }
2727 }
2728 if (structure & (1 << 8)) {
aff04ace
TW		 2729 newmode = drm_display_mode_from_vic_index(connector, video_db,
2730 video_len,
2731 video_index);
fbf46025 2732 if (newmode) {
89570eeb 2733 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 2734 drm_mode_probed_add(connector, newmode);
2735 modes++;
2736 }
2737 }
2738
2739 return modes;
2740}
2741
7ebe1963
LD		 2742/*
2743 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2744 * @connector: connector corresponding to the HDMI sink
2745 * @db: start of the CEA vendor specific block
2746 * @len: length of the CEA block payload, ie. one can access up to db[len]
2747 *
c858cfca
DL		 2748 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2749 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 2750 */
2751static int
fbf46025
TW		 2752do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2753 const u8 *video_db, u8 video_len)
7ebe1963 2754{
0e5083aa 2755 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 2756 u8 vic_len, hdmi_3d_len = 0;
2757 u16 mask;
2758 u16 structure_all;
7ebe1963
LD		 2759
2760 if (len < 8)
2761 goto out;
2762
2763 /* no HDMI_Video_Present */
2764 if (!(db[8] & (1 << 5)))
2765 goto out;
2766
2767 /* Latency_Fields_Present */
2768 if (db[8] & (1 << 7))
2769 offset += 2;
2770
2771 /* I_Latency_Fields_Present */
2772 if (db[8] & (1 << 6))
2773 offset += 2;
2774
2775 /* the declared length is not long enough for the 2 first bytes
2776 * of additional video format capabilities */
c858cfca 2777 if (len < (8 + offset + 2))
7ebe1963
LD		 2778 goto out;
2779
c858cfca
DL		 2780 /* 3D_Present */
2781 offset++;
fbf46025 2782 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 2783 modes += add_hdmi_mandatory_stereo_modes(connector);
2784
fbf46025
TW		 2785 /* 3D_Multi_present */
2786 multi_present = (db[8 + offset] & 0x60) >> 5;
2787 }
2788
c858cfca 2789 offset++;
7ebe1963 2790 vic_len = db[8 + offset] >> 5;
fbf46025 2791 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 2792
2793 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 2794 u8 vic;
2795
2796 vic = db[9 + offset + i];
1deee8d7 2797 modes += add_hdmi_mode(connector, vic);
7ebe1963 2798 }
fbf46025
TW		 2799 offset += 1 + vic_len;
2800
0e5083aa
TW		 2801 if (multi_present == 1)
2802 multi_len = 2;
2803 else if (multi_present == 2)
2804 multi_len = 4;
2805 else
2806 multi_len = 0;
fbf46025 2807
0e5083aa 2808 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 2809 goto out;
2810
0e5083aa 2811 if (hdmi_3d_len < multi_len)
fbf46025
TW		 2812 goto out;
2813
0e5083aa
TW		 2814 if (multi_present == 1 || multi_present == 2) {
2815 /* 3D_Structure_ALL */
2816 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 2817
0e5083aa
TW		 2818 /* check if 3D_MASK is present */
2819 if (multi_present == 2)
2820 mask = (db[10 + offset] << 8) | db[11 + offset];
2821 else
2822 mask = 0xffff;
2823
2824 for (i = 0; i < 16; i++) {
2825 if (mask & (1 << i))
2826 modes += add_3d_struct_modes(connector,
2827 structure_all,
2828 video_db,
2829 video_len, i);
2830 }
2831 }
2832
2833 offset += multi_len;
2834
2835 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
2836 int vic_index;
2837 struct drm_display_mode *newmode = NULL;
2838 unsigned int newflag = 0;
2839 bool detail_present;
2840
2841 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
2842
2843 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
2844 break;
2845
2846 /* 2D_VIC_order_X */
2847 vic_index = db[8 + offset + i] >> 4;
2848
2849 /* 3D_Structure_X */
2850 switch (db[8 + offset + i] & 0x0f) {
2851 case 0:
2852 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
2853 break;
2854 case 6:
2855 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2856 break;
2857 case 8:
2858 /* 3D_Detail_X */
2859 if ((db[9 + offset + i] >> 4) == 1)
2860 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2861 break;
2862 }
2863
2864 if (newflag != 0) {
2865 newmode = drm_display_mode_from_vic_index(connector,
2866 video_db,
2867 video_len,
2868 vic_index);
2869
2870 if (newmode) {
2871 newmode->flags |= newflag;
2872 drm_mode_probed_add(connector, newmode);
2873 modes++;
2874 }
2875 }
2876
2877 if (detail_present)
2878 i++;
fbf46025 2879 }
7ebe1963
LD		 2880
2881out:
2882 return modes;
2883}
2884
9e50b9d5
VS		 2885static int
2886cea_db_payload_len(const u8 *db)
2887{
2888 return db[0] & 0x1f;
2889}
2890
2891static int
2892cea_db_tag(const u8 *db)
2893{
2894 return db[0] >> 5;
2895}
2896
2897static int
2898cea_revision(const u8 *cea)
2899{
2900 return cea[1];
2901}
2902
2903static int
2904cea_db_offsets(const u8 *cea, int *start, int *end)
2905{
2906 /* Data block offset in CEA extension block */
2907 *start = 4;
2908 *end = cea[2];
2909 if (*end == 0)
2910 *end = 127;
2911 if (*end < 4 || *end > 127)
2912 return -ERANGE;
2913 return 0;
2914}
2915
7ebe1963
LD		 2916static bool cea_db_is_hdmi_vsdb(const u8 *db)
2917{
2918 int hdmi_id;
2919
2920 if (cea_db_tag(db) != VENDOR_BLOCK)
2921 return false;
2922
2923 if (cea_db_payload_len(db) < 5)
2924 return false;
2925
2926 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
2927
6cb3b7f1 2928 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 2929}
2930
9e50b9d5
VS		 2931#define for_each_cea_db(cea, i, start, end) \
2932 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
2933
54ac76f8
CS		 2934static int
2935add_cea_modes(struct drm_connector *connector, struct edid *edid)
2936{
13ac3f55 2937 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 2938 const u8 *db, *hdmi = NULL, *video = NULL;
2939 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 2940 int modes = 0;
2941
9e50b9d5
VS		 2942 if (cea && cea_revision(cea) >= 3) {
2943 int i, start, end;
2944
2945 if (cea_db_offsets(cea, &start, &end))
2946 return 0;
2947
2948 for_each_cea_db(cea, i, start, end) {
2949 db = &cea[i];
2950 dbl = cea_db_payload_len(db);
2951
fbf46025
TW		 2952 if (cea_db_tag(db) == VIDEO_BLOCK) {
2953 video = db + 1;
2954 video_len = dbl;
2955 modes += do_cea_modes(connector, video, dbl);
2956 }
c858cfca
DL		 2957 else if (cea_db_is_hdmi_vsdb(db)) {
2958 hdmi = db;
2959 hdmi_len = dbl;
2960 }
54ac76f8
CS		 2961 }
2962 }
2963
c858cfca
DL		 2964 /*
2965 * We parse the HDMI VSDB after having added the cea modes as we will
2966 * be patching their flags when the sink supports stereo 3D.
2967 */
2968 if (hdmi)
fbf46025
TW		 2969 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
2970 video_len);
c858cfca 2971
54ac76f8
CS		 2972 return modes;
2973}
2974
76adaa34 2975static void
8504072a 2976parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
76adaa34 2977{
8504072a 2978 u8 len = cea_db_payload_len(db);
76adaa34 2979
8504072a
VS		 2980 if (len >= 6) {
2981 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
2982 connector->dvi_dual = db[6] & 1;
2983 }
2984 if (len >= 7)
2985 connector->max_tmds_clock = db[7] * 5;
2986 if (len >= 8) {
2987 connector->latency_present[0] = db[8] >> 7;
2988 connector->latency_present[1] = (db[8] >> 6) & 1;
2989 }
2990 if (len >= 9)
2991 connector->video_latency[0] = db[9];
2992 if (len >= 10)
2993 connector->audio_latency[0] = db[10];
2994 if (len >= 11)
2995 connector->video_latency[1] = db[11];
2996 if (len >= 12)
2997 connector->audio_latency[1] = db[12];
76adaa34 2998
670c1ef6 2999 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
76adaa34
WF		 3000 "max TMDS clock %d, "
3001 "latency present %d %d, "
3002 "video latency %d %d, "
3003 "audio latency %d %d\n",
3004 connector->dvi_dual,
3005 connector->max_tmds_clock,
3006 (int) connector->latency_present[0],
3007 (int) connector->latency_present[1],
3008 connector->video_latency[0],
3009 connector->video_latency[1],
3010 connector->audio_latency[0],
3011 connector->audio_latency[1]);
3012}
3013
3014static void
3015monitor_name(struct detailed_timing *t, void *data)
3016{
3017 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3018 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3019}
3020
76adaa34
WF		 3021/**
3022 * drm_edid_to_eld - build ELD from EDID
3023 * @connector: connector corresponding to the HDMI/DP sink
3024 * @edid: EDID to parse
3025 *
3026 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver.
3027 * Some ELD fields are left to the graphics driver caller:
3028 * - Conn_Type
3029 * - HDCP
3030 * - Port_ID
3031 */
3032void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3033{
3034 uint8_t *eld = connector->eld;
3035 u8 *cea;
3036 u8 *name;
3037 u8 *db;
3038 int sad_count = 0;
3039 int mnl;
3040 int dbl;
3041
3042 memset(eld, 0, sizeof(connector->eld));
3043
3044 cea = drm_find_cea_extension(edid);
3045 if (!cea) {
3046 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3047 return;
3048 }
3049
3050 name = NULL;
3051 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3052 for (mnl = 0; name && mnl < 13; mnl++) {
3053 if (name[mnl] == 0x0a)
3054 break;
3055 eld[20 + mnl] = name[mnl];
3056 }
3057 eld[4] = (cea[1] << 5) | mnl;
3058 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3059
3060 eld[0] = 2 << 3; /* ELD version: 2 */
3061
3062 eld[16] = edid->mfg_id[0];
3063 eld[17] = edid->mfg_id[1];
3064 eld[18] = edid->prod_code[0];
3065 eld[19] = edid->prod_code[1];
3066
9e50b9d5
VS		 3067 if (cea_revision(cea) >= 3) {
3068 int i, start, end;
3069
3070 if (cea_db_offsets(cea, &start, &end)) {
3071 start = 0;
3072 end = 0;
3073 }
3074
3075 for_each_cea_db(cea, i, start, end) {
3076 db = &cea[i];
3077 dbl = cea_db_payload_len(db);
3078
3079 switch (cea_db_tag(db)) {
a0ab734d
CS		 3080 case AUDIO_BLOCK:
3081 /* Audio Data Block, contains SADs */
3082 sad_count = dbl / 3;
9e50b9d5
VS		 3083 if (dbl >= 1)
3084 memcpy(eld + 20 + mnl, &db[1], dbl);
a0ab734d
CS		 3085 break;
3086 case SPEAKER_BLOCK:
9e50b9d5
VS		 3087 /* Speaker Allocation Data Block */
3088 if (dbl >= 1)
3089 eld[7] = db[1];
a0ab734d
CS		 3090 break;
3091 case VENDOR_BLOCK:
3092 /* HDMI Vendor-Specific Data Block */
14f77fdd 3093 if (cea_db_is_hdmi_vsdb(db))
a0ab734d
CS		 3094 parse_hdmi_vsdb(connector, db);
3095 break;
3096 default:
3097 break;
3098 }
76adaa34 3099 }
9e50b9d5 3100 }
76adaa34
WF		 3101 eld[5] |= sad_count << 4;
3102 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
3103
3104 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);
3105}
3106EXPORT_SYMBOL(drm_edid_to_eld);
3107
fe214163
RM		 3108/**
3109 * drm_edid_to_sad - extracts SADs from EDID
3110 * @edid: EDID to parse
3111 * @sads: pointer that will be set to the extracted SADs
3112 *
3113 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3114 * Note: returned pointer needs to be kfreed
3115 *
3116 * Return number of found SADs or negative number on error.
3117 */
3118int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3119{
3120 int count = 0;
3121 int i, start, end, dbl;
3122 u8 *cea;
3123
3124 cea = drm_find_cea_extension(edid);
3125 if (!cea) {
3126 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3127 return -ENOENT;
3128 }
3129
3130 if (cea_revision(cea) < 3) {
3131 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3132 return -ENOTSUPP;
3133 }
3134
3135 if (cea_db_offsets(cea, &start, &end)) {
3136 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3137 return -EPROTO;
3138 }
3139
3140 for_each_cea_db(cea, i, start, end) {
3141 u8 *db = &cea[i];
3142
3143 if (cea_db_tag(db) == AUDIO_BLOCK) {
3144 int j;
3145 dbl = cea_db_payload_len(db);
3146
3147 count = dbl / 3; /* SAD is 3B */
3148 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3149 if (!*sads)
3150 return -ENOMEM;
3151 for (j = 0; j < count; j++) {
3152 u8 *sad = &db[1 + j * 3];
3153
3154 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3155 (*sads)[j].channels = sad[0] & 0x7;
3156 (*sads)[j].freq = sad[1] & 0x7F;
3157 (*sads)[j].byte2 = sad[2];
3158 }
3159 break;
3160 }
3161 }
3162
3163 return count;
3164}
3165EXPORT_SYMBOL(drm_edid_to_sad);
3166
d105f476
AD		 3167/**
3168 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3169 * @edid: EDID to parse
3170 * @sadb: pointer to the speaker block
3171 *
3172 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3173 * Note: returned pointer needs to be kfreed
3174 *
3175 * Return number of found Speaker Allocation Blocks or negative number on error.
3176 */
3177int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3178{
3179 int count = 0;
3180 int i, start, end, dbl;
3181 const u8 *cea;
3182
3183 cea = drm_find_cea_extension(edid);
3184 if (!cea) {
3185 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3186 return -ENOENT;
3187 }
3188
3189 if (cea_revision(cea) < 3) {
3190 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3191 return -ENOTSUPP;
3192 }
3193
3194 if (cea_db_offsets(cea, &start, &end)) {
3195 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3196 return -EPROTO;
3197 }
3198
3199 for_each_cea_db(cea, i, start, end) {
3200 const u8 *db = &cea[i];
3201
3202 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3203 dbl = cea_db_payload_len(db);
3204
3205 /* Speaker Allocation Data Block */
3206 if (dbl == 3) {
3207 *sadb = kmalloc(dbl, GFP_KERNEL);
618e3776
AD		 3208 if (!*sadb)
3209 return -ENOMEM;
d105f476
AD		 3210 memcpy(*sadb, &db[1], dbl);
3211 count = dbl;
3212 break;
3213 }
3214 }
3215 }
3216
3217 return count;
3218}
3219EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3220
76adaa34
WF		 3221/**
3222 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond
3223 * @connector: connector associated with the HDMI/DP sink
3224 * @mode: the display mode
3225 */
3226int drm_av_sync_delay(struct drm_connector *connector,
3227 struct drm_display_mode *mode)
3228{
3229 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3230 int a, v;
3231
3232 if (!connector->latency_present[0])
3233 return 0;
3234 if (!connector->latency_present[1])
3235 i = 0;
3236
3237 a = connector->audio_latency[i];
3238 v = connector->video_latency[i];
3239
3240 /*
3241 * HDMI/DP sink doesn't support audio or video?
3242 */
3243 if (a == 255 || v == 255)
3244 return 0;
3245
3246 /*
3247 * Convert raw EDID values to millisecond.
3248 * Treat unknown latency as 0ms.
3249 */
3250 if (a)
3251 a = min(2 * (a - 1), 500);
3252 if (v)
3253 v = min(2 * (v - 1), 500);
3254
3255 return max(v - a, 0);
3256}
3257EXPORT_SYMBOL(drm_av_sync_delay);
3258
3259/**
3260 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3261 * @encoder: the encoder just changed display mode
3262 * @mode: the adjusted display mode
3263 *
3264 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3265 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3266 */
3267struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
3268 struct drm_display_mode *mode)
3269{
3270 struct drm_connector *connector;
3271 struct drm_device *dev = encoder->dev;
3272
3273 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
3274 if (connector->encoder == encoder && connector->eld[0])
3275 return connector;
3276
3277 return NULL;
3278}
3279EXPORT_SYMBOL(drm_select_eld);
3280
8fe9790d
ZW		 3281/**
3282 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
3283 * @edid: monitor EDID information
3284 *
3285 * Parse the CEA extension according to CEA-861-B.
3286 * Return true if HDMI, false if not or unknown.
3287 */
3288bool drm_detect_hdmi_monitor(struct edid *edid)
3289{
3290 u8 *edid_ext;
14f77fdd 3291 int i;
8fe9790d 3292 int start_offset, end_offset;
8fe9790d
ZW		 3293
3294 edid_ext = drm_find_cea_extension(edid);
3295 if (!edid_ext)
14f77fdd 3296 return false;
f23c20c8 3297
9e50b9d5 3298 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 3299 return false;
f23c20c8
ML		 3300
3301 /*
3302 * Because HDMI identifier is in Vendor Specific Block,
3303 * search it from all data blocks of CEA extension.
3304 */
9e50b9d5 3305 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 3306 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3307 return true;
f23c20c8
ML		 3308 }
3309
14f77fdd 3310 return false;
f23c20c8
ML		 3311}
3312EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3313
8fe9790d
ZW		 3314/**
3315 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 3316 * @edid: EDID block to scan
8fe9790d
ZW		 3317 *
3318 * Monitor should have CEA extension block.
3319 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3320 * audio' only. If there is any audio extension block and supported
3321 * audio format, assume at least 'basic audio' support, even if 'basic
3322 * audio' is not defined in EDID.
3323 *
3324 */
3325bool drm_detect_monitor_audio(struct edid *edid)
3326{
3327 u8 *edid_ext;
3328 int i, j;
3329 bool has_audio = false;
3330 int start_offset, end_offset;
3331
3332 edid_ext = drm_find_cea_extension(edid);
3333 if (!edid_ext)
3334 goto end;
3335
3336 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3337
3338 if (has_audio) {
3339 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3340 goto end;
3341 }
3342
9e50b9d5
VS		 3343 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3344 goto end;
8fe9790d 3345
9e50b9d5
VS		 3346 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3347 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 3348 has_audio = true;
9e50b9d5 3349 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 3350 DRM_DEBUG_KMS("CEA audio format %d\n",
3351 (edid_ext[i + j] >> 3) & 0xf);
3352 goto end;
3353 }
3354 }
3355end:
3356 return has_audio;
3357}
3358EXPORT_SYMBOL(drm_detect_monitor_audio);
3359
b1edd6a6
VS		 3360/**
3361 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 3362 * @edid: EDID block to scan
b1edd6a6
VS		 3363 *
3364 * Check whether the monitor reports the RGB quantization range selection
3365 * as supported. The AVI infoframe can then be used to inform the monitor
3366 * which quantization range (full or limited) is used.
3367 */
3368bool drm_rgb_quant_range_selectable(struct edid *edid)
3369{
3370 u8 *edid_ext;
3371 int i, start, end;
3372
3373 edid_ext = drm_find_cea_extension(edid);
3374 if (!edid_ext)
3375 return false;
3376
3377 if (cea_db_offsets(edid_ext, &start, &end))
3378 return false;
3379
3380 for_each_cea_db(edid_ext, i, start, end) {
3381 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3382 cea_db_payload_len(&edid_ext[i]) == 2) {
3383 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3384 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3385 }
3386 }
3387
3388 return false;
3389}
3390EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3391
3b11228b
JB		 3392/**
3393 * drm_add_display_info - pull display info out if present
3394 * @edid: EDID data
3395 * @info: display info (attached to connector)
3396 *
3397 * Grab any available display info and stuff it into the drm_display_info
3398 * structure that's part of the connector. Useful for tracking bpp and
3399 * color spaces.
3400 */
3401static void drm_add_display_info(struct edid *edid,
3402 struct drm_display_info *info)
3403{
ebec9a7b
JB		 3404 u8 *edid_ext;
3405
3b11228b
JB		 3406 info->width_mm = edid->width_cm * 10;
3407 info->height_mm = edid->height_cm * 10;
3408
3409 /* driver figures it out in this case */
3410 info->bpc = 0;
da05a5a7 3411 info->color_formats = 0;
3b11228b 3412
a988bc72 3413 if (edid->revision < 3)
3b11228b
JB		 3414 return;
3415
3416 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3417 return;
3418
a988bc72
LPC		 3419 /* Get data from CEA blocks if present */
3420 edid_ext = drm_find_cea_extension(edid);
3421 if (edid_ext) {
3422 info->cea_rev = edid_ext[1];
3423
3424 /* The existence of a CEA block should imply RGB support */
3425 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3426 if (edid_ext[3] & EDID_CEA_YCRCB444)
3427 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3428 if (edid_ext[3] & EDID_CEA_YCRCB422)
3429 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3430 }
3431
3432 /* Only defined for 1.4 with digital displays */
3433 if (edid->revision < 4)
3434 return;
3435
3b11228b
JB		 3436 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3437 case DRM_EDID_DIGITAL_DEPTH_6:
3438 info->bpc = 6;
3439 break;
3440 case DRM_EDID_DIGITAL_DEPTH_8:
3441 info->bpc = 8;
3442 break;
3443 case DRM_EDID_DIGITAL_DEPTH_10:
3444 info->bpc = 10;
3445 break;
3446 case DRM_EDID_DIGITAL_DEPTH_12:
3447 info->bpc = 12;
3448 break;
3449 case DRM_EDID_DIGITAL_DEPTH_14:
3450 info->bpc = 14;
3451 break;
3452 case DRM_EDID_DIGITAL_DEPTH_16:
3453 info->bpc = 16;
3454 break;
3455 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3456 default:
3457 info->bpc = 0;
3458 break;
3459 }
da05a5a7 3460
a988bc72 3461 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 3462 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3463 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3464 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3465 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3b11228b
JB		 3466}
3467
f453ba04
DA		 3468/**
3469 * drm_add_edid_modes - add modes from EDID data, if available
3470 * @connector: connector we're probing
3471 * @edid: edid data
3472 *
3473 * Add the specified modes to the connector's mode list.
3474 *
3475 * Return number of modes added or 0 if we couldn't find any.
3476 */
3477int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3478{
3479 int num_modes = 0;
3480 u32 quirks;
3481
3482 if (edid == NULL) {
3483 return 0;
3484 }
3c537889 3485 if (!drm_edid_is_valid(edid)) {
dcdb1674 3486 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
f453ba04
DA		 3487 drm_get_connector_name(connector));
3488 return 0;
3489 }
3490
3491 quirks = edid_get_quirks(edid);
3492
c867df70
AJ		 3493 /*
3494 * EDID spec says modes should be preferred in this order:
3495 * - preferred detailed mode
3496 * - other detailed modes from base block
3497 * - detailed modes from extension blocks
3498 * - CVT 3-byte code modes
3499 * - standard timing codes
3500 * - established timing codes
3501 * - modes inferred from GTF or CVT range information
3502 *
13931579 3503 * We get this pretty much right.
c867df70
AJ		 3504 *
3505 * XXX order for additional mode types in extension blocks?
3506 */
13931579
AJ		 3507 num_modes += add_detailed_modes(connector, edid, quirks);
3508 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 3509 num_modes += add_standard_modes(connector, edid);
3510 num_modes += add_established_modes(connector, edid);
196e077d
PZ		 3511 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3512 num_modes += add_inferred_modes(connector, edid);
54ac76f8 3513 num_modes += add_cea_modes(connector, edid);
e6e79209 3514 num_modes += add_alternate_cea_modes(connector, edid);
f453ba04
DA		 3515
3516 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3517 edid_fixup_preferred(connector, quirks);
3518
3b11228b 3519 drm_add_display_info(edid, &connector->display_info);
f453ba04 3520
49d45a31
RM		 3521 if (quirks & EDID_QUIRK_FORCE_8BPC)
3522 connector->display_info.bpc = 8;
3523
f453ba04
DA		 3524 return num_modes;
3525}
3526EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 3527
3528/**
3529 * drm_add_modes_noedid - add modes for the connectors without EDID
3530 * @connector: connector we're probing
3531 * @hdisplay: the horizontal display limit
3532 * @vdisplay: the vertical display limit
3533 *
3534 * Add the specified modes to the connector's mode list. Only when the
3535 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3536 *
3537 * Return number of modes added or 0 if we couldn't find any.
3538 */
3539int drm_add_modes_noedid(struct drm_connector *connector,
3540 int hdisplay, int vdisplay)
3541{
3542 int i, count, num_modes = 0;
b1f559ec 3543 struct drm_display_mode *mode;
f0fda0a4
ZY		 3544 struct drm_device *dev = connector->dev;
3545
3546 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
3547 if (hdisplay < 0)
3548 hdisplay = 0;
3549 if (vdisplay < 0)
3550 vdisplay = 0;
3551
3552 for (i = 0; i < count; i++) {
b1f559ec 3553 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 3554 if (hdisplay && vdisplay) {
3555 /*
3556 * Only when two are valid, they will be used to check
3557 * whether the mode should be added to the mode list of
3558 * the connector.
3559 */
3560 if (ptr->hdisplay > hdisplay ||
3561 ptr->vdisplay > vdisplay)
3562 continue;
3563 }
f985dedb
AJ		 3564 if (drm_mode_vrefresh(ptr) > 61)
3565 continue;
f0fda0a4
ZY		 3566 mode = drm_mode_duplicate(dev, ptr);
3567 if (mode) {
3568 drm_mode_probed_add(connector, mode);
3569 num_modes++;
3570 }
3571 }
3572 return num_modes;
3573}
3574EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 3575
3cf70daf
GH		 3576void drm_set_preferred_mode(struct drm_connector *connector,
3577 int hpref, int vpref)
3578{
3579 struct drm_display_mode *mode;
3580
3581 list_for_each_entry(mode, &connector->probed_modes, head) {
9d3de138
DV		 3582 if (mode->hdisplay == hpref &&
3583 mode->vdisplay == vpref)
3cf70daf
GH		 3584 mode->type |= DRM_MODE_TYPE_PREFERRED;
3585 }
3586}
3587EXPORT_SYMBOL(drm_set_preferred_mode);
3588
10a85120
TR		 3589/**
3590 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
3591 * data from a DRM display mode
3592 * @frame: HDMI AVI infoframe
3593 * @mode: DRM display mode
3594 *
3595 * Returns 0 on success or a negative error code on failure.
3596 */
3597int
3598drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
3599 const struct drm_display_mode *mode)
3600{
3601 int err;
3602
3603 if (!frame || !mode)
3604 return -EINVAL;
3605
3606 err = hdmi_avi_infoframe_init(frame);
3607 if (err < 0)
3608 return err;
3609
bf02db99
DL		 3610 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
3611 frame->pixel_repeat = 1;
3612
10a85120 3613 frame->video_code = drm_match_cea_mode(mode);
10a85120
TR		 3614
3615 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
3616 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 3617 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 3618
3619 return 0;
3620}
3621EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 3622
4eed4a0a
DL		 3623static enum hdmi_3d_structure
3624s3d_structure_from_display_mode(const struct drm_display_mode *mode)
3625{
3626 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
3627
3628 switch (layout) {
3629 case DRM_MODE_FLAG_3D_FRAME_PACKING:
3630 return HDMI_3D_STRUCTURE_FRAME_PACKING;
3631 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
3632 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
3633 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
3634 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
3635 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
3636 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
3637 case DRM_MODE_FLAG_3D_L_DEPTH:
3638 return HDMI_3D_STRUCTURE_L_DEPTH;
3639 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
3640 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
3641 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
3642 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
3643 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
3644 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
3645 default:
3646 return HDMI_3D_STRUCTURE_INVALID;
3647 }
3648}
3649
83dd0008
LD		 3650/**
3651 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
3652 * data from a DRM display mode
3653 * @frame: HDMI vendor infoframe
3654 * @mode: DRM display mode
3655 *
3656 * Note that there's is a need to send HDMI vendor infoframes only when using a
3657 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
3658 * function will return -EINVAL, error that can be safely ignored.
3659 *
3660 * Returns 0 on success or a negative error code on failure.
3661 */
3662int
3663drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
3664 const struct drm_display_mode *mode)
3665{
3666 int err;
4eed4a0a 3667 u32 s3d_flags;
83dd0008
LD		 3668 u8 vic;
3669
3670 if (!frame || !mode)
3671 return -EINVAL;
3672
3673 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 3674 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
3675
3676 if (!vic && !s3d_flags)
3677 return -EINVAL;
3678
3679 if (vic && s3d_flags)
83dd0008
LD		 3680 return -EINVAL;
3681
3682 err = hdmi_vendor_infoframe_init(frame);
3683 if (err < 0)
3684 return err;
3685
4eed4a0a
DL		 3686 if (vic)
3687 frame->vic = vic;
3688 else
3689 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 3690
3691 return 0;
3692}
3693EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
Linux kernel - Deliverables
This page took 0.50258 seconds and 5 git commands to generate.