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e9474be4 JH |
1 | /* |
2 | * Samsung DP (Display port) register interface driver. | |
3 | * | |
4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. | |
5 | * Author: Jingoo Han <jg1.han@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/device.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
b8b52471 | 16 | #include <linux/gpio.h> |
e9474be4 | 17 | |
e9474be4 JH |
18 | #include "exynos_dp_core.h" |
19 | #include "exynos_dp_reg.h" | |
20 | ||
c30ffb90 SP |
21 | #define COMMON_INT_MASK_1 0 |
22 | #define COMMON_INT_MASK_2 0 | |
23 | #define COMMON_INT_MASK_3 0 | |
24 | #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) | |
25 | #define INT_STA_MASK INT_HPD | |
e9474be4 JH |
26 | |
27 | void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable) | |
28 | { | |
29 | u32 reg; | |
30 | ||
31 | if (enable) { | |
32 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
33 | reg |= HDCP_VIDEO_MUTE; | |
34 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
35 | } else { | |
36 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
37 | reg &= ~HDCP_VIDEO_MUTE; | |
38 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
39 | } | |
40 | } | |
41 | ||
42 | void exynos_dp_stop_video(struct exynos_dp_device *dp) | |
43 | { | |
44 | u32 reg; | |
45 | ||
46 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
47 | reg &= ~VIDEO_EN; | |
48 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
49 | } | |
50 | ||
51 | void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable) | |
52 | { | |
53 | u32 reg; | |
54 | ||
55 | if (enable) | |
56 | reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | | |
57 | LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; | |
58 | else | |
59 | reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | | |
60 | LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; | |
61 | ||
62 | writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); | |
63 | } | |
64 | ||
8affaf5c JH |
65 | void exynos_dp_init_analog_param(struct exynos_dp_device *dp) |
66 | { | |
67 | u32 reg; | |
68 | ||
69 | reg = TX_TERMINAL_CTRL_50_OHM; | |
70 | writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); | |
71 | ||
72 | reg = SEL_24M | TX_DVDD_BIT_1_0625V; | |
73 | writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); | |
74 | ||
75 | reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; | |
76 | writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); | |
77 | ||
78 | reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | | |
5fdc62ca | 79 | TX_CUR1_2X | TX_CUR_16_MA; |
8affaf5c JH |
80 | writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); |
81 | ||
82 | reg = CH3_AMP_400_MV | CH2_AMP_400_MV | | |
83 | CH1_AMP_400_MV | CH0_AMP_400_MV; | |
84 | writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); | |
85 | } | |
86 | ||
e9474be4 JH |
87 | void exynos_dp_init_interrupt(struct exynos_dp_device *dp) |
88 | { | |
89 | /* Set interrupt pin assertion polarity as high */ | |
2f85f97e | 90 | writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); |
e9474be4 JH |
91 | |
92 | /* Clear pending regisers */ | |
93 | writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); | |
94 | writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2); | |
95 | writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3); | |
96 | writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); | |
97 | writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA); | |
98 | ||
99 | /* 0:mask,1: unmask */ | |
100 | writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); | |
101 | writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); | |
102 | writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); | |
103 | writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); | |
104 | writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK); | |
105 | } | |
106 | ||
107 | void exynos_dp_reset(struct exynos_dp_device *dp) | |
108 | { | |
109 | u32 reg; | |
110 | ||
e9474be4 JH |
111 | exynos_dp_stop_video(dp); |
112 | exynos_dp_enable_video_mute(dp, 0); | |
113 | ||
114 | reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | | |
115 | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | | |
116 | HDCP_FUNC_EN_N | SW_FUNC_EN_N; | |
117 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); | |
118 | ||
119 | reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | | |
120 | SERDES_FIFO_FUNC_EN_N | | |
121 | LS_CLK_DOMAIN_FUNC_EN_N; | |
122 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
123 | ||
a2c81bc1 | 124 | usleep_range(20, 30); |
e9474be4 JH |
125 | |
126 | exynos_dp_lane_swap(dp, 0); | |
127 | ||
128 | writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); | |
129 | writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2); | |
130 | writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
131 | writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
132 | ||
133 | writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL); | |
134 | writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL); | |
135 | ||
136 | writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L); | |
137 | writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H); | |
138 | ||
139 | writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL); | |
140 | ||
141 | writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST); | |
142 | ||
143 | writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD); | |
144 | writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN); | |
145 | ||
146 | writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH); | |
147 | writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); | |
148 | ||
149 | writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); | |
e9474be4 JH |
150 | } |
151 | ||
24db03a8 JH |
152 | void exynos_dp_swreset(struct exynos_dp_device *dp) |
153 | { | |
154 | writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET); | |
155 | } | |
156 | ||
e9474be4 JH |
157 | void exynos_dp_config_interrupt(struct exynos_dp_device *dp) |
158 | { | |
159 | u32 reg; | |
160 | ||
161 | /* 0: mask, 1: unmask */ | |
162 | reg = COMMON_INT_MASK_1; | |
163 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); | |
164 | ||
165 | reg = COMMON_INT_MASK_2; | |
166 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); | |
167 | ||
168 | reg = COMMON_INT_MASK_3; | |
169 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); | |
170 | ||
171 | reg = COMMON_INT_MASK_4; | |
172 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); | |
173 | ||
174 | reg = INT_STA_MASK; | |
175 | writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); | |
176 | } | |
177 | ||
09d00d17 | 178 | enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp) |
e9474be4 JH |
179 | { |
180 | u32 reg; | |
181 | ||
182 | reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); | |
183 | if (reg & PLL_LOCK) | |
184 | return PLL_LOCKED; | |
185 | else | |
186 | return PLL_UNLOCKED; | |
187 | } | |
188 | ||
189 | void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable) | |
190 | { | |
191 | u32 reg; | |
192 | ||
193 | if (enable) { | |
194 | reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); | |
195 | reg |= DP_PLL_PD; | |
196 | writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); | |
197 | } else { | |
198 | reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); | |
199 | reg &= ~DP_PLL_PD; | |
200 | writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); | |
201 | } | |
202 | } | |
203 | ||
204 | void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, | |
205 | enum analog_power_block block, | |
206 | bool enable) | |
207 | { | |
208 | u32 reg; | |
209 | ||
210 | switch (block) { | |
211 | case AUX_BLOCK: | |
212 | if (enable) { | |
213 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
214 | reg |= AUX_PD; | |
215 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
216 | } else { | |
217 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
218 | reg &= ~AUX_PD; | |
219 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
220 | } | |
221 | break; | |
222 | case CH0_BLOCK: | |
223 | if (enable) { | |
224 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
225 | reg |= CH0_PD; | |
226 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
227 | } else { | |
228 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
229 | reg &= ~CH0_PD; | |
230 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
231 | } | |
232 | break; | |
233 | case CH1_BLOCK: | |
234 | if (enable) { | |
235 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
236 | reg |= CH1_PD; | |
237 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
238 | } else { | |
239 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
240 | reg &= ~CH1_PD; | |
241 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
242 | } | |
243 | break; | |
244 | case CH2_BLOCK: | |
245 | if (enable) { | |
246 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
247 | reg |= CH2_PD; | |
248 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
249 | } else { | |
250 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
251 | reg &= ~CH2_PD; | |
252 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
253 | } | |
254 | break; | |
255 | case CH3_BLOCK: | |
256 | if (enable) { | |
257 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
258 | reg |= CH3_PD; | |
259 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
260 | } else { | |
261 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
262 | reg &= ~CH3_PD; | |
263 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
264 | } | |
265 | break; | |
266 | case ANALOG_TOTAL: | |
267 | if (enable) { | |
268 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
269 | reg |= DP_PHY_PD; | |
270 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
271 | } else { | |
272 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); | |
273 | reg &= ~DP_PHY_PD; | |
274 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
275 | } | |
276 | break; | |
277 | case POWER_ALL: | |
278 | if (enable) { | |
279 | reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | | |
280 | CH1_PD | CH0_PD; | |
281 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); | |
282 | } else { | |
283 | writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD); | |
284 | } | |
285 | break; | |
286 | default: | |
287 | break; | |
288 | } | |
289 | } | |
290 | ||
291 | void exynos_dp_init_analog_func(struct exynos_dp_device *dp) | |
292 | { | |
293 | u32 reg; | |
b5cfeed6 | 294 | int timeout_loop = 0; |
e9474be4 JH |
295 | |
296 | exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); | |
297 | ||
298 | reg = PLL_LOCK_CHG; | |
299 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); | |
300 | ||
301 | reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); | |
302 | reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); | |
303 | writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); | |
304 | ||
305 | /* Power up PLL */ | |
b5cfeed6 | 306 | if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
e9474be4 JH |
307 | exynos_dp_set_pll_power_down(dp, 0); |
308 | ||
b5cfeed6 JH |
309 | while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
310 | timeout_loop++; | |
311 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { | |
312 | dev_err(dp->dev, "failed to get pll lock status\n"); | |
313 | return; | |
314 | } | |
315 | usleep_range(10, 20); | |
316 | } | |
317 | } | |
318 | ||
e9474be4 JH |
319 | /* Enable Serdes FIFO function and Link symbol clock domain module */ |
320 | reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
321 | reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | |
322 | | AUX_FUNC_EN_N); | |
323 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
324 | } | |
325 | ||
c30ffb90 | 326 | void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp) |
e9474be4 JH |
327 | { |
328 | u32 reg; | |
329 | ||
b8b52471 AB |
330 | if (gpio_is_valid(dp->hpd_gpio)) |
331 | return; | |
332 | ||
e9474be4 JH |
333 | reg = HOTPLUG_CHG | HPD_LOST | PLUG; |
334 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); | |
335 | ||
336 | reg = INT_HPD; | |
337 | writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); | |
c30ffb90 SP |
338 | } |
339 | ||
340 | void exynos_dp_init_hpd(struct exynos_dp_device *dp) | |
341 | { | |
342 | u32 reg; | |
343 | ||
b8b52471 AB |
344 | if (gpio_is_valid(dp->hpd_gpio)) |
345 | return; | |
346 | ||
c30ffb90 | 347 | exynos_dp_clear_hotplug_interrupts(dp); |
e9474be4 JH |
348 | |
349 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
350 | reg &= ~(F_HPD | HPD_CTRL); | |
351 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
352 | } | |
353 | ||
c30ffb90 SP |
354 | enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp) |
355 | { | |
356 | u32 reg; | |
357 | ||
b8b52471 AB |
358 | if (gpio_is_valid(dp->hpd_gpio)) { |
359 | reg = gpio_get_value(dp->hpd_gpio); | |
360 | if (reg) | |
361 | return DP_IRQ_TYPE_HP_CABLE_IN; | |
362 | else | |
363 | return DP_IRQ_TYPE_HP_CABLE_OUT; | |
364 | } else { | |
365 | /* Parse hotplug interrupt status register */ | |
366 | reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); | |
c30ffb90 | 367 | |
b8b52471 AB |
368 | if (reg & PLUG) |
369 | return DP_IRQ_TYPE_HP_CABLE_IN; | |
c30ffb90 | 370 | |
b8b52471 AB |
371 | if (reg & HPD_LOST) |
372 | return DP_IRQ_TYPE_HP_CABLE_OUT; | |
c30ffb90 | 373 | |
b8b52471 AB |
374 | if (reg & HOTPLUG_CHG) |
375 | return DP_IRQ_TYPE_HP_CHANGE; | |
c30ffb90 | 376 | |
b8b52471 AB |
377 | return DP_IRQ_TYPE_UNKNOWN; |
378 | } | |
c30ffb90 SP |
379 | } |
380 | ||
e9474be4 JH |
381 | void exynos_dp_reset_aux(struct exynos_dp_device *dp) |
382 | { | |
383 | u32 reg; | |
384 | ||
385 | /* Disable AUX channel module */ | |
386 | reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
387 | reg |= AUX_FUNC_EN_N; | |
388 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
389 | } | |
390 | ||
391 | void exynos_dp_init_aux(struct exynos_dp_device *dp) | |
392 | { | |
393 | u32 reg; | |
394 | ||
395 | /* Clear inerrupts related to AUX channel */ | |
396 | reg = RPLY_RECEIV | AUX_ERR; | |
397 | writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); | |
398 | ||
399 | exynos_dp_reset_aux(dp); | |
400 | ||
401 | /* Disable AUX transaction H/W retry */ | |
402 | reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)| | |
403 | AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; | |
7a80ec79 | 404 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL); |
e9474be4 JH |
405 | |
406 | /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ | |
407 | reg = DEFER_CTRL_EN | DEFER_COUNT(1); | |
408 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); | |
409 | ||
410 | /* Enable AUX channel module */ | |
411 | reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
412 | reg &= ~AUX_FUNC_EN_N; | |
413 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); | |
414 | } | |
415 | ||
416 | int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp) | |
417 | { | |
418 | u32 reg; | |
419 | ||
b8b52471 AB |
420 | if (gpio_is_valid(dp->hpd_gpio)) { |
421 | if (gpio_get_value(dp->hpd_gpio)) | |
422 | return 0; | |
423 | } else { | |
424 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
425 | if (reg & HPD_STATUS) | |
426 | return 0; | |
427 | } | |
e9474be4 JH |
428 | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
432 | void exynos_dp_enable_sw_function(struct exynos_dp_device *dp) | |
433 | { | |
434 | u32 reg; | |
435 | ||
436 | reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); | |
437 | reg &= ~SW_FUNC_EN_N; | |
438 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); | |
439 | } | |
440 | ||
441 | int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp) | |
442 | { | |
443 | int reg; | |
444 | int retval = 0; | |
bada5537 | 445 | int timeout_loop = 0; |
e9474be4 JH |
446 | |
447 | /* Enable AUX CH operation */ | |
448 | reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); | |
449 | reg |= AUX_EN; | |
450 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); | |
451 | ||
452 | /* Is AUX CH command reply received? */ | |
453 | reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); | |
bada5537 JH |
454 | while (!(reg & RPLY_RECEIV)) { |
455 | timeout_loop++; | |
456 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { | |
457 | dev_err(dp->dev, "AUX CH command reply failed!\n"); | |
458 | return -ETIMEDOUT; | |
459 | } | |
e9474be4 | 460 | reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); |
bada5537 JH |
461 | usleep_range(10, 11); |
462 | } | |
e9474be4 JH |
463 | |
464 | /* Clear interrupt source for AUX CH command reply */ | |
465 | writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); | |
466 | ||
467 | /* Clear interrupt source for AUX CH access error */ | |
468 | reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); | |
469 | if (reg & AUX_ERR) { | |
470 | writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA); | |
471 | return -EREMOTEIO; | |
472 | } | |
473 | ||
474 | /* Check AUX CH error access status */ | |
475 | reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA); | |
476 | if ((reg & AUX_STATUS_MASK) != 0) { | |
477 | dev_err(dp->dev, "AUX CH error happens: %d\n\n", | |
478 | reg & AUX_STATUS_MASK); | |
479 | return -EREMOTEIO; | |
480 | } | |
481 | ||
482 | return retval; | |
483 | } | |
484 | ||
485 | int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, | |
486 | unsigned int reg_addr, | |
487 | unsigned char data) | |
488 | { | |
489 | u32 reg; | |
490 | int i; | |
491 | int retval; | |
492 | ||
493 | for (i = 0; i < 3; i++) { | |
494 | /* Clear AUX CH data buffer */ | |
495 | reg = BUF_CLR; | |
496 | writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); | |
497 | ||
498 | /* Select DPCD device address */ | |
499 | reg = AUX_ADDR_7_0(reg_addr); | |
500 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); | |
501 | reg = AUX_ADDR_15_8(reg_addr); | |
502 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); | |
503 | reg = AUX_ADDR_19_16(reg_addr); | |
504 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); | |
505 | ||
506 | /* Write data buffer */ | |
507 | reg = (unsigned int)data; | |
508 | writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); | |
509 | ||
510 | /* | |
511 | * Set DisplayPort transaction and write 1 byte | |
512 | * If bit 3 is 1, DisplayPort transaction. | |
513 | * If Bit 3 is 0, I2C transaction. | |
514 | */ | |
515 | reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; | |
516 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); | |
517 | ||
518 | /* Start AUX transaction */ | |
519 | retval = exynos_dp_start_aux_transaction(dp); | |
520 | if (retval == 0) | |
521 | break; | |
522 | else | |
8fefbb75 SP |
523 | dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", |
524 | __func__); | |
e9474be4 JH |
525 | } |
526 | ||
527 | return retval; | |
528 | } | |
529 | ||
530 | int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, | |
531 | unsigned int reg_addr, | |
532 | unsigned char *data) | |
533 | { | |
534 | u32 reg; | |
535 | int i; | |
536 | int retval; | |
537 | ||
99f54152 | 538 | for (i = 0; i < 3; i++) { |
e9474be4 JH |
539 | /* Clear AUX CH data buffer */ |
540 | reg = BUF_CLR; | |
541 | writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); | |
542 | ||
543 | /* Select DPCD device address */ | |
544 | reg = AUX_ADDR_7_0(reg_addr); | |
545 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); | |
546 | reg = AUX_ADDR_15_8(reg_addr); | |
547 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); | |
548 | reg = AUX_ADDR_19_16(reg_addr); | |
549 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); | |
550 | ||
551 | /* | |
552 | * Set DisplayPort transaction and read 1 byte | |
553 | * If bit 3 is 1, DisplayPort transaction. | |
554 | * If Bit 3 is 0, I2C transaction. | |
555 | */ | |
556 | reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; | |
557 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); | |
558 | ||
559 | /* Start AUX transaction */ | |
560 | retval = exynos_dp_start_aux_transaction(dp); | |
561 | if (retval == 0) | |
562 | break; | |
563 | else | |
8fefbb75 SP |
564 | dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", |
565 | __func__); | |
e9474be4 JH |
566 | } |
567 | ||
568 | /* Read data buffer */ | |
569 | reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); | |
570 | *data = (unsigned char)(reg & 0xff); | |
571 | ||
572 | return retval; | |
573 | } | |
574 | ||
575 | int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, | |
576 | unsigned int reg_addr, | |
577 | unsigned int count, | |
578 | unsigned char data[]) | |
579 | { | |
580 | u32 reg; | |
581 | unsigned int start_offset; | |
582 | unsigned int cur_data_count; | |
583 | unsigned int cur_data_idx; | |
584 | int i; | |
585 | int retval = 0; | |
586 | ||
587 | /* Clear AUX CH data buffer */ | |
588 | reg = BUF_CLR; | |
589 | writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); | |
590 | ||
591 | start_offset = 0; | |
592 | while (start_offset < count) { | |
593 | /* Buffer size of AUX CH is 16 * 4bytes */ | |
594 | if ((count - start_offset) > 16) | |
595 | cur_data_count = 16; | |
596 | else | |
597 | cur_data_count = count - start_offset; | |
598 | ||
99f54152 | 599 | for (i = 0; i < 3; i++) { |
e9474be4 JH |
600 | /* Select DPCD device address */ |
601 | reg = AUX_ADDR_7_0(reg_addr + start_offset); | |
602 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); | |
603 | reg = AUX_ADDR_15_8(reg_addr + start_offset); | |
604 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); | |
605 | reg = AUX_ADDR_19_16(reg_addr + start_offset); | |
606 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); | |
607 | ||
608 | for (cur_data_idx = 0; cur_data_idx < cur_data_count; | |
609 | cur_data_idx++) { | |
610 | reg = data[start_offset + cur_data_idx]; | |
611 | writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 | |
612 | + 4 * cur_data_idx); | |
613 | } | |
614 | ||
615 | /* | |
616 | * Set DisplayPort transaction and write | |
617 | * If bit 3 is 1, DisplayPort transaction. | |
618 | * If Bit 3 is 0, I2C transaction. | |
619 | */ | |
620 | reg = AUX_LENGTH(cur_data_count) | | |
621 | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; | |
622 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); | |
623 | ||
624 | /* Start AUX transaction */ | |
625 | retval = exynos_dp_start_aux_transaction(dp); | |
626 | if (retval == 0) | |
627 | break; | |
628 | else | |
8fefbb75 SP |
629 | dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", |
630 | __func__); | |
e9474be4 JH |
631 | } |
632 | ||
633 | start_offset += cur_data_count; | |
634 | } | |
635 | ||
636 | return retval; | |
637 | } | |
638 | ||
639 | int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, | |
640 | unsigned int reg_addr, | |
641 | unsigned int count, | |
642 | unsigned char data[]) | |
643 | { | |
644 | u32 reg; | |
645 | unsigned int start_offset; | |
646 | unsigned int cur_data_count; | |
647 | unsigned int cur_data_idx; | |
648 | int i; | |
649 | int retval = 0; | |
650 | ||
651 | /* Clear AUX CH data buffer */ | |
652 | reg = BUF_CLR; | |
653 | writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); | |
654 | ||
655 | start_offset = 0; | |
656 | while (start_offset < count) { | |
657 | /* Buffer size of AUX CH is 16 * 4bytes */ | |
658 | if ((count - start_offset) > 16) | |
659 | cur_data_count = 16; | |
660 | else | |
661 | cur_data_count = count - start_offset; | |
662 | ||
663 | /* AUX CH Request Transaction process */ | |
99f54152 | 664 | for (i = 0; i < 3; i++) { |
e9474be4 JH |
665 | /* Select DPCD device address */ |
666 | reg = AUX_ADDR_7_0(reg_addr + start_offset); | |
667 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); | |
668 | reg = AUX_ADDR_15_8(reg_addr + start_offset); | |
669 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); | |
670 | reg = AUX_ADDR_19_16(reg_addr + start_offset); | |
671 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); | |
672 | ||
673 | /* | |
674 | * Set DisplayPort transaction and read | |
675 | * If bit 3 is 1, DisplayPort transaction. | |
676 | * If Bit 3 is 0, I2C transaction. | |
677 | */ | |
678 | reg = AUX_LENGTH(cur_data_count) | | |
679 | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; | |
680 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); | |
681 | ||
682 | /* Start AUX transaction */ | |
683 | retval = exynos_dp_start_aux_transaction(dp); | |
684 | if (retval == 0) | |
685 | break; | |
686 | else | |
8fefbb75 SP |
687 | dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", |
688 | __func__); | |
e9474be4 JH |
689 | } |
690 | ||
691 | for (cur_data_idx = 0; cur_data_idx < cur_data_count; | |
692 | cur_data_idx++) { | |
693 | reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 | |
694 | + 4 * cur_data_idx); | |
695 | data[start_offset + cur_data_idx] = | |
696 | (unsigned char)reg; | |
697 | } | |
698 | ||
699 | start_offset += cur_data_count; | |
700 | } | |
701 | ||
702 | return retval; | |
703 | } | |
704 | ||
705 | int exynos_dp_select_i2c_device(struct exynos_dp_device *dp, | |
706 | unsigned int device_addr, | |
707 | unsigned int reg_addr) | |
708 | { | |
709 | u32 reg; | |
710 | int retval; | |
711 | ||
712 | /* Set EDID device address */ | |
713 | reg = device_addr; | |
714 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); | |
715 | writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); | |
716 | writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); | |
717 | ||
718 | /* Set offset from base address of EDID device */ | |
719 | writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0); | |
720 | ||
721 | /* | |
722 | * Set I2C transaction and write address | |
723 | * If bit 3 is 1, DisplayPort transaction. | |
724 | * If Bit 3 is 0, I2C transaction. | |
725 | */ | |
726 | reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | | |
727 | AUX_TX_COMM_WRITE; | |
728 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); | |
729 | ||
730 | /* Start AUX transaction */ | |
731 | retval = exynos_dp_start_aux_transaction(dp); | |
732 | if (retval != 0) | |
8fefbb75 | 733 | dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); |
e9474be4 JH |
734 | |
735 | return retval; | |
736 | } | |
737 | ||
738 | int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, | |
739 | unsigned int device_addr, | |
740 | unsigned int reg_addr, | |
741 | unsigned int *data) | |
742 | { | |
743 | u32 reg; | |
744 | int i; | |
745 | int retval; | |
746 | ||
99f54152 | 747 | for (i = 0; i < 3; i++) { |
e9474be4 JH |
748 | /* Clear AUX CH data buffer */ |
749 | reg = BUF_CLR; | |
750 | writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); | |
751 | ||
752 | /* Select EDID device */ | |
753 | retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr); | |
99f54152 | 754 | if (retval != 0) |
e9474be4 | 755 | continue; |
e9474be4 JH |
756 | |
757 | /* | |
758 | * Set I2C transaction and read data | |
759 | * If bit 3 is 1, DisplayPort transaction. | |
760 | * If Bit 3 is 0, I2C transaction. | |
761 | */ | |
762 | reg = AUX_TX_COMM_I2C_TRANSACTION | | |
763 | AUX_TX_COMM_READ; | |
764 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); | |
765 | ||
766 | /* Start AUX transaction */ | |
767 | retval = exynos_dp_start_aux_transaction(dp); | |
768 | if (retval == 0) | |
769 | break; | |
770 | else | |
8fefbb75 SP |
771 | dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", |
772 | __func__); | |
e9474be4 JH |
773 | } |
774 | ||
775 | /* Read data */ | |
776 | if (retval == 0) | |
777 | *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); | |
778 | ||
779 | return retval; | |
780 | } | |
781 | ||
782 | int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, | |
783 | unsigned int device_addr, | |
784 | unsigned int reg_addr, | |
785 | unsigned int count, | |
786 | unsigned char edid[]) | |
787 | { | |
788 | u32 reg; | |
789 | unsigned int i, j; | |
790 | unsigned int cur_data_idx; | |
791 | unsigned int defer = 0; | |
792 | int retval = 0; | |
793 | ||
794 | for (i = 0; i < count; i += 16) { | |
99f54152 | 795 | for (j = 0; j < 3; j++) { |
e9474be4 JH |
796 | /* Clear AUX CH data buffer */ |
797 | reg = BUF_CLR; | |
798 | writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); | |
799 | ||
800 | /* Set normal AUX CH command */ | |
801 | reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); | |
802 | reg &= ~ADDR_ONLY; | |
803 | writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); | |
804 | ||
805 | /* | |
806 | * If Rx sends defer, Tx sends only reads | |
ff0c2642 | 807 | * request without sending address |
e9474be4 JH |
808 | */ |
809 | if (!defer) | |
810 | retval = exynos_dp_select_i2c_device(dp, | |
811 | device_addr, reg_addr + i); | |
812 | else | |
813 | defer = 0; | |
814 | ||
815 | if (retval == 0) { | |
816 | /* | |
817 | * Set I2C transaction and write data | |
818 | * If bit 3 is 1, DisplayPort transaction. | |
819 | * If Bit 3 is 0, I2C transaction. | |
820 | */ | |
821 | reg = AUX_LENGTH(16) | | |
822 | AUX_TX_COMM_I2C_TRANSACTION | | |
823 | AUX_TX_COMM_READ; | |
824 | writel(reg, dp->reg_base + | |
825 | EXYNOS_DP_AUX_CH_CTL_1); | |
826 | ||
827 | /* Start AUX transaction */ | |
828 | retval = exynos_dp_start_aux_transaction(dp); | |
829 | if (retval == 0) | |
830 | break; | |
831 | else | |
8fefbb75 SP |
832 | dev_dbg(dp->dev, |
833 | "%s: Aux Transaction fail!\n", | |
834 | __func__); | |
e9474be4 JH |
835 | } |
836 | /* Check if Rx sends defer */ | |
837 | reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); | |
838 | if (reg == AUX_RX_COMM_AUX_DEFER || | |
839 | reg == AUX_RX_COMM_I2C_DEFER) { | |
840 | dev_err(dp->dev, "Defer: %d\n\n", reg); | |
841 | defer = 1; | |
842 | } | |
843 | } | |
844 | ||
845 | for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { | |
846 | reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 | |
847 | + 4 * cur_data_idx); | |
848 | edid[i + cur_data_idx] = (unsigned char)reg; | |
849 | } | |
850 | } | |
851 | ||
852 | return retval; | |
853 | } | |
854 | ||
855 | void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype) | |
856 | { | |
857 | u32 reg; | |
858 | ||
859 | reg = bwtype; | |
860 | if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS)) | |
861 | writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); | |
862 | } | |
863 | ||
864 | void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype) | |
865 | { | |
866 | u32 reg; | |
867 | ||
868 | reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET); | |
869 | *bwtype = reg; | |
870 | } | |
871 | ||
872 | void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count) | |
873 | { | |
874 | u32 reg; | |
875 | ||
876 | reg = count; | |
877 | writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); | |
878 | } | |
879 | ||
880 | void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count) | |
881 | { | |
882 | u32 reg; | |
883 | ||
884 | reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); | |
885 | *count = reg; | |
886 | } | |
887 | ||
888 | void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable) | |
889 | { | |
890 | u32 reg; | |
891 | ||
892 | if (enable) { | |
893 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
894 | reg |= ENHANCED; | |
895 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
896 | } else { | |
897 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
898 | reg &= ~ENHANCED; | |
899 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
900 | } | |
901 | } | |
902 | ||
903 | void exynos_dp_set_training_pattern(struct exynos_dp_device *dp, | |
904 | enum pattern_set pattern) | |
905 | { | |
906 | u32 reg; | |
907 | ||
908 | switch (pattern) { | |
909 | case PRBS7: | |
910 | reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; | |
911 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
912 | break; | |
913 | case D10_2: | |
914 | reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; | |
915 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
916 | break; | |
917 | case TRAINING_PTN1: | |
918 | reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; | |
919 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
920 | break; | |
921 | case TRAINING_PTN2: | |
922 | reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; | |
923 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
924 | break; | |
925 | case DP_NONE: | |
926 | reg = SCRAMBLING_ENABLE | | |
927 | LINK_QUAL_PATTERN_SET_DISABLE | | |
928 | SW_TRAINING_PATTERN_SET_NORMAL; | |
929 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
930 | break; | |
931 | default: | |
932 | break; | |
933 | } | |
934 | } | |
935 | ||
936 | void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level) | |
937 | { | |
938 | u32 reg; | |
939 | ||
e3c02009 JH |
940 | reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); |
941 | reg &= ~PRE_EMPHASIS_SET_MASK; | |
942 | reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
e9474be4 JH |
943 | writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); |
944 | } | |
945 | ||
946 | void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level) | |
947 | { | |
948 | u32 reg; | |
949 | ||
e3c02009 JH |
950 | reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); |
951 | reg &= ~PRE_EMPHASIS_SET_MASK; | |
952 | reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
e9474be4 JH |
953 | writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); |
954 | } | |
955 | ||
956 | void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level) | |
957 | { | |
958 | u32 reg; | |
959 | ||
e3c02009 JH |
960 | reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); |
961 | reg &= ~PRE_EMPHASIS_SET_MASK; | |
962 | reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
e9474be4 JH |
963 | writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); |
964 | } | |
965 | ||
966 | void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level) | |
967 | { | |
968 | u32 reg; | |
969 | ||
e3c02009 JH |
970 | reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); |
971 | reg &= ~PRE_EMPHASIS_SET_MASK; | |
972 | reg |= level << PRE_EMPHASIS_SET_SHIFT; | |
e9474be4 JH |
973 | writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); |
974 | } | |
975 | ||
976 | void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp, | |
977 | u32 training_lane) | |
978 | { | |
979 | u32 reg; | |
980 | ||
981 | reg = training_lane; | |
982 | writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); | |
983 | } | |
984 | ||
985 | void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp, | |
986 | u32 training_lane) | |
987 | { | |
988 | u32 reg; | |
989 | ||
990 | reg = training_lane; | |
991 | writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); | |
992 | } | |
993 | ||
994 | void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp, | |
995 | u32 training_lane) | |
996 | { | |
997 | u32 reg; | |
998 | ||
999 | reg = training_lane; | |
1000 | writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); | |
1001 | } | |
1002 | ||
1003 | void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp, | |
1004 | u32 training_lane) | |
1005 | { | |
1006 | u32 reg; | |
1007 | ||
1008 | reg = training_lane; | |
1009 | writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); | |
1010 | } | |
1011 | ||
1012 | u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp) | |
1013 | { | |
1014 | u32 reg; | |
1015 | ||
1016 | reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); | |
1017 | return reg; | |
1018 | } | |
1019 | ||
1020 | u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp) | |
1021 | { | |
1022 | u32 reg; | |
1023 | ||
1024 | reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); | |
1025 | return reg; | |
1026 | } | |
1027 | ||
1028 | u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp) | |
1029 | { | |
1030 | u32 reg; | |
1031 | ||
1032 | reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); | |
1033 | return reg; | |
1034 | } | |
1035 | ||
1036 | u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp) | |
1037 | { | |
1038 | u32 reg; | |
1039 | ||
1040 | reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); | |
1041 | return reg; | |
1042 | } | |
1043 | ||
1044 | void exynos_dp_reset_macro(struct exynos_dp_device *dp) | |
1045 | { | |
1046 | u32 reg; | |
1047 | ||
1048 | reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST); | |
1049 | reg |= MACRO_RST; | |
1050 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); | |
1051 | ||
1052 | /* 10 us is the minimum reset time. */ | |
a2c81bc1 | 1053 | usleep_range(10, 20); |
e9474be4 JH |
1054 | |
1055 | reg &= ~MACRO_RST; | |
1056 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); | |
1057 | } | |
1058 | ||
1ec7be9c | 1059 | void exynos_dp_init_video(struct exynos_dp_device *dp) |
e9474be4 JH |
1060 | { |
1061 | u32 reg; | |
1062 | ||
1063 | reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; | |
1064 | writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); | |
1065 | ||
1066 | reg = 0x0; | |
1067 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); | |
1068 | ||
1069 | reg = CHA_CRI(4) | CHA_CTRL; | |
1070 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); | |
1071 | ||
1072 | reg = 0x0; | |
1073 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
1074 | ||
1075 | reg = VID_HRES_TH(2) | VID_VRES_TH(0); | |
1076 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); | |
e9474be4 JH |
1077 | } |
1078 | ||
3fcb6eb4 | 1079 | void exynos_dp_set_video_color_format(struct exynos_dp_device *dp) |
e9474be4 JH |
1080 | { |
1081 | u32 reg; | |
1082 | ||
1083 | /* Configure the input color depth, color space, dynamic range */ | |
3fcb6eb4 AK |
1084 | reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) | |
1085 | (dp->video_info->color_depth << IN_BPC_SHIFT) | | |
1086 | (dp->video_info->color_space << IN_COLOR_F_SHIFT); | |
e9474be4 JH |
1087 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); |
1088 | ||
1089 | /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ | |
1090 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); | |
1091 | reg &= ~IN_YC_COEFFI_MASK; | |
3fcb6eb4 | 1092 | if (dp->video_info->ycbcr_coeff) |
e9474be4 JH |
1093 | reg |= IN_YC_COEFFI_ITU709; |
1094 | else | |
1095 | reg |= IN_YC_COEFFI_ITU601; | |
1096 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); | |
1097 | } | |
1098 | ||
1099 | int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp) | |
1100 | { | |
1101 | u32 reg; | |
1102 | ||
1103 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); | |
1104 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); | |
1105 | ||
1106 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); | |
1107 | ||
1108 | if (!(reg & DET_STA)) { | |
1109 | dev_dbg(dp->dev, "Input stream clock not detected.\n"); | |
1110 | return -EINVAL; | |
1111 | } | |
1112 | ||
1113 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); | |
1114 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); | |
1115 | ||
1116 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); | |
1117 | dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); | |
1118 | ||
1119 | if (reg & CHA_STA) { | |
1120 | dev_dbg(dp->dev, "Input stream clk is changing\n"); | |
1121 | return -EINVAL; | |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp, | |
1128 | enum clock_recovery_m_value_type type, | |
1129 | u32 m_value, | |
1130 | u32 n_value) | |
1131 | { | |
1132 | u32 reg; | |
1133 | ||
1134 | if (type == REGISTER_M) { | |
1135 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
1136 | reg |= FIX_M_VID; | |
1137 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
1138 | reg = m_value & 0xff; | |
1139 | writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); | |
1140 | reg = (m_value >> 8) & 0xff; | |
1141 | writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); | |
1142 | reg = (m_value >> 16) & 0xff; | |
1143 | writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); | |
1144 | ||
1145 | reg = n_value & 0xff; | |
1146 | writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); | |
1147 | reg = (n_value >> 8) & 0xff; | |
1148 | writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); | |
1149 | reg = (n_value >> 16) & 0xff; | |
1150 | writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); | |
1151 | } else { | |
1152 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
1153 | reg &= ~FIX_M_VID; | |
1154 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); | |
1155 | ||
1156 | writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0); | |
1157 | writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1); | |
1158 | writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2); | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type) | |
1163 | { | |
1164 | u32 reg; | |
1165 | ||
1166 | if (type == VIDEO_TIMING_FROM_CAPTURE) { | |
1167 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1168 | reg &= ~FORMAT_SEL; | |
1169 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1170 | } else { | |
1171 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1172 | reg |= FORMAT_SEL; | |
1173 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable) | |
1178 | { | |
1179 | u32 reg; | |
1180 | ||
1181 | if (enable) { | |
1182 | reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); | |
1183 | reg &= ~VIDEO_MODE_MASK; | |
1184 | reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; | |
1185 | writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); | |
1186 | } else { | |
1187 | reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); | |
1188 | reg &= ~VIDEO_MODE_MASK; | |
1189 | reg |= VIDEO_MODE_SLAVE_MODE; | |
1190 | writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | void exynos_dp_start_video(struct exynos_dp_device *dp) | |
1195 | { | |
1196 | u32 reg; | |
1197 | ||
1198 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
1199 | reg |= VIDEO_EN; | |
1200 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); | |
1201 | } | |
1202 | ||
1203 | int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp) | |
1204 | { | |
1205 | u32 reg; | |
1206 | ||
1207 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
1208 | writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
1209 | ||
1210 | reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); | |
1211 | if (!(reg & STRM_VALID)) { | |
1212 | dev_dbg(dp->dev, "Input video stream is not detected.\n"); | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
3fcb6eb4 | 1219 | void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp) |
e9474be4 JH |
1220 | { |
1221 | u32 reg; | |
1222 | ||
1223 | reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); | |
1224 | reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); | |
1225 | reg |= MASTER_VID_FUNC_EN_N; | |
1226 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); | |
1227 | ||
1228 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1229 | reg &= ~INTERACE_SCAN_CFG; | |
3fcb6eb4 | 1230 | reg |= (dp->video_info->interlaced << 2); |
e9474be4 JH |
1231 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); |
1232 | ||
1233 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1234 | reg &= ~VSYNC_POLARITY_CFG; | |
3fcb6eb4 | 1235 | reg |= (dp->video_info->v_sync_polarity << 1); |
e9474be4 JH |
1236 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); |
1237 | ||
1238 | reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); | |
1239 | reg &= ~HSYNC_POLARITY_CFG; | |
3fcb6eb4 | 1240 | reg |= (dp->video_info->h_sync_polarity << 0); |
e9474be4 JH |
1241 | writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); |
1242 | ||
1243 | reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; | |
1244 | writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); | |
1245 | } | |
1246 | ||
1247 | void exynos_dp_enable_scrambling(struct exynos_dp_device *dp) | |
1248 | { | |
1249 | u32 reg; | |
1250 | ||
1251 | reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
1252 | reg &= ~SCRAMBLING_DISABLE; | |
1253 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
1254 | } | |
1255 | ||
1256 | void exynos_dp_disable_scrambling(struct exynos_dp_device *dp) | |
1257 | { | |
1258 | u32 reg; | |
1259 | ||
1260 | reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
1261 | reg |= SCRAMBLING_DISABLE; | |
1262 | writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); | |
1263 | } |