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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
f37cd5e8 | 22 | #include <linux/component.h> |
3854fab2 YC |
23 | #include <linux/mfd/syscon.h> |
24 | #include <linux/regmap.h> | |
1c248b7d | 25 | |
7f4596f4 | 26 | #include <video/of_display_timing.h> |
111e6055 | 27 | #include <video/of_videomode.h> |
5a213a55 | 28 | #include <video/samsung_fimd.h> |
1c248b7d | 29 | #include <drm/exynos_drm.h> |
1c248b7d ID |
30 | |
31 | #include "exynos_drm_drv.h" | |
0488f50e | 32 | #include "exynos_drm_fb.h" |
1c248b7d ID |
33 | #include "exynos_drm_fbdev.h" |
34 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 35 | #include "exynos_drm_plane.h" |
bcc5cd1c | 36 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
37 | |
38 | /* | |
b8654b37 | 39 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
40 | * as a display controller, it transfers contents drawn on memory |
41 | * to a LCD Panel through Display Interfaces such as RGB or | |
42 | * CPU Interface. | |
43 | */ | |
44 | ||
66367461 | 45 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 46 | |
1c248b7d ID |
47 | /* position control register for hardware window 0, 2 ~ 4.*/ |
48 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
49 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
50 | /* |
51 | * size control register for hardware windows 0 and alpha control register | |
52 | * for hardware windows 1 ~ 4 | |
53 | */ | |
54 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
55 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
56 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
57 | ||
453b44a3 GP |
58 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
59 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
60 | ||
1c248b7d | 61 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
cb11b3f1 | 62 | #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) |
1c248b7d ID |
63 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) |
64 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
65 | ||
66 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 67 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 68 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 69 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 70 | |
3854fab2 YC |
71 | /* I80 / RGB trigger control register */ |
72 | #define TRIGCON 0x1A4 | |
73 | #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) | |
74 | #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) | |
75 | ||
76 | /* display mode change control register except exynos4 */ | |
77 | #define VIDOUT_CON 0x000 | |
78 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
79 | ||
80 | /* I80 interface control for main LDI register */ | |
81 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
82 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
83 | #define LCD_CS_SETUP(x) ((x) << 16) | |
84 | #define LCD_WR_SETUP(x) ((x) << 12) | |
85 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
86 | #define LCD_WR_HOLD(x) ((x) << 4) | |
87 | #define I80IFEN_ENABLE (1 << 0) | |
88 | ||
1c248b7d ID |
89 | /* FIMD has totally five hardware windows. */ |
90 | #define WINDOWS_NR 5 | |
91 | ||
e2e13389 LKA |
92 | struct fimd_driver_data { |
93 | unsigned int timing_base; | |
3854fab2 YC |
94 | unsigned int lcdblk_offset; |
95 | unsigned int lcdblk_vt_shift; | |
96 | unsigned int lcdblk_bypass_shift; | |
de7af100 TF |
97 | |
98 | unsigned int has_shadowcon:1; | |
411d9ed4 | 99 | unsigned int has_clksel:1; |
5cc4621a | 100 | unsigned int has_limited_fmt:1; |
3854fab2 | 101 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 102 | unsigned int has_vtsel:1; |
e2e13389 LKA |
103 | }; |
104 | ||
725ddead TF |
105 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
106 | .timing_base = 0x0, | |
107 | .has_clksel = 1, | |
5cc4621a | 108 | .has_limited_fmt = 1, |
725ddead TF |
109 | }; |
110 | ||
d6ce7b58 ID |
111 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
112 | .timing_base = 0x20000, | |
113 | .lcdblk_offset = 0x210, | |
114 | .lcdblk_bypass_shift = 1, | |
115 | .has_shadowcon = 1, | |
116 | .has_vidoutcon = 1, | |
117 | }; | |
118 | ||
6ecf18f9 | 119 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 120 | .timing_base = 0x0, |
3854fab2 YC |
121 | .lcdblk_offset = 0x210, |
122 | .lcdblk_vt_shift = 10, | |
123 | .lcdblk_bypass_shift = 1, | |
de7af100 | 124 | .has_shadowcon = 1, |
3c3c9c1d | 125 | .has_vtsel = 1, |
e2e13389 LKA |
126 | }; |
127 | ||
dcb622aa YC |
128 | static struct fimd_driver_data exynos4415_fimd_driver_data = { |
129 | .timing_base = 0x20000, | |
130 | .lcdblk_offset = 0x210, | |
131 | .lcdblk_vt_shift = 10, | |
132 | .lcdblk_bypass_shift = 1, | |
133 | .has_shadowcon = 1, | |
134 | .has_vidoutcon = 1, | |
3c3c9c1d | 135 | .has_vtsel = 1, |
dcb622aa YC |
136 | }; |
137 | ||
6ecf18f9 | 138 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 139 | .timing_base = 0x20000, |
3854fab2 YC |
140 | .lcdblk_offset = 0x214, |
141 | .lcdblk_vt_shift = 24, | |
142 | .lcdblk_bypass_shift = 15, | |
de7af100 | 143 | .has_shadowcon = 1, |
3854fab2 | 144 | .has_vidoutcon = 1, |
3c3c9c1d | 145 | .has_vtsel = 1, |
e2e13389 LKA |
146 | }; |
147 | ||
1c248b7d | 148 | struct fimd_context { |
bb7704d6 | 149 | struct device *dev; |
40c8ab4b | 150 | struct drm_device *drm_dev; |
93bca243 | 151 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 152 | struct exynos_drm_plane planes[WINDOWS_NR]; |
fd2d2fc2 | 153 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
1c248b7d ID |
154 | struct clk *bus_clk; |
155 | struct clk *lcd_clk; | |
1c248b7d | 156 | void __iomem *regs; |
3854fab2 | 157 | struct regmap *sysreg; |
1c248b7d | 158 | unsigned long irq_flags; |
3854fab2 | 159 | u32 vidcon0; |
1c248b7d | 160 | u32 vidcon1; |
3854fab2 YC |
161 | u32 vidout_con; |
162 | u32 i80ifcon; | |
163 | bool i80_if; | |
cb91f6a0 | 164 | bool suspended; |
080be03d | 165 | int pipe; |
01ce113c P |
166 | wait_queue_head_t wait_vsync_queue; |
167 | atomic_t wait_vsync_event; | |
3854fab2 YC |
168 | atomic_t win_updated; |
169 | atomic_t triggering; | |
1c248b7d | 170 | |
562ad9f4 | 171 | struct exynos_drm_panel_info panel; |
18873465 | 172 | struct fimd_driver_data *driver_data; |
2b8376c8 | 173 | struct drm_encoder *encoder; |
1c248b7d ID |
174 | }; |
175 | ||
d636ead8 | 176 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
177 | { .compatible = "samsung,s3c6400-fimd", |
178 | .data = &s3c64xx_fimd_driver_data }, | |
d6ce7b58 ID |
179 | { .compatible = "samsung,exynos3250-fimd", |
180 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 181 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 182 | .data = &exynos4_fimd_driver_data }, |
dcb622aa YC |
183 | { .compatible = "samsung,exynos4415-fimd", |
184 | .data = &exynos4415_fimd_driver_data }, | |
5830daf8 | 185 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
186 | .data = &exynos5_fimd_driver_data }, |
187 | {}, | |
188 | }; | |
0262ceeb | 189 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 190 | |
fd2d2fc2 MS |
191 | static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { |
192 | DRM_PLANE_TYPE_PRIMARY, | |
193 | DRM_PLANE_TYPE_OVERLAY, | |
194 | DRM_PLANE_TYPE_OVERLAY, | |
195 | DRM_PLANE_TYPE_OVERLAY, | |
196 | DRM_PLANE_TYPE_CURSOR, | |
197 | }; | |
198 | ||
fbbb1e1a MS |
199 | static const uint32_t fimd_formats[] = { |
200 | DRM_FORMAT_C8, | |
201 | DRM_FORMAT_XRGB1555, | |
202 | DRM_FORMAT_RGB565, | |
203 | DRM_FORMAT_XRGB8888, | |
204 | DRM_FORMAT_ARGB8888, | |
205 | }; | |
206 | ||
e2e13389 LKA |
207 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
208 | struct platform_device *pdev) | |
209 | { | |
d636ead8 JS |
210 | const struct of_device_id *of_id = |
211 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
212 | ||
2d3f173c | 213 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
214 | } |
215 | ||
fb88e214 MS |
216 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
217 | { | |
218 | struct fimd_context *ctx = crtc->ctx; | |
219 | u32 val; | |
220 | ||
221 | if (ctx->suspended) | |
222 | return -EPERM; | |
223 | ||
224 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
225 | val = readl(ctx->regs + VIDINTCON0); | |
226 | ||
227 | val |= VIDINTCON0_INT_ENABLE; | |
228 | ||
229 | if (ctx->i80_if) { | |
230 | val |= VIDINTCON0_INT_I80IFDONE; | |
231 | val |= VIDINTCON0_INT_SYSMAINCON; | |
232 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
233 | } else { | |
234 | val |= VIDINTCON0_INT_FRAME; | |
235 | ||
236 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
237 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
238 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
239 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
240 | } | |
241 | ||
242 | writel(val, ctx->regs + VIDINTCON0); | |
243 | } | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) | |
249 | { | |
250 | struct fimd_context *ctx = crtc->ctx; | |
251 | u32 val; | |
252 | ||
253 | if (ctx->suspended) | |
254 | return; | |
255 | ||
256 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
257 | val = readl(ctx->regs + VIDINTCON0); | |
258 | ||
259 | val &= ~VIDINTCON0_INT_ENABLE; | |
260 | ||
261 | if (ctx->i80_if) { | |
262 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
263 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
264 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
265 | } else | |
266 | val &= ~VIDINTCON0_INT_FRAME; | |
267 | ||
268 | writel(val, ctx->regs + VIDINTCON0); | |
269 | } | |
270 | } | |
271 | ||
93bca243 | 272 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 273 | { |
93bca243 | 274 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
275 | |
276 | if (ctx->suspended) | |
277 | return; | |
278 | ||
279 | atomic_set(&ctx->wait_vsync_event, 1); | |
280 | ||
281 | /* | |
282 | * wait for FIMD to signal VSYNC interrupt or return after | |
283 | * timeout which is set to 50ms (refresh rate of 20). | |
284 | */ | |
285 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
286 | !atomic_read(&ctx->wait_vsync_event), | |
287 | HZ/20)) | |
288 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
289 | } | |
290 | ||
5b1d5bc6 | 291 | static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, |
f181a543 YC |
292 | bool enable) |
293 | { | |
294 | u32 val = readl(ctx->regs + WINCON(win)); | |
295 | ||
296 | if (enable) | |
297 | val |= WINCONx_ENWIN; | |
298 | else | |
299 | val &= ~WINCONx_ENWIN; | |
300 | ||
301 | writel(val, ctx->regs + WINCON(win)); | |
302 | } | |
303 | ||
5b1d5bc6 TJ |
304 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, |
305 | unsigned int win, | |
999d8b31 YC |
306 | bool enable) |
307 | { | |
308 | u32 val = readl(ctx->regs + SHADOWCON); | |
309 | ||
310 | if (enable) | |
311 | val |= SHADOWCON_CHx_ENABLE(win); | |
312 | else | |
313 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
314 | ||
315 | writel(val, ctx->regs + SHADOWCON); | |
316 | } | |
317 | ||
fc2e013f | 318 | static void fimd_clear_channels(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 319 | { |
fc2e013f | 320 | struct fimd_context *ctx = crtc->ctx; |
5b1d5bc6 | 321 | unsigned int win, ch_enabled = 0; |
f13bdbd1 AA |
322 | |
323 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
324 | ||
fb88e214 MS |
325 | /* Hardware is in unknown state, so ensure it gets enabled properly */ |
326 | pm_runtime_get_sync(ctx->dev); | |
327 | ||
328 | clk_prepare_enable(ctx->bus_clk); | |
329 | clk_prepare_enable(ctx->lcd_clk); | |
330 | ||
f13bdbd1 AA |
331 | /* Check if any channel is enabled. */ |
332 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
333 | u32 val = readl(ctx->regs + WINCON(win)); |
334 | ||
335 | if (val & WINCONx_ENWIN) { | |
f181a543 | 336 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 337 | |
999d8b31 YC |
338 | if (ctx->driver_data->has_shadowcon) |
339 | fimd_enable_shadow_channel_path(ctx, win, | |
340 | false); | |
341 | ||
f13bdbd1 AA |
342 | ch_enabled = 1; |
343 | } | |
344 | } | |
345 | ||
346 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 | 347 | if (ch_enabled) { |
fb88e214 MS |
348 | int pipe = ctx->pipe; |
349 | ||
350 | /* ensure that vblank interrupt won't be reported to core */ | |
351 | ctx->suspended = false; | |
352 | ctx->pipe = -1; | |
eb8a3bf7 | 353 | |
fb88e214 | 354 | fimd_enable_vblank(ctx->crtc); |
92dc7a04 | 355 | fimd_wait_for_vblank(ctx->crtc); |
fb88e214 MS |
356 | fimd_disable_vblank(ctx->crtc); |
357 | ||
358 | ctx->suspended = true; | |
359 | ctx->pipe = pipe; | |
eb8a3bf7 | 360 | } |
fb88e214 MS |
361 | |
362 | clk_disable_unprepare(ctx->lcd_clk); | |
363 | clk_disable_unprepare(ctx->bus_clk); | |
364 | ||
365 | pm_runtime_put(ctx->dev); | |
f13bdbd1 AA |
366 | } |
367 | ||
a968e727 SP |
368 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
369 | const struct drm_display_mode *mode) | |
370 | { | |
371 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
372 | u32 clkdiv; | |
373 | ||
3854fab2 YC |
374 | if (ctx->i80_if) { |
375 | /* | |
376 | * The frame done interrupt should be occurred prior to the | |
377 | * next TE signal. | |
378 | */ | |
379 | ideal_clk *= 2; | |
380 | } | |
381 | ||
a968e727 SP |
382 | /* Find the clock divider value that gets us closest to ideal_clk */ |
383 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); | |
384 | ||
385 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
386 | } | |
387 | ||
93bca243 | 388 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 389 | { |
93bca243 | 390 | struct fimd_context *ctx = crtc->ctx; |
020e79de | 391 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
3854fab2 YC |
392 | struct fimd_driver_data *driver_data = ctx->driver_data; |
393 | void *timing_base = ctx->regs + driver_data->timing_base; | |
394 | u32 val, clkdiv; | |
1c248b7d | 395 | |
e30d4bcf ID |
396 | if (ctx->suspended) |
397 | return; | |
398 | ||
a968e727 SP |
399 | /* nothing to do if we haven't set the mode yet */ |
400 | if (mode->htotal == 0 || mode->vtotal == 0) | |
401 | return; | |
402 | ||
3854fab2 YC |
403 | if (ctx->i80_if) { |
404 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
405 | writel(val, timing_base + I80IFCONFAx(0)); | |
406 | ||
407 | /* disable auto frame rate */ | |
408 | writel(0, timing_base + I80IFCONFBx(0)); | |
409 | ||
410 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
411 | if (driver_data->has_vtsel && ctx->sysreg && |
412 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
413 | driver_data->lcdblk_offset, |
414 | 0x3 << driver_data->lcdblk_vt_shift, | |
415 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
416 | DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); | |
417 | return; | |
418 | } | |
419 | } else { | |
420 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
421 | u32 vidcon1; | |
422 | ||
423 | /* setup polarity values */ | |
424 | vidcon1 = ctx->vidcon1; | |
425 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
426 | vidcon1 |= VIDCON1_INV_VSYNC; | |
427 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
428 | vidcon1 |= VIDCON1_INV_HSYNC; | |
429 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
430 | ||
431 | /* setup vertical timing values. */ | |
432 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
433 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
434 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
435 | ||
436 | val = VIDTCON0_VBPD(vbpd - 1) | | |
437 | VIDTCON0_VFPD(vfpd - 1) | | |
438 | VIDTCON0_VSPW(vsync_len - 1); | |
439 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
440 | ||
441 | /* setup horizontal timing values. */ | |
442 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
443 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
444 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
445 | ||
446 | val = VIDTCON1_HBPD(hbpd - 1) | | |
447 | VIDTCON1_HFPD(hfpd - 1) | | |
448 | VIDTCON1_HSPW(hsync_len - 1); | |
449 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
450 | } | |
451 | ||
452 | if (driver_data->has_vidoutcon) | |
453 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
454 | ||
455 | /* set bypass selection */ | |
456 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
457 | driver_data->lcdblk_offset, | |
458 | 0x1 << driver_data->lcdblk_bypass_shift, | |
459 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
460 | DRM_ERROR("Failed to update sysreg for bypass setting.\n"); | |
461 | return; | |
462 | } | |
1c248b7d ID |
463 | |
464 | /* setup horizontal and vertical display size. */ | |
a968e727 SP |
465 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
466 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
467 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
468 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 469 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 470 | |
1d531062 AH |
471 | /* |
472 | * fields of register with prefix '_F' would be updated | |
473 | * at vsync(same as dma start) | |
474 | */ | |
3854fab2 YC |
475 | val = ctx->vidcon0; |
476 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 477 | |
1d531062 | 478 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 479 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 480 | |
a968e727 SP |
481 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
482 | if (clkdiv > 1) | |
483 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 484 | |
1c248b7d ID |
485 | writel(val, ctx->regs + VIDCON0); |
486 | } | |
487 | ||
1c248b7d | 488 | |
2eeb2e5e | 489 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, |
8b704d8a | 490 | uint32_t pixel_format, int width) |
1c248b7d | 491 | { |
1c248b7d ID |
492 | unsigned long val; |
493 | ||
1c248b7d ID |
494 | val = WINCONx_ENWIN; |
495 | ||
5cc4621a ID |
496 | /* |
497 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
498 | * So the request format is ARGB8888 then change it to XRGB8888. | |
499 | */ | |
500 | if (ctx->driver_data->has_limited_fmt && !win) { | |
8b704d8a MS |
501 | if (pixel_format == DRM_FORMAT_ARGB8888) |
502 | pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
503 | } |
504 | ||
8b704d8a | 505 | switch (pixel_format) { |
a4f38a80 | 506 | case DRM_FORMAT_C8: |
1c248b7d ID |
507 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
508 | val |= WINCONx_BURSTLEN_8WORD; | |
509 | val |= WINCONx_BYTSWP; | |
510 | break; | |
a4f38a80 ID |
511 | case DRM_FORMAT_XRGB1555: |
512 | val |= WINCON0_BPPMODE_16BPP_1555; | |
513 | val |= WINCONx_HAWSWP; | |
514 | val |= WINCONx_BURSTLEN_16WORD; | |
515 | break; | |
516 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
517 | val |= WINCON0_BPPMODE_16BPP_565; |
518 | val |= WINCONx_HAWSWP; | |
519 | val |= WINCONx_BURSTLEN_16WORD; | |
520 | break; | |
a4f38a80 | 521 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
522 | val |= WINCON0_BPPMODE_24BPP_888; |
523 | val |= WINCONx_WSWP; | |
524 | val |= WINCONx_BURSTLEN_16WORD; | |
525 | break; | |
a4f38a80 ID |
526 | case DRM_FORMAT_ARGB8888: |
527 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
528 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
529 | val |= WINCONx_WSWP; | |
530 | val |= WINCONx_BURSTLEN_16WORD; | |
531 | break; | |
532 | default: | |
533 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
534 | ||
535 | val |= WINCON0_BPPMODE_24BPP_888; | |
536 | val |= WINCONx_WSWP; | |
537 | val |= WINCONx_BURSTLEN_16WORD; | |
538 | break; | |
539 | } | |
540 | ||
66367461 | 541 | /* |
8b704d8a MS |
542 | * Setting dma-burst to 16Word causes permanent tearing for very small |
543 | * buffers, e.g. cursor buffer. Burst Mode switching which based on | |
544 | * plane size is not recommended as plane size varies alot towards the | |
545 | * end of the screen and rapid movement causes unstable DMA, but it is | |
546 | * still better to change dma-burst than displaying garbage. | |
66367461 RS |
547 | */ |
548 | ||
8b704d8a | 549 | if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
550 | val &= ~WINCONx_BURSTLEN_MASK; |
551 | val |= WINCONx_BURSTLEN_4WORD; | |
552 | } | |
553 | ||
1c248b7d | 554 | writel(val, ctx->regs + WINCON(win)); |
453b44a3 GP |
555 | |
556 | /* hardware window 0 doesn't support alpha channel. */ | |
557 | if (win != 0) { | |
558 | /* OSD alpha */ | |
559 | val = VIDISD14C_ALPHA0_R(0xf) | | |
560 | VIDISD14C_ALPHA0_G(0xf) | | |
561 | VIDISD14C_ALPHA0_B(0xf) | | |
562 | VIDISD14C_ALPHA1_R(0xf) | | |
563 | VIDISD14C_ALPHA1_G(0xf) | | |
564 | VIDISD14C_ALPHA1_B(0xf); | |
565 | ||
566 | writel(val, ctx->regs + VIDOSD_C(win)); | |
567 | ||
568 | val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | | |
569 | VIDW_ALPHA_G(0xf); | |
570 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
571 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
572 | } | |
1c248b7d ID |
573 | } |
574 | ||
bb7704d6 | 575 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 576 | { |
1c248b7d ID |
577 | unsigned int keycon0 = 0, keycon1 = 0; |
578 | ||
1c248b7d ID |
579 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
580 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
581 | ||
582 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
583 | ||
584 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
585 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
586 | } | |
587 | ||
de7af100 TF |
588 | /** |
589 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
590 | * | |
591 | * @win: window to protect registers for | |
592 | * @protect: 1 to protect (disable updates) | |
593 | */ | |
594 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 595 | unsigned int win, bool protect) |
de7af100 TF |
596 | { |
597 | u32 reg, bits, val; | |
598 | ||
ce3ff36b GP |
599 | /* |
600 | * SHADOWCON/PRTCON register is used for enabling timing. | |
601 | * | |
602 | * for example, once only width value of a register is set, | |
603 | * if the dma is started then fimd hardware could malfunction so | |
604 | * with protect window setting, the register fields with prefix '_F' | |
605 | * wouldn't be updated at vsync also but updated once unprotect window | |
606 | * is set. | |
607 | */ | |
608 | ||
de7af100 TF |
609 | if (ctx->driver_data->has_shadowcon) { |
610 | reg = SHADOWCON; | |
611 | bits = SHADOWCON_WINx_PROTECT(win); | |
612 | } else { | |
613 | reg = PRTCON; | |
614 | bits = PRTCON_PROTECT; | |
615 | } | |
616 | ||
617 | val = readl(ctx->regs + reg); | |
618 | if (protect) | |
619 | val |= bits; | |
620 | else | |
621 | val &= ~bits; | |
622 | writel(val, ctx->regs + reg); | |
623 | } | |
624 | ||
d29c2c14 | 625 | static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
626 | { |
627 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 628 | int i; |
ce3ff36b GP |
629 | |
630 | if (ctx->suspended) | |
631 | return; | |
632 | ||
d29c2c14 MS |
633 | for (i = 0; i < WINDOWS_NR; i++) |
634 | fimd_shadow_protect_win(ctx, i, true); | |
ce3ff36b GP |
635 | } |
636 | ||
d29c2c14 | 637 | static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
638 | { |
639 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 640 | int i; |
ce3ff36b GP |
641 | |
642 | if (ctx->suspended) | |
643 | return; | |
644 | ||
d29c2c14 MS |
645 | for (i = 0; i < WINDOWS_NR; i++) |
646 | fimd_shadow_protect_win(ctx, i, false); | |
ce3ff36b GP |
647 | } |
648 | ||
1e1d1393 GP |
649 | static void fimd_update_plane(struct exynos_drm_crtc *crtc, |
650 | struct exynos_drm_plane *plane) | |
1c248b7d | 651 | { |
0114f404 MS |
652 | struct exynos_drm_plane_state *state = |
653 | to_exynos_plane_state(plane->base.state); | |
93bca243 | 654 | struct fimd_context *ctx = crtc->ctx; |
0114f404 | 655 | struct drm_framebuffer *fb = state->base.fb; |
7ee14cdc GP |
656 | dma_addr_t dma_addr; |
657 | unsigned long val, size, offset; | |
658 | unsigned int last_x, last_y, buf_offsize, line_size; | |
40bdfb0a | 659 | unsigned int win = plane->index; |
0488f50e MS |
660 | unsigned int bpp = fb->bits_per_pixel >> 3; |
661 | unsigned int pitch = fb->pitches[0]; | |
1c248b7d | 662 | |
e30d4bcf ID |
663 | if (ctx->suspended) |
664 | return; | |
665 | ||
0114f404 MS |
666 | offset = state->src.x * bpp; |
667 | offset += state->src.y * pitch; | |
7ee14cdc | 668 | |
1c248b7d | 669 | /* buffer start address */ |
0488f50e | 670 | dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; |
7ee14cdc | 671 | val = (unsigned long)dma_addr; |
1c248b7d ID |
672 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
673 | ||
674 | /* buffer end address */ | |
0114f404 | 675 | size = pitch * state->crtc.h; |
7ee14cdc | 676 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
677 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
678 | ||
679 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
7ee14cdc | 680 | (unsigned long)dma_addr, val, size); |
19c8b834 | 681 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
0114f404 | 682 | state->crtc.w, state->crtc.h); |
1c248b7d ID |
683 | |
684 | /* buffer size */ | |
0114f404 MS |
685 | buf_offsize = pitch - (state->crtc.w * bpp); |
686 | line_size = state->crtc.w * bpp; | |
7ee14cdc GP |
687 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | |
688 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
689 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
690 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
691 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
692 | ||
693 | /* OSD position */ | |
0114f404 MS |
694 | val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | |
695 | VIDOSDxA_TOPLEFT_Y(state->crtc.y) | | |
696 | VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | | |
697 | VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); | |
1c248b7d ID |
698 | writel(val, ctx->regs + VIDOSD_A(win)); |
699 | ||
0114f404 | 700 | last_x = state->crtc.x + state->crtc.w; |
f56aad3a JS |
701 | if (last_x) |
702 | last_x--; | |
0114f404 | 703 | last_y = state->crtc.y + state->crtc.h; |
f56aad3a JS |
704 | if (last_y) |
705 | last_y--; | |
706 | ||
ca555e5a JS |
707 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
708 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
709 | ||
1c248b7d ID |
710 | writel(val, ctx->regs + VIDOSD_B(win)); |
711 | ||
19c8b834 | 712 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
0114f404 | 713 | state->crtc.x, state->crtc.y, last_x, last_y); |
1c248b7d | 714 | |
1c248b7d ID |
715 | /* OSD size */ |
716 | if (win != 3 && win != 4) { | |
717 | u32 offset = VIDOSD_D(win); | |
718 | if (win == 0) | |
0f10cf14 | 719 | offset = VIDOSD_C(win); |
0114f404 | 720 | val = state->crtc.w * state->crtc.h; |
1c248b7d ID |
721 | writel(val, ctx->regs + offset); |
722 | ||
723 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
724 | } | |
725 | ||
8b704d8a | 726 | fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w); |
1c248b7d ID |
727 | |
728 | /* hardware window 0 doesn't support color key. */ | |
729 | if (win != 0) | |
bb7704d6 | 730 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 731 | |
f181a543 | 732 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 733 | |
999d8b31 YC |
734 | if (ctx->driver_data->has_shadowcon) |
735 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 736 | |
3854fab2 YC |
737 | if (ctx->i80_if) |
738 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
739 | } |
740 | ||
1e1d1393 GP |
741 | static void fimd_disable_plane(struct exynos_drm_crtc *crtc, |
742 | struct exynos_drm_plane *plane) | |
1c248b7d | 743 | { |
93bca243 | 744 | struct fimd_context *ctx = crtc->ctx; |
40bdfb0a | 745 | unsigned int win = plane->index; |
ec05da95 | 746 | |
c329f667 | 747 | if (ctx->suspended) |
db7e55ae | 748 | return; |
db7e55ae | 749 | |
f181a543 | 750 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 751 | |
999d8b31 YC |
752 | if (ctx->driver_data->has_shadowcon) |
753 | fimd_enable_shadow_channel_path(ctx, win, false); | |
a43b933b SP |
754 | } |
755 | ||
3cecda03 | 756 | static void fimd_enable(struct exynos_drm_crtc *crtc) |
a43b933b | 757 | { |
3cecda03 | 758 | struct fimd_context *ctx = crtc->ctx; |
a43b933b SP |
759 | |
760 | if (!ctx->suspended) | |
3cecda03 | 761 | return; |
a43b933b SP |
762 | |
763 | ctx->suspended = false; | |
764 | ||
af65c804 SP |
765 | pm_runtime_get_sync(ctx->dev); |
766 | ||
a43b933b | 767 | /* if vblank was enabled status, enable it again. */ |
3cecda03 GP |
768 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
769 | fimd_enable_vblank(ctx->crtc); | |
a43b933b | 770 | |
c329f667 | 771 | fimd_commit(ctx->crtc); |
a43b933b SP |
772 | } |
773 | ||
3cecda03 | 774 | static void fimd_disable(struct exynos_drm_crtc *crtc) |
a43b933b | 775 | { |
3cecda03 | 776 | struct fimd_context *ctx = crtc->ctx; |
c329f667 | 777 | int i; |
3cecda03 | 778 | |
a43b933b | 779 | if (ctx->suspended) |
3cecda03 | 780 | return; |
a43b933b SP |
781 | |
782 | /* | |
783 | * We need to make sure that all windows are disabled before we | |
784 | * suspend that connector. Otherwise we might try to scan from | |
785 | * a destroyed buffer later. | |
786 | */ | |
c329f667 | 787 | for (i = 0; i < WINDOWS_NR; i++) |
1e1d1393 | 788 | fimd_disable_plane(crtc, &ctx->planes[i]); |
a43b933b | 789 | |
94ab95a9 ID |
790 | fimd_enable_vblank(crtc); |
791 | fimd_wait_for_vblank(crtc); | |
792 | fimd_disable_vblank(crtc); | |
793 | ||
b74f14fd JS |
794 | writel(0, ctx->regs + VIDCON0); |
795 | ||
af65c804 | 796 | pm_runtime_put_sync(ctx->dev); |
a43b933b | 797 | ctx->suspended = true; |
080be03d SP |
798 | } |
799 | ||
3854fab2 YC |
800 | static void fimd_trigger(struct device *dev) |
801 | { | |
e152dbd7 | 802 | struct fimd_context *ctx = dev_get_drvdata(dev); |
3854fab2 YC |
803 | struct fimd_driver_data *driver_data = ctx->driver_data; |
804 | void *timing_base = ctx->regs + driver_data->timing_base; | |
805 | u32 reg; | |
806 | ||
9b67eb73 | 807 | /* |
1c905d95 YC |
808 | * Skips triggering if in triggering state, because multiple triggering |
809 | * requests can cause panel reset. | |
810 | */ | |
9b67eb73 JS |
811 | if (atomic_read(&ctx->triggering)) |
812 | return; | |
813 | ||
1c905d95 | 814 | /* Enters triggering mode */ |
3854fab2 YC |
815 | atomic_set(&ctx->triggering, 1); |
816 | ||
3854fab2 YC |
817 | reg = readl(timing_base + TRIGCON); |
818 | reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); | |
819 | writel(reg, timing_base + TRIGCON); | |
87ab85b3 YC |
820 | |
821 | /* | |
822 | * Exits triggering mode if vblank is not enabled yet, because when the | |
823 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
824 | */ | |
825 | if (!test_bit(0, &ctx->irq_flags)) | |
826 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
827 | } |
828 | ||
93bca243 | 829 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 830 | { |
93bca243 | 831 | struct fimd_context *ctx = crtc->ctx; |
3854fab2 YC |
832 | |
833 | /* Checks the crtc is detached already from encoder */ | |
834 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
835 | return; | |
836 | ||
3854fab2 YC |
837 | /* |
838 | * If there is a page flip request, triggers and handles the page flip | |
839 | * event so that current fb can be updated into panel GRAM. | |
840 | */ | |
841 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
842 | fimd_trigger(ctx->dev); | |
843 | ||
844 | /* Wakes up vsync event queue */ | |
845 | if (atomic_read(&ctx->wait_vsync_event)) { | |
846 | atomic_set(&ctx->wait_vsync_event, 0); | |
847 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 848 | } |
b301ae24 | 849 | |
adf67abf | 850 | if (test_bit(0, &ctx->irq_flags)) |
eafd540a | 851 | drm_crtc_handle_vblank(&ctx->crtc->base); |
3854fab2 YC |
852 | } |
853 | ||
48107d7b KK |
854 | static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) |
855 | { | |
856 | struct fimd_context *ctx = crtc->ctx; | |
857 | u32 val; | |
858 | ||
859 | /* | |
860 | * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE | |
861 | * clock. On these SoCs the bootloader may enable it but any | |
862 | * power domain off/on will reset it to disable state. | |
863 | */ | |
864 | if (ctx->driver_data != &exynos5_fimd_driver_data) | |
865 | return; | |
866 | ||
867 | val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
3c79fb8c | 868 | writel(val, ctx->regs + DP_MIE_CLKCON); |
48107d7b KK |
869 | } |
870 | ||
f3aaf762 | 871 | static const struct exynos_drm_crtc_ops fimd_crtc_ops = { |
3cecda03 GP |
872 | .enable = fimd_enable, |
873 | .disable = fimd_disable, | |
1c6244c3 SP |
874 | .commit = fimd_commit, |
875 | .enable_vblank = fimd_enable_vblank, | |
876 | .disable_vblank = fimd_disable_vblank, | |
877 | .wait_for_vblank = fimd_wait_for_vblank, | |
ce3ff36b | 878 | .atomic_begin = fimd_atomic_begin, |
9cc7610a GP |
879 | .update_plane = fimd_update_plane, |
880 | .disable_plane = fimd_disable_plane, | |
ce3ff36b | 881 | .atomic_flush = fimd_atomic_flush, |
3854fab2 | 882 | .te_handler = fimd_te_handler, |
48107d7b | 883 | .clock_enable = fimd_dp_clock_enable, |
1c248b7d ID |
884 | }; |
885 | ||
1c248b7d ID |
886 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
887 | { | |
888 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
cb11b3f1 | 889 | u32 val, clear_bit, start, start_s; |
822f6dfd | 890 | int win; |
1c248b7d ID |
891 | |
892 | val = readl(ctx->regs + VIDINTCON1); | |
893 | ||
3854fab2 YC |
894 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
895 | if (val & clear_bit) | |
896 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 897 | |
ec05da95 | 898 | /* check the crtc is detached already from encoder */ |
080be03d | 899 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 900 | goto out; |
483b88f8 | 901 | |
fc75f710 GP |
902 | if (!ctx->i80_if) |
903 | drm_crtc_handle_vblank(&ctx->crtc->base); | |
904 | ||
822f6dfd GP |
905 | for (win = 0 ; win < WINDOWS_NR ; win++) { |
906 | struct exynos_drm_plane *plane = &ctx->planes[win]; | |
907 | ||
908 | if (!plane->pending_fb) | |
909 | continue; | |
910 | ||
cb11b3f1 GP |
911 | start = readl(ctx->regs + VIDWx_BUF_START(win, 0)); |
912 | start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0)); | |
913 | if (start == start_s) | |
914 | exynos_drm_crtc_finish_update(ctx->crtc, plane); | |
822f6dfd | 915 | } |
adf67abf | 916 | |
fc75f710 | 917 | if (ctx->i80_if) { |
1c905d95 | 918 | /* Exits triggering mode */ |
3854fab2 | 919 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 920 | } else { |
3854fab2 YC |
921 | /* set wait vsync event to zero and wake up queue. */ |
922 | if (atomic_read(&ctx->wait_vsync_event)) { | |
923 | atomic_set(&ctx->wait_vsync_event, 0); | |
924 | wake_up(&ctx->wait_vsync_queue); | |
925 | } | |
01ce113c | 926 | } |
3854fab2 | 927 | |
ec05da95 | 928 | out: |
1c248b7d ID |
929 | return IRQ_HANDLED; |
930 | } | |
931 | ||
f37cd5e8 | 932 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 933 | { |
e152dbd7 | 934 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 935 | struct drm_device *drm_dev = data; |
cdbfca89 | 936 | struct exynos_drm_private *priv = drm_dev->dev_private; |
7ee14cdc | 937 | struct exynos_drm_plane *exynos_plane; |
fd2d2fc2 | 938 | unsigned int i; |
6e2a3b66 | 939 | int ret; |
000cc920 | 940 | |
cdbfca89 HH |
941 | ctx->drm_dev = drm_dev; |
942 | ctx->pipe = priv->pipe++; | |
efa75bcd | 943 | |
fd2d2fc2 MS |
944 | for (i = 0; i < WINDOWS_NR; i++) { |
945 | ctx->configs[i].pixel_formats = fimd_formats; | |
946 | ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); | |
947 | ctx->configs[i].zpos = i; | |
948 | ctx->configs[i].type = fimd_win_types[i]; | |
40bdfb0a | 949 | ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, |
fd2d2fc2 | 950 | 1 << ctx->pipe, &ctx->configs[i]); |
7ee14cdc GP |
951 | if (ret) |
952 | return ret; | |
953 | } | |
954 | ||
5d3d0995 | 955 | exynos_plane = &ctx->planes[DEFAULT_WIN]; |
7ee14cdc GP |
956 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
957 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
0f04cf8d | 958 | &fimd_crtc_ops, ctx); |
d1222842 HH |
959 | if (IS_ERR(ctx->crtc)) |
960 | return PTR_ERR(ctx->crtc); | |
93bca243 | 961 | |
cf67cc9a | 962 | if (ctx->encoder) |
a2986e80 | 963 | exynos_dpi_bind(drm_dev, ctx->encoder); |
000cc920 | 964 | |
43a3b866 JS |
965 | if (is_drm_iommu_supported(drm_dev)) |
966 | fimd_clear_channels(ctx->crtc); | |
eb7a3fc7 JS |
967 | |
968 | ret = drm_iommu_attach_device(drm_dev, dev); | |
fc2e013f HH |
969 | if (ret) |
970 | priv->pipe--; | |
971 | ||
972 | return ret; | |
000cc920 AH |
973 | } |
974 | ||
975 | static void fimd_unbind(struct device *dev, struct device *master, | |
976 | void *data) | |
977 | { | |
e152dbd7 | 978 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 979 | |
3cecda03 | 980 | fimd_disable(ctx->crtc); |
000cc920 | 981 | |
bf56608a | 982 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
cdbfca89 | 983 | |
cf67cc9a GP |
984 | if (ctx->encoder) |
985 | exynos_dpi_remove(ctx->encoder); | |
000cc920 AH |
986 | } |
987 | ||
988 | static const struct component_ops fimd_component_ops = { | |
989 | .bind = fimd_bind, | |
990 | .unbind = fimd_unbind, | |
991 | }; | |
992 | ||
993 | static int fimd_probe(struct platform_device *pdev) | |
994 | { | |
995 | struct device *dev = &pdev->dev; | |
562ad9f4 | 996 | struct fimd_context *ctx; |
3854fab2 | 997 | struct device_node *i80_if_timings; |
562ad9f4 | 998 | struct resource *res; |
fe42cfb4 | 999 | int ret; |
1c248b7d | 1000 | |
e152dbd7 AH |
1001 | if (!dev->of_node) |
1002 | return -ENODEV; | |
2d3f173c | 1003 | |
d873ab99 | 1004 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
1005 | if (!ctx) |
1006 | return -ENOMEM; | |
1007 | ||
bb7704d6 | 1008 | ctx->dev = dev; |
a43b933b | 1009 | ctx->suspended = true; |
3854fab2 | 1010 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
bb7704d6 | 1011 | |
1417f109 SP |
1012 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
1013 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1014 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1015 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1016 | |
3854fab2 YC |
1017 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1018 | if (i80_if_timings) { | |
1019 | u32 val; | |
1020 | ||
1021 | ctx->i80_if = true; | |
1022 | ||
1023 | if (ctx->driver_data->has_vidoutcon) | |
1024 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1025 | else | |
1026 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1027 | /* | |
1028 | * The user manual describes that this "DSI_EN" bit is required | |
1029 | * to enable I80 24-bit data interface. | |
1030 | */ | |
1031 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1032 | ||
1033 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1034 | val = 0; | |
1035 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1036 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1037 | val = 0; | |
1038 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1039 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1040 | val = 1; | |
1041 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1042 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1043 | val = 0; | |
1044 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1045 | } | |
1046 | of_node_put(i80_if_timings); | |
1047 | ||
1048 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1049 | "samsung,sysreg"); | |
1050 | if (IS_ERR(ctx->sysreg)) { | |
1051 | dev_warn(dev, "failed to get system register.\n"); | |
1052 | ctx->sysreg = NULL; | |
1053 | } | |
1054 | ||
a968e727 SP |
1055 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1056 | if (IS_ERR(ctx->bus_clk)) { | |
1057 | dev_err(dev, "failed to get bus clock\n"); | |
86650408 | 1058 | return PTR_ERR(ctx->bus_clk); |
a968e727 SP |
1059 | } |
1060 | ||
1061 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1062 | if (IS_ERR(ctx->lcd_clk)) { | |
1063 | dev_err(dev, "failed to get lcd clock\n"); | |
86650408 | 1064 | return PTR_ERR(ctx->lcd_clk); |
a968e727 | 1065 | } |
1c248b7d | 1066 | |
1c248b7d | 1067 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 1068 | |
d873ab99 | 1069 | ctx->regs = devm_ioremap_resource(dev, res); |
86650408 AH |
1070 | if (IS_ERR(ctx->regs)) |
1071 | return PTR_ERR(ctx->regs); | |
1c248b7d | 1072 | |
3854fab2 YC |
1073 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
1074 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
1c248b7d ID |
1075 | if (!res) { |
1076 | dev_err(dev, "irq request failed.\n"); | |
86650408 | 1077 | return -ENXIO; |
1c248b7d ID |
1078 | } |
1079 | ||
055e0c06 | 1080 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
1081 | 0, "drm_fimd", ctx); |
1082 | if (ret) { | |
1c248b7d | 1083 | dev_err(dev, "irq request failed.\n"); |
86650408 | 1084 | return ret; |
1c248b7d ID |
1085 | } |
1086 | ||
57ed0f7b | 1087 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1088 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1089 | |
e152dbd7 | 1090 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1091 | |
cf67cc9a GP |
1092 | ctx->encoder = exynos_dpi_probe(dev); |
1093 | if (IS_ERR(ctx->encoder)) | |
1094 | return PTR_ERR(ctx->encoder); | |
f37cd5e8 | 1095 | |
e152dbd7 | 1096 | pm_runtime_enable(dev); |
f37cd5e8 | 1097 | |
e152dbd7 | 1098 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1099 | if (ret) |
1100 | goto err_disable_pm_runtime; | |
1101 | ||
1102 | return ret; | |
1103 | ||
1104 | err_disable_pm_runtime: | |
e152dbd7 | 1105 | pm_runtime_disable(dev); |
df5225bc | 1106 | |
df5225bc | 1107 | return ret; |
f37cd5e8 | 1108 | } |
cb91f6a0 | 1109 | |
f37cd5e8 ID |
1110 | static int fimd_remove(struct platform_device *pdev) |
1111 | { | |
af65c804 | 1112 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1113 | |
df5225bc | 1114 | component_del(&pdev->dev, &fimd_component_ops); |
df5225bc | 1115 | |
5d55393a | 1116 | return 0; |
e30d4bcf ID |
1117 | } |
1118 | ||
41571976 GP |
1119 | #ifdef CONFIG_PM |
1120 | static int exynos_fimd_suspend(struct device *dev) | |
1121 | { | |
1122 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1123 | ||
1124 | clk_disable_unprepare(ctx->lcd_clk); | |
1125 | clk_disable_unprepare(ctx->bus_clk); | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static int exynos_fimd_resume(struct device *dev) | |
1131 | { | |
1132 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1133 | int ret; | |
1134 | ||
1135 | ret = clk_prepare_enable(ctx->bus_clk); | |
1136 | if (ret < 0) { | |
1137 | DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); | |
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | ret = clk_prepare_enable(ctx->lcd_clk); | |
1142 | if (ret < 0) { | |
1143 | DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); | |
1144 | return ret; | |
1145 | } | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | #endif | |
1150 | ||
1151 | static const struct dev_pm_ops exynos_fimd_pm_ops = { | |
1152 | SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL) | |
1153 | }; | |
1154 | ||
132a5b91 | 1155 | struct platform_driver fimd_driver = { |
1c248b7d | 1156 | .probe = fimd_probe, |
56550d94 | 1157 | .remove = fimd_remove, |
1c248b7d ID |
1158 | .driver = { |
1159 | .name = "exynos4-fb", | |
1160 | .owner = THIS_MODULE, | |
41571976 | 1161 | .pm = &exynos_fimd_pm_ops, |
2d3f173c | 1162 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1163 | }, |
1164 | }; |