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drm/exynos: control blending of mixer graphic layer 0
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_hdmi.c
CommitLineData
d8408326
SWK		 1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
760285e7
DH		 17#include <drm/drmP.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_crtc_helper.h>
d8408326
SWK		 20
21#include "regs-hdmi.h"
22
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/wait.h>
26#include <linux/i2c.h>
d8408326
SWK		 27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
33#include <linux/regulator/consumer.h>
22c4f428 34#include <linux/io.h>
3f1c781d 35#include <linux/of.h>
d5e9ca4c 36#include <linux/of_address.h>
22c4f428 37#include <linux/of_gpio.h>
d34d59bd 38#include <linux/hdmi.h>
f37cd5e8 39#include <linux/component.h>
049d34e9
RS		 40#include <linux/mfd/syscon.h>
41#include <linux/regmap.h>
d8408326
SWK		 42
43#include <drm/exynos_drm.h>
44
45#include "exynos_drm_drv.h"
f37cd5e8 46#include "exynos_drm_crtc.h"
f041b257 47#include "exynos_mixer.h"
d8408326 48
fca57122
TS		 49#include <linux/gpio.h>
50#include <media/s5p_hdmi.h>
51
f041b257 52#define get_hdmi_display(dev) platform_get_drvdata(to_platform_device(dev))
d9716ee3 53#define ctx_from_connector(c) container_of(c, struct hdmi_context, connector)
d8408326 54
724fd140
SP		 55#define HOTPLUG_DEBOUNCE_MS 1100
56
a144c2e9
RS		 57/* AVI header and aspect ratio */
58#define HDMI_AVI_VERSION 0x02
59#define HDMI_AVI_LENGTH 0x0D
a144c2e9
RS		 60
61/* AUI header info */
62#define HDMI_AUI_VERSION 0x01
63#define HDMI_AUI_LENGTH 0x0A
46154152
S		 64#define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
65#define AVI_4_3_CENTER_RATIO 0x9
66#define AVI_16_9_CENTER_RATIO 0xa
a144c2e9 67
5a325071
RS		 68enum hdmi_type {
69 HDMI_TYPE13,
70 HDMI_TYPE14,
71};
72
bfe4e84c
ID		 73struct hdmi_driver_data {
74 unsigned int type;
d5e9ca4c
RS		 75 const struct hdmiphy_config *phy_confs;
76 unsigned int phy_conf_count;
bfe4e84c
ID		 77 unsigned int is_apb_phy:1;
78};
79
590f418a
JS		 80struct hdmi_resources {
81 struct clk *hdmi;
82 struct clk *sclk_hdmi;
83 struct clk *sclk_pixel;
84 struct clk *sclk_hdmiphy;
59956d35 85 struct clk *mout_hdmi;
590f418a 86 struct regulator_bulk_data *regul_bulk;
05fdf987 87 struct regulator *reg_hdmi_en;
590f418a
JS		 88 int regul_count;
89};
90
2f7e2ed0
SP		 91struct hdmi_tg_regs {
92 u8 cmd[1];
93 u8 h_fsz[2];
94 u8 hact_st[2];
95 u8 hact_sz[2];
96 u8 v_fsz[2];
97 u8 vsync[2];
98 u8 vsync2[2];
99 u8 vact_st[2];
100 u8 vact_sz[2];
101 u8 field_chg[2];
102 u8 vact_st2[2];
103 u8 vact_st3[2];
104 u8 vact_st4[2];
105 u8 vsync_top_hdmi[2];
106 u8 vsync_bot_hdmi[2];
107 u8 field_top_hdmi[2];
108 u8 field_bot_hdmi[2];
109 u8 tg_3d[1];
110};
111
6b986edf
RS		 112struct hdmi_v13_core_regs {
113 u8 h_blank[2];
114 u8 v_blank[3];
115 u8 h_v_line[3];
116 u8 vsync_pol[1];
117 u8 int_pro_mode[1];
118 u8 v_blank_f[3];
119 u8 h_sync_gen[3];
120 u8 v_sync_gen1[3];
121 u8 v_sync_gen2[3];
122 u8 v_sync_gen3[3];
123};
124
125struct hdmi_v14_core_regs {
2f7e2ed0
SP		 126 u8 h_blank[2];
127 u8 v2_blank[2];
128 u8 v1_blank[2];
129 u8 v_line[2];
130 u8 h_line[2];
131 u8 hsync_pol[1];
132 u8 vsync_pol[1];
133 u8 int_pro_mode[1];
134 u8 v_blank_f0[2];
135 u8 v_blank_f1[2];
136 u8 h_sync_start[2];
137 u8 h_sync_end[2];
138 u8 v_sync_line_bef_2[2];
139 u8 v_sync_line_bef_1[2];
140 u8 v_sync_line_aft_2[2];
141 u8 v_sync_line_aft_1[2];
142 u8 v_sync_line_aft_pxl_2[2];
143 u8 v_sync_line_aft_pxl_1[2];
144 u8 v_blank_f2[2]; /* for 3D mode */
145 u8 v_blank_f3[2]; /* for 3D mode */
146 u8 v_blank_f4[2]; /* for 3D mode */
147 u8 v_blank_f5[2]; /* for 3D mode */
148 u8 v_sync_line_aft_3[2];
149 u8 v_sync_line_aft_4[2];
150 u8 v_sync_line_aft_5[2];
151 u8 v_sync_line_aft_6[2];
152 u8 v_sync_line_aft_pxl_3[2];
153 u8 v_sync_line_aft_pxl_4[2];
154 u8 v_sync_line_aft_pxl_5[2];
155 u8 v_sync_line_aft_pxl_6[2];
156 u8 vact_space_1[2];
157 u8 vact_space_2[2];
158 u8 vact_space_3[2];
159 u8 vact_space_4[2];
160 u8 vact_space_5[2];
161 u8 vact_space_6[2];
162};
163
6b986edf
RS		 164struct hdmi_v13_conf {
165 struct hdmi_v13_core_regs core;
166 struct hdmi_tg_regs tg;
167};
168
2f7e2ed0 169struct hdmi_v14_conf {
6b986edf 170 struct hdmi_v14_core_regs core;
2f7e2ed0 171 struct hdmi_tg_regs tg;
6b986edf
RS		 172};
173
174struct hdmi_conf_regs {
175 int pixel_clock;
2f7e2ed0 176 int cea_video_id;
46154152 177 enum hdmi_picture_aspect aspect_ratio;
6b986edf
RS		 178 union {
179 struct hdmi_v13_conf v13_conf;
180 struct hdmi_v14_conf v14_conf;
181 } conf;
2f7e2ed0
SP		 182};
183
590f418a
JS		 184struct hdmi_context {
185 struct device *dev;
186 struct drm_device *drm_dev;
d9716ee3
SP		 187 struct drm_connector connector;
188 struct drm_encoder *encoder;
cf8fc4f1
JS		 189 bool hpd;
190 bool powered;
872d20d6 191 bool dvi_mode;
cf8fc4f1 192 struct mutex hdmi_mutex;
590f418a 193
590f418a 194 void __iomem *regs;
77006a7a 195 int irq;
724fd140 196 struct delayed_work hotplug_work;
590f418a 197
8fa04aae 198 struct i2c_adapter *ddc_adpt;
590f418a
JS		 199 struct i2c_client *hdmiphy_port;
200
6b986edf 201 /* current hdmiphy conf regs */
bfa48423 202 struct drm_display_mode current_mode;
6b986edf 203 struct hdmi_conf_regs mode_conf;
590f418a
JS		 204
205 struct hdmi_resources res;
7ecd34e8 206
fca57122 207 int hpd_gpio;
d5e9ca4c
RS		 208 void __iomem *regs_hdmiphy;
209 const struct hdmiphy_config *phy_confs;
210 unsigned int phy_conf_count;
5a325071 211
049d34e9 212 struct regmap *pmureg;
5a325071 213 enum hdmi_type type;
590f418a
JS		 214};
215
6b986edf
RS		 216struct hdmiphy_config {
217 int pixel_clock;
218 u8 conf[32];
d8408326
SWK		 219};
220
6b986edf
RS		 221/* list of phy config settings */
222static const struct hdmiphy_config hdmiphy_v13_configs[] = {
223 {
224 .pixel_clock = 27000000,
225 .conf = {
226 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
227 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
228 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
229 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
230 },
d8408326 231 },
6b986edf
RS		 232 {
233 .pixel_clock = 27027000,
234 .conf = {
235 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
236 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
237 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
238 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
239 },
d8408326 240 },
6b986edf
RS		 241 {
242 .pixel_clock = 74176000,
243 .conf = {
244 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
245 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
246 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
247 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
248 },
d8408326 249 },
6b986edf
RS		 250 {
251 .pixel_clock = 74250000,
252 .conf = {
253 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
254 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
255 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
256 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
257 },
d8408326 258 },
6b986edf
RS		 259 {
260 .pixel_clock = 148500000,
261 .conf = {
262 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
263 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
264 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
265 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
266 },
d8408326
SWK		 267 },
268};
269
2f7e2ed0
SP		 270static const struct hdmiphy_config hdmiphy_v14_configs[] = {
271 {
272 .pixel_clock = 25200000,
273 .conf = {
274 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
275 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
276 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
277 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
278 },
3ecd70b1 279 },
2f7e2ed0
SP		 280 {
281 .pixel_clock = 27000000,
282 .conf = {
283 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
284 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
285 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
286 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
287 },
3ecd70b1 288 },
2f7e2ed0
SP		 289 {
290 .pixel_clock = 27027000,
291 .conf = {
292 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
293 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
294 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
295 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
296 },
3ecd70b1 297 },
2f7e2ed0
SP		 298 {
299 .pixel_clock = 36000000,
300 .conf = {
301 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
302 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
303 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
304 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
305 },
3ecd70b1 306 },
2f7e2ed0
SP		 307 {
308 .pixel_clock = 40000000,
309 .conf = {
310 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
311 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
312 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
313 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
314 },
3ecd70b1 315 },
2f7e2ed0
SP		 316 {
317 .pixel_clock = 65000000,
318 .conf = {
319 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
320 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
321 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
322 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
323 },
3ecd70b1 324 },
e1d883c0
S		 325 {
326 .pixel_clock = 71000000,
327 .conf = {
96d2653a
S		 328 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
329 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
330 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
e1d883c0
S		 331 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
332 },
333 },
334 {
335 .pixel_clock = 73250000,
336 .conf = {
96d2653a
S		 337 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
338 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
339 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
e1d883c0
S		 340 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
341 },
342 },
2f7e2ed0
SP		 343 {
344 .pixel_clock = 74176000,
345 .conf = {
346 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
347 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
348 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
349 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
350 },
3ecd70b1 351 },
2f7e2ed0
SP		 352 {
353 .pixel_clock = 74250000,
354 .conf = {
355 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
356 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
357 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
358 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
359 },
e540adf3 360 },
2f7e2ed0
SP		 361 {
362 .pixel_clock = 83500000,
363 .conf = {
364 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
365 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
366 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
367 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
368 },
e540adf3 369 },
2f7e2ed0
SP		 370 {
371 .pixel_clock = 106500000,
372 .conf = {
373 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
374 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
375 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
376 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
377 },
3ecd70b1 378 },
2f7e2ed0
SP		 379 {
380 .pixel_clock = 108000000,
381 .conf = {
382 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
383 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
384 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
385 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
386 },
3ecd70b1 387 },
e1d883c0
S		 388 {
389 .pixel_clock = 115500000,
390 .conf = {
96d2653a
S		 391 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
392 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
393 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
e1d883c0
S		 394 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
395 },
396 },
397 {
398 .pixel_clock = 119000000,
399 .conf = {
96d2653a
S		 400 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
401 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
402 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
e1d883c0
S		 403 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
404 },
405 },
2f7e2ed0
SP		 406 {
407 .pixel_clock = 146250000,
408 .conf = {
409 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
410 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
411 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
412 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
413 },
3ecd70b1 414 },
2f7e2ed0
SP		 415 {
416 .pixel_clock = 148500000,
417 .conf = {
418 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
419 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
420 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
421 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
422 },
3ecd70b1
JS		 423 },
424};
425
a18a2dda
RS		 426static const struct hdmiphy_config hdmiphy_5420_configs[] = {
427 {
428 .pixel_clock = 25200000,
429 .conf = {
430 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
431 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
432 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
433 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
434 },
435 },
436 {
437 .pixel_clock = 27000000,
438 .conf = {
439 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
440 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
441 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
442 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
443 },
444 },
445 {
446 .pixel_clock = 27027000,
447 .conf = {
448 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
449 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
450 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
451 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
452 },
453 },
454 {
455 .pixel_clock = 36000000,
456 .conf = {
457 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
458 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
459 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
460 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
461 },
462 },
463 {
464 .pixel_clock = 40000000,
465 .conf = {
466 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
467 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
468 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
469 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
470 },
471 },
472 {
473 .pixel_clock = 65000000,
474 .conf = {
475 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
476 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
477 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
478 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
479 },
480 },
481 {
482 .pixel_clock = 71000000,
483 .conf = {
484 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
485 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
486 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
487 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
488 },
489 },
490 {
491 .pixel_clock = 73250000,
492 .conf = {
493 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
494 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
495 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
496 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
497 },
498 },
499 {
500 .pixel_clock = 74176000,
501 .conf = {
502 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
503 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
504 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
505 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
506 },
507 },
508 {
509 .pixel_clock = 74250000,
510 .conf = {
511 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
512 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
513 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
514 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
515 },
516 },
517 {
518 .pixel_clock = 83500000,
519 .conf = {
520 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
521 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
522 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
523 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
524 },
525 },
526 {
527 .pixel_clock = 88750000,
528 .conf = {
529 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
530 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
531 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
532 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
533 },
534 },
535 {
536 .pixel_clock = 106500000,
537 .conf = {
538 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
539 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
540 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
541 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
542 },
543 },
544 {
545 .pixel_clock = 108000000,
546 .conf = {
547 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
548 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
549 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
550 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
551 },
552 },
553 {
554 .pixel_clock = 115500000,
555 .conf = {
556 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
557 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
558 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
559 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
560 },
561 },
562 {
563 .pixel_clock = 146250000,
564 .conf = {
565 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
566 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
567 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
568 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
569 },
570 },
571 {
572 .pixel_clock = 148500000,
573 .conf = {
574 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
575 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
576 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
577 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
578 },
579 },
580};
581
16337077 582static struct hdmi_driver_data exynos5420_hdmi_driver_data = {
a18a2dda
RS		 583 .type = HDMI_TYPE14,
584 .phy_confs = hdmiphy_5420_configs,
585 .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs),
586 .is_apb_phy = 1,
587};
d5e9ca4c 588
16337077 589static struct hdmi_driver_data exynos4212_hdmi_driver_data = {
d5e9ca4c
RS		 590 .type = HDMI_TYPE14,
591 .phy_confs = hdmiphy_v14_configs,
592 .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
593 .is_apb_phy = 0,
594};
595
ff830c96
MS		 596static struct hdmi_driver_data exynos4210_hdmi_driver_data = {
597 .type = HDMI_TYPE13,
598 .phy_confs = hdmiphy_v13_configs,
599 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
600 .is_apb_phy = 0,
601};
602
16337077 603static struct hdmi_driver_data exynos5_hdmi_driver_data = {
d5e9ca4c
RS		 604 .type = HDMI_TYPE14,
605 .phy_confs = hdmiphy_v13_configs,
606 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
607 .is_apb_phy = 0,
608};
609
d8408326
SWK		 610static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
611{
612 return readl(hdata->regs + reg_id);
613}
614
615static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
616 u32 reg_id, u8 value)
617{
618 writeb(value, hdata->regs + reg_id);
619}
620
621static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
622 u32 reg_id, u32 value, u32 mask)
623{
624 u32 old = readl(hdata->regs + reg_id);
625 value = (value & mask) | (old & ~mask);
626 writel(value, hdata->regs + reg_id);
627}
628
d5e9ca4c
RS		 629static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
630 u32 reg_offset, u8 value)
631{
632 if (hdata->hdmiphy_port) {
633 u8 buffer[2];
634 int ret;
635
636 buffer[0] = reg_offset;
637 buffer[1] = value;
638
639 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
640 if (ret == 2)
641 return 0;
642 return ret;
643 } else {
644 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
645 return 0;
646 }
647}
648
649static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
650 u32 reg_offset, const u8 *buf, u32 len)
651{
652 if ((reg_offset + len) > 32)
653 return -EINVAL;
654
655 if (hdata->hdmiphy_port) {
656 int ret;
657
658 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
659 if (ret == len)
660 return 0;
661 return ret;
662 } else {
663 int i;
664 for (i = 0; i < len; i++)
665 writeb(buf[i], hdata->regs_hdmiphy +
666 ((reg_offset + i)<<2));
667 return 0;
668 }
669}
670
3ecd70b1 671static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
d8408326
SWK		 672{
673#define DUMPREG(reg_id) \
674 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
675 readl(hdata->regs + reg_id))
676 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
677 DUMPREG(HDMI_INTC_FLAG);
678 DUMPREG(HDMI_INTC_CON);
679 DUMPREG(HDMI_HPD_STATUS);
3ecd70b1
JS		 680 DUMPREG(HDMI_V13_PHY_RSTOUT);
681 DUMPREG(HDMI_V13_PHY_VPLL);
682 DUMPREG(HDMI_V13_PHY_CMU);
683 DUMPREG(HDMI_V13_CORE_RSTOUT);
684
685 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
686 DUMPREG(HDMI_CON_0);
687 DUMPREG(HDMI_CON_1);
688 DUMPREG(HDMI_CON_2);
689 DUMPREG(HDMI_SYS_STATUS);
690 DUMPREG(HDMI_V13_PHY_STATUS);
691 DUMPREG(HDMI_STATUS_EN);
692 DUMPREG(HDMI_HPD);
693 DUMPREG(HDMI_MODE_SEL);
694 DUMPREG(HDMI_V13_HPD_GEN);
695 DUMPREG(HDMI_V13_DC_CONTROL);
696 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
697
698 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
699 DUMPREG(HDMI_H_BLANK_0);
700 DUMPREG(HDMI_H_BLANK_1);
701 DUMPREG(HDMI_V13_V_BLANK_0);
702 DUMPREG(HDMI_V13_V_BLANK_1);
703 DUMPREG(HDMI_V13_V_BLANK_2);
704 DUMPREG(HDMI_V13_H_V_LINE_0);
705 DUMPREG(HDMI_V13_H_V_LINE_1);
706 DUMPREG(HDMI_V13_H_V_LINE_2);
707 DUMPREG(HDMI_VSYNC_POL);
708 DUMPREG(HDMI_INT_PRO_MODE);
709 DUMPREG(HDMI_V13_V_BLANK_F_0);
710 DUMPREG(HDMI_V13_V_BLANK_F_1);
711 DUMPREG(HDMI_V13_V_BLANK_F_2);
712 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
713 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
714 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
715 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
716 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
717 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
718 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
719 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
720 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
721 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
722 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
723 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
724
725 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
726 DUMPREG(HDMI_TG_CMD);
727 DUMPREG(HDMI_TG_H_FSZ_L);
728 DUMPREG(HDMI_TG_H_FSZ_H);
729 DUMPREG(HDMI_TG_HACT_ST_L);
730 DUMPREG(HDMI_TG_HACT_ST_H);
731 DUMPREG(HDMI_TG_HACT_SZ_L);
732 DUMPREG(HDMI_TG_HACT_SZ_H);
733 DUMPREG(HDMI_TG_V_FSZ_L);
734 DUMPREG(HDMI_TG_V_FSZ_H);
735 DUMPREG(HDMI_TG_VSYNC_L);
736 DUMPREG(HDMI_TG_VSYNC_H);
737 DUMPREG(HDMI_TG_VSYNC2_L);
738 DUMPREG(HDMI_TG_VSYNC2_H);
739 DUMPREG(HDMI_TG_VACT_ST_L);
740 DUMPREG(HDMI_TG_VACT_ST_H);
741 DUMPREG(HDMI_TG_VACT_SZ_L);
742 DUMPREG(HDMI_TG_VACT_SZ_H);
743 DUMPREG(HDMI_TG_FIELD_CHG_L);
744 DUMPREG(HDMI_TG_FIELD_CHG_H);
745 DUMPREG(HDMI_TG_VACT_ST2_L);
746 DUMPREG(HDMI_TG_VACT_ST2_H);
747 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
748 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
749 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
750 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
751 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
752 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
753 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
754 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
755#undef DUMPREG
756}
757
758static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
759{
760 int i;
761
762#define DUMPREG(reg_id) \
763 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
764 readl(hdata->regs + reg_id))
765
766 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
767 DUMPREG(HDMI_INTC_CON);
768 DUMPREG(HDMI_INTC_FLAG);
769 DUMPREG(HDMI_HPD_STATUS);
770 DUMPREG(HDMI_INTC_CON_1);
771 DUMPREG(HDMI_INTC_FLAG_1);
772 DUMPREG(HDMI_PHY_STATUS_0);
773 DUMPREG(HDMI_PHY_STATUS_PLL);
774 DUMPREG(HDMI_PHY_CON_0);
d8408326
SWK		 775 DUMPREG(HDMI_PHY_RSTOUT);
776 DUMPREG(HDMI_PHY_VPLL);
777 DUMPREG(HDMI_PHY_CMU);
778 DUMPREG(HDMI_CORE_RSTOUT);
779
780 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
781 DUMPREG(HDMI_CON_0);
782 DUMPREG(HDMI_CON_1);
783 DUMPREG(HDMI_CON_2);
784 DUMPREG(HDMI_SYS_STATUS);
3ecd70b1 785 DUMPREG(HDMI_PHY_STATUS_0);
d8408326
SWK		 786 DUMPREG(HDMI_STATUS_EN);
787 DUMPREG(HDMI_HPD);
788 DUMPREG(HDMI_MODE_SEL);
3ecd70b1 789 DUMPREG(HDMI_ENC_EN);
d8408326
SWK		 790 DUMPREG(HDMI_DC_CONTROL);
791 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
792
793 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
794 DUMPREG(HDMI_H_BLANK_0);
795 DUMPREG(HDMI_H_BLANK_1);
3ecd70b1
JS		 796 DUMPREG(HDMI_V2_BLANK_0);
797 DUMPREG(HDMI_V2_BLANK_1);
798 DUMPREG(HDMI_V1_BLANK_0);
799 DUMPREG(HDMI_V1_BLANK_1);
800 DUMPREG(HDMI_V_LINE_0);
801 DUMPREG(HDMI_V_LINE_1);
802 DUMPREG(HDMI_H_LINE_0);
803 DUMPREG(HDMI_H_LINE_1);
804 DUMPREG(HDMI_HSYNC_POL);
805
d8408326
SWK		 806 DUMPREG(HDMI_VSYNC_POL);
807 DUMPREG(HDMI_INT_PRO_MODE);
3ecd70b1
JS		 808 DUMPREG(HDMI_V_BLANK_F0_0);
809 DUMPREG(HDMI_V_BLANK_F0_1);
810 DUMPREG(HDMI_V_BLANK_F1_0);
811 DUMPREG(HDMI_V_BLANK_F1_1);
812
813 DUMPREG(HDMI_H_SYNC_START_0);
814 DUMPREG(HDMI_H_SYNC_START_1);
815 DUMPREG(HDMI_H_SYNC_END_0);
816 DUMPREG(HDMI_H_SYNC_END_1);
817
818 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
819 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
820 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
821 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
822
823 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
824 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
825 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
826 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
827
828 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
829 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
830 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
831 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
832
833 DUMPREG(HDMI_V_BLANK_F2_0);
834 DUMPREG(HDMI_V_BLANK_F2_1);
835 DUMPREG(HDMI_V_BLANK_F3_0);
836 DUMPREG(HDMI_V_BLANK_F3_1);
837 DUMPREG(HDMI_V_BLANK_F4_0);
838 DUMPREG(HDMI_V_BLANK_F4_1);
839 DUMPREG(HDMI_V_BLANK_F5_0);
840 DUMPREG(HDMI_V_BLANK_F5_1);
841
842 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
843 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
844 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
845 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
846 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
847 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
848 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
849 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
850
851 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
852 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
853 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
854 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
855 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
856 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
857 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
858 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
859
860 DUMPREG(HDMI_VACT_SPACE_1_0);
861 DUMPREG(HDMI_VACT_SPACE_1_1);
862 DUMPREG(HDMI_VACT_SPACE_2_0);
863 DUMPREG(HDMI_VACT_SPACE_2_1);
864 DUMPREG(HDMI_VACT_SPACE_3_0);
865 DUMPREG(HDMI_VACT_SPACE_3_1);
866 DUMPREG(HDMI_VACT_SPACE_4_0);
867 DUMPREG(HDMI_VACT_SPACE_4_1);
868 DUMPREG(HDMI_VACT_SPACE_5_0);
869 DUMPREG(HDMI_VACT_SPACE_5_1);
870 DUMPREG(HDMI_VACT_SPACE_6_0);
871 DUMPREG(HDMI_VACT_SPACE_6_1);
d8408326
SWK		 872
873 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
874 DUMPREG(HDMI_TG_CMD);
875 DUMPREG(HDMI_TG_H_FSZ_L);
876 DUMPREG(HDMI_TG_H_FSZ_H);
877 DUMPREG(HDMI_TG_HACT_ST_L);
878 DUMPREG(HDMI_TG_HACT_ST_H);
879 DUMPREG(HDMI_TG_HACT_SZ_L);
880 DUMPREG(HDMI_TG_HACT_SZ_H);
881 DUMPREG(HDMI_TG_V_FSZ_L);
882 DUMPREG(HDMI_TG_V_FSZ_H);
883 DUMPREG(HDMI_TG_VSYNC_L);
884 DUMPREG(HDMI_TG_VSYNC_H);
885 DUMPREG(HDMI_TG_VSYNC2_L);
886 DUMPREG(HDMI_TG_VSYNC2_H);
887 DUMPREG(HDMI_TG_VACT_ST_L);
888 DUMPREG(HDMI_TG_VACT_ST_H);
889 DUMPREG(HDMI_TG_VACT_SZ_L);
890 DUMPREG(HDMI_TG_VACT_SZ_H);
891 DUMPREG(HDMI_TG_FIELD_CHG_L);
892 DUMPREG(HDMI_TG_FIELD_CHG_H);
893 DUMPREG(HDMI_TG_VACT_ST2_L);
894 DUMPREG(HDMI_TG_VACT_ST2_H);
3ecd70b1
JS		 895 DUMPREG(HDMI_TG_VACT_ST3_L);
896 DUMPREG(HDMI_TG_VACT_ST3_H);
897 DUMPREG(HDMI_TG_VACT_ST4_L);
898 DUMPREG(HDMI_TG_VACT_ST4_H);
d8408326
SWK		 899 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
900 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
901 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
902 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
903 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
904 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
905 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
906 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
3ecd70b1
JS		 907 DUMPREG(HDMI_TG_3D);
908
909 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
910 DUMPREG(HDMI_AVI_CON);
911 DUMPREG(HDMI_AVI_HEADER0);
912 DUMPREG(HDMI_AVI_HEADER1);
913 DUMPREG(HDMI_AVI_HEADER2);
914 DUMPREG(HDMI_AVI_CHECK_SUM);
915 DUMPREG(HDMI_VSI_CON);
916 DUMPREG(HDMI_VSI_HEADER0);
917 DUMPREG(HDMI_VSI_HEADER1);
918 DUMPREG(HDMI_VSI_HEADER2);
919 for (i = 0; i < 7; ++i)
920 DUMPREG(HDMI_VSI_DATA(i));
921
d8408326
SWK		 922#undef DUMPREG
923}
924
3ecd70b1
JS		 925static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
926{
5a325071 927 if (hdata->type == HDMI_TYPE13)
3ecd70b1
JS		 928 hdmi_v13_regs_dump(hdata, prefix);
929 else
930 hdmi_v14_regs_dump(hdata, prefix);
931}
932
a144c2e9
RS		 933static u8 hdmi_chksum(struct hdmi_context *hdata,
934 u32 start, u8 len, u32 hdr_sum)
935{
936 int i;
937
938 /* hdr_sum : header0 + header1 + header2
939 * start : start address of packet byte1
940 * len : packet bytes - 1 */
941 for (i = 0; i < len; ++i)
942 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
943
944 /* return 2's complement of 8 bit hdr_sum */
945 return (u8)(~(hdr_sum & 0xff) + 1);
946}
947
948static void hdmi_reg_infoframe(struct hdmi_context *hdata,
d34d59bd 949 union hdmi_infoframe *infoframe)
a144c2e9
RS		 950{
951 u32 hdr_sum;
952 u8 chksum;
a144c2e9
RS		 953 u32 mod;
954 u32 vic;
955
a144c2e9
RS		 956 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
957 if (hdata->dvi_mode) {
958 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
959 HDMI_VSI_CON_DO_NOT_TRANSMIT);
960 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
961 HDMI_AVI_CON_DO_NOT_TRANSMIT);
962 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
963 return;
964 }
965
d34d59bd
SK		 966 switch (infoframe->any.type) {
967 case HDMI_INFOFRAME_TYPE_AVI:
a144c2e9 968 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
d34d59bd
SK		 969 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
970 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
971 infoframe->any.version);
972 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
973 hdr_sum = infoframe->any.type + infoframe->any.version +
974 infoframe->any.length;
a144c2e9
RS		 975
976 /* Output format zero hardcoded ,RGB YBCR selection */
977 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
978 AVI_ACTIVE_FORMAT_VALID |
979 AVI_UNDERSCANNED_DISPLAY_VALID);
980
46154152
S		 981 /*
982 * Set the aspect ratio as per the mode, mentioned in
983 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
984 */
985 switch (hdata->mode_conf.aspect_ratio) {
986 case HDMI_PICTURE_ASPECT_4_3:
987 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
988 hdata->mode_conf.aspect_ratio |
989 AVI_4_3_CENTER_RATIO);
990 break;
991 case HDMI_PICTURE_ASPECT_16_9:
992 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
993 hdata->mode_conf.aspect_ratio |
994 AVI_16_9_CENTER_RATIO);
995 break;
996 case HDMI_PICTURE_ASPECT_NONE:
997 default:
998 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
999 hdata->mode_conf.aspect_ratio |
1000 AVI_SAME_AS_PIC_ASPECT_RATIO);
1001 break;
1002 }
a144c2e9 1003
6b986edf 1004 vic = hdata->mode_conf.cea_video_id;
a144c2e9
RS		 1005 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
1006
1007 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
d34d59bd 1008 infoframe->any.length, hdr_sum);
a144c2e9
RS		 1009 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1010 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1011 break;
d34d59bd 1012 case HDMI_INFOFRAME_TYPE_AUDIO:
a144c2e9 1013 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
d34d59bd
SK		 1014 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
1015 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
1016 infoframe->any.version);
1017 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
1018 hdr_sum = infoframe->any.type + infoframe->any.version +
1019 infoframe->any.length;
a144c2e9 1020 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
d34d59bd 1021 infoframe->any.length, hdr_sum);
a144c2e9
RS		 1022 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1023 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1024 break;
1025 default:
1026 break;
1027 }
1028}
1029
d9716ee3
SP		 1030static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
1031 bool force)
4551789f 1032{
d9716ee3 1033 struct hdmi_context *hdata = ctx_from_connector(connector);
4551789f 1034
5137c8ca
SP		 1035 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1036
d9716ee3
SP		 1037 return hdata->hpd ? connector_status_connected :
1038 connector_status_disconnected;
4551789f
SP		 1039}
1040
d9716ee3 1041static void hdmi_connector_destroy(struct drm_connector *connector)
d8408326 1042{
d8408326
SWK		 1043}
1044
d9716ee3
SP		 1045static struct drm_connector_funcs hdmi_connector_funcs = {
1046 .dpms = drm_helper_connector_dpms,
1047 .fill_modes = drm_helper_probe_single_connector_modes,
1048 .detect = hdmi_detect,
1049 .destroy = hdmi_connector_destroy,
1050};
1051
1052static int hdmi_get_modes(struct drm_connector *connector)
d8408326 1053{
d9716ee3
SP		 1054 struct hdmi_context *hdata = ctx_from_connector(connector);
1055 struct edid *edid;
d8408326 1056
8fa04aae 1057 if (!hdata->ddc_adpt)
d9716ee3 1058 return -ENODEV;
d8408326 1059
8fa04aae 1060 edid = drm_get_edid(connector, hdata->ddc_adpt);
d9716ee3
SP		 1061 if (!edid)
1062 return -ENODEV;
9c08e4ba 1063
d9716ee3 1064 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
9c08e4ba
RS		 1065 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
1066 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
d9716ee3 1067 edid->width_cm, edid->height_cm);
d8408326 1068
d9716ee3
SP		 1069 drm_mode_connector_update_edid_property(connector, edid);
1070
1071 return drm_add_edid_modes(connector, edid);
d8408326
SWK		 1072}
1073
6b986edf 1074static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
d8408326 1075{
d5e9ca4c 1076 int i;
6b986edf 1077
d5e9ca4c
RS		 1078 for (i = 0; i < hdata->phy_conf_count; i++)
1079 if (hdata->phy_confs[i].pixel_clock == pixel_clock)
2f7e2ed0 1080 return i;
2f7e2ed0
SP		 1081
1082 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1083 return -EINVAL;
1084}
1085
d9716ee3 1086static int hdmi_mode_valid(struct drm_connector *connector,
f041b257 1087 struct drm_display_mode *mode)
3ecd70b1 1088{
d9716ee3 1089 struct hdmi_context *hdata = ctx_from_connector(connector);
6b986edf 1090 int ret;
3ecd70b1 1091
16844fb1
RS		 1092 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1093 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1094 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
1095 false, mode->clock * 1000);
3ecd70b1 1096
f041b257
SP		 1097 ret = mixer_check_mode(mode);
1098 if (ret)
d9716ee3 1099 return MODE_BAD;
f041b257 1100
16844fb1 1101 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
6b986edf 1102 if (ret < 0)
d9716ee3
SP		 1103 return MODE_BAD;
1104
1105 return MODE_OK;
1106}
1107
1108static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
1109{
1110 struct hdmi_context *hdata = ctx_from_connector(connector);
1111
1112 return hdata->encoder;
1113}
1114
1115static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
1116 .get_modes = hdmi_get_modes,
1117 .mode_valid = hdmi_mode_valid,
1118 .best_encoder = hdmi_best_encoder,
1119};
1120
1121static int hdmi_create_connector(struct exynos_drm_display *display,
1122 struct drm_encoder *encoder)
1123{
1124 struct hdmi_context *hdata = display->ctx;
1125 struct drm_connector *connector = &hdata->connector;
1126 int ret;
1127
1128 hdata->encoder = encoder;
1129 connector->interlace_allowed = true;
1130 connector->polled = DRM_CONNECTOR_POLL_HPD;
1131
1132 ret = drm_connector_init(hdata->drm_dev, connector,
1133 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1134 if (ret) {
1135 DRM_ERROR("Failed to initialize connector with drm\n");
6b986edf 1136 return ret;
d9716ee3
SP		 1137 }
1138
1139 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
34ea3d38 1140 drm_connector_register(connector);
d9716ee3
SP		 1141 drm_mode_connector_attach_encoder(connector, encoder);
1142
1143 return 0;
1144}
1145
f041b257
SP		 1146static void hdmi_mode_fixup(struct exynos_drm_display *display,
1147 struct drm_connector *connector,
1148 const struct drm_display_mode *mode,
1149 struct drm_display_mode *adjusted_mode)
1150{
1151 struct drm_display_mode *m;
1152 int mode_ok;
1153
1154 DRM_DEBUG_KMS("%s\n", __FILE__);
1155
1156 drm_mode_set_crtcinfo(adjusted_mode, 0);
1157
d9716ee3 1158 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
f041b257
SP		 1159
1160 /* just return if user desired mode exists. */
d9716ee3 1161 if (mode_ok == MODE_OK)
f041b257
SP		 1162 return;
1163
1164 /*
1165 * otherwise, find the most suitable mode among modes and change it
1166 * to adjusted_mode.
1167 */
1168 list_for_each_entry(m, &connector->modes, head) {
d9716ee3 1169 mode_ok = hdmi_mode_valid(connector, m);
f041b257 1170
d9716ee3 1171 if (mode_ok == MODE_OK) {
f041b257
SP		 1172 DRM_INFO("desired mode doesn't exist so\n");
1173 DRM_INFO("use the most suitable mode among modes.\n");
1174
1175 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1176 m->hdisplay, m->vdisplay, m->vrefresh);
1177
75626853 1178 drm_mode_copy(adjusted_mode, m);
f041b257
SP		 1179 break;
1180 }
1181 }
1182}
1183
3e148baf
SWK		 1184static void hdmi_set_acr(u32 freq, u8 *acr)
1185{
1186 u32 n, cts;
1187
1188 switch (freq) {
1189 case 32000:
1190 n = 4096;
1191 cts = 27000;
1192 break;
1193 case 44100:
1194 n = 6272;
1195 cts = 30000;
1196 break;
1197 case 88200:
1198 n = 12544;
1199 cts = 30000;
1200 break;
1201 case 176400:
1202 n = 25088;
1203 cts = 30000;
1204 break;
1205 case 48000:
1206 n = 6144;
1207 cts = 27000;
1208 break;
1209 case 96000:
1210 n = 12288;
1211 cts = 27000;
1212 break;
1213 case 192000:
1214 n = 24576;
1215 cts = 27000;
1216 break;
1217 default:
1218 n = 0;
1219 cts = 0;
1220 break;
1221 }
1222
1223 acr[1] = cts >> 16;
1224 acr[2] = cts >> 8 & 0xff;
1225 acr[3] = cts & 0xff;
1226
1227 acr[4] = n >> 16;
1228 acr[5] = n >> 8 & 0xff;
1229 acr[6] = n & 0xff;
1230}
1231
1232static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1233{
1234 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1235 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1236 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1237 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1238 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1239 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1240 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1241 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1242 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1243
5a325071 1244 if (hdata->type == HDMI_TYPE13)
3e148baf
SWK		 1245 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1246 else
1247 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1248}
1249
1250static void hdmi_audio_init(struct hdmi_context *hdata)
1251{
7a9bf6e5 1252 u32 sample_rate, bits_per_sample;
3e148baf
SWK		 1253 u32 data_num, bit_ch, sample_frq;
1254 u32 val;
1255 u8 acr[7];
1256
1257 sample_rate = 44100;
1258 bits_per_sample = 16;
3e148baf
SWK		 1259
1260 switch (bits_per_sample) {
1261 case 20:
1262 data_num = 2;
1263 bit_ch = 1;
1264 break;
1265 case 24:
1266 data_num = 3;
1267 bit_ch = 1;
1268 break;
1269 default:
1270 data_num = 1;
1271 bit_ch = 0;
1272 break;
1273 }
1274
1275 hdmi_set_acr(sample_rate, acr);
1276 hdmi_reg_acr(hdata, acr);
1277
1278 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1279 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1280 | HDMI_I2S_MUX_ENABLE);
1281
1282 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1283 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1284
1285 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1286
1287 sample_frq = (sample_rate == 44100) ? 0 :
1288 (sample_rate == 48000) ? 2 :
1289 (sample_rate == 32000) ? 3 :
1290 (sample_rate == 96000) ? 0xa : 0x0;
1291
1292 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1293 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1294
1295 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1296 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1297
1298 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1299 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1300 | HDMI_I2S_SEL_LRCK(6));
1301 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1302 | HDMI_I2S_SEL_SDATA2(4));
1303 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1304 | HDMI_I2S_SEL_SDATA2(2));
1305 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1306
1307 /* I2S_CON_1 & 2 */
1308 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1309 | HDMI_I2S_L_CH_LOW_POL);
1310 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1311 | HDMI_I2S_SET_BIT_CH(bit_ch)
1312 | HDMI_I2S_SET_SDATA_BIT(data_num)
1313 | HDMI_I2S_BASIC_FORMAT);
1314
1315 /* Configure register related to CUV information */
1316 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1317 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1318 | HDMI_I2S_COPYRIGHT
1319 | HDMI_I2S_LINEAR_PCM
1320 | HDMI_I2S_CONSUMER_FORMAT);
1321 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1322 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1323 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1324 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1325 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1326 HDMI_I2S_ORG_SMP_FREQ_44_1
1327 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1328 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1329
1330 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1331}
1332
1333static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1334{
872d20d6 1335 if (hdata->dvi_mode)
3e148baf
SWK		 1336 return;
1337
1338 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1339 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1340 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1341}
1342
bfa48423 1343static void hdmi_start(struct hdmi_context *hdata, bool start)
d8408326 1344{
bfa48423 1345 u32 val = start ? HDMI_TG_EN : 0;
3ecd70b1 1346
bfa48423
RS		 1347 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1348 val |= HDMI_FIELD_EN;
3ecd70b1 1349
bfa48423
RS		 1350 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1351 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
d8408326
SWK		 1352}
1353
1354static void hdmi_conf_init(struct hdmi_context *hdata)
1355{
d34d59bd 1356 union hdmi_infoframe infoframe;
a144c2e9 1357
77006a7a 1358 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
d8408326
SWK		 1359 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1360 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
d8408326
SWK		 1361
1362 /* choose HDMI mode */
1363 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1364 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
9a8e1cb0
S		 1365 /* Apply Video preable and Guard band in HDMI mode only */
1366 hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
d8408326
SWK		 1367 /* disable bluescreen */
1368 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
3ecd70b1 1369
872d20d6
SWK		 1370 if (hdata->dvi_mode) {
1371 /* choose DVI mode */
1372 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1373 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1374 hdmi_reg_writeb(hdata, HDMI_CON_2,
1375 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1376 }
1377
5a325071 1378 if (hdata->type == HDMI_TYPE13) {
3ecd70b1
JS		 1379 /* choose bluescreen (fecal) color */
1380 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1381 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1382 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1383
1384 /* enable AVI packet every vsync, fixes purple line problem */
1385 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1386 /* force RGB, look to CEA-861-D, table 7 for more detail */
1387 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1388 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1389
1390 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1391 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1392 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1393 } else {
d34d59bd
SK		 1394 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1395 infoframe.any.version = HDMI_AVI_VERSION;
1396 infoframe.any.length = HDMI_AVI_LENGTH;
a144c2e9
RS		 1397 hdmi_reg_infoframe(hdata, &infoframe);
1398
d34d59bd
SK		 1399 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1400 infoframe.any.version = HDMI_AUI_VERSION;
1401 infoframe.any.length = HDMI_AUI_LENGTH;
a144c2e9
RS		 1402 hdmi_reg_infoframe(hdata, &infoframe);
1403
3ecd70b1 1404 /* enable AVI packet every vsync, fixes purple line problem */
3ecd70b1
JS		 1405 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1406 }
d8408326
SWK		 1407}
1408
16844fb1 1409static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
d8408326 1410{
6b986edf
RS		 1411 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1412 const struct hdmi_v13_core_regs *core =
1413 &hdata->mode_conf.conf.v13_conf.core;
3ecd70b1
JS		 1414 int tries;
1415
1416 /* setting core registers */
1417 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1418 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1419 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1420 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1421 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1422 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1423 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1424 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1425 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1426 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1427 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1428 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1429 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1430 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1431 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1432 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1433 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1434 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1435 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1436 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1437 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1438 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1439 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1440 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1441 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1442 /* Timing generator registers */
6b986edf
RS		 1443 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1444 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1445 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1446 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1447 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1448 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1449 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1450 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1451 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1452 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1453 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1454 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1455 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1456 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1457 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1458 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1459 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1460 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1461 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1462 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1463 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1464 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1465 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1466 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1467 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1468 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1469 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1470 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
3ecd70b1
JS		 1471
1472 /* waiting for HDMIPHY's PLL to get to steady state */
1473 for (tries = 100; tries; --tries) {
1474 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1475 if (val & HDMI_PHY_STATUS_READY)
1476 break;
09760ea3 1477 usleep_range(1000, 2000);
3ecd70b1
JS		 1478 }
1479 /* steady state not achieved */
1480 if (tries == 0) {
1481 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1482 hdmi_regs_dump(hdata, "timing apply");
1483 }
1484
0bfb1f8b 1485 clk_disable_unprepare(hdata->res.sclk_hdmi);
59956d35 1486 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
0bfb1f8b 1487 clk_prepare_enable(hdata->res.sclk_hdmi);
3ecd70b1
JS		 1488
1489 /* enable HDMI and timing generator */
bfa48423 1490 hdmi_start(hdata, true);
3ecd70b1
JS		 1491}
1492
16844fb1 1493static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
3ecd70b1 1494{
6b986edf
RS		 1495 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1496 const struct hdmi_v14_core_regs *core =
1497 &hdata->mode_conf.conf.v14_conf.core;
d8408326
SWK		 1498 int tries;
1499
1500 /* setting core registers */
1501 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1502 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
3ecd70b1
JS		 1503 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1504 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1505 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1506 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1507 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1508 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1509 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1510 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1511 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
d8408326
SWK		 1512 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1513 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
3ecd70b1
JS		 1514 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1515 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1516 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1517 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1518 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1519 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1520 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1521 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1522 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1523 core->v_sync_line_bef_2[0]);
1524 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1525 core->v_sync_line_bef_2[1]);
1526 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1527 core->v_sync_line_bef_1[0]);
1528 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1529 core->v_sync_line_bef_1[1]);
1530 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1531 core->v_sync_line_aft_2[0]);
1532 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1533 core->v_sync_line_aft_2[1]);
1534 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1535 core->v_sync_line_aft_1[0]);
1536 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1537 core->v_sync_line_aft_1[1]);
1538 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1539 core->v_sync_line_aft_pxl_2[0]);
1540 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1541 core->v_sync_line_aft_pxl_2[1]);
1542 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1543 core->v_sync_line_aft_pxl_1[0]);
1544 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1545 core->v_sync_line_aft_pxl_1[1]);
1546 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1547 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1548 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1549 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1550 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1551 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1552 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1553 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1554 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1555 core->v_sync_line_aft_3[0]);
1556 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1557 core->v_sync_line_aft_3[1]);
1558 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1559 core->v_sync_line_aft_4[0]);
1560 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1561 core->v_sync_line_aft_4[1]);
1562 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1563 core->v_sync_line_aft_5[0]);
1564 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1565 core->v_sync_line_aft_5[1]);
1566 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1567 core->v_sync_line_aft_6[0]);
1568 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1569 core->v_sync_line_aft_6[1]);
1570 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1571 core->v_sync_line_aft_pxl_3[0]);
1572 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1573 core->v_sync_line_aft_pxl_3[1]);
1574 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1575 core->v_sync_line_aft_pxl_4[0]);
1576 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1577 core->v_sync_line_aft_pxl_4[1]);
1578 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1579 core->v_sync_line_aft_pxl_5[0]);
1580 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1581 core->v_sync_line_aft_pxl_5[1]);
1582 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1583 core->v_sync_line_aft_pxl_6[0]);
1584 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1585 core->v_sync_line_aft_pxl_6[1]);
1586 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1587 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1588 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1589 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1590 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1591 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1592 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1593 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1594 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1595 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1596 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1597 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1598
d8408326 1599 /* Timing generator registers */
2f7e2ed0
SP		 1600 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1601 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1602 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1603 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1604 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1605 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1606 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1607 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1608 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1609 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1610 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1611 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1612 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1613 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1614 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1615 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1616 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1617 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1618 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1619 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1620 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1621 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1622 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1623 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1624 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1625 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1626 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1627 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1628 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1629 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1630 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1631 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1632 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
d8408326
SWK		 1633
1634 /* waiting for HDMIPHY's PLL to get to steady state */
1635 for (tries = 100; tries; --tries) {
3ecd70b1 1636 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
d8408326
SWK		 1637 if (val & HDMI_PHY_STATUS_READY)
1638 break;
09760ea3 1639 usleep_range(1000, 2000);
d8408326
SWK		 1640 }
1641 /* steady state not achieved */
1642 if (tries == 0) {
1643 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1644 hdmi_regs_dump(hdata, "timing apply");
1645 }
1646
0bfb1f8b 1647 clk_disable_unprepare(hdata->res.sclk_hdmi);
59956d35 1648 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
0bfb1f8b 1649 clk_prepare_enable(hdata->res.sclk_hdmi);
d8408326
SWK		 1650
1651 /* enable HDMI and timing generator */
bfa48423 1652 hdmi_start(hdata, true);
d8408326
SWK		 1653}
1654
16844fb1 1655static void hdmi_mode_apply(struct hdmi_context *hdata)
3ecd70b1 1656{
5a325071 1657 if (hdata->type == HDMI_TYPE13)
16844fb1 1658 hdmi_v13_mode_apply(hdata);
3ecd70b1 1659 else
16844fb1 1660 hdmi_v14_mode_apply(hdata);
3ecd70b1
JS		 1661}
1662
d8408326
SWK		 1663static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1664{
1665 u8 buffer[2];
3ecd70b1 1666 u32 reg;
d8408326 1667
0bfb1f8b 1668 clk_disable_unprepare(hdata->res.sclk_hdmi);
59956d35 1669 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
0bfb1f8b 1670 clk_prepare_enable(hdata->res.sclk_hdmi);
d8408326
SWK		 1671
1672 /* operation mode */
1673 buffer[0] = 0x1f;
1674 buffer[1] = 0x00;
1675
1676 if (hdata->hdmiphy_port)
1677 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1678
5a325071 1679 if (hdata->type == HDMI_TYPE13)
3ecd70b1
JS		 1680 reg = HDMI_V13_PHY_RSTOUT;
1681 else
1682 reg = HDMI_PHY_RSTOUT;
1683
d8408326 1684 /* reset hdmiphy */
3ecd70b1 1685 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
09760ea3 1686 usleep_range(10000, 12000);
3ecd70b1 1687 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
09760ea3 1688 usleep_range(10000, 12000);
d8408326
SWK		 1689}
1690
a5562257
RS		 1691static void hdmiphy_poweron(struct hdmi_context *hdata)
1692{
6a296e20
S		 1693 if (hdata->type != HDMI_TYPE14)
1694 return;
1695
1696 DRM_DEBUG_KMS("\n");
1697
1698 /* For PHY Mode Setting */
1699 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1700 HDMI_PHY_ENABLE_MODE_SET);
1701 /* Phy Power On */
1702 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1703 HDMI_PHY_POWER_ON);
1704 /* For PHY Mode Setting */
1705 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1706 HDMI_PHY_DISABLE_MODE_SET);
1707 /* PHY SW Reset */
1708 hdmiphy_conf_reset(hdata);
a5562257
RS		 1709}
1710
1711static void hdmiphy_poweroff(struct hdmi_context *hdata)
1712{
6a296e20
S		 1713 if (hdata->type != HDMI_TYPE14)
1714 return;
1715
1716 DRM_DEBUG_KMS("\n");
1717
1718 /* PHY SW Reset */
1719 hdmiphy_conf_reset(hdata);
1720 /* For PHY Mode Setting */
1721 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1722 HDMI_PHY_ENABLE_MODE_SET);
1723
1724 /* PHY Power Off */
1725 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1726 HDMI_PHY_POWER_OFF);
1727
1728 /* For PHY Mode Setting */
1729 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1730 HDMI_PHY_DISABLE_MODE_SET);
a5562257
RS		 1731}
1732
d8408326
SWK		 1733static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1734{
d8408326
SWK		 1735 int ret;
1736 int i;
1737
d8408326 1738 /* pixel clock */
6b986edf
RS		 1739 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1740 if (i < 0) {
1741 DRM_ERROR("failed to find hdmiphy conf\n");
1742 return;
1743 }
1744
d5e9ca4c
RS		 1745 ret = hdmiphy_reg_write_buf(hdata, 0, hdata->phy_confs[i].conf, 32);
1746 if (ret) {
1747 DRM_ERROR("failed to configure hdmiphy\n");
d8408326
SWK		 1748 return;
1749 }
1750
09760ea3 1751 usleep_range(10000, 12000);
d8408326 1752
d5e9ca4c
RS		 1753 ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1754 HDMI_PHY_DISABLE_MODE_SET);
1755 if (ret) {
d8408326
SWK		 1756 DRM_ERROR("failed to enable hdmiphy\n");
1757 return;
1758 }
1759
d8408326
SWK		 1760}
1761
1762static void hdmi_conf_apply(struct hdmi_context *hdata)
1763{
d8408326
SWK		 1764 hdmiphy_conf_reset(hdata);
1765 hdmiphy_conf_apply(hdata);
1766
cf8fc4f1 1767 mutex_lock(&hdata->hdmi_mutex);
bfa48423 1768 hdmi_start(hdata, false);
d8408326 1769 hdmi_conf_init(hdata);
cf8fc4f1
JS		 1770 mutex_unlock(&hdata->hdmi_mutex);
1771
3e148baf 1772 hdmi_audio_init(hdata);
d8408326
SWK		 1773
1774 /* setting core registers */
16844fb1 1775 hdmi_mode_apply(hdata);
3e148baf 1776 hdmi_audio_control(hdata, true);
d8408326
SWK		 1777
1778 hdmi_regs_dump(hdata, "start");
1779}
1780
2f7e2ed0
SP		 1781static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1782{
1783 int i;
1784 BUG_ON(num_bytes > 4);
1785 for (i = 0; i < num_bytes; i++)
1786 reg_pair[i] = (value >> (8 * i)) & 0xff;
1787}
1788
6b986edf 1789static void hdmi_v13_mode_set(struct hdmi_context *hdata,
2f7e2ed0
SP		 1790 struct drm_display_mode *m)
1791{
6b986edf
RS		 1792 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1793 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1794 unsigned int val;
2f7e2ed0 1795
6b986edf
RS		 1796 hdata->mode_conf.cea_video_id =
1797 drm_match_cea_mode((struct drm_display_mode *)m);
1798 hdata->mode_conf.pixel_clock = m->clock * 1000;
46154152 1799 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
6b986edf
RS		 1800
1801 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1802 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1803
1804 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1805 hdmi_set_reg(core->vsync_pol, 1, val);
1806
1807 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1808 hdmi_set_reg(core->int_pro_mode, 1, val);
1809
1810 val = (m->hsync_start - m->hdisplay - 2);
1811 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1812 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1813 hdmi_set_reg(core->h_sync_gen, 3, val);
1814
1815 /*
1816 * Quirk requirement for exynos HDMI IP design,
1817 * 2 pixels less than the actual calculation for hsync_start
1818 * and end.
1819 */
1820
1821 /* Following values & calculations differ for different type of modes */
1822 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1823 /* Interlaced Mode */
1824 val = ((m->vsync_end - m->vdisplay) / 2);
1825 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1826 hdmi_set_reg(core->v_sync_gen1, 3, val);
1827
1828 val = m->vtotal / 2;
1829 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1830 hdmi_set_reg(core->v_blank, 3, val);
1831
1832 val = (m->vtotal +
1833 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1834 val |= m->vtotal << 11;
1835 hdmi_set_reg(core->v_blank_f, 3, val);
1836
1837 val = ((m->vtotal / 2) + 7);
1838 val |= ((m->vtotal / 2) + 2) << 12;
1839 hdmi_set_reg(core->v_sync_gen2, 3, val);
1840
1841 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1842 val |= ((m->htotal / 2) +
1843 (m->hsync_start - m->hdisplay)) << 12;
1844 hdmi_set_reg(core->v_sync_gen3, 3, val);
1845
1846 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1847 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1848
1849 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1850 } else {
1851 /* Progressive Mode */
1852
1853 val = m->vtotal;
1854 val |= (m->vtotal - m->vdisplay) << 11;
1855 hdmi_set_reg(core->v_blank, 3, val);
1856
1857 hdmi_set_reg(core->v_blank_f, 3, 0);
2f7e2ed0 1858
6b986edf
RS		 1859 val = (m->vsync_end - m->vdisplay);
1860 val |= ((m->vsync_start - m->vdisplay) << 12);
1861 hdmi_set_reg(core->v_sync_gen1, 3, val);
1862
1863 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1864 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1865 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1866 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1867 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1868 }
1869
1870 /* Timing generator registers */
1871 hdmi_set_reg(tg->cmd, 1, 0x0);
1872 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1873 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1874 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1875 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1876 hdmi_set_reg(tg->vsync, 2, 0x1);
1877 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1878 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1879 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1880 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1881 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1882 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1883 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1884}
1885
1886static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1887 struct drm_display_mode *m)
1888{
1889 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1890 struct hdmi_v14_core_regs *core =
1891 &hdata->mode_conf.conf.v14_conf.core;
1892
1893 hdata->mode_conf.cea_video_id =
1894 drm_match_cea_mode((struct drm_display_mode *)m);
2f7e2ed0 1895 hdata->mode_conf.pixel_clock = m->clock * 1000;
46154152 1896 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
6b986edf 1897
2f7e2ed0
SP		 1898 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1899 hdmi_set_reg(core->v_line, 2, m->vtotal);
1900 hdmi_set_reg(core->h_line, 2, m->htotal);
1901 hdmi_set_reg(core->hsync_pol, 1,
1902 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1903 hdmi_set_reg(core->vsync_pol, 1,
1904 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1905 hdmi_set_reg(core->int_pro_mode, 1,
1906 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1907
1908 /*
1909 * Quirk requirement for exynos 5 HDMI IP design,
1910 * 2 pixels less than the actual calculation for hsync_start
1911 * and end.
1912 */
1913
1914 /* Following values & calculations differ for different type of modes */
1915 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1916 /* Interlaced Mode */
1917 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1918 (m->vsync_end - m->vdisplay) / 2);
1919 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1920 (m->vsync_start - m->vdisplay) / 2);
1921 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1922 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1482995c 1923 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
2f7e2ed0
SP		 1924 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1925 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1926 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1927 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1928 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1929 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1930 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1931 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1932 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1482995c
RS		 1933 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1934 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1935 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1936 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
2f7e2ed0
SP		 1937 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1938 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1939 } else {
1940 /* Progressive Mode */
1941 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1942 m->vsync_end - m->vdisplay);
1943 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1944 m->vsync_start - m->vdisplay);
1945 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1946 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1947 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1948 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1949 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1950 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1951 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1952 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1953 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1954 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1955 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1956 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1957 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1482995c
RS		 1958 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1959 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1960 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
2f7e2ed0
SP		 1961 }
1962
1963 /* Following values & calculations are same irrespective of mode type */
1964 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1965 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1966 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1967 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1968 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1969 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1970 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1971 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1972 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1973 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1974 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1975 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1976 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1977 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1978 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1979 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1980 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1981 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1982 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1983 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1984
1985 /* Timing generator registers */
1986 hdmi_set_reg(tg->cmd, 1, 0x0);
1987 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1988 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1989 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1990 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1991 hdmi_set_reg(tg->vsync, 2, 0x1);
2f7e2ed0
SP		 1992 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1993 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
2f7e2ed0 1994 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
2f7e2ed0 1995 hdmi_set_reg(tg->tg_3d, 1, 0x0);
2f7e2ed0
SP		 1996}
1997
f041b257
SP		 1998static void hdmi_mode_set(struct exynos_drm_display *display,
1999 struct drm_display_mode *mode)
d8408326 2000{
f041b257 2001 struct hdmi_context *hdata = display->ctx;
6b986edf 2002 struct drm_display_mode *m = mode;
d8408326 2003
cbc4c33d
YC		 2004 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
2005 m->hdisplay, m->vdisplay,
6b986edf
RS		 2006 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
2007 "INTERLACED" : "PROGERESSIVE");
d8408326 2008
bfa48423
RS		 2009 /* preserve mode information for later use. */
2010 drm_mode_copy(&hdata->current_mode, mode);
2011
5f46c333 2012 if (hdata->type == HDMI_TYPE13)
6b986edf 2013 hdmi_v13_mode_set(hdata, mode);
5f46c333 2014 else
2f7e2ed0 2015 hdmi_v14_mode_set(hdata, mode);
d8408326
SWK		 2016}
2017
f041b257 2018static void hdmi_commit(struct exynos_drm_display *display)
d8408326 2019{
f041b257 2020 struct hdmi_context *hdata = display->ctx;
d8408326 2021
dda9012b
S		 2022 mutex_lock(&hdata->hdmi_mutex);
2023 if (!hdata->powered) {
2024 mutex_unlock(&hdata->hdmi_mutex);
2025 return;
2026 }
2027 mutex_unlock(&hdata->hdmi_mutex);
2028
d8408326 2029 hdmi_conf_apply(hdata);
cf8fc4f1
JS		 2030}
2031
f041b257 2032static void hdmi_poweron(struct exynos_drm_display *display)
cf8fc4f1 2033{
f041b257 2034 struct hdmi_context *hdata = display->ctx;
cf8fc4f1
JS		 2035 struct hdmi_resources *res = &hdata->res;
2036
cf8fc4f1
JS		 2037 mutex_lock(&hdata->hdmi_mutex);
2038 if (hdata->powered) {
2039 mutex_unlock(&hdata->hdmi_mutex);
2040 return;
2041 }
d8408326 2042
cf8fc4f1
JS		 2043 hdata->powered = true;
2044
cf8fc4f1
JS		 2045 mutex_unlock(&hdata->hdmi_mutex);
2046
af65c804
SP		 2047 pm_runtime_get_sync(hdata->dev);
2048
ad07945a
SWK		 2049 if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
2050 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
2051
049d34e9
RS		 2052 /* set pmu hdmiphy control bit to enable hdmiphy */
2053 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2054 PMU_HDMI_PHY_ENABLE_BIT, 1);
2055
0bfb1f8b
SP		 2056 clk_prepare_enable(res->hdmi);
2057 clk_prepare_enable(res->sclk_hdmi);
a5562257
RS		 2058
2059 hdmiphy_poweron(hdata);
f041b257 2060 hdmi_commit(display);
cf8fc4f1
JS		 2061}
2062
f041b257 2063static void hdmi_poweroff(struct exynos_drm_display *display)
cf8fc4f1 2064{
f041b257 2065 struct hdmi_context *hdata = display->ctx;
cf8fc4f1
JS		 2066 struct hdmi_resources *res = &hdata->res;
2067
cf8fc4f1
JS		 2068 mutex_lock(&hdata->hdmi_mutex);
2069 if (!hdata->powered)
2070 goto out;
2071 mutex_unlock(&hdata->hdmi_mutex);
2072
bfa48423
RS		 2073 /* HDMI System Disable */
2074 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
2075
a5562257 2076 hdmiphy_poweroff(hdata);
cf8fc4f1 2077
724fd140
SP		 2078 cancel_delayed_work(&hdata->hotplug_work);
2079
0bfb1f8b
SP		 2080 clk_disable_unprepare(res->sclk_hdmi);
2081 clk_disable_unprepare(res->hdmi);
049d34e9
RS		 2082
2083 /* reset pmu hdmiphy control bit to disable hdmiphy */
2084 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2085 PMU_HDMI_PHY_ENABLE_BIT, 0);
2086
cf8fc4f1
JS		 2087 regulator_bulk_disable(res->regul_count, res->regul_bulk);
2088
af65c804 2089 pm_runtime_put_sync(hdata->dev);
cf8fc4f1 2090
af65c804 2091 mutex_lock(&hdata->hdmi_mutex);
cf8fc4f1
JS		 2092 hdata->powered = false;
2093
2094out:
2095 mutex_unlock(&hdata->hdmi_mutex);
d8408326
SWK		 2096}
2097
f041b257 2098static void hdmi_dpms(struct exynos_drm_display *display, int mode)
d8408326 2099{
245f98f2
ID		 2100 struct hdmi_context *hdata = display->ctx;
2101 struct drm_encoder *encoder = hdata->encoder;
2102 struct drm_crtc *crtc = encoder->crtc;
2103 struct drm_crtc_helper_funcs *funcs = NULL;
2104
cbc4c33d 2105 DRM_DEBUG_KMS("mode %d\n", mode);
d8408326 2106
cf8fc4f1
JS		 2107 switch (mode) {
2108 case DRM_MODE_DPMS_ON:
af65c804 2109 hdmi_poweron(display);
cf8fc4f1
JS		 2110 break;
2111 case DRM_MODE_DPMS_STANDBY:
2112 case DRM_MODE_DPMS_SUSPEND:
2113 case DRM_MODE_DPMS_OFF:
245f98f2
ID		 2114 /*
2115 * The SFRs of VP and Mixer are updated by Vertical Sync of
2116 * Timing generator which is a part of HDMI so the sequence
2117 * to disable TV Subsystem should be as following,
2118 * VP -> Mixer -> HDMI
2119 *
2120 * Below codes will try to disable Mixer and VP(if used)
2121 * prior to disabling HDMI.
2122 */
2123 if (crtc)
2124 funcs = crtc->helper_private;
2125 if (funcs && funcs->dpms)
2126 (*funcs->dpms)(crtc, mode);
2127
af65c804 2128 hdmi_poweroff(display);
cf8fc4f1
JS		 2129 break;
2130 default:
2131 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2132 break;
d8408326
SWK		 2133 }
2134}
2135
f041b257 2136static struct exynos_drm_display_ops hdmi_display_ops = {
d9716ee3 2137 .create_connector = hdmi_create_connector,
f041b257 2138 .mode_fixup = hdmi_mode_fixup,
d8408326 2139 .mode_set = hdmi_mode_set,
f041b257 2140 .dpms = hdmi_dpms,
d8408326 2141 .commit = hdmi_commit,
d8408326
SWK		 2142};
2143
f041b257
SP		 2144static struct exynos_drm_display hdmi_display = {
2145 .type = EXYNOS_DISPLAY_TYPE_HDMI,
2146 .ops = &hdmi_display_ops,
2147};
2148
724fd140 2149static void hdmi_hotplug_work_func(struct work_struct *work)
cf8fc4f1 2150{
724fd140
SP		 2151 struct hdmi_context *hdata;
2152
2153 hdata = container_of(work, struct hdmi_context, hotplug_work.work);
cf8fc4f1 2154
cf8fc4f1 2155 mutex_lock(&hdata->hdmi_mutex);
fca57122 2156 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
cf8fc4f1
JS		 2157 mutex_unlock(&hdata->hdmi_mutex);
2158
4551789f
SP		 2159 if (hdata->drm_dev)
2160 drm_helper_hpd_irq_event(hdata->drm_dev);
724fd140
SP		 2161}
2162
2163static irqreturn_t hdmi_irq_thread(int irq, void *arg)
2164{
2165 struct hdmi_context *hdata = arg;
2166
2167 mod_delayed_work(system_wq, &hdata->hotplug_work,
2168 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
cf8fc4f1 2169
cf8fc4f1
JS		 2170 return IRQ_HANDLED;
2171}
2172
56550d94 2173static int hdmi_resources_init(struct hdmi_context *hdata)
d8408326
SWK		 2174{
2175 struct device *dev = hdata->dev;
2176 struct hdmi_resources *res = &hdata->res;
2177 static char *supply[] = {
d8408326
SWK		 2178 "vdd",
2179 "vdd_osc",
2180 "vdd_pll",
2181 };
2182 int i, ret;
2183
2184 DRM_DEBUG_KMS("HDMI resource init\n");
2185
d8408326 2186 /* get clocks, power */
9f49d9fb 2187 res->hdmi = devm_clk_get(dev, "hdmi");
ee7cbafa 2188 if (IS_ERR(res->hdmi)) {
d8408326 2189 DRM_ERROR("failed to get clock 'hdmi'\n");
df5225bc 2190 ret = PTR_ERR(res->hdmi);
d8408326
SWK		 2191 goto fail;
2192 }
9f49d9fb 2193 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
ee7cbafa 2194 if (IS_ERR(res->sclk_hdmi)) {
d8408326 2195 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
df5225bc 2196 ret = PTR_ERR(res->sclk_hdmi);
d8408326
SWK		 2197 goto fail;
2198 }
9f49d9fb 2199 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
ee7cbafa 2200 if (IS_ERR(res->sclk_pixel)) {
d8408326 2201 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
df5225bc 2202 ret = PTR_ERR(res->sclk_pixel);
d8408326
SWK		 2203 goto fail;
2204 }
9f49d9fb 2205 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
ee7cbafa 2206 if (IS_ERR(res->sclk_hdmiphy)) {
d8408326 2207 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
df5225bc 2208 ret = PTR_ERR(res->sclk_hdmiphy);
d8408326
SWK		 2209 goto fail;
2210 }
59956d35
RS		 2211 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
2212 if (IS_ERR(res->mout_hdmi)) {
2213 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
df5225bc 2214 ret = PTR_ERR(res->mout_hdmi);
59956d35
RS		 2215 goto fail;
2216 }
d8408326 2217
59956d35 2218 clk_set_parent(res->mout_hdmi, res->sclk_pixel);
d8408326 2219
9f49d9fb 2220 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
adc837ac 2221 sizeof(res->regul_bulk[0]), GFP_KERNEL);
df5225bc
ID		 2222 if (!res->regul_bulk) {
2223 ret = -ENOMEM;
d8408326 2224 goto fail;
df5225bc 2225 }
d8408326
SWK		 2226 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2227 res->regul_bulk[i].supply = supply[i];
2228 res->regul_bulk[i].consumer = NULL;
2229 }
9f49d9fb 2230 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
d8408326
SWK		 2231 if (ret) {
2232 DRM_ERROR("failed to get regulators\n");
df5225bc 2233 return ret;
d8408326
SWK		 2234 }
2235 res->regul_count = ARRAY_SIZE(supply);
2236
05fdf987
MS		 2237 res->reg_hdmi_en = devm_regulator_get(dev, "hdmi-en");
2238 if (IS_ERR(res->reg_hdmi_en) && PTR_ERR(res->reg_hdmi_en) != -ENOENT) {
2239 DRM_ERROR("failed to get hdmi-en regulator\n");
2240 return PTR_ERR(res->reg_hdmi_en);
2241 }
2242 if (!IS_ERR(res->reg_hdmi_en)) {
2243 ret = regulator_enable(res->reg_hdmi_en);
2244 if (ret) {
2245 DRM_ERROR("failed to enable hdmi-en regulator\n");
2246 return ret;
2247 }
2248 } else
2249 res->reg_hdmi_en = NULL;
2250
df5225bc 2251 return ret;
d8408326
SWK		 2252fail:
2253 DRM_ERROR("HDMI resource init - failed\n");
df5225bc 2254 return ret;
d8408326
SWK		 2255}
2256
22c4f428
RS		 2257static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
2258 (struct device *dev)
2259{
2260 struct device_node *np = dev->of_node;
2261 struct s5p_hdmi_platform_data *pd;
22c4f428
RS		 2262 u32 value;
2263
2264 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
38bb5253 2265 if (!pd)
22c4f428 2266 goto err_data;
22c4f428
RS		 2267
2268 if (!of_find_property(np, "hpd-gpio", &value)) {
2269 DRM_ERROR("no hpd gpio property found\n");
2270 goto err_data;
2271 }
2272
5f916e28 2273 pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
22c4f428
RS		 2274
2275 return pd;
2276
2277err_data:
2278 return NULL;
2279}
22c4f428
RS		 2280
2281static struct of_device_id hdmi_match_types[] = {
2282 {
2283 .compatible = "samsung,exynos5-hdmi",
bfe4e84c 2284 .data = &exynos5_hdmi_driver_data,
ff830c96
MS		 2285 }, {
2286 .compatible = "samsung,exynos4210-hdmi",
2287 .data = &exynos4210_hdmi_driver_data,
cc57caf0
RS		 2288 }, {
2289 .compatible = "samsung,exynos4212-hdmi",
bfe4e84c 2290 .data = &exynos4212_hdmi_driver_data,
a18a2dda
RS		 2291 }, {
2292 .compatible = "samsung,exynos5420-hdmi",
2293 .data = &exynos5420_hdmi_driver_data,
c119ed05
TS		 2294 }, {
2295 /* end node */
2296 }
2297};
39b58a39 2298MODULE_DEVICE_TABLE (of, hdmi_match_types);
c119ed05 2299
f37cd5e8
ID		 2300static int hdmi_bind(struct device *dev, struct device *master, void *data)
2301{
2302 struct drm_device *drm_dev = data;
2303 struct hdmi_context *hdata;
2304
2305 hdata = hdmi_display.ctx;
2306 hdata->drm_dev = drm_dev;
2307
2308 return exynos_drm_create_enc_conn(drm_dev, &hdmi_display);
2309}
2310
2311static void hdmi_unbind(struct device *dev, struct device *master, void *data)
2312{
2313 struct exynos_drm_display *display = get_hdmi_display(dev);
2314 struct drm_encoder *encoder = display->encoder;
2315 struct hdmi_context *hdata = display->ctx;
2316
2317 encoder->funcs->destroy(encoder);
2318 drm_connector_cleanup(&hdata->connector);
2319}
2320
2321static const struct component_ops hdmi_component_ops = {
2322 .bind = hdmi_bind,
2323 .unbind = hdmi_unbind,
2324};
2325
e2a562dc
ID		 2326static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev)
2327{
2328 const char *compatible_str = "samsung,exynos4210-hdmiddc";
2329 struct device_node *np;
2330
2331 np = of_find_compatible_node(NULL, NULL, compatible_str);
2332 if (np)
2333 return of_get_next_parent(np);
2334
2335 return NULL;
2336}
2337
2338static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
2339{
2340 const char *compatible_str = "samsung,exynos4212-hdmiphy";
2341
2342 return of_find_compatible_node(NULL, NULL, compatible_str);
2343}
2344
56550d94 2345static int hdmi_probe(struct platform_device *pdev)
d8408326 2346{
f37cd5e8
ID		 2347 struct device_node *ddc_node, *phy_node;
2348 struct s5p_hdmi_platform_data *pdata;
2349 struct hdmi_driver_data *drv_data;
2350 const struct of_device_id *match;
d8408326 2351 struct device *dev = &pdev->dev;
d8408326 2352 struct hdmi_context *hdata;
d8408326
SWK		 2353 struct resource *res;
2354 int ret;
2355
df5225bc
ID		 2356 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
2357 hdmi_display.type);
2358 if (ret)
2359 return ret;
2360
2361 if (!dev->of_node) {
2362 ret = -ENODEV;
2363 goto err_del_component;
2364 }
22c4f428 2365
88c49815 2366 pdata = drm_hdmi_dt_parse_pdata(dev);
df5225bc
ID		 2367 if (!pdata) {
2368 ret = -EINVAL;
2369 goto err_del_component;
2370 }
d8408326 2371
88c49815 2372 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
df5225bc
ID		 2373 if (!hdata) {
2374 ret = -ENOMEM;
2375 goto err_del_component;
2376 }
d8408326 2377
cf8fc4f1
JS		 2378 mutex_init(&hdata->hdmi_mutex);
2379
f041b257 2380 platform_set_drvdata(pdev, &hdmi_display);
d8408326 2381
88c49815 2382 match = of_match_node(hdmi_match_types, dev->of_node);
df5225bc
ID		 2383 if (!match) {
2384 ret = -ENODEV;
2385 goto err_del_component;
2386 }
bfe4e84c
ID		 2387
2388 drv_data = (struct hdmi_driver_data *)match->data;
2389 hdata->type = drv_data->type;
d5e9ca4c
RS		 2390 hdata->phy_confs = drv_data->phy_confs;
2391 hdata->phy_conf_count = drv_data->phy_conf_count;
22c4f428 2392
fca57122 2393 hdata->hpd_gpio = pdata->hpd_gpio;
d8408326
SWK		 2394 hdata->dev = dev;
2395
2396 ret = hdmi_resources_init(hdata);
2397 if (ret) {
22c4f428 2398 DRM_ERROR("hdmi_resources_init failed\n");
df5225bc 2399 return ret;
d8408326
SWK		 2400 }
2401
2402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d873ab99 2403 hdata->regs = devm_ioremap_resource(dev, res);
df5225bc
ID		 2404 if (IS_ERR(hdata->regs)) {
2405 ret = PTR_ERR(hdata->regs);
2406 goto err_del_component;
2407 }
d8408326 2408
d873ab99 2409 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
fca57122
TS		 2410 if (ret) {
2411 DRM_ERROR("failed to request HPD gpio\n");
df5225bc 2412 goto err_del_component;
fca57122
TS		 2413 }
2414
e2a562dc
ID		 2415 ddc_node = hdmi_legacy_ddc_dt_binding(dev);
2416 if (ddc_node)
2417 goto out_get_ddc_adpt;
2418
d8408326 2419 /* DDC i2c driver */
2b768132
DK		 2420 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2421 if (!ddc_node) {
2422 DRM_ERROR("Failed to find ddc node in device tree\n");
df5225bc
ID		 2423 ret = -ENODEV;
2424 goto err_del_component;
2b768132 2425 }
e2a562dc
ID		 2426
2427out_get_ddc_adpt:
8fa04aae
ID		 2428 hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2429 if (!hdata->ddc_adpt) {
2430 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
df5225bc 2431 return -EPROBE_DEFER;
d8408326 2432 }
d8408326 2433
e2a562dc
ID		 2434 phy_node = hdmi_legacy_phy_dt_binding(dev);
2435 if (phy_node)
2436 goto out_get_phy_port;
2437
d8408326 2438 /* hdmiphy i2c driver */
2b768132
DK		 2439 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2440 if (!phy_node) {
2441 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2442 ret = -ENODEV;
2443 goto err_ddc;
2444 }
d5e9ca4c 2445
e2a562dc 2446out_get_phy_port:
d5e9ca4c
RS		 2447 if (drv_data->is_apb_phy) {
2448 hdata->regs_hdmiphy = of_iomap(phy_node, 0);
2449 if (!hdata->regs_hdmiphy) {
2450 DRM_ERROR("failed to ioremap hdmi phy\n");
2451 ret = -ENOMEM;
2452 goto err_ddc;
2453 }
2454 } else {
2455 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2456 if (!hdata->hdmiphy_port) {
2457 DRM_ERROR("Failed to get hdmi phy i2c client\n");
df5225bc 2458 ret = -EPROBE_DEFER;
d5e9ca4c
RS		 2459 goto err_ddc;
2460 }
d8408326 2461 }
d8408326 2462
77006a7a
SP		 2463 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2464 if (hdata->irq < 0) {
2465 DRM_ERROR("failed to get GPIO irq\n");
2466 ret = hdata->irq;
cf8fc4f1
JS		 2467 goto err_hdmiphy;
2468 }
2469
fca57122
TS		 2470 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2471
724fd140
SP		 2472 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2473
dcb9a7c7 2474 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
77006a7a 2475 hdmi_irq_thread, IRQF_TRIGGER_RISING |
cf8fc4f1 2476 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
f041b257 2477 "hdmi", hdata);
d8408326 2478 if (ret) {
77006a7a 2479 DRM_ERROR("failed to register hdmi interrupt\n");
66265a2e 2480 goto err_hdmiphy;
d8408326 2481 }
d8408326 2482
049d34e9
RS		 2483 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2484 "samsung,syscon-phandle");
2485 if (IS_ERR(hdata->pmureg)) {
2486 DRM_ERROR("syscon regmap lookup failed.\n");
df5225bc 2487 ret = -EPROBE_DEFER;
049d34e9
RS		 2488 goto err_hdmiphy;
2489 }
2490
af65c804 2491 pm_runtime_enable(dev);
f041b257 2492 hdmi_display.ctx = hdata;
d8408326 2493
df5225bc
ID		 2494 ret = component_add(&pdev->dev, &hdmi_component_ops);
2495 if (ret)
2496 goto err_disable_pm_runtime;
2497
2498 return ret;
2499
2500err_disable_pm_runtime:
2501 pm_runtime_disable(dev);
d8408326 2502
d8408326 2503err_hdmiphy:
b21a3bf4
PT		 2504 if (hdata->hdmiphy_port)
2505 put_device(&hdata->hdmiphy_port->dev);
d8408326 2506err_ddc:
8fa04aae 2507 put_device(&hdata->ddc_adpt->dev);
df5225bc
ID		 2508
2509err_del_component:
2510 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
2511
d8408326
SWK		 2512 return ret;
2513}
2514
56550d94 2515static int hdmi_remove(struct platform_device *pdev)
d8408326 2516{
f37cd5e8 2517 struct hdmi_context *hdata = hdmi_display.ctx;
d8408326 2518
724fd140
SP		 2519 cancel_delayed_work_sync(&hdata->hotplug_work);
2520
05fdf987
MS		 2521 if (hdata->res.reg_hdmi_en)
2522 regulator_disable(hdata->res.reg_hdmi_en);
2523
2b768132 2524 put_device(&hdata->hdmiphy_port->dev);
8fa04aae 2525 put_device(&hdata->ddc_adpt->dev);
f37cd5e8 2526
af65c804 2527 pm_runtime_disable(&pdev->dev);
df5225bc 2528 component_del(&pdev->dev, &hdmi_component_ops);
d8408326 2529
df5225bc 2530 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
d8408326
SWK		 2531 return 0;
2532}
2533
2534struct platform_driver hdmi_driver = {
2535 .probe = hdmi_probe,
56550d94 2536 .remove = hdmi_remove,
d8408326 2537 .driver = {
22c4f428 2538 .name = "exynos-hdmi",
d8408326 2539 .owner = THIS_MODULE,
88c49815 2540 .of_match_table = hdmi_match_types,
d8408326
SWK		 2541 },
2542};
Linux kernel - Deliverables
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