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Merge tag 'stable/for-linus-3.16-rc1-tag' of git://git.kernel.org/pub/scm/linux/kerne...
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_mixer.c
CommitLineData
d8408326
SWK		 1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/mixer_reg.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
760285e7 17#include <drm/drmP.h>
d8408326
SWK		 18
19#include "regs-mixer.h"
20#include "regs-vp.h"
21
22#include <linux/kernel.h>
23#include <linux/spinlock.h>
24#include <linux/wait.h>
25#include <linux/i2c.h>
d8408326
SWK		 26#include <linux/platform_device.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/delay.h>
30#include <linux/pm_runtime.h>
31#include <linux/clk.h>
32#include <linux/regulator/consumer.h>
3f1c781d 33#include <linux/of.h>
f37cd5e8 34#include <linux/component.h>
d8408326
SWK		 35
36#include <drm/exynos_drm.h>
37
38#include "exynos_drm_drv.h"
663d8766 39#include "exynos_drm_crtc.h"
1055b39f 40#include "exynos_drm_iommu.h"
f041b257 41#include "exynos_mixer.h"
22b21ae6 42
f041b257
SP		 43#define get_mixer_manager(dev) platform_get_drvdata(to_platform_device(dev))
44
45#define MIXER_WIN_NR 3
46#define MIXER_DEFAULT_WIN 0
d8408326 47
22b21ae6
JS		 48struct hdmi_win_data {
49 dma_addr_t dma_addr;
22b21ae6 50 dma_addr_t chroma_dma_addr;
22b21ae6
JS		 51 uint32_t pixel_format;
52 unsigned int bpp;
53 unsigned int crtc_x;
54 unsigned int crtc_y;
55 unsigned int crtc_width;
56 unsigned int crtc_height;
57 unsigned int fb_x;
58 unsigned int fb_y;
59 unsigned int fb_width;
60 unsigned int fb_height;
8dcb96b6
SWK		 61 unsigned int src_width;
62 unsigned int src_height;
22b21ae6
JS		 63 unsigned int mode_width;
64 unsigned int mode_height;
65 unsigned int scan_flags;
db43fd16
P		 66 bool enabled;
67 bool resume;
22b21ae6
JS		 68};
69
70struct mixer_resources {
22b21ae6
JS		 71 int irq;
72 void __iomem *mixer_regs;
73 void __iomem *vp_regs;
74 spinlock_t reg_slock;
75 struct clk *mixer;
76 struct clk *vp;
77 struct clk *sclk_mixer;
78 struct clk *sclk_hdmi;
79 struct clk *sclk_dac;
80};
81
1e123441
RS		 82enum mixer_version_id {
83 MXR_VER_0_0_0_16,
84 MXR_VER_16_0_33_0,
def5e095 85 MXR_VER_128_0_0_184,
1e123441
RS		 86};
87
22b21ae6 88struct mixer_context {
4551789f 89 struct platform_device *pdev;
cf8fc4f1 90 struct device *dev;
1055b39f 91 struct drm_device *drm_dev;
22b21ae6
JS		 92 int pipe;
93 bool interlace;
cf8fc4f1 94 bool powered;
1b8e5747 95 bool vp_enabled;
cf8fc4f1 96 u32 int_en;
22b21ae6 97
cf8fc4f1 98 struct mutex mixer_mutex;
22b21ae6 99 struct mixer_resources mixer_res;
a634dd54 100 struct hdmi_win_data win_data[MIXER_WIN_NR];
1e123441 101 enum mixer_version_id mxr_ver;
6e95d5e6
P		 102 wait_queue_head_t wait_vsync_queue;
103 atomic_t wait_vsync_event;
1e123441
RS		 104};
105
106struct mixer_drv_data {
107 enum mixer_version_id version;
1b8e5747 108 bool is_vp_enabled;
22b21ae6
JS		 109};
110
d8408326
SWK		 111static const u8 filter_y_horiz_tap8[] = {
112 0, -1, -1, -1, -1, -1, -1, -1,
113 -1, -1, -1, -1, -1, 0, 0, 0,
114 0, 2, 4, 5, 6, 6, 6, 6,
115 6, 5, 5, 4, 3, 2, 1, 1,
116 0, -6, -12, -16, -18, -20, -21, -20,
117 -20, -18, -16, -13, -10, -8, -5, -2,
118 127, 126, 125, 121, 114, 107, 99, 89,
119 79, 68, 57, 46, 35, 25, 16, 8,
120};
121
122static const u8 filter_y_vert_tap4[] = {
123 0, -3, -6, -8, -8, -8, -8, -7,
124 -6, -5, -4, -3, -2, -1, -1, 0,
125 127, 126, 124, 118, 111, 102, 92, 81,
126 70, 59, 48, 37, 27, 19, 11, 5,
127 0, 5, 11, 19, 27, 37, 48, 59,
128 70, 81, 92, 102, 111, 118, 124, 126,
129 0, 0, -1, -1, -2, -3, -4, -5,
130 -6, -7, -8, -8, -8, -8, -6, -3,
131};
132
133static const u8 filter_cr_horiz_tap4[] = {
134 0, -3, -6, -8, -8, -8, -8, -7,
135 -6, -5, -4, -3, -2, -1, -1, 0,
136 127, 126, 124, 118, 111, 102, 92, 81,
137 70, 59, 48, 37, 27, 19, 11, 5,
138};
139
140static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
141{
142 return readl(res->vp_regs + reg_id);
143}
144
145static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
146 u32 val)
147{
148 writel(val, res->vp_regs + reg_id);
149}
150
151static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
152 u32 val, u32 mask)
153{
154 u32 old = vp_reg_read(res, reg_id);
155
156 val = (val & mask) | (old & ~mask);
157 writel(val, res->vp_regs + reg_id);
158}
159
160static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
161{
162 return readl(res->mixer_regs + reg_id);
163}
164
165static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
166 u32 val)
167{
168 writel(val, res->mixer_regs + reg_id);
169}
170
171static inline void mixer_reg_writemask(struct mixer_resources *res,
172 u32 reg_id, u32 val, u32 mask)
173{
174 u32 old = mixer_reg_read(res, reg_id);
175
176 val = (val & mask) | (old & ~mask);
177 writel(val, res->mixer_regs + reg_id);
178}
179
180static void mixer_regs_dump(struct mixer_context *ctx)
181{
182#define DUMPREG(reg_id) \
183do { \
184 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
185 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
186} while (0)
187
188 DUMPREG(MXR_STATUS);
189 DUMPREG(MXR_CFG);
190 DUMPREG(MXR_INT_EN);
191 DUMPREG(MXR_INT_STATUS);
192
193 DUMPREG(MXR_LAYER_CFG);
194 DUMPREG(MXR_VIDEO_CFG);
195
196 DUMPREG(MXR_GRAPHIC0_CFG);
197 DUMPREG(MXR_GRAPHIC0_BASE);
198 DUMPREG(MXR_GRAPHIC0_SPAN);
199 DUMPREG(MXR_GRAPHIC0_WH);
200 DUMPREG(MXR_GRAPHIC0_SXY);
201 DUMPREG(MXR_GRAPHIC0_DXY);
202
203 DUMPREG(MXR_GRAPHIC1_CFG);
204 DUMPREG(MXR_GRAPHIC1_BASE);
205 DUMPREG(MXR_GRAPHIC1_SPAN);
206 DUMPREG(MXR_GRAPHIC1_WH);
207 DUMPREG(MXR_GRAPHIC1_SXY);
208 DUMPREG(MXR_GRAPHIC1_DXY);
209#undef DUMPREG
210}
211
212static void vp_regs_dump(struct mixer_context *ctx)
213{
214#define DUMPREG(reg_id) \
215do { \
216 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
217 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
218} while (0)
219
220 DUMPREG(VP_ENABLE);
221 DUMPREG(VP_SRESET);
222 DUMPREG(VP_SHADOW_UPDATE);
223 DUMPREG(VP_FIELD_ID);
224 DUMPREG(VP_MODE);
225 DUMPREG(VP_IMG_SIZE_Y);
226 DUMPREG(VP_IMG_SIZE_C);
227 DUMPREG(VP_PER_RATE_CTRL);
228 DUMPREG(VP_TOP_Y_PTR);
229 DUMPREG(VP_BOT_Y_PTR);
230 DUMPREG(VP_TOP_C_PTR);
231 DUMPREG(VP_BOT_C_PTR);
232 DUMPREG(VP_ENDIAN_MODE);
233 DUMPREG(VP_SRC_H_POSITION);
234 DUMPREG(VP_SRC_V_POSITION);
235 DUMPREG(VP_SRC_WIDTH);
236 DUMPREG(VP_SRC_HEIGHT);
237 DUMPREG(VP_DST_H_POSITION);
238 DUMPREG(VP_DST_V_POSITION);
239 DUMPREG(VP_DST_WIDTH);
240 DUMPREG(VP_DST_HEIGHT);
241 DUMPREG(VP_H_RATIO);
242 DUMPREG(VP_V_RATIO);
243
244#undef DUMPREG
245}
246
247static inline void vp_filter_set(struct mixer_resources *res,
248 int reg_id, const u8 *data, unsigned int size)
249{
250 /* assure 4-byte align */
251 BUG_ON(size & 3);
252 for (; size; size -= 4, reg_id += 4, data += 4) {
253 u32 val = (data[0] << 24) | (data[1] << 16) |
254 (data[2] << 8) | data[3];
255 vp_reg_write(res, reg_id, val);
256 }
257}
258
259static void vp_default_filter(struct mixer_resources *res)
260{
261 vp_filter_set(res, VP_POLY8_Y0_LL,
e25e1b66 262 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
d8408326 263 vp_filter_set(res, VP_POLY4_Y0_LL,
e25e1b66 264 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
d8408326 265 vp_filter_set(res, VP_POLY4_C0_LL,
e25e1b66 266 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
d8408326
SWK		 267}
268
269static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
270{
271 struct mixer_resources *res = &ctx->mixer_res;
272
273 /* block update on vsync */
274 mixer_reg_writemask(res, MXR_STATUS, enable ?
275 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
276
1b8e5747
RS		 277 if (ctx->vp_enabled)
278 vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
d8408326
SWK		 279 VP_SHADOW_UPDATE_ENABLE : 0);
280}
281
282static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
283{
284 struct mixer_resources *res = &ctx->mixer_res;
285 u32 val;
286
287 /* choosing between interlace and progressive mode */
288 val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
289 MXR_CFG_SCAN_PROGRASSIVE);
290
def5e095
RS		 291 if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
292 /* choosing between proper HD and SD mode */
293 if (height <= 480)
294 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
295 else if (height <= 576)
296 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
297 else if (height <= 720)
298 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
299 else if (height <= 1080)
300 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
301 else
302 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
303 }
d8408326
SWK		 304
305 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
306}
307
308static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
309{
310 struct mixer_resources *res = &ctx->mixer_res;
311 u32 val;
312
313 if (height == 480) {
314 val = MXR_CFG_RGB601_0_255;
315 } else if (height == 576) {
316 val = MXR_CFG_RGB601_0_255;
317 } else if (height == 720) {
318 val = MXR_CFG_RGB709_16_235;
319 mixer_reg_write(res, MXR_CM_COEFF_Y,
320 (1 << 30) | (94 << 20) | (314 << 10) |
321 (32 << 0));
322 mixer_reg_write(res, MXR_CM_COEFF_CB,
323 (972 << 20) | (851 << 10) | (225 << 0));
324 mixer_reg_write(res, MXR_CM_COEFF_CR,
325 (225 << 20) | (820 << 10) | (1004 << 0));
326 } else if (height == 1080) {
327 val = MXR_CFG_RGB709_16_235;
328 mixer_reg_write(res, MXR_CM_COEFF_Y,
329 (1 << 30) | (94 << 20) | (314 << 10) |
330 (32 << 0));
331 mixer_reg_write(res, MXR_CM_COEFF_CB,
332 (972 << 20) | (851 << 10) | (225 << 0));
333 mixer_reg_write(res, MXR_CM_COEFF_CR,
334 (225 << 20) | (820 << 10) | (1004 << 0));
335 } else {
336 val = MXR_CFG_RGB709_16_235;
337 mixer_reg_write(res, MXR_CM_COEFF_Y,
338 (1 << 30) | (94 << 20) | (314 << 10) |
339 (32 << 0));
340 mixer_reg_write(res, MXR_CM_COEFF_CB,
341 (972 << 20) | (851 << 10) | (225 << 0));
342 mixer_reg_write(res, MXR_CM_COEFF_CR,
343 (225 << 20) | (820 << 10) | (1004 << 0));
344 }
345
346 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
347}
348
349static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
350{
351 struct mixer_resources *res = &ctx->mixer_res;
352 u32 val = enable ? ~0 : 0;
353
354 switch (win) {
355 case 0:
356 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
357 break;
358 case 1:
359 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
360 break;
361 case 2:
1b8e5747
RS		 362 if (ctx->vp_enabled) {
363 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
364 mixer_reg_writemask(res, MXR_CFG, val,
365 MXR_CFG_VP_ENABLE);
366 }
d8408326
SWK		 367 break;
368 }
369}
370
371static void mixer_run(struct mixer_context *ctx)
372{
373 struct mixer_resources *res = &ctx->mixer_res;
374
375 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
376
377 mixer_regs_dump(ctx);
378}
379
380static void vp_video_buffer(struct mixer_context *ctx, int win)
381{
382 struct mixer_resources *res = &ctx->mixer_res;
383 unsigned long flags;
384 struct hdmi_win_data *win_data;
d8408326 385 unsigned int x_ratio, y_ratio;
782953ec 386 unsigned int buf_num = 1;
d8408326
SWK		 387 dma_addr_t luma_addr[2], chroma_addr[2];
388 bool tiled_mode = false;
389 bool crcb_mode = false;
390 u32 val;
391
392 win_data = &ctx->win_data[win];
393
394 switch (win_data->pixel_format) {
395 case DRM_FORMAT_NV12MT:
396 tiled_mode = true;
363b06aa 397 case DRM_FORMAT_NV12:
d8408326
SWK		 398 crcb_mode = false;
399 buf_num = 2;
400 break;
401 /* TODO: single buffer format NV12, NV21 */
402 default:
403 /* ignore pixel format at disable time */
404 if (!win_data->dma_addr)
405 break;
406
407 DRM_ERROR("pixel format for vp is wrong [%d].\n",
408 win_data->pixel_format);
409 return;
410 }
411
d8408326 412 /* scaling feature: (src << 16) / dst */
8dcb96b6
SWK		 413 x_ratio = (win_data->src_width << 16) / win_data->crtc_width;
414 y_ratio = (win_data->src_height << 16) / win_data->crtc_height;
d8408326
SWK		 415
416 if (buf_num == 2) {
417 luma_addr[0] = win_data->dma_addr;
418 chroma_addr[0] = win_data->chroma_dma_addr;
419 } else {
420 luma_addr[0] = win_data->dma_addr;
421 chroma_addr[0] = win_data->dma_addr
8dcb96b6 422 + (win_data->fb_width * win_data->fb_height);
d8408326
SWK		 423 }
424
425 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) {
426 ctx->interlace = true;
427 if (tiled_mode) {
428 luma_addr[1] = luma_addr[0] + 0x40;
429 chroma_addr[1] = chroma_addr[0] + 0x40;
430 } else {
8dcb96b6
SWK		 431 luma_addr[1] = luma_addr[0] + win_data->fb_width;
432 chroma_addr[1] = chroma_addr[0] + win_data->fb_width;
d8408326
SWK		 433 }
434 } else {
435 ctx->interlace = false;
436 luma_addr[1] = 0;
437 chroma_addr[1] = 0;
438 }
439
440 spin_lock_irqsave(&res->reg_slock, flags);
441 mixer_vsync_set_update(ctx, false);
442
443 /* interlace or progressive scan mode */
444 val = (ctx->interlace ? ~0 : 0);
445 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
446
447 /* setup format */
448 val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
449 val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
450 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
451
452 /* setting size of input image */
8dcb96b6
SWK		 453 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_width) |
454 VP_IMG_VSIZE(win_data->fb_height));
d8408326 455 /* chroma height has to reduced by 2 to avoid chroma distorions */
8dcb96b6
SWK		 456 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_width) |
457 VP_IMG_VSIZE(win_data->fb_height / 2));
d8408326 458
8dcb96b6
SWK		 459 vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width);
460 vp_reg_write(res, VP_SRC_HEIGHT, win_data->src_height);
d8408326 461 vp_reg_write(res, VP_SRC_H_POSITION,
8dcb96b6
SWK		 462 VP_SRC_H_POSITION_VAL(win_data->fb_x));
463 vp_reg_write(res, VP_SRC_V_POSITION, win_data->fb_y);
d8408326 464
8dcb96b6
SWK		 465 vp_reg_write(res, VP_DST_WIDTH, win_data->crtc_width);
466 vp_reg_write(res, VP_DST_H_POSITION, win_data->crtc_x);
d8408326 467 if (ctx->interlace) {
8dcb96b6
SWK		 468 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height / 2);
469 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y / 2);
d8408326 470 } else {
8dcb96b6
SWK		 471 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height);
472 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y);
d8408326
SWK		 473 }
474
475 vp_reg_write(res, VP_H_RATIO, x_ratio);
476 vp_reg_write(res, VP_V_RATIO, y_ratio);
477
478 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
479
480 /* set buffer address to vp */
481 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
482 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
483 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
484 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
485
8dcb96b6
SWK		 486 mixer_cfg_scan(ctx, win_data->mode_height);
487 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
d8408326
SWK		 488 mixer_cfg_layer(ctx, win, true);
489 mixer_run(ctx);
490
491 mixer_vsync_set_update(ctx, true);
492 spin_unlock_irqrestore(&res->reg_slock, flags);
493
494 vp_regs_dump(ctx);
495}
496
aaf8b49e
RS		 497static void mixer_layer_update(struct mixer_context *ctx)
498{
499 struct mixer_resources *res = &ctx->mixer_res;
500 u32 val;
501
502 val = mixer_reg_read(res, MXR_CFG);
503
504 /* allow one update per vsync only */
505 if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK))
506 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
507}
508
d8408326
SWK		 509static void mixer_graph_buffer(struct mixer_context *ctx, int win)
510{
511 struct mixer_resources *res = &ctx->mixer_res;
512 unsigned long flags;
513 struct hdmi_win_data *win_data;
d8408326
SWK		 514 unsigned int x_ratio, y_ratio;
515 unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
d8408326
SWK		 516 dma_addr_t dma_addr;
517 unsigned int fmt;
518 u32 val;
519
520 win_data = &ctx->win_data[win];
521
522 #define RGB565 4
523 #define ARGB1555 5
524 #define ARGB4444 6
525 #define ARGB8888 7
526
527 switch (win_data->bpp) {
528 case 16:
529 fmt = ARGB4444;
530 break;
531 case 32:
532 fmt = ARGB8888;
533 break;
534 default:
535 fmt = ARGB8888;
536 }
537
d8408326
SWK		 538 /* 2x scaling feature */
539 x_ratio = 0;
540 y_ratio = 0;
541
d8408326
SWK		 542 dst_x_offset = win_data->crtc_x;
543 dst_y_offset = win_data->crtc_y;
544
545 /* converting dma address base and source offset */
8dcb96b6
SWK		 546 dma_addr = win_data->dma_addr
547 + (win_data->fb_x * win_data->bpp >> 3)
548 + (win_data->fb_y * win_data->fb_width * win_data->bpp >> 3);
d8408326
SWK		 549 src_x_offset = 0;
550 src_y_offset = 0;
551
552 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE)
553 ctx->interlace = true;
554 else
555 ctx->interlace = false;
556
557 spin_lock_irqsave(&res->reg_slock, flags);
558 mixer_vsync_set_update(ctx, false);
559
560 /* setup format */
561 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
562 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
563
564 /* setup geometry */
8dcb96b6 565 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
d8408326 566
def5e095
RS		 567 /* setup display size */
568 if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
569 win == MIXER_DEFAULT_WIN) {
570 val = MXR_MXR_RES_HEIGHT(win_data->fb_height);
571 val |= MXR_MXR_RES_WIDTH(win_data->fb_width);
572 mixer_reg_write(res, MXR_RESOLUTION, val);
573 }
574
8dcb96b6
SWK		 575 val = MXR_GRP_WH_WIDTH(win_data->crtc_width);
576 val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height);
d8408326
SWK		 577 val |= MXR_GRP_WH_H_SCALE(x_ratio);
578 val |= MXR_GRP_WH_V_SCALE(y_ratio);
579 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
580
581 /* setup offsets in source image */
582 val = MXR_GRP_SXY_SX(src_x_offset);
583 val |= MXR_GRP_SXY_SY(src_y_offset);
584 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);
585
586 /* setup offsets in display image */
587 val = MXR_GRP_DXY_DX(dst_x_offset);
588 val |= MXR_GRP_DXY_DY(dst_y_offset);
589 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
590
591 /* set buffer address to mixer */
592 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
593
8dcb96b6
SWK		 594 mixer_cfg_scan(ctx, win_data->mode_height);
595 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
d8408326 596 mixer_cfg_layer(ctx, win, true);
aaf8b49e
RS		 597
598 /* layer update mandatory for mixer 16.0.33.0 */
def5e095
RS		 599 if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
600 ctx->mxr_ver == MXR_VER_128_0_0_184)
aaf8b49e
RS		 601 mixer_layer_update(ctx);
602
d8408326
SWK		 603 mixer_run(ctx);
604
605 mixer_vsync_set_update(ctx, true);
606 spin_unlock_irqrestore(&res->reg_slock, flags);
607}
608
609static void vp_win_reset(struct mixer_context *ctx)
610{
611 struct mixer_resources *res = &ctx->mixer_res;
612 int tries = 100;
613
614 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
615 for (tries = 100; tries; --tries) {
616 /* waiting until VP_SRESET_PROCESSING is 0 */
617 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
618 break;
09760ea3 619 usleep_range(10000, 12000);
d8408326
SWK		 620 }
621 WARN(tries == 0, "failed to reset Video Processor\n");
622}
623
cf8fc4f1
JS		 624static void mixer_win_reset(struct mixer_context *ctx)
625{
626 struct mixer_resources *res = &ctx->mixer_res;
627 unsigned long flags;
628 u32 val; /* value stored to register */
629
630 spin_lock_irqsave(&res->reg_slock, flags);
631 mixer_vsync_set_update(ctx, false);
632
633 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
634
635 /* set output in RGB888 mode */
636 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
637
638 /* 16 beat burst in DMA */
639 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
640 MXR_STATUS_BURST_MASK);
641
642 /* setting default layer priority: layer1 > layer0 > video
643 * because typical usage scenario would be
644 * layer1 - OSD
645 * layer0 - framebuffer
646 * video - video overlay
647 */
648 val = MXR_LAYER_CFG_GRP1_VAL(3);
649 val |= MXR_LAYER_CFG_GRP0_VAL(2);
1b8e5747
RS		 650 if (ctx->vp_enabled)
651 val |= MXR_LAYER_CFG_VP_VAL(1);
cf8fc4f1
JS		 652 mixer_reg_write(res, MXR_LAYER_CFG, val);
653
654 /* setting background color */
655 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
656 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
657 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
658
659 /* setting graphical layers */
cf8fc4f1
JS		 660 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
661 val |= MXR_GRP_CFG_WIN_BLEND_EN;
662 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
663
0377f4ed 664 /* Don't blend layer 0 onto the mixer background */
cf8fc4f1 665 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
0377f4ed
SP		 666
667 /* Blend layer 1 into layer 0 */
668 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
669 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
cf8fc4f1
JS		 670 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
671
5736603b
SWK		 672 /* setting video layers */
673 val = MXR_GRP_CFG_ALPHA_VAL(0);
674 mixer_reg_write(res, MXR_VIDEO_CFG, val);
675
1b8e5747
RS		 676 if (ctx->vp_enabled) {
677 /* configuration of Video Processor Registers */
678 vp_win_reset(ctx);
679 vp_default_filter(res);
680 }
cf8fc4f1
JS		 681
682 /* disable all layers */
683 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
684 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
1b8e5747
RS		 685 if (ctx->vp_enabled)
686 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
cf8fc4f1
JS		 687
688 mixer_vsync_set_update(ctx, true);
689 spin_unlock_irqrestore(&res->reg_slock, flags);
690}
691
4551789f
SP		 692static irqreturn_t mixer_irq_handler(int irq, void *arg)
693{
694 struct mixer_context *ctx = arg;
695 struct mixer_resources *res = &ctx->mixer_res;
696 u32 val, base, shadow;
697
698 spin_lock(&res->reg_slock);
699
700 /* read interrupt status for handling and clearing flags for VSYNC */
701 val = mixer_reg_read(res, MXR_INT_STATUS);
702
703 /* handling VSYNC */
704 if (val & MXR_INT_STATUS_VSYNC) {
705 /* interlace scan need to check shadow register */
706 if (ctx->interlace) {
707 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
708 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
709 if (base != shadow)
710 goto out;
711
712 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
713 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
714 if (base != shadow)
715 goto out;
716 }
717
718 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
719 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
720
721 /* set wait vsync event to zero and wake up queue. */
722 if (atomic_read(&ctx->wait_vsync_event)) {
723 atomic_set(&ctx->wait_vsync_event, 0);
724 wake_up(&ctx->wait_vsync_queue);
725 }
726 }
727
728out:
729 /* clear interrupts */
730 if (~val & MXR_INT_EN_VSYNC) {
731 /* vsync interrupt use different bit for read and clear */
732 val &= ~MXR_INT_EN_VSYNC;
733 val |= MXR_INT_CLEAR_VSYNC;
734 }
735 mixer_reg_write(res, MXR_INT_STATUS, val);
736
737 spin_unlock(&res->reg_slock);
738
739 return IRQ_HANDLED;
740}
741
742static int mixer_resources_init(struct mixer_context *mixer_ctx)
743{
744 struct device *dev = &mixer_ctx->pdev->dev;
745 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
746 struct resource *res;
747 int ret;
748
749 spin_lock_init(&mixer_res->reg_slock);
750
751 mixer_res->mixer = devm_clk_get(dev, "mixer");
752 if (IS_ERR(mixer_res->mixer)) {
753 dev_err(dev, "failed to get clock 'mixer'\n");
754 return -ENODEV;
755 }
756
757 mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
758 if (IS_ERR(mixer_res->sclk_hdmi)) {
759 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
760 return -ENODEV;
761 }
762 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);
763 if (res == NULL) {
764 dev_err(dev, "get memory resource failed.\n");
765 return -ENXIO;
766 }
767
768 mixer_res->mixer_regs = devm_ioremap(dev, res->start,
769 resource_size(res));
770 if (mixer_res->mixer_regs == NULL) {
771 dev_err(dev, "register mapping failed.\n");
772 return -ENXIO;
773 }
774
775 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);
776 if (res == NULL) {
777 dev_err(dev, "get interrupt resource failed.\n");
778 return -ENXIO;
779 }
780
781 ret = devm_request_irq(dev, res->start, mixer_irq_handler,
782 0, "drm_mixer", mixer_ctx);
783 if (ret) {
784 dev_err(dev, "request interrupt failed.\n");
785 return ret;
786 }
787 mixer_res->irq = res->start;
788
789 return 0;
790}
791
792static int vp_resources_init(struct mixer_context *mixer_ctx)
793{
794 struct device *dev = &mixer_ctx->pdev->dev;
795 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
796 struct resource *res;
797
798 mixer_res->vp = devm_clk_get(dev, "vp");
799 if (IS_ERR(mixer_res->vp)) {
800 dev_err(dev, "failed to get clock 'vp'\n");
801 return -ENODEV;
802 }
803 mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
804 if (IS_ERR(mixer_res->sclk_mixer)) {
805 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
806 return -ENODEV;
807 }
808 mixer_res->sclk_dac = devm_clk_get(dev, "sclk_dac");
809 if (IS_ERR(mixer_res->sclk_dac)) {
810 dev_err(dev, "failed to get clock 'sclk_dac'\n");
811 return -ENODEV;
812 }
813
814 if (mixer_res->sclk_hdmi)
815 clk_set_parent(mixer_res->sclk_mixer, mixer_res->sclk_hdmi);
816
817 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
818 if (res == NULL) {
819 dev_err(dev, "get memory resource failed.\n");
820 return -ENXIO;
821 }
822
823 mixer_res->vp_regs = devm_ioremap(dev, res->start,
824 resource_size(res));
825 if (mixer_res->vp_regs == NULL) {
826 dev_err(dev, "register mapping failed.\n");
827 return -ENXIO;
828 }
829
830 return 0;
831}
832
f041b257 833static int mixer_initialize(struct exynos_drm_manager *mgr,
f37cd5e8 834 struct drm_device *drm_dev)
4551789f
SP		 835{
836 int ret;
f041b257 837 struct mixer_context *mixer_ctx = mgr->ctx;
f37cd5e8
ID		 838 struct exynos_drm_private *priv;
839 priv = drm_dev->dev_private;
4551789f 840
f37cd5e8
ID		 841 mgr->drm_dev = mixer_ctx->drm_dev = drm_dev;
842 mgr->pipe = mixer_ctx->pipe = priv->pipe++;
4551789f
SP		 843
844 /* acquire resources: regs, irqs, clocks */
845 ret = mixer_resources_init(mixer_ctx);
846 if (ret) {
847 DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
848 return ret;
849 }
850
851 if (mixer_ctx->vp_enabled) {
852 /* acquire vp resources: regs, irqs, clocks */
853 ret = vp_resources_init(mixer_ctx);
854 if (ret) {
855 DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
856 return ret;
857 }
858 }
859
f041b257
SP		 860 if (!is_drm_iommu_supported(mixer_ctx->drm_dev))
861 return 0;
862
863 return drm_iommu_attach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
4551789f
SP		 864}
865
f041b257 866static void mixer_mgr_remove(struct exynos_drm_manager *mgr)
1055b39f 867{
f041b257 868 struct mixer_context *mixer_ctx = mgr->ctx;
1055b39f 869
f041b257
SP		 870 if (is_drm_iommu_supported(mixer_ctx->drm_dev))
871 drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
1055b39f
ID		 872}
873
f041b257 874static int mixer_enable_vblank(struct exynos_drm_manager *mgr)
d8408326 875{
f041b257 876 struct mixer_context *mixer_ctx = mgr->ctx;
d8408326
SWK		 877 struct mixer_resources *res = &mixer_ctx->mixer_res;
878
f041b257
SP		 879 if (!mixer_ctx->powered) {
880 mixer_ctx->int_en |= MXR_INT_EN_VSYNC;
881 return 0;
882 }
d8408326
SWK		 883
884 /* enable vsync interrupt */
885 mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
886 MXR_INT_EN_VSYNC);
887
888 return 0;
889}
890
f041b257 891static void mixer_disable_vblank(struct exynos_drm_manager *mgr)
d8408326 892{
f041b257 893 struct mixer_context *mixer_ctx = mgr->ctx;
d8408326
SWK		 894 struct mixer_resources *res = &mixer_ctx->mixer_res;
895
d8408326
SWK		 896 /* disable vsync interrupt */
897 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
898}
899
f041b257
SP		 900static void mixer_win_mode_set(struct exynos_drm_manager *mgr,
901 struct exynos_drm_overlay *overlay)
d8408326 902{
f041b257 903 struct mixer_context *mixer_ctx = mgr->ctx;
d8408326
SWK		 904 struct hdmi_win_data *win_data;
905 int win;
906
d8408326
SWK		 907 if (!overlay) {
908 DRM_ERROR("overlay is NULL\n");
909 return;
910 }
911
912 DRM_DEBUG_KMS("set [%d]x[%d] at (%d,%d) to [%d]x[%d] at (%d,%d)\n",
913 overlay->fb_width, overlay->fb_height,
914 overlay->fb_x, overlay->fb_y,
915 overlay->crtc_width, overlay->crtc_height,
916 overlay->crtc_x, overlay->crtc_y);
917
918 win = overlay->zpos;
919 if (win == DEFAULT_ZPOS)
a2ee151b 920 win = MIXER_DEFAULT_WIN;
d8408326 921
1586d80c 922 if (win < 0 || win >= MIXER_WIN_NR) {
cf8fc4f1 923 DRM_ERROR("mixer window[%d] is wrong\n", win);
d8408326
SWK		 924 return;
925 }
926
927 win_data = &mixer_ctx->win_data[win];
928
929 win_data->dma_addr = overlay->dma_addr[0];
d8408326 930 win_data->chroma_dma_addr = overlay->dma_addr[1];
d8408326
SWK		 931 win_data->pixel_format = overlay->pixel_format;
932 win_data->bpp = overlay->bpp;
933
934 win_data->crtc_x = overlay->crtc_x;
935 win_data->crtc_y = overlay->crtc_y;
936 win_data->crtc_width = overlay->crtc_width;
937 win_data->crtc_height = overlay->crtc_height;
938
939 win_data->fb_x = overlay->fb_x;
940 win_data->fb_y = overlay->fb_y;
941 win_data->fb_width = overlay->fb_width;
942 win_data->fb_height = overlay->fb_height;
8dcb96b6
SWK		 943 win_data->src_width = overlay->src_width;
944 win_data->src_height = overlay->src_height;
d8408326
SWK		 945
946 win_data->mode_width = overlay->mode_width;
947 win_data->mode_height = overlay->mode_height;
948
949 win_data->scan_flags = overlay->scan_flag;
950}
951
f041b257 952static void mixer_win_commit(struct exynos_drm_manager *mgr, int zpos)
d8408326 953{
f041b257
SP		 954 struct mixer_context *mixer_ctx = mgr->ctx;
955 int win = zpos == DEFAULT_ZPOS ? MIXER_DEFAULT_WIN : zpos;
d8408326 956
cbc4c33d 957 DRM_DEBUG_KMS("win: %d\n", win);
d8408326 958
dda9012b
S		 959 mutex_lock(&mixer_ctx->mixer_mutex);
960 if (!mixer_ctx->powered) {
961 mutex_unlock(&mixer_ctx->mixer_mutex);
962 return;
963 }
964 mutex_unlock(&mixer_ctx->mixer_mutex);
965
1b8e5747 966 if (win > 1 && mixer_ctx->vp_enabled)
d8408326
SWK		 967 vp_video_buffer(mixer_ctx, win);
968 else
969 mixer_graph_buffer(mixer_ctx, win);
db43fd16
P		 970
971 mixer_ctx->win_data[win].enabled = true;
d8408326
SWK		 972}
973
f041b257 974static void mixer_win_disable(struct exynos_drm_manager *mgr, int zpos)
d8408326 975{
f041b257 976 struct mixer_context *mixer_ctx = mgr->ctx;
d8408326 977 struct mixer_resources *res = &mixer_ctx->mixer_res;
f041b257 978 int win = zpos == DEFAULT_ZPOS ? MIXER_DEFAULT_WIN : zpos;
d8408326 979 unsigned long flags;
d8408326 980
cbc4c33d 981 DRM_DEBUG_KMS("win: %d\n", win);
d8408326 982
db43fd16
P		 983 mutex_lock(&mixer_ctx->mixer_mutex);
984 if (!mixer_ctx->powered) {
985 mutex_unlock(&mixer_ctx->mixer_mutex);
986 mixer_ctx->win_data[win].resume = false;
987 return;
988 }
989 mutex_unlock(&mixer_ctx->mixer_mutex);
990
d8408326
SWK		 991 spin_lock_irqsave(&res->reg_slock, flags);
992 mixer_vsync_set_update(mixer_ctx, false);
993
994 mixer_cfg_layer(mixer_ctx, win, false);
995
996 mixer_vsync_set_update(mixer_ctx, true);
997 spin_unlock_irqrestore(&res->reg_slock, flags);
db43fd16
P		 998
999 mixer_ctx->win_data[win].enabled = false;
d8408326
SWK		 1000}
1001
f041b257 1002static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr)
8137a2e2 1003{
f041b257 1004 struct mixer_context *mixer_ctx = mgr->ctx;
8137a2e2 1005
6e95d5e6
P		 1006 mutex_lock(&mixer_ctx->mixer_mutex);
1007 if (!mixer_ctx->powered) {
1008 mutex_unlock(&mixer_ctx->mixer_mutex);
1009 return;
1010 }
1011 mutex_unlock(&mixer_ctx->mixer_mutex);
1012
1013 atomic_set(&mixer_ctx->wait_vsync_event, 1);
1014
1015 /*
1016 * wait for MIXER to signal VSYNC interrupt or return after
1017 * timeout which is set to 50ms (refresh rate of 20).
1018 */
1019 if (!wait_event_timeout(mixer_ctx->wait_vsync_queue,
1020 !atomic_read(&mixer_ctx->wait_vsync_event),
bfd8303a 1021 HZ/20))
8137a2e2
P		 1022 DRM_DEBUG_KMS("vblank wait timed out.\n");
1023}
1024
f041b257 1025static void mixer_window_suspend(struct exynos_drm_manager *mgr)
db43fd16 1026{
f041b257 1027 struct mixer_context *ctx = mgr->ctx;
db43fd16
P		 1028 struct hdmi_win_data *win_data;
1029 int i;
1030
1031 for (i = 0; i < MIXER_WIN_NR; i++) {
1032 win_data = &ctx->win_data[i];
1033 win_data->resume = win_data->enabled;
f041b257 1034 mixer_win_disable(mgr, i);
db43fd16 1035 }
f041b257 1036 mixer_wait_for_vblank(mgr);
db43fd16
P		 1037}
1038
f041b257 1039static void mixer_window_resume(struct exynos_drm_manager *mgr)
db43fd16 1040{
f041b257 1041 struct mixer_context *ctx = mgr->ctx;
db43fd16
P		 1042 struct hdmi_win_data *win_data;
1043 int i;
1044
1045 for (i = 0; i < MIXER_WIN_NR; i++) {
1046 win_data = &ctx->win_data[i];
1047 win_data->enabled = win_data->resume;
1048 win_data->resume = false;
87244fa6 1049 if (win_data->enabled)
f041b257 1050 mixer_win_commit(mgr, i);
db43fd16
P		 1051 }
1052}
1053
f041b257 1054static void mixer_poweron(struct exynos_drm_manager *mgr)
db43fd16 1055{
f041b257 1056 struct mixer_context *ctx = mgr->ctx;
db43fd16
P		 1057 struct mixer_resources *res = &ctx->mixer_res;
1058
db43fd16
P		 1059 mutex_lock(&ctx->mixer_mutex);
1060 if (ctx->powered) {
1061 mutex_unlock(&ctx->mixer_mutex);
1062 return;
1063 }
1064 ctx->powered = true;
1065 mutex_unlock(&ctx->mixer_mutex);
1066
af65c804
SP		 1067 pm_runtime_get_sync(ctx->dev);
1068
0bfb1f8b 1069 clk_prepare_enable(res->mixer);
db43fd16 1070 if (ctx->vp_enabled) {
0bfb1f8b
SP		 1071 clk_prepare_enable(res->vp);
1072 clk_prepare_enable(res->sclk_mixer);
db43fd16
P		 1073 }
1074
1075 mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
1076 mixer_win_reset(ctx);
1077
f041b257 1078 mixer_window_resume(mgr);
db43fd16
P		 1079}
1080
f041b257 1081static void mixer_poweroff(struct exynos_drm_manager *mgr)
db43fd16 1082{
f041b257 1083 struct mixer_context *ctx = mgr->ctx;
db43fd16
P		 1084 struct mixer_resources *res = &ctx->mixer_res;
1085
db43fd16
P		 1086 mutex_lock(&ctx->mixer_mutex);
1087 if (!ctx->powered)
1088 goto out;
1089 mutex_unlock(&ctx->mixer_mutex);
1090
f041b257 1091 mixer_window_suspend(mgr);
db43fd16
P		 1092
1093 ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
1094
0bfb1f8b 1095 clk_disable_unprepare(res->mixer);
db43fd16 1096 if (ctx->vp_enabled) {
0bfb1f8b
SP		 1097 clk_disable_unprepare(res->vp);
1098 clk_disable_unprepare(res->sclk_mixer);
db43fd16
P		 1099 }
1100
af65c804
SP		 1101 pm_runtime_put_sync(ctx->dev);
1102
db43fd16
P		 1103 mutex_lock(&ctx->mixer_mutex);
1104 ctx->powered = false;
1105
1106out:
1107 mutex_unlock(&ctx->mixer_mutex);
1108}
1109
f041b257 1110static void mixer_dpms(struct exynos_drm_manager *mgr, int mode)
db43fd16 1111{
db43fd16
P		 1112 switch (mode) {
1113 case DRM_MODE_DPMS_ON:
af65c804 1114 mixer_poweron(mgr);
db43fd16
P		 1115 break;
1116 case DRM_MODE_DPMS_STANDBY:
1117 case DRM_MODE_DPMS_SUSPEND:
1118 case DRM_MODE_DPMS_OFF:
af65c804 1119 mixer_poweroff(mgr);
db43fd16
P		 1120 break;
1121 default:
1122 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1123 break;
1124 }
1125}
1126
f041b257
SP		 1127/* Only valid for Mixer version 16.0.33.0 */
1128int mixer_check_mode(struct drm_display_mode *mode)
1129{
1130 u32 w, h;
1131
1132 w = mode->hdisplay;
1133 h = mode->vdisplay;
1134
1135 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
1136 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1137 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1138
1139 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
1140 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
1141 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
1142 return 0;
1143
1144 return -EINVAL;
1145}
1146
1147static struct exynos_drm_manager_ops mixer_manager_ops = {
f041b257 1148 .dpms = mixer_dpms,
d8408326
SWK		 1149 .enable_vblank = mixer_enable_vblank,
1150 .disable_vblank = mixer_disable_vblank,
8137a2e2 1151 .wait_for_vblank = mixer_wait_for_vblank,
d8408326
SWK		 1152 .win_mode_set = mixer_win_mode_set,
1153 .win_commit = mixer_win_commit,
1154 .win_disable = mixer_win_disable,
f041b257 1155};
0ea6822f 1156
f041b257
SP		 1157static struct exynos_drm_manager mixer_manager = {
1158 .type = EXYNOS_DISPLAY_TYPE_HDMI,
1159 .ops = &mixer_manager_ops,
d8408326
SWK		 1160};
1161
def5e095
RS		 1162static struct mixer_drv_data exynos5420_mxr_drv_data = {
1163 .version = MXR_VER_128_0_0_184,
1164 .is_vp_enabled = 0,
1165};
1166
cc57caf0 1167static struct mixer_drv_data exynos5250_mxr_drv_data = {
aaf8b49e
RS		 1168 .version = MXR_VER_16_0_33_0,
1169 .is_vp_enabled = 0,
1170};
1171
cc57caf0 1172static struct mixer_drv_data exynos4210_mxr_drv_data = {
1e123441 1173 .version = MXR_VER_0_0_0_16,
1b8e5747 1174 .is_vp_enabled = 1,
1e123441
RS		 1175};
1176
1177static struct platform_device_id mixer_driver_types[] = {
1178 {
1179 .name = "s5p-mixer",
cc57caf0 1180 .driver_data = (unsigned long)&exynos4210_mxr_drv_data,
aaf8b49e
RS		 1181 }, {
1182 .name = "exynos5-mixer",
cc57caf0 1183 .driver_data = (unsigned long)&exynos5250_mxr_drv_data,
aaf8b49e
RS		 1184 }, {
1185 /* end node */
1186 }
1187};
1188
1189static struct of_device_id mixer_match_types[] = {
1190 {
1191 .compatible = "samsung,exynos5-mixer",
cc57caf0
RS		 1192 .data = &exynos5250_mxr_drv_data,
1193 }, {
1194 .compatible = "samsung,exynos5250-mixer",
1195 .data = &exynos5250_mxr_drv_data,
def5e095
RS		 1196 }, {
1197 .compatible = "samsung,exynos5420-mixer",
1198 .data = &exynos5420_mxr_drv_data,
1e123441
RS		 1199 }, {
1200 /* end node */
1201 }
1202};
1203
f37cd5e8 1204static int mixer_bind(struct device *dev, struct device *manager, void *data)
d8408326 1205{
f37cd5e8
ID		 1206 struct platform_device *pdev = to_platform_device(dev);
1207 struct drm_device *drm_dev = data;
d8408326 1208 struct mixer_context *ctx;
1e123441 1209 struct mixer_drv_data *drv;
f37cd5e8 1210 int ret;
d8408326
SWK		 1211
1212 dev_info(dev, "probe start\n");
1213
f041b257
SP		 1214 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
1215 if (!ctx) {
1216 DRM_ERROR("failed to alloc mixer context.\n");
d8408326 1217 return -ENOMEM;
f041b257 1218 }
d8408326 1219
cf8fc4f1
JS		 1220 mutex_init(&ctx->mixer_mutex);
1221
aaf8b49e
RS		 1222 if (dev->of_node) {
1223 const struct of_device_id *match;
e436b09d 1224 match = of_match_node(mixer_match_types, dev->of_node);
2cdc53b3 1225 drv = (struct mixer_drv_data *)match->data;
aaf8b49e
RS		 1226 } else {
1227 drv = (struct mixer_drv_data *)
1228 platform_get_device_id(pdev)->driver_data;
1229 }
1230
4551789f 1231 ctx->pdev = pdev;
d873ab99 1232 ctx->dev = dev;
1b8e5747 1233 ctx->vp_enabled = drv->is_vp_enabled;
1e123441 1234 ctx->mxr_ver = drv->version;
57ed0f7b 1235 init_waitqueue_head(&ctx->wait_vsync_queue);
6e95d5e6 1236 atomic_set(&ctx->wait_vsync_event, 0);
d8408326 1237
f041b257 1238 mixer_manager.ctx = ctx;
f37cd5e8
ID		 1239 ret = mixer_initialize(&mixer_manager, drm_dev);
1240 if (ret)
1241 return ret;
1242
f041b257 1243 platform_set_drvdata(pdev, &mixer_manager);
f37cd5e8
ID		 1244 ret = exynos_drm_crtc_create(&mixer_manager);
1245 if (ret) {
1246 mixer_mgr_remove(&mixer_manager);
1247 return ret;
1248 }
d8408326 1249
cf8fc4f1 1250 pm_runtime_enable(dev);
d8408326
SWK		 1251
1252 return 0;
d8408326
SWK		 1253}
1254
f37cd5e8 1255static void mixer_unbind(struct device *dev, struct device *master, void *data)
d8408326 1256{
f37cd5e8
ID		 1257 struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
1258 struct drm_crtc *crtc = mgr->crtc;
1259
1260 dev_info(dev, "remove successful\n");
1261
1262 mixer_mgr_remove(mgr);
d8408326 1263
f37cd5e8 1264 pm_runtime_disable(dev);
cf8fc4f1 1265
f37cd5e8
ID		 1266 crtc->funcs->destroy(crtc);
1267}
1268
1269static const struct component_ops mixer_component_ops = {
1270 .bind = mixer_bind,
1271 .unbind = mixer_unbind,
1272};
1273
1274static int mixer_probe(struct platform_device *pdev)
1275{
df5225bc
ID		 1276 int ret;
1277
1278 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1279 mixer_manager.type);
1280 if (ret)
1281 return ret;
1282
1283 ret = component_add(&pdev->dev, &mixer_component_ops);
1284 if (ret)
1285 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1286
1287 return ret;
f37cd5e8
ID		 1288}
1289
1290static int mixer_remove(struct platform_device *pdev)
1291{
df5225bc
ID		 1292 component_del(&pdev->dev, &mixer_component_ops);
1293 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1294
d8408326
SWK		 1295 return 0;
1296}
1297
1298struct platform_driver mixer_driver = {
1299 .driver = {
aaf8b49e 1300 .name = "exynos-mixer",
d8408326 1301 .owner = THIS_MODULE,
aaf8b49e 1302 .of_match_table = mixer_match_types,
d8408326
SWK		 1303 },
1304 .probe = mixer_probe,
56550d94 1305 .remove = mixer_remove,
1e123441 1306 .id_table = mixer_driver_types,
d8408326 1307};
Linux kernel - Deliverables
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