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gma500: Fix build without ACPI
[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
CommitLineData
6a227d5f
AC		 1/*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21#include <linux/i2c.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drmP.h>
25#include "framebuffer.h"
26#include "psb_drv.h"
27#include "psb_intel_drv.h"
28#include "psb_intel_reg.h"
29#include "psb_intel_display.h"
30#include "power.h"
31#include "cdv_device.h"
32
33
34struct cdv_intel_range_t {
35 int min, max;
36};
37
38struct cdv_intel_p2_t {
39 int dot_limit;
40 int p2_slow, p2_fast;
41};
42
43struct cdv_intel_clock_t {
44 /* given values */
45 int n;
46 int m1, m2;
47 int p1, p2;
48 /* derived values */
49 int dot;
50 int vco;
51 int m;
52 int p;
53};
54
55#define INTEL_P2_NUM 2
56
57struct cdv_intel_limit_t {
58 struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
59 struct cdv_intel_p2_t p2;
60};
61
62#define CDV_LIMIT_SINGLE_LVDS_96 0
63#define CDV_LIMIT_SINGLE_LVDS_100 1
64#define CDV_LIMIT_DAC_HDMI_27 2
65#define CDV_LIMIT_DAC_HDMI_96 3
66
67static const struct cdv_intel_limit_t cdv_intel_limits[] = {
68 { /* CDV_SIGNLE_LVDS_96MHz */
69 .dot = {.min = 20000, .max = 115500},
70 .vco = {.min = 1800000, .max = 3600000},
71 .n = {.min = 2, .max = 6},
72 .m = {.min = 60, .max = 160},
73 .m1 = {.min = 0, .max = 0},
74 .m2 = {.min = 58, .max = 158},
75 .p = {.min = 28, .max = 140},
76 .p1 = {.min = 2, .max = 10},
77 .p2 = {.dot_limit = 200000,
78 .p2_slow = 14, .p2_fast = 14},
79 },
80 { /* CDV_SINGLE_LVDS_100MHz */
81 .dot = {.min = 20000, .max = 115500},
82 .vco = {.min = 1800000, .max = 3600000},
83 .n = {.min = 2, .max = 6},
84 .m = {.min = 60, .max = 160},
85 .m1 = {.min = 0, .max = 0},
86 .m2 = {.min = 58, .max = 158},
87 .p = {.min = 28, .max = 140},
88 .p1 = {.min = 2, .max = 10},
89 /* The single-channel range is 25-112Mhz, and dual-channel
90 * is 80-224Mhz. Prefer single channel as much as possible.
91 */
92 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
93 },
94 { /* CDV_DAC_HDMI_27MHz */
95 .dot = {.min = 20000, .max = 400000},
96 .vco = {.min = 1809000, .max = 3564000},
97 .n = {.min = 1, .max = 1},
98 .m = {.min = 67, .max = 132},
99 .m1 = {.min = 0, .max = 0},
100 .m2 = {.min = 65, .max = 130},
101 .p = {.min = 5, .max = 90},
102 .p1 = {.min = 1, .max = 9},
103 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
104 },
105 { /* CDV_DAC_HDMI_96MHz */
106 .dot = {.min = 20000, .max = 400000},
107 .vco = {.min = 1800000, .max = 3600000},
108 .n = {.min = 2, .max = 6},
109 .m = {.min = 60, .max = 160},
110 .m1 = {.min = 0, .max = 0},
111 .m2 = {.min = 58, .max = 158},
112 .p = {.min = 5, .max = 100},
113 .p1 = {.min = 1, .max = 10},
114 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
115 },
116};
117
118#define _wait_for(COND, MS, W) ({ \
119 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
120 int ret__ = 0; \
121 while (!(COND)) { \
122 if (time_after(jiffies, timeout__)) { \
123 ret__ = -ETIMEDOUT; \
124 break; \
125 } \
126 if (W && !in_dbg_master()) \
127 msleep(W); \
128 } \
129 ret__; \
130})
131
132#define wait_for(COND, MS) _wait_for(COND, MS, 1)
133
134
135static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
136{
137 int ret;
138
139 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
140 if (ret) {
141 DRM_ERROR("timeout waiting for SB to idle before read\n");
142 return ret;
143 }
144
145 REG_WRITE(SB_ADDR, reg);
146 REG_WRITE(SB_PCKT,
147 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
148 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
149 SET_FIELD(0xf, SB_BYTE_ENABLE));
150
151 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
152 if (ret) {
153 DRM_ERROR("timeout waiting for SB to idle after read\n");
154 return ret;
155 }
156
157 *val = REG_READ(SB_DATA);
158
159 return 0;
160}
161
162static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
163{
164 int ret;
165 static bool dpio_debug = true;
166 u32 temp;
167
168 if (dpio_debug) {
169 if (cdv_sb_read(dev, reg, &temp) == 0)
170 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
171 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
172 }
173
174 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
175 if (ret) {
176 DRM_ERROR("timeout waiting for SB to idle before write\n");
177 return ret;
178 }
179
180 REG_WRITE(SB_ADDR, reg);
181 REG_WRITE(SB_DATA, val);
182 REG_WRITE(SB_PCKT,
183 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
184 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
185 SET_FIELD(0xf, SB_BYTE_ENABLE));
186
187 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
188 if (ret) {
189 DRM_ERROR("timeout waiting for SB to idle after write\n");
190 return ret;
191 }
192
193 if (dpio_debug) {
194 if (cdv_sb_read(dev, reg, &temp) == 0)
195 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
196 }
197
198 return 0;
199}
200
201/* Reset the DPIO configuration register. The BIOS does this at every
202 * mode set.
203 */
204static void cdv_sb_reset(struct drm_device *dev)
205{
206
207 REG_WRITE(DPIO_CFG, 0);
208 REG_READ(DPIO_CFG);
209 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
210}
211
212/* Unlike most Intel display engines, on Cedarview the DPLL registers
213 * are behind this sideband bus. They must be programmed while the
214 * DPLL reference clock is on in the DPLL control register, but before
215 * the DPLL is enabled in the DPLL control register.
216 */
217static int
218cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
acd7ef92 219 struct cdv_intel_clock_t *clock, bool is_lvds)
6a227d5f
AC		 220{
221 struct psb_intel_crtc *psb_crtc =
222 to_psb_intel_crtc(crtc);
223 int pipe = psb_crtc->pipe;
224 u32 m, n_vco, p;
225 int ret = 0;
226 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
acd7ef92 227 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
6a227d5f 228 u32 ref_value;
d235e64a 229 u32 lane_reg, lane_value;
6a227d5f
AC		 230
231 cdv_sb_reset(dev);
232
d235e64a
AC		 233 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
234
235 udelay(100);
6a227d5f
AC		 236
237 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
238 ref_value = 0x68A701;
239
240 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
241
242 /* We don't know what the other fields of these regs are, so
243 * leave them in place.
244 */
acd7ef92
AC		 245 /*
246 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
247 * for the pipe A/B. Display spec 1.06 has wrong definition.
248 * Correct definition is like below:
249 *
250 * refclka mean use clock from same PLL
251 *
252 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
253 *
254 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
255 *
256 */
257 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
258 if (ret)
259 return ret;
260 ref_value &= ~(REF_CLK_MASK);
261
262 /* use DPLL_A for pipeB on CRT/HDMI */
263 if (pipe == 1 && !is_lvds) {
264 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
265 ref_value |= REF_CLK_DPLLA;
266 } else {
267 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
268 ref_value |= REF_CLK_DPLL;
269 }
270 ret = cdv_sb_write(dev, ref_sfr, ref_value);
271 if (ret)
272 return ret;
273
6a227d5f
AC		 274 ret = cdv_sb_read(dev, SB_M(pipe), &m);
275 if (ret)
276 return ret;
277 m &= ~SB_M_DIVIDER_MASK;
278 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
279 ret = cdv_sb_write(dev, SB_M(pipe), m);
280 if (ret)
281 return ret;
282
283 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
284 if (ret)
285 return ret;
286
287 /* Follow the BIOS to program the N_DIVIDER REG */
288 n_vco &= 0xFFFF;
289 n_vco |= 0x107;
290 n_vco &= ~(SB_N_VCO_SEL_MASK |
291 SB_N_DIVIDER_MASK |
292 SB_N_CB_TUNE_MASK);
293
294 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
295
296 if (clock->vco < 2250000) {
297 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
298 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
299 } else if (clock->vco < 2750000) {
300 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
301 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
302 } else if (clock->vco < 3300000) {
303 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
304 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
305 } else {
306 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
307 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
308 }
309
310 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
311 if (ret)
312 return ret;
313
314 ret = cdv_sb_read(dev, SB_P(pipe), &p);
315 if (ret)
316 return ret;
317 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
318 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
319 switch (clock->p2) {
320 case 5:
321 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
322 break;
323 case 10:
324 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
325 break;
326 case 14:
327 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
328 break;
329 case 7:
330 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
331 break;
332 default:
333 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
334 return -EINVAL;
335 }
336 ret = cdv_sb_write(dev, SB_P(pipe), p);
337 if (ret)
338 return ret;
339
d235e64a
AC		 340 lane_reg = PSB_LANE0;
341 cdv_sb_read(dev, lane_reg, &lane_value);
342 lane_value &= ~(LANE_PLL_MASK);
343 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
344 cdv_sb_write(dev, lane_reg, lane_value);
345
346 lane_reg = PSB_LANE1;
347 cdv_sb_read(dev, lane_reg, &lane_value);
348 lane_value &= ~(LANE_PLL_MASK);
349 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
350 cdv_sb_write(dev, lane_reg, lane_value);
351
352 lane_reg = PSB_LANE2;
353 cdv_sb_read(dev, lane_reg, &lane_value);
354 lane_value &= ~(LANE_PLL_MASK);
355 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
356 cdv_sb_write(dev, lane_reg, lane_value);
357
358 lane_reg = PSB_LANE3;
359 cdv_sb_read(dev, lane_reg, &lane_value);
360 lane_value &= ~(LANE_PLL_MASK);
361 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
362 cdv_sb_write(dev, lane_reg, lane_value);
6a227d5f
AC		 363
364 return 0;
365}
366
367/*
a12d6a07 368 * Returns whether any encoder on the specified pipe is of the specified type
6a227d5f 369 */
657da160 370static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
6a227d5f
AC		 371{
372 struct drm_device *dev = crtc->dev;
373 struct drm_mode_config *mode_config = &dev->mode_config;
374 struct drm_connector *l_entry;
375
376 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
377 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
a12d6a07
PJ		 378 struct psb_intel_encoder *psb_intel_encoder =
379 psb_intel_attached_encoder(l_entry);
380 if (psb_intel_encoder->type == type)
6a227d5f
AC		 381 return true;
382 }
383 }
384 return false;
385}
386
387static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
388 int refclk)
389{
390 const struct cdv_intel_limit_t *limit;
391 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
392 /*
393 * Now only single-channel LVDS is supported on CDV. If it is
394 * incorrect, please add the dual-channel LVDS.
395 */
396 if (refclk == 96000)
397 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
398 else
399 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
400 } else {
401 if (refclk == 27000)
402 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
403 else
404 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
405 }
406 return limit;
407}
408
409/* m1 is reserved as 0 in CDV, n is a ring counter */
410static void cdv_intel_clock(struct drm_device *dev,
411 int refclk, struct cdv_intel_clock_t *clock)
412{
413 clock->m = clock->m2 + 2;
414 clock->p = clock->p1 * clock->p2;
415 clock->vco = (refclk * clock->m) / clock->n;
416 clock->dot = clock->vco / clock->p;
417}
418
419
420#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
421static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
422 const struct cdv_intel_limit_t *limit,
423 struct cdv_intel_clock_t *clock)
424{
425 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
426 INTELPllInvalid("p1 out of range\n");
427 if (clock->p < limit->p.min || limit->p.max < clock->p)
428 INTELPllInvalid("p out of range\n");
429 /* unnecessary to check the range of m(m1/M2)/n again */
430 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
431 INTELPllInvalid("vco out of range\n");
432 /* XXX: We may need to be checking "Dot clock"
433 * depending on the multiplier, connector, etc.,
434 * rather than just a single range.
435 */
436 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
437 INTELPllInvalid("dot out of range\n");
438
439 return true;
440}
441
442static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
443 int refclk,
444 struct cdv_intel_clock_t *best_clock)
445{
446 struct drm_device *dev = crtc->dev;
447 struct cdv_intel_clock_t clock;
448 const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk);
449 int err = target;
450
451
452 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
453 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
454 /*
455 * For LVDS, if the panel is on, just rely on its current
456 * settings for dual-channel. We haven't figured out how to
457 * reliably set up different single/dual channel state, if we
458 * even can.
459 */
460 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
461 LVDS_CLKB_POWER_UP)
462 clock.p2 = limit->p2.p2_fast;
463 else
464 clock.p2 = limit->p2.p2_slow;
465 } else {
466 if (target < limit->p2.dot_limit)
467 clock.p2 = limit->p2.p2_slow;
468 else
469 clock.p2 = limit->p2.p2_fast;
470 }
471
472 memset(best_clock, 0, sizeof(*best_clock));
473 clock.m1 = 0;
474 /* m1 is reserved as 0 in CDV, n is a ring counter.
475 So skip the m1 loop */
476 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
477 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
478 clock.m2++) {
479 for (clock.p1 = limit->p1.min;
480 clock.p1 <= limit->p1.max;
481 clock.p1++) {
482 int this_err;
483
484 cdv_intel_clock(dev, refclk, &clock);
485
486 if (!cdv_intel_PLL_is_valid(crtc,
487 limit, &clock))
488 continue;
489
490 this_err = abs(clock.dot - target);
491 if (this_err < err) {
492 *best_clock = clock;
493 err = this_err;
494 }
495 }
496 }
497 }
498
499 return err != target;
500}
501
657da160 502static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
6a227d5f
AC		 503 int x, int y, struct drm_framebuffer *old_fb)
504{
505 struct drm_device *dev = crtc->dev;
506 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
507 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
508 int pipe = psb_intel_crtc->pipe;
509 unsigned long start, offset;
510 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
511 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
512 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
513 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
514 u32 dspcntr;
515 int ret = 0;
516
517 if (!gma_power_begin(dev, true))
518 return 0;
519
520 /* no fb bound */
521 if (!crtc->fb) {
522 dev_err(dev->dev, "No FB bound\n");
523 goto psb_intel_pipe_cleaner;
524 }
525
526
527 /* We are displaying this buffer, make sure it is actually loaded
528 into the GTT */
529 ret = psb_gtt_pin(psbfb->gtt);
530 if (ret < 0)
531 goto psb_intel_pipe_set_base_exit;
532 start = psbfb->gtt->offset;
01f2c773 533 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
6a227d5f 534
01f2c773 535 REG_WRITE(dspstride, crtc->fb->pitches[0]);
6a227d5f
AC		 536
537 dspcntr = REG_READ(dspcntr_reg);
538 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
539
540 switch (crtc->fb->bits_per_pixel) {
541 case 8:
542 dspcntr |= DISPPLANE_8BPP;
543 break;
544 case 16:
545 if (crtc->fb->depth == 15)
546 dspcntr |= DISPPLANE_15_16BPP;
547 else
548 dspcntr |= DISPPLANE_16BPP;
549 break;
550 case 24:
551 case 32:
552 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
553 break;
554 default:
555 dev_err(dev->dev, "Unknown color depth\n");
556 ret = -EINVAL;
557 goto psb_intel_pipe_set_base_exit;
558 }
559 REG_WRITE(dspcntr_reg, dspcntr);
560
561 dev_dbg(dev->dev,
562 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
563
564 REG_WRITE(dspbase, offset);
565 REG_READ(dspbase);
566 REG_WRITE(dspsurf, start);
567 REG_READ(dspsurf);
568
569psb_intel_pipe_cleaner:
570 /* If there was a previous display we can now unpin it */
571 if (old_fb)
572 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
573
574psb_intel_pipe_set_base_exit:
575 gma_power_end(dev);
576 return ret;
577}
578
acd7ef92
AC		 579#define FIFO_PIPEA (1 << 0)
580#define FIFO_PIPEB (1 << 1)
581
582static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
583{
584 struct drm_crtc *crtc;
585 struct drm_psb_private *dev_priv = dev->dev_private;
586 struct psb_intel_crtc *psb_intel_crtc = NULL;
587
588 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
589 psb_intel_crtc = to_psb_intel_crtc(crtc);
590
591 if (crtc->fb == NULL || !psb_intel_crtc->active)
592 return false;
593 return true;
594}
595
596static bool cdv_intel_single_pipe_active (struct drm_device *dev)
597{
598 uint32_t pipe_enabled = 0;
599
600 if (cdv_intel_pipe_enabled(dev, 0))
601 pipe_enabled |= FIFO_PIPEA;
602
603 if (cdv_intel_pipe_enabled(dev, 1))
604 pipe_enabled |= FIFO_PIPEB;
605
606
607 DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
608
609 if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
610 return true;
611 else
612 return false;
613}
614
615static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
616{
617 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
618 struct drm_mode_config *mode_config = &dev->mode_config;
619 struct drm_connector *connector;
620
621 if (psb_intel_crtc->pipe != 1)
622 return false;
623
624 list_for_each_entry(connector, &mode_config->connector_list, head) {
625 struct psb_intel_encoder *psb_intel_encoder =
626 psb_intel_attached_encoder(connector);
627
628 if (!connector->encoder
629 || connector->encoder->crtc != crtc)
630 continue;
631
632 if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
633 return true;
634 }
635
636 return false;
637}
638
639static void cdv_intel_disable_self_refresh (struct drm_device *dev)
640{
641 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
642
643 /* Disable self-refresh before adjust WM */
644 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
645 REG_READ(FW_BLC_SELF);
646
647 cdv_intel_wait_for_vblank(dev);
648
649 /* Cedarview workaround to write ovelay plane, which force to leave
650 * MAX_FIFO state.
651 */
652 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
653 REG_READ(OV_OVADD);
654
655 cdv_intel_wait_for_vblank(dev);
656 }
657
658}
659
660static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc)
661{
662
663 if (cdv_intel_single_pipe_active(dev)) {
664 u32 fw;
665
666 fw = REG_READ(DSPFW1);
667 fw &= ~DSP_FIFO_SR_WM_MASK;
668 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
669 fw &= ~CURSOR_B_FIFO_WM_MASK;
670 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
671 REG_WRITE(DSPFW1, fw);
672
673 fw = REG_READ(DSPFW2);
674 fw &= ~CURSOR_A_FIFO_WM_MASK;
675 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
676 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
677 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
678 REG_WRITE(DSPFW2, fw);
679
680 REG_WRITE(DSPFW3, 0x36000000);
681
682 /* ignore FW4 */
683
684 if (is_pipeb_lvds(dev, crtc)) {
685 REG_WRITE(DSPFW5, 0x00040330);
686 } else {
687 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
688 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
689 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
690 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
691 REG_WRITE(DSPFW5, fw);
692 }
693
694 REG_WRITE(DSPFW6, 0x10);
695
696 cdv_intel_wait_for_vblank(dev);
697
698 /* enable self-refresh for single pipe active */
699 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
700 REG_READ(FW_BLC_SELF);
701 cdv_intel_wait_for_vblank(dev);
702
703 } else {
704
705 /* HW team suggested values... */
706 REG_WRITE(DSPFW1, 0x3f880808);
707 REG_WRITE(DSPFW2, 0x0b020202);
708 REG_WRITE(DSPFW3, 0x24000000);
709 REG_WRITE(DSPFW4, 0x08030202);
710 REG_WRITE(DSPFW5, 0x01010101);
711 REG_WRITE(DSPFW6, 0x1d0);
712
713 cdv_intel_wait_for_vblank(dev);
714
715 cdv_intel_disable_self_refresh(dev);
716
717 }
718}
719
720/** Loads the palette/gamma unit for the CRTC with the prepared values */
721static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
722{
723 struct drm_device *dev = crtc->dev;
724 struct drm_psb_private *dev_priv =
725 (struct drm_psb_private *)dev->dev_private;
726 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
727 int palreg = PALETTE_A;
728 int i;
729
730 /* The clocks have to be on to load the palette. */
731 if (!crtc->enabled)
732 return;
733
734 switch (psb_intel_crtc->pipe) {
735 case 0:
736 break;
737 case 1:
738 palreg = PALETTE_B;
739 break;
740 case 2:
741 palreg = PALETTE_C;
742 break;
743 default:
744 dev_err(dev->dev, "Illegal Pipe Number.\n");
745 return;
746 }
747
748 if (gma_power_begin(dev, false)) {
749 for (i = 0; i < 256; i++) {
750 REG_WRITE(palreg + 4 * i,
751 ((psb_intel_crtc->lut_r[i] +
752 psb_intel_crtc->lut_adj[i]) << 16) |
753 ((psb_intel_crtc->lut_g[i] +
754 psb_intel_crtc->lut_adj[i]) << 8) |
755 (psb_intel_crtc->lut_b[i] +
756 psb_intel_crtc->lut_adj[i]));
757 }
758 gma_power_end(dev);
759 } else {
760 for (i = 0; i < 256; i++) {
761 dev_priv->regs.psb.save_palette_a[i] =
762 ((psb_intel_crtc->lut_r[i] +
763 psb_intel_crtc->lut_adj[i]) << 16) |
764 ((psb_intel_crtc->lut_g[i] +
765 psb_intel_crtc->lut_adj[i]) << 8) |
766 (psb_intel_crtc->lut_b[i] +
767 psb_intel_crtc->lut_adj[i]);
768 }
769
770 }
771}
772
6a227d5f
AC		 773/**
774 * Sets the power management mode of the pipe and plane.
775 *
776 * This code should probably grow support for turning the cursor off and back
777 * on appropriately at the same time as we're turning the pipe off/on.
778 */
779static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
780{
781 struct drm_device *dev = crtc->dev;
782 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
783 int pipe = psb_intel_crtc->pipe;
784 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
785 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
786 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
787 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
acd7ef92 788 int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT;
6a227d5f 789 u32 temp;
6a227d5f
AC		 790
791 /* XXX: When our outputs are all unaware of DPMS modes other than off
792 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
793 */
acd7ef92
AC		 794 cdv_intel_disable_self_refresh(dev);
795
6a227d5f
AC		 796 switch (mode) {
797 case DRM_MODE_DPMS_ON:
798 case DRM_MODE_DPMS_STANDBY:
799 case DRM_MODE_DPMS_SUSPEND:
acd7ef92
AC		 800 if (psb_intel_crtc->active)
801 return;
802
803 psb_intel_crtc->active = true;
804
6a227d5f
AC		 805 /* Enable the DPLL */
806 temp = REG_READ(dpll_reg);
807 if ((temp & DPLL_VCO_ENABLE) == 0) {
808 REG_WRITE(dpll_reg, temp);
809 REG_READ(dpll_reg);
810 /* Wait for the clocks to stabilize. */
811 udelay(150);
812 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
813 REG_READ(dpll_reg);
814 /* Wait for the clocks to stabilize. */
815 udelay(150);
816 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
817 REG_READ(dpll_reg);
818 /* Wait for the clocks to stabilize. */
819 udelay(150);
820 }
821
822 /* Jim Bish - switch plan and pipe per scott */
823 /* Enable the plane */
824 temp = REG_READ(dspcntr_reg);
825 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
826 REG_WRITE(dspcntr_reg,
827 temp | DISPLAY_PLANE_ENABLE);
828 /* Flush the plane changes */
829 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
830 }
831
832 udelay(150);
833
834 /* Enable the pipe */
835 temp = REG_READ(pipeconf_reg);
836 if ((temp & PIPEACONF_ENABLE) == 0)
837 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
838
acd7ef92
AC		 839 temp = REG_READ(pipestat_reg);
840 temp &= ~(0xFFFF);
841 temp |= PIPE_FIFO_UNDERRUN;
842 REG_WRITE(pipestat_reg, temp);
843 REG_READ(pipestat_reg);
844
845 cdv_intel_update_watermark(dev, crtc);
846 cdv_intel_crtc_load_lut(crtc);
6a227d5f
AC		 847
848 /* Give the overlay scaler a chance to enable
849 * if it's on this pipe */
850 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
acd7ef92 851 psb_intel_crtc->crtc_enable = true;
6a227d5f
AC		 852 break;
853 case DRM_MODE_DPMS_OFF:
acd7ef92
AC		 854 if (!psb_intel_crtc->active)
855 return;
856
857 psb_intel_crtc->active = false;
858
6a227d5f
AC		 859 /* Give the overlay scaler a chance to disable
860 * if it's on this pipe */
861 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
862
863 /* Disable the VGA plane that we never use */
864 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
865
866 /* Jim Bish - changed pipe/plane here as well. */
867
acd7ef92 868 drm_vblank_off(dev, pipe);
6a227d5f
AC		 869 /* Wait for vblank for the disable to take effect */
870 cdv_intel_wait_for_vblank(dev);
871
872 /* Next, disable display pipes */
873 temp = REG_READ(pipeconf_reg);
874 if ((temp & PIPEACONF_ENABLE) != 0) {
875 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
876 REG_READ(pipeconf_reg);
877 }
878
879 /* Wait for vblank for the disable to take effect. */
880 cdv_intel_wait_for_vblank(dev);
881
882 udelay(150);
883
884 /* Disable display plane */
885 temp = REG_READ(dspcntr_reg);
886 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
887 REG_WRITE(dspcntr_reg,
888 temp & ~DISPLAY_PLANE_ENABLE);
889 /* Flush the plane changes */
890 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
891 REG_READ(dspbase_reg);
892 }
893
894 temp = REG_READ(dpll_reg);
895 if ((temp & DPLL_VCO_ENABLE) != 0) {
896 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
897 REG_READ(dpll_reg);
898 }
899
900 /* Wait for the clocks to turn off. */
901 udelay(150);
acd7ef92
AC		 902 cdv_intel_update_watermark(dev, crtc);
903 psb_intel_crtc->crtc_enable = false;
6a227d5f
AC		 904 break;
905 }
6a227d5f
AC		 906 /*Set FIFO Watermarks*/
907 REG_WRITE(DSPARB, 0x3F3E);
908}
909
910static void cdv_intel_crtc_prepare(struct drm_crtc *crtc)
911{
912 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
913 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
914}
915
916static void cdv_intel_crtc_commit(struct drm_crtc *crtc)
917{
918 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
919 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
920}
921
6a227d5f
AC		 922static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc,
923 struct drm_display_mode *mode,
924 struct drm_display_mode *adjusted_mode)
925{
926 return true;
927}
928
929
930/**
931 * Return the pipe currently connected to the panel fitter,
932 * or -1 if the panel fitter is not present or not in use
933 */
934static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
935{
936 u32 pfit_control;
937
938 pfit_control = REG_READ(PFIT_CONTROL);
939
940 /* See if the panel fitter is in use */
941 if ((pfit_control & PFIT_ENABLE) == 0)
942 return -1;
943 return (pfit_control >> 29) & 0x3;
944}
945
946static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
947 struct drm_display_mode *mode,
948 struct drm_display_mode *adjusted_mode,
949 int x, int y,
950 struct drm_framebuffer *old_fb)
951{
952 struct drm_device *dev = crtc->dev;
acd7ef92 953 struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f
AC		 954 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
955 int pipe = psb_intel_crtc->pipe;
956 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
957 int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
958 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
959 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
960 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
961 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
962 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
963 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
964 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
965 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
966 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
967 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
968 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
969 int refclk;
970 struct cdv_intel_clock_t clock;
971 u32 dpll = 0, dspcntr, pipeconf;
0313c0de 972 bool ok;
6a227d5f
AC		 973 bool is_crt = false, is_lvds = false, is_tv = false;
974 bool is_hdmi = false;
975 struct drm_mode_config *mode_config = &dev->mode_config;
976 struct drm_connector *connector;
977
978 list_for_each_entry(connector, &mode_config->connector_list, head) {
a12d6a07
PJ		 979 struct psb_intel_encoder *psb_intel_encoder =
980 psb_intel_attached_encoder(connector);
6a227d5f
AC		 981
982 if (!connector->encoder
983 || connector->encoder->crtc != crtc)
984 continue;
985
a12d6a07 986 switch (psb_intel_encoder->type) {
6a227d5f
AC		 987 case INTEL_OUTPUT_LVDS:
988 is_lvds = true;
989 break;
6a227d5f
AC		 990 case INTEL_OUTPUT_TVOUT:
991 is_tv = true;
992 break;
993 case INTEL_OUTPUT_ANALOG:
994 is_crt = true;
995 break;
996 case INTEL_OUTPUT_HDMI:
997 is_hdmi = true;
998 break;
999 }
1000 }
1001
acd7ef92
AC		 1002 if (dev_priv->dplla_96mhz)
1003 /* low-end sku, 96/100 mhz */
1004 refclk = 96000;
1005 else
1006 /* high-end sku, 27/100 mhz */
6a227d5f
AC		 1007 refclk = 27000;
1008
acd7ef92
AC		 1009 if (is_lvds && dev_priv->lvds_use_ssc) {
1010 refclk = dev_priv->lvds_ssc_freq * 1000;
1011 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
1012 }
1013
6a227d5f
AC		 1014 drm_mode_debug_printmodeline(adjusted_mode);
1015
1016 ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
1017 &clock);
1018 if (!ok) {
1019 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
1020 return 0;
1021 }
1022
1023 dpll = DPLL_VGA_MODE_DIS;
1024 if (is_tv) {
1025 /* XXX: just matching BIOS for now */
1026/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
1027 dpll |= 3;
1028 }
acd7ef92 1029/* dpll |= PLL_REF_INPUT_DREFCLK; */
6a227d5f
AC		 1030
1031 dpll |= DPLL_SYNCLOCK_ENABLE;
acd7ef92 1032/* if (is_lvds)
6a227d5f
AC		 1033 dpll |= DPLLB_MODE_LVDS;
1034 else
acd7ef92 1035 dpll |= DPLLB_MODE_DAC_SERIAL; */
6a227d5f
AC		 1036 /* dpll |= (2 << 11); */
1037
1038 /* setup pipeconf */
1039 pipeconf = REG_READ(pipeconf_reg);
1040
1041 /* Set up the display plane register */
1042 dspcntr = DISPPLANE_GAMMA_ENABLE;
1043
1044 if (pipe == 0)
1045 dspcntr |= DISPPLANE_SEL_PIPE_A;
1046 else
1047 dspcntr |= DISPPLANE_SEL_PIPE_B;
1048
1049 dspcntr |= DISPLAY_PLANE_ENABLE;
1050 pipeconf |= PIPEACONF_ENABLE;
1051
1052 REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
1053 REG_READ(dpll_reg);
1054
acd7ef92 1055 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds);
6a227d5f
AC		 1056
1057 udelay(150);
1058
1059
1060 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1061 * This is an exception to the general rule that mode_set doesn't turn
1062 * things on.
1063 */
1064 if (is_lvds) {
1065 u32 lvds = REG_READ(LVDS);
1066
1067 lvds |=
1068 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
1069 LVDS_PIPEB_SELECT;
1070 /* Set the B0-B3 data pairs corresponding to
1071 * whether we're going to
1072 * set the DPLLs for dual-channel mode or not.
1073 */
1074 if (clock.p2 == 7)
1075 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1076 else
1077 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1078
1079 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1080 * appropriately here, but we need to look more
1081 * thoroughly into how panels behave in the two modes.
1082 */
1083
1084 REG_WRITE(LVDS, lvds);
1085 REG_READ(LVDS);
1086 }
1087
1088 dpll |= DPLL_VCO_ENABLE;
1089
1090 /* Disable the panel fitter if it was on our pipe */
1091 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
1092 REG_WRITE(PFIT_CONTROL, 0);
1093
1094 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1095 drm_mode_debug_printmodeline(mode);
1096
1097 REG_WRITE(dpll_reg,
1098 (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
1099 REG_READ(dpll_reg);
1100 /* Wait for the clocks to stabilize. */
1101 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
1102
1103 if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
1104 dev_err(dev->dev, "Failed to get DPLL lock\n");
1105 return -EBUSY;
1106 }
1107
1108 {
1109 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1110 REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1111 }
1112
1113 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1114 ((adjusted_mode->crtc_htotal - 1) << 16));
1115 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1116 ((adjusted_mode->crtc_hblank_end - 1) << 16));
1117 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1118 ((adjusted_mode->crtc_hsync_end - 1) << 16));
1119 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1120 ((adjusted_mode->crtc_vtotal - 1) << 16));
1121 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1122 ((adjusted_mode->crtc_vblank_end - 1) << 16));
1123 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1124 ((adjusted_mode->crtc_vsync_end - 1) << 16));
1125 /* pipesrc and dspsize control the size that is scaled from,
1126 * which should always be the user's requested size.
1127 */
1128 REG_WRITE(dspsize_reg,
1129 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
1130 REG_WRITE(dsppos_reg, 0);
1131 REG_WRITE(pipesrc_reg,
1132 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1133 REG_WRITE(pipeconf_reg, pipeconf);
1134 REG_READ(pipeconf_reg);
1135
1136 cdv_intel_wait_for_vblank(dev);
1137
1138 REG_WRITE(dspcntr_reg, dspcntr);
1139
1140 /* Flush the plane changes */
1141 {
1142 struct drm_crtc_helper_funcs *crtc_funcs =
1143 crtc->helper_private;
1144 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
1145 }
1146
1147 cdv_intel_wait_for_vblank(dev);
1148
1149 return 0;
1150}
1151
6a227d5f
AC		 1152
1153/**
1154 * Save HW states of giving crtc
1155 */
1156static void cdv_intel_crtc_save(struct drm_crtc *crtc)
1157{
1158 struct drm_device *dev = crtc->dev;
1159 /* struct drm_psb_private *dev_priv =
1160 (struct drm_psb_private *)dev->dev_private; */
1161 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1162 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
1163 int pipeA = (psb_intel_crtc->pipe == 0);
1164 uint32_t paletteReg;
1165 int i;
1166
1167 if (!crtc_state) {
1168 dev_dbg(dev->dev, "No CRTC state found\n");
1169 return;
1170 }
1171
1172 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
1173 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
1174 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
1175 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
1176 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
1177 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
1178 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
1179 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
1180 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
1181 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
1182 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
1183 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
1184 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
1185
1186 /*NOTE: DSPSIZE DSPPOS only for psb*/
1187 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
1188 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
1189
1190 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
1191
1192 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1193 crtc_state->saveDSPCNTR,
1194 crtc_state->savePIPECONF,
1195 crtc_state->savePIPESRC,
1196 crtc_state->saveFP0,
1197 crtc_state->saveFP1,
1198 crtc_state->saveDPLL,
1199 crtc_state->saveHTOTAL,
1200 crtc_state->saveHBLANK,
1201 crtc_state->saveHSYNC,
1202 crtc_state->saveVTOTAL,
1203 crtc_state->saveVBLANK,
1204 crtc_state->saveVSYNC,
1205 crtc_state->saveDSPSTRIDE,
1206 crtc_state->saveDSPSIZE,
1207 crtc_state->saveDSPPOS,
1208 crtc_state->saveDSPBASE
1209 );
1210
1211 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
1212 for (i = 0; i < 256; ++i)
1213 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
1214}
1215
1216/**
1217 * Restore HW states of giving crtc
1218 */
1219static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
1220{
1221 struct drm_device *dev = crtc->dev;
1222 /* struct drm_psb_private * dev_priv =
1223 (struct drm_psb_private *)dev->dev_private; */
1224 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1225 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
1226 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
1227 int pipeA = (psb_intel_crtc->pipe == 0);
1228 uint32_t paletteReg;
1229 int i;
1230
1231 if (!crtc_state) {
1232 dev_dbg(dev->dev, "No crtc state\n");
1233 return;
1234 }
1235
1236 DRM_DEBUG(
1237 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1238 REG_READ(pipeA ? DSPACNTR : DSPBCNTR),
1239 REG_READ(pipeA ? PIPEACONF : PIPEBCONF),
1240 REG_READ(pipeA ? PIPEASRC : PIPEBSRC),
1241 REG_READ(pipeA ? FPA0 : FPB0),
1242 REG_READ(pipeA ? FPA1 : FPB1),
1243 REG_READ(pipeA ? DPLL_A : DPLL_B),
1244 REG_READ(pipeA ? HTOTAL_A : HTOTAL_B),
1245 REG_READ(pipeA ? HBLANK_A : HBLANK_B),
1246 REG_READ(pipeA ? HSYNC_A : HSYNC_B),
1247 REG_READ(pipeA ? VTOTAL_A : VTOTAL_B),
1248 REG_READ(pipeA ? VBLANK_A : VBLANK_B),
1249 REG_READ(pipeA ? VSYNC_A : VSYNC_B),
1250 REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE),
1251 REG_READ(pipeA ? DSPASIZE : DSPBSIZE),
1252 REG_READ(pipeA ? DSPAPOS : DSPBPOS),
1253 REG_READ(pipeA ? DSPABASE : DSPBBASE)
1254 );
1255
1256 DRM_DEBUG(
1257 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1258 crtc_state->saveDSPCNTR,
1259 crtc_state->savePIPECONF,
1260 crtc_state->savePIPESRC,
1261 crtc_state->saveFP0,
1262 crtc_state->saveFP1,
1263 crtc_state->saveDPLL,
1264 crtc_state->saveHTOTAL,
1265 crtc_state->saveHBLANK,
1266 crtc_state->saveHSYNC,
1267 crtc_state->saveVTOTAL,
1268 crtc_state->saveVBLANK,
1269 crtc_state->saveVSYNC,
1270 crtc_state->saveDSPSTRIDE,
1271 crtc_state->saveDSPSIZE,
1272 crtc_state->saveDSPPOS,
1273 crtc_state->saveDSPBASE
1274 );
1275
1276
1277 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
1278 REG_WRITE(pipeA ? DPLL_A : DPLL_B,
1279 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
1280 REG_READ(pipeA ? DPLL_A : DPLL_B);
1281 DRM_DEBUG("write dpll: %x\n",
1282 REG_READ(pipeA ? DPLL_A : DPLL_B));
1283 udelay(150);
1284 }
1285
1286 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
1287 REG_READ(pipeA ? FPA0 : FPB0);
1288
1289 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
1290 REG_READ(pipeA ? FPA1 : FPB1);
1291
1292 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
1293 REG_READ(pipeA ? DPLL_A : DPLL_B);
1294 udelay(150);
1295
1296 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
1297 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
1298 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
1299 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
1300 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
1301 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
1302 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
1303
1304 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
1305 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
1306
1307 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
1308 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
1309 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
1310
1311 cdv_intel_wait_for_vblank(dev);
1312
1313 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
1314 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
1315
1316 cdv_intel_wait_for_vblank(dev);
1317
1318 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
1319 for (i = 0; i < 256; ++i)
1320 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1321}
1322
1323static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
1324 struct drm_file *file_priv,
1325 uint32_t handle,
1326 uint32_t width, uint32_t height)
1327{
1328 struct drm_device *dev = crtc->dev;
1329 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1330 int pipe = psb_intel_crtc->pipe;
1331 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1332 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1333 uint32_t temp;
1334 size_t addr = 0;
1335 struct gtt_range *gt;
1336 struct drm_gem_object *obj;
1337 int ret;
1338
1339 /* if we want to turn of the cursor ignore width and height */
1340 if (!handle) {
1341 /* turn off the cursor */
1342 temp = CURSOR_MODE_DISABLE;
1343
1344 if (gma_power_begin(dev, false)) {
1345 REG_WRITE(control, temp);
1346 REG_WRITE(base, 0);
1347 gma_power_end(dev);
1348 }
1349
1350 /* unpin the old GEM object */
1351 if (psb_intel_crtc->cursor_obj) {
1352 gt = container_of(psb_intel_crtc->cursor_obj,
1353 struct gtt_range, gem);
1354 psb_gtt_unpin(gt);
1355 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1356 psb_intel_crtc->cursor_obj = NULL;
1357 }
1358
1359 return 0;
1360 }
1361
1362 /* Currently we only support 64x64 cursors */
1363 if (width != 64 || height != 64) {
1364 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1365 return -EINVAL;
1366 }
1367
1368 obj = drm_gem_object_lookup(dev, file_priv, handle);
1369 if (!obj)
1370 return -ENOENT;
1371
1372 if (obj->size < width * height * 4) {
1373 dev_dbg(dev->dev, "buffer is to small\n");
1374 return -ENOMEM;
1375 }
1376
1377 gt = container_of(obj, struct gtt_range, gem);
1378
1379 /* Pin the memory into the GTT */
1380 ret = psb_gtt_pin(gt);
1381 if (ret) {
1382 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1383 return ret;
1384 }
1385
1386 addr = gt->offset; /* Or resource.start ??? */
1387
1388 psb_intel_crtc->cursor_addr = addr;
1389
1390 temp = 0;
1391 /* set the pipe for the cursor */
1392 temp |= (pipe << 28);
1393 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1394
1395 if (gma_power_begin(dev, false)) {
1396 REG_WRITE(control, temp);
1397 REG_WRITE(base, addr);
1398 gma_power_end(dev);
1399 }
1400
1401 /* unpin the old GEM object */
1402 if (psb_intel_crtc->cursor_obj) {
1403 gt = container_of(psb_intel_crtc->cursor_obj,
1404 struct gtt_range, gem);
1405 psb_gtt_unpin(gt);
1406 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1407 psb_intel_crtc->cursor_obj = obj;
1408 }
1409 return 0;
1410}
1411
1412static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1413{
1414 struct drm_device *dev = crtc->dev;
1415 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1416 int pipe = psb_intel_crtc->pipe;
1417 uint32_t temp = 0;
1418 uint32_t adder;
1419
1420
1421 if (x < 0) {
1422 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1423 x = -x;
1424 }
1425 if (y < 0) {
1426 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1427 y = -y;
1428 }
1429
1430 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1431 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1432
1433 adder = psb_intel_crtc->cursor_addr;
1434
1435 if (gma_power_begin(dev, false)) {
1436 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1437 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1438 gma_power_end(dev);
1439 }
1440 return 0;
1441}
1442
1443static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1444 u16 *green, u16 *blue, uint32_t start, uint32_t size)
1445{
1446 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1447 int i;
1448 int end = (start + size > 256) ? 256 : start + size;
1449
1450 for (i = start; i < end; i++) {
1451 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1452 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1453 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1454 }
1455
1456 cdv_intel_crtc_load_lut(crtc);
1457}
1458
1459static int cdv_crtc_set_config(struct drm_mode_set *set)
1460{
1461 int ret = 0;
1462 struct drm_device *dev = set->crtc->dev;
1463 struct drm_psb_private *dev_priv = dev->dev_private;
1464
1465 if (!dev_priv->rpm_enabled)
1466 return drm_crtc_helper_set_config(set);
1467
1468 pm_runtime_forbid(&dev->pdev->dev);
1469
1470 ret = drm_crtc_helper_set_config(set);
1471
1472 pm_runtime_allow(&dev->pdev->dev);
1473
1474 return ret;
1475}
1476
1477/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1478
1479/* FIXME: why are we using this, should it be cdv_ in this tree ? */
1480
1481static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
1482{
1483 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1484 clock->p = clock->p1 * clock->p2;
1485 clock->vco = refclk * clock->m / (clock->n + 2);
1486 clock->dot = clock->vco / clock->p;
1487}
1488
1489/* Returns the clock of the currently programmed mode of the given pipe. */
1490static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1491 struct drm_crtc *crtc)
1492{
1493 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1494 int pipe = psb_intel_crtc->pipe;
1495 u32 dpll;
1496 u32 fp;
1497 struct cdv_intel_clock_t clock;
1498 bool is_lvds;
1499 struct drm_psb_private *dev_priv = dev->dev_private;
1500
1501 if (gma_power_begin(dev, false)) {
1502 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
1503 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1504 fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
1505 else
1506 fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
1507 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1508 gma_power_end(dev);
1509 } else {
1510 dpll = (pipe == 0) ?
c6265ff5
AC		 1511 dev_priv->regs.psb.saveDPLL_A :
1512 dev_priv->regs.psb.saveDPLL_B;
6a227d5f
AC		 1513
1514 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1515 fp = (pipe == 0) ?
c6265ff5
AC		 1516 dev_priv->regs.psb.saveFPA0 :
1517 dev_priv->regs.psb.saveFPB0;
6a227d5f
AC		 1518 else
1519 fp = (pipe == 0) ?
c6265ff5
AC		 1520 dev_priv->regs.psb.saveFPA1 :
1521 dev_priv->regs.psb.saveFPB1;
6a227d5f 1522
648a8e34 1523 is_lvds = (pipe == 1) &&
c6265ff5 1524 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
6a227d5f
AC		 1525 }
1526
1527 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1528 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1529 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1530
1531 if (is_lvds) {
1532 clock.p1 =
1533 ffs((dpll &
1534 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1535 DPLL_FPA01_P1_POST_DIV_SHIFT);
1536 if (clock.p1 == 0) {
1537 clock.p1 = 4;
1538 dev_err(dev->dev, "PLL %d\n", dpll);
1539 }
1540 clock.p2 = 14;
1541
1542 if ((dpll & PLL_REF_INPUT_MASK) ==
1543 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1544 /* XXX: might not be 66MHz */
1545 i8xx_clock(66000, &clock);
1546 } else
1547 i8xx_clock(48000, &clock);
1548 } else {
1549 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1550 clock.p1 = 2;
1551 else {
1552 clock.p1 =
1553 ((dpll &
1554 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1555 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1556 }
1557 if (dpll & PLL_P2_DIVIDE_BY_4)
1558 clock.p2 = 4;
1559 else
1560 clock.p2 = 2;
1561
1562 i8xx_clock(48000, &clock);
1563 }
1564
1565 /* XXX: It would be nice to validate the clocks, but we can't reuse
1566 * i830PllIsValid() because it relies on the xf86_config connector
1567 * configuration being accurate, which it isn't necessarily.
1568 */
1569
1570 return clock.dot;
1571}
1572
1573/** Returns the currently programmed mode of the given pipe. */
1574struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1575 struct drm_crtc *crtc)
1576{
1577 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1578 int pipe = psb_intel_crtc->pipe;
1579 struct drm_display_mode *mode;
1580 int htot;
1581 int hsync;
1582 int vtot;
1583 int vsync;
1584 struct drm_psb_private *dev_priv = dev->dev_private;
1585
1586 if (gma_power_begin(dev, false)) {
1587 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1588 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1589 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1590 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1591 gma_power_end(dev);
1592 } else {
1593 htot = (pipe == 0) ?
c6265ff5
AC		 1594 dev_priv->regs.psb.saveHTOTAL_A :
1595 dev_priv->regs.psb.saveHTOTAL_B;
6a227d5f 1596 hsync = (pipe == 0) ?
c6265ff5
AC		 1597 dev_priv->regs.psb.saveHSYNC_A :
1598 dev_priv->regs.psb.saveHSYNC_B;
6a227d5f 1599 vtot = (pipe == 0) ?
c6265ff5
AC		 1600 dev_priv->regs.psb.saveVTOTAL_A :
1601 dev_priv->regs.psb.saveVTOTAL_B;
6a227d5f 1602 vsync = (pipe == 0) ?
c6265ff5
AC		 1603 dev_priv->regs.psb.saveVSYNC_A :
1604 dev_priv->regs.psb.saveVSYNC_B;
6a227d5f
AC		 1605 }
1606
1607 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1608 if (!mode)
1609 return NULL;
1610
1611 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1612 mode->hdisplay = (htot & 0xffff) + 1;
1613 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1614 mode->hsync_start = (hsync & 0xffff) + 1;
1615 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1616 mode->vdisplay = (vtot & 0xffff) + 1;
1617 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1618 mode->vsync_start = (vsync & 0xffff) + 1;
1619 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1620
1621 drm_mode_set_name(mode);
1622 drm_mode_set_crtcinfo(mode, 0);
1623
1624 return mode;
1625}
1626
1627static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
1628{
1629 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1630
1631 kfree(psb_intel_crtc->crtc_state);
1632 drm_crtc_cleanup(crtc);
1633 kfree(psb_intel_crtc);
1634}
1635
1636const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1637 .dpms = cdv_intel_crtc_dpms,
1638 .mode_fixup = cdv_intel_crtc_mode_fixup,
1639 .mode_set = cdv_intel_crtc_mode_set,
1640 .mode_set_base = cdv_intel_pipe_set_base,
1641 .prepare = cdv_intel_crtc_prepare,
1642 .commit = cdv_intel_crtc_commit,
1643};
1644
1645const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1646 .save = cdv_intel_crtc_save,
1647 .restore = cdv_intel_crtc_restore,
1648 .cursor_set = cdv_intel_crtc_cursor_set,
1649 .cursor_move = cdv_intel_crtc_cursor_move,
1650 .gamma_set = cdv_intel_crtc_gamma_set,
1651 .set_config = cdv_crtc_set_config,
1652 .destroy = cdv_intel_crtc_destroy,
1653};
Linux kernel - Deliverables
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